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1/*
2 * Renesas R-Car GPIO Support
3 *
4 * Copyright (C) 2013 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/err.h>
17#include <linux/gpio.h>
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/ioport.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/pinctrl/consumer.h>
27#include <linux/platform_data/gpio-rcar.h>
28#include <linux/platform_device.h>
29#include <linux/spinlock.h>
30#include <linux/slab.h>
31
32struct gpio_rcar_priv {
33 void __iomem *base;
34 spinlock_t lock;
35 struct gpio_rcar_config config;
36 struct platform_device *pdev;
37 struct gpio_chip gpio_chip;
38 struct irq_chip irq_chip;
39 struct irq_domain *irq_domain;
40};
41
42#define IOINTSEL 0x00
43#define INOUTSEL 0x04
44#define OUTDT 0x08
45#define INDT 0x0c
46#define INTDT 0x10
47#define INTCLR 0x14
48#define INTMSK 0x18
49#define MSKCLR 0x1c
50#define POSNEG 0x20
51#define EDGLEVEL 0x24
52#define FILONOFF 0x28
53#define BOTHEDGE 0x4c
54
55#define RCAR_MAX_GPIO_PER_BANK 32
56
57static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
58{
59 return ioread32(p->base + offs);
60}
61
62static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
63 u32 value)
64{
65 iowrite32(value, p->base + offs);
66}
67
68static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
69 int bit, bool value)
70{
71 u32 tmp = gpio_rcar_read(p, offs);
72
73 if (value)
74 tmp |= BIT(bit);
75 else
76 tmp &= ~BIT(bit);
77
78 gpio_rcar_write(p, offs, tmp);
79}
80
81static void gpio_rcar_irq_disable(struct irq_data *d)
82{
83 struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
84
85 gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
86}
87
88static void gpio_rcar_irq_enable(struct irq_data *d)
89{
90 struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
91
92 gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
93}
94
95static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
96 unsigned int hwirq,
97 bool active_high_rising_edge,
98 bool level_trigger,
99 bool both)
100{
101 unsigned long flags;
102
103 /* follow steps in the GPIO documentation for
104 * "Setting Edge-Sensitive Interrupt Input Mode" and
105 * "Setting Level-Sensitive Interrupt Input Mode"
106 */
107
108 spin_lock_irqsave(&p->lock, flags);
109
110 /* Configure postive or negative logic in POSNEG */
111 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
112
113 /* Configure edge or level trigger in EDGLEVEL */
114 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
115
116 /* Select one edge or both edges in BOTHEDGE */
117 if (p->config.has_both_edge_trigger)
118 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
119
120 /* Select "Interrupt Input Mode" in IOINTSEL */
121 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
122
123 /* Write INTCLR in case of edge trigger */
124 if (!level_trigger)
125 gpio_rcar_write(p, INTCLR, BIT(hwirq));
126
127 spin_unlock_irqrestore(&p->lock, flags);
128}
129
130static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
131{
132 struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
133 unsigned int hwirq = irqd_to_hwirq(d);
134
135 dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
136
137 switch (type & IRQ_TYPE_SENSE_MASK) {
138 case IRQ_TYPE_LEVEL_HIGH:
139 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
140 false);
141 break;
142 case IRQ_TYPE_LEVEL_LOW:
143 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
144 false);
145 break;
146 case IRQ_TYPE_EDGE_RISING:
147 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
148 false);
149 break;
150 case IRQ_TYPE_EDGE_FALLING:
151 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
152 false);
153 break;
154 case IRQ_TYPE_EDGE_BOTH:
155 if (!p->config.has_both_edge_trigger)
156 return -EINVAL;
157 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
158 true);
159 break;
160 default:
161 return -EINVAL;
162 }
163 return 0;
164}
165
166static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
167{
168 struct gpio_rcar_priv *p = dev_id;
169 u32 pending;
170 unsigned int offset, irqs_handled = 0;
171
172 while ((pending = gpio_rcar_read(p, INTDT) &
173 gpio_rcar_read(p, INTMSK))) {
174 offset = __ffs(pending);
175 gpio_rcar_write(p, INTCLR, BIT(offset));
176 generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
177 irqs_handled++;
178 }
179
180 return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
181}
182
183static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip)
184{
185 return container_of(chip, struct gpio_rcar_priv, gpio_chip);
186}
187
188static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
189 unsigned int gpio,
190 bool output)
191{
192 struct gpio_rcar_priv *p = gpio_to_priv(chip);
193 unsigned long flags;
194
195 /* follow steps in the GPIO documentation for
196 * "Setting General Output Mode" and
197 * "Setting General Input Mode"
198 */
199
200 spin_lock_irqsave(&p->lock, flags);
201
202 /* Configure postive logic in POSNEG */
203 gpio_rcar_modify_bit(p, POSNEG, gpio, false);
204
205 /* Select "General Input/Output Mode" in IOINTSEL */
206 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
207
208 /* Select Input Mode or Output Mode in INOUTSEL */
209 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
210
211 spin_unlock_irqrestore(&p->lock, flags);
212}
213
214static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
215{
216 return pinctrl_request_gpio(chip->base + offset);
217}
218
219static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
220{
221 pinctrl_free_gpio(chip->base + offset);
222
223 /* Set the GPIO as an input to ensure that the next GPIO request won't
224 * drive the GPIO pin as an output.
225 */
226 gpio_rcar_config_general_input_output_mode(chip, offset, false);
227}
228
229static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
230{
231 gpio_rcar_config_general_input_output_mode(chip, offset, false);
232 return 0;
233}
234
235static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
236{
237 u32 bit = BIT(offset);
238
239 /* testing on r8a7790 shows that INDT does not show correct pin state
240 * when configured as output, so use OUTDT in case of output pins */
241 if (gpio_rcar_read(gpio_to_priv(chip), INOUTSEL) & bit)
242 return (int)(gpio_rcar_read(gpio_to_priv(chip), OUTDT) & bit);
243 else
244 return (int)(gpio_rcar_read(gpio_to_priv(chip), INDT) & bit);
245}
246
247static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
248{
249 struct gpio_rcar_priv *p = gpio_to_priv(chip);
250 unsigned long flags;
251
252 spin_lock_irqsave(&p->lock, flags);
253 gpio_rcar_modify_bit(p, OUTDT, offset, value);
254 spin_unlock_irqrestore(&p->lock, flags);
255}
256
257static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
258 int value)
259{
260 /* write GPIO value to output before selecting output mode of pin */
261 gpio_rcar_set(chip, offset, value);
262 gpio_rcar_config_general_input_output_mode(chip, offset, true);
263 return 0;
264}
265
266static int gpio_rcar_to_irq(struct gpio_chip *chip, unsigned offset)
267{
268 return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
269}
270
271static int gpio_rcar_irq_domain_map(struct irq_domain *h, unsigned int irq,
272 irq_hw_number_t hwirq)
273{
274 struct gpio_rcar_priv *p = h->host_data;
275
276 dev_dbg(&p->pdev->dev, "map hw irq = %d, irq = %d\n", (int)hwirq, irq);
277
278 irq_set_chip_data(irq, h->host_data);
279 irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq);
280 set_irq_flags(irq, IRQF_VALID); /* kill me now */
281 return 0;
282}
283
284static struct irq_domain_ops gpio_rcar_irq_domain_ops = {
285 .map = gpio_rcar_irq_domain_map,
286};
287
288struct gpio_rcar_info {
289 bool has_both_edge_trigger;
290};
291
292static const struct of_device_id gpio_rcar_of_table[] = {
293 {
294 .compatible = "renesas,gpio-r8a7790",
295 .data = (void *)&(const struct gpio_rcar_info) {
296 .has_both_edge_trigger = true,
297 },
298 }, {
299 .compatible = "renesas,gpio-r8a7791",
300 .data = (void *)&(const struct gpio_rcar_info) {
301 .has_both_edge_trigger = true,
302 },
303 }, {
304 .compatible = "renesas,gpio-rcar",
305 .data = (void *)&(const struct gpio_rcar_info) {
306 .has_both_edge_trigger = false,
307 },
308 }, {
309 /* Terminator */
310 },
311};
312
313MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
314
315static int gpio_rcar_parse_pdata(struct gpio_rcar_priv *p)
316{
317 struct gpio_rcar_config *pdata = dev_get_platdata(&p->pdev->dev);
318 struct device_node *np = p->pdev->dev.of_node;
319 struct of_phandle_args args;
320 int ret;
321
322 if (pdata) {
323 p->config = *pdata;
324 } else if (IS_ENABLED(CONFIG_OF) && np) {
325 const struct of_device_id *match;
326 const struct gpio_rcar_info *info;
327
328 match = of_match_node(gpio_rcar_of_table, np);
329 if (!match)
330 return -EINVAL;
331
332 info = match->data;
333
334 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
335 &args);
336 p->config.number_of_pins = ret == 0 ? args.args[2]
337 : RCAR_MAX_GPIO_PER_BANK;
338 p->config.gpio_base = -1;
339 p->config.has_both_edge_trigger = info->has_both_edge_trigger;
340 }
341
342 if (p->config.number_of_pins == 0 ||
343 p->config.number_of_pins > RCAR_MAX_GPIO_PER_BANK) {
344 dev_warn(&p->pdev->dev,
345 "Invalid number of gpio lines %u, using %u\n",
346 p->config.number_of_pins, RCAR_MAX_GPIO_PER_BANK);
347 p->config.number_of_pins = RCAR_MAX_GPIO_PER_BANK;
348 }
349
350 return 0;
351}
352
353static int gpio_rcar_probe(struct platform_device *pdev)
354{
355 struct gpio_rcar_priv *p;
356 struct resource *io, *irq;
357 struct gpio_chip *gpio_chip;
358 struct irq_chip *irq_chip;
359 struct device *dev = &pdev->dev;
360 const char *name = dev_name(dev);
361 int ret;
362
363 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
364 if (!p) {
365 dev_err(dev, "failed to allocate driver data\n");
366 ret = -ENOMEM;
367 goto err0;
368 }
369
370 p->pdev = pdev;
371 spin_lock_init(&p->lock);
372
373 /* Get device configuration from DT node or platform data. */
374 ret = gpio_rcar_parse_pdata(p);
375 if (ret < 0)
376 return ret;
377
378 platform_set_drvdata(pdev, p);
379
380 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
381 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
382
383 if (!io || !irq) {
384 dev_err(dev, "missing IRQ or IOMEM\n");
385 ret = -EINVAL;
386 goto err0;
387 }
388
389 p->base = devm_ioremap_nocache(dev, io->start, resource_size(io));
390 if (!p->base) {
391 dev_err(dev, "failed to remap I/O memory\n");
392 ret = -ENXIO;
393 goto err0;
394 }
395
396 gpio_chip = &p->gpio_chip;
397 gpio_chip->request = gpio_rcar_request;
398 gpio_chip->free = gpio_rcar_free;
399 gpio_chip->direction_input = gpio_rcar_direction_input;
400 gpio_chip->get = gpio_rcar_get;
401 gpio_chip->direction_output = gpio_rcar_direction_output;
402 gpio_chip->set = gpio_rcar_set;
403 gpio_chip->to_irq = gpio_rcar_to_irq;
404 gpio_chip->label = name;
405 gpio_chip->dev = dev;
406 gpio_chip->owner = THIS_MODULE;
407 gpio_chip->base = p->config.gpio_base;
408 gpio_chip->ngpio = p->config.number_of_pins;
409
410 irq_chip = &p->irq_chip;
411 irq_chip->name = name;
412 irq_chip->irq_mask = gpio_rcar_irq_disable;
413 irq_chip->irq_unmask = gpio_rcar_irq_enable;
414 irq_chip->irq_set_type = gpio_rcar_irq_set_type;
415 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED
416 | IRQCHIP_MASK_ON_SUSPEND;
417
418 p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
419 p->config.number_of_pins,
420 p->config.irq_base,
421 &gpio_rcar_irq_domain_ops, p);
422 if (!p->irq_domain) {
423 ret = -ENXIO;
424 dev_err(dev, "cannot initialize irq domain\n");
425 goto err0;
426 }
427
428 if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
429 IRQF_SHARED, name, p)) {
430 dev_err(dev, "failed to request IRQ\n");
431 ret = -ENOENT;
432 goto err1;
433 }
434
435 ret = gpiochip_add(gpio_chip);
436 if (ret) {
437 dev_err(dev, "failed to add GPIO controller\n");
438 goto err1;
439 }
440
441 dev_info(dev, "driving %d GPIOs\n", p->config.number_of_pins);
442
443 /* warn in case of mismatch if irq base is specified */
444 if (p->config.irq_base) {
445 ret = irq_find_mapping(p->irq_domain, 0);
446 if (p->config.irq_base != ret)
447 dev_warn(dev, "irq base mismatch (%u/%u)\n",
448 p->config.irq_base, ret);
449 }
450
451 if (p->config.pctl_name) {
452 ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0,
453 gpio_chip->base, gpio_chip->ngpio);
454 if (ret < 0)
455 dev_warn(dev, "failed to add pin range\n");
456 }
457
458 return 0;
459
460err1:
461 irq_domain_remove(p->irq_domain);
462err0:
463 return ret;
464}
465
466static int gpio_rcar_remove(struct platform_device *pdev)
467{
468 struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
469 int ret;
470
471 ret = gpiochip_remove(&p->gpio_chip);
472 if (ret)
473 return ret;
474
475 irq_domain_remove(p->irq_domain);
476 return 0;
477}
478
479static struct platform_driver gpio_rcar_device_driver = {
480 .probe = gpio_rcar_probe,
481 .remove = gpio_rcar_remove,
482 .driver = {
483 .name = "gpio_rcar",
484 .of_match_table = of_match_ptr(gpio_rcar_of_table),
485 }
486};
487
488module_platform_driver(gpio_rcar_device_driver);
489
490MODULE_AUTHOR("Magnus Damm");
491MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
492MODULE_LICENSE("GPL v2");
1/*
2 * Renesas R-Car GPIO Support
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/clk.h>
18#include <linux/err.h>
19#include <linux/gpio.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
23#include <linux/ioport.h>
24#include <linux/irq.h>
25#include <linux/module.h>
26#include <linux/of.h>
27#include <linux/pinctrl/consumer.h>
28#include <linux/platform_device.h>
29#include <linux/pm_runtime.h>
30#include <linux/spinlock.h>
31#include <linux/slab.h>
32
33struct gpio_rcar_priv {
34 void __iomem *base;
35 spinlock_t lock;
36 struct platform_device *pdev;
37 struct gpio_chip gpio_chip;
38 struct irq_chip irq_chip;
39 struct clk *clk;
40 unsigned int irq_parent;
41 bool has_both_edge_trigger;
42 bool needs_clk;
43};
44
45#define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
46#define INOUTSEL 0x04 /* General Input/Output Switching Register */
47#define OUTDT 0x08 /* General Output Register */
48#define INDT 0x0c /* General Input Register */
49#define INTDT 0x10 /* Interrupt Display Register */
50#define INTCLR 0x14 /* Interrupt Clear Register */
51#define INTMSK 0x18 /* Interrupt Mask Register */
52#define MSKCLR 0x1c /* Interrupt Mask Clear Register */
53#define POSNEG 0x20 /* Positive/Negative Logic Select Register */
54#define EDGLEVEL 0x24 /* Edge/level Select Register */
55#define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
56#define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
57
58#define RCAR_MAX_GPIO_PER_BANK 32
59
60static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
61{
62 return ioread32(p->base + offs);
63}
64
65static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
66 u32 value)
67{
68 iowrite32(value, p->base + offs);
69}
70
71static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
72 int bit, bool value)
73{
74 u32 tmp = gpio_rcar_read(p, offs);
75
76 if (value)
77 tmp |= BIT(bit);
78 else
79 tmp &= ~BIT(bit);
80
81 gpio_rcar_write(p, offs, tmp);
82}
83
84static void gpio_rcar_irq_disable(struct irq_data *d)
85{
86 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
87 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
88
89 gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
90}
91
92static void gpio_rcar_irq_enable(struct irq_data *d)
93{
94 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
95 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
96
97 gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
98}
99
100static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
101 unsigned int hwirq,
102 bool active_high_rising_edge,
103 bool level_trigger,
104 bool both)
105{
106 unsigned long flags;
107
108 /* follow steps in the GPIO documentation for
109 * "Setting Edge-Sensitive Interrupt Input Mode" and
110 * "Setting Level-Sensitive Interrupt Input Mode"
111 */
112
113 spin_lock_irqsave(&p->lock, flags);
114
115 /* Configure postive or negative logic in POSNEG */
116 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
117
118 /* Configure edge or level trigger in EDGLEVEL */
119 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
120
121 /* Select one edge or both edges in BOTHEDGE */
122 if (p->has_both_edge_trigger)
123 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
124
125 /* Select "Interrupt Input Mode" in IOINTSEL */
126 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
127
128 /* Write INTCLR in case of edge trigger */
129 if (!level_trigger)
130 gpio_rcar_write(p, INTCLR, BIT(hwirq));
131
132 spin_unlock_irqrestore(&p->lock, flags);
133}
134
135static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
136{
137 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
138 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
139 unsigned int hwirq = irqd_to_hwirq(d);
140
141 dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
142
143 switch (type & IRQ_TYPE_SENSE_MASK) {
144 case IRQ_TYPE_LEVEL_HIGH:
145 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
146 false);
147 break;
148 case IRQ_TYPE_LEVEL_LOW:
149 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
150 false);
151 break;
152 case IRQ_TYPE_EDGE_RISING:
153 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
154 false);
155 break;
156 case IRQ_TYPE_EDGE_FALLING:
157 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
158 false);
159 break;
160 case IRQ_TYPE_EDGE_BOTH:
161 if (!p->has_both_edge_trigger)
162 return -EINVAL;
163 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
164 true);
165 break;
166 default:
167 return -EINVAL;
168 }
169 return 0;
170}
171
172static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
173{
174 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
175 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
176 int error;
177
178 if (p->irq_parent) {
179 error = irq_set_irq_wake(p->irq_parent, on);
180 if (error) {
181 dev_dbg(&p->pdev->dev,
182 "irq %u doesn't support irq_set_wake\n",
183 p->irq_parent);
184 p->irq_parent = 0;
185 }
186 }
187
188 if (!p->clk)
189 return 0;
190
191 if (on)
192 clk_enable(p->clk);
193 else
194 clk_disable(p->clk);
195
196 return 0;
197}
198
199static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
200{
201 struct gpio_rcar_priv *p = dev_id;
202 u32 pending;
203 unsigned int offset, irqs_handled = 0;
204
205 while ((pending = gpio_rcar_read(p, INTDT) &
206 gpio_rcar_read(p, INTMSK))) {
207 offset = __ffs(pending);
208 gpio_rcar_write(p, INTCLR, BIT(offset));
209 generic_handle_irq(irq_find_mapping(p->gpio_chip.irqdomain,
210 offset));
211 irqs_handled++;
212 }
213
214 return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
215}
216
217static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
218 unsigned int gpio,
219 bool output)
220{
221 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
222 unsigned long flags;
223
224 /* follow steps in the GPIO documentation for
225 * "Setting General Output Mode" and
226 * "Setting General Input Mode"
227 */
228
229 spin_lock_irqsave(&p->lock, flags);
230
231 /* Configure postive logic in POSNEG */
232 gpio_rcar_modify_bit(p, POSNEG, gpio, false);
233
234 /* Select "General Input/Output Mode" in IOINTSEL */
235 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
236
237 /* Select Input Mode or Output Mode in INOUTSEL */
238 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
239
240 spin_unlock_irqrestore(&p->lock, flags);
241}
242
243static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
244{
245 return pinctrl_request_gpio(chip->base + offset);
246}
247
248static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
249{
250 pinctrl_free_gpio(chip->base + offset);
251
252 /*
253 * Set the GPIO as an input to ensure that the next GPIO request won't
254 * drive the GPIO pin as an output.
255 */
256 gpio_rcar_config_general_input_output_mode(chip, offset, false);
257}
258
259static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
260{
261 gpio_rcar_config_general_input_output_mode(chip, offset, false);
262 return 0;
263}
264
265static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
266{
267 u32 bit = BIT(offset);
268
269 /* testing on r8a7790 shows that INDT does not show correct pin state
270 * when configured as output, so use OUTDT in case of output pins */
271 if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
272 return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
273 else
274 return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
275}
276
277static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
278{
279 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
280 unsigned long flags;
281
282 spin_lock_irqsave(&p->lock, flags);
283 gpio_rcar_modify_bit(p, OUTDT, offset, value);
284 spin_unlock_irqrestore(&p->lock, flags);
285}
286
287static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
288 int value)
289{
290 /* write GPIO value to output before selecting output mode of pin */
291 gpio_rcar_set(chip, offset, value);
292 gpio_rcar_config_general_input_output_mode(chip, offset, true);
293 return 0;
294}
295
296struct gpio_rcar_info {
297 bool has_both_edge_trigger;
298 bool needs_clk;
299};
300
301static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
302 .has_both_edge_trigger = false,
303 .needs_clk = false,
304};
305
306static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
307 .has_both_edge_trigger = true,
308 .needs_clk = true,
309};
310
311static const struct of_device_id gpio_rcar_of_table[] = {
312 {
313 .compatible = "renesas,gpio-r8a7790",
314 .data = &gpio_rcar_info_gen2,
315 }, {
316 .compatible = "renesas,gpio-r8a7791",
317 .data = &gpio_rcar_info_gen2,
318 }, {
319 .compatible = "renesas,gpio-r8a7793",
320 .data = &gpio_rcar_info_gen2,
321 }, {
322 .compatible = "renesas,gpio-r8a7794",
323 .data = &gpio_rcar_info_gen2,
324 }, {
325 .compatible = "renesas,gpio-r8a7795",
326 /* Gen3 GPIO is identical to Gen2. */
327 .data = &gpio_rcar_info_gen2,
328 }, {
329 .compatible = "renesas,gpio-rcar",
330 .data = &gpio_rcar_info_gen1,
331 }, {
332 /* Terminator */
333 },
334};
335
336MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
337
338static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
339{
340 struct device_node *np = p->pdev->dev.of_node;
341 const struct of_device_id *match;
342 const struct gpio_rcar_info *info;
343 struct of_phandle_args args;
344 int ret;
345
346 match = of_match_node(gpio_rcar_of_table, np);
347 if (!match)
348 return -EINVAL;
349
350 info = match->data;
351
352 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
353 *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
354 p->has_both_edge_trigger = info->has_both_edge_trigger;
355 p->needs_clk = info->needs_clk;
356
357 if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
358 dev_warn(&p->pdev->dev,
359 "Invalid number of gpio lines %u, using %u\n", *npins,
360 RCAR_MAX_GPIO_PER_BANK);
361 *npins = RCAR_MAX_GPIO_PER_BANK;
362 }
363
364 return 0;
365}
366
367static int gpio_rcar_probe(struct platform_device *pdev)
368{
369 struct gpio_rcar_priv *p;
370 struct resource *io, *irq;
371 struct gpio_chip *gpio_chip;
372 struct irq_chip *irq_chip;
373 struct device *dev = &pdev->dev;
374 const char *name = dev_name(dev);
375 unsigned int npins;
376 int ret;
377
378 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
379 if (!p)
380 return -ENOMEM;
381
382 p->pdev = pdev;
383 spin_lock_init(&p->lock);
384
385 /* Get device configuration from DT node */
386 ret = gpio_rcar_parse_dt(p, &npins);
387 if (ret < 0)
388 return ret;
389
390 platform_set_drvdata(pdev, p);
391
392 p->clk = devm_clk_get(dev, NULL);
393 if (IS_ERR(p->clk)) {
394 if (p->needs_clk) {
395 dev_err(dev, "unable to get clock\n");
396 ret = PTR_ERR(p->clk);
397 goto err0;
398 }
399 p->clk = NULL;
400 }
401
402 pm_runtime_enable(dev);
403 pm_runtime_get_sync(dev);
404
405 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
406 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
407
408 if (!io || !irq) {
409 dev_err(dev, "missing IRQ or IOMEM\n");
410 ret = -EINVAL;
411 goto err0;
412 }
413
414 p->base = devm_ioremap_nocache(dev, io->start, resource_size(io));
415 if (!p->base) {
416 dev_err(dev, "failed to remap I/O memory\n");
417 ret = -ENXIO;
418 goto err0;
419 }
420
421 gpio_chip = &p->gpio_chip;
422 gpio_chip->request = gpio_rcar_request;
423 gpio_chip->free = gpio_rcar_free;
424 gpio_chip->direction_input = gpio_rcar_direction_input;
425 gpio_chip->get = gpio_rcar_get;
426 gpio_chip->direction_output = gpio_rcar_direction_output;
427 gpio_chip->set = gpio_rcar_set;
428 gpio_chip->label = name;
429 gpio_chip->parent = dev;
430 gpio_chip->owner = THIS_MODULE;
431 gpio_chip->base = -1;
432 gpio_chip->ngpio = npins;
433
434 irq_chip = &p->irq_chip;
435 irq_chip->name = name;
436 irq_chip->irq_mask = gpio_rcar_irq_disable;
437 irq_chip->irq_unmask = gpio_rcar_irq_enable;
438 irq_chip->irq_set_type = gpio_rcar_irq_set_type;
439 irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
440 irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
441
442 ret = gpiochip_add_data(gpio_chip, p);
443 if (ret) {
444 dev_err(dev, "failed to add GPIO controller\n");
445 goto err0;
446 }
447
448 ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
449 IRQ_TYPE_NONE);
450 if (ret) {
451 dev_err(dev, "cannot add irqchip\n");
452 goto err1;
453 }
454
455 p->irq_parent = irq->start;
456 if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
457 IRQF_SHARED, name, p)) {
458 dev_err(dev, "failed to request IRQ\n");
459 ret = -ENOENT;
460 goto err1;
461 }
462
463 dev_info(dev, "driving %d GPIOs\n", npins);
464
465 return 0;
466
467err1:
468 gpiochip_remove(gpio_chip);
469err0:
470 pm_runtime_put(dev);
471 pm_runtime_disable(dev);
472 return ret;
473}
474
475static int gpio_rcar_remove(struct platform_device *pdev)
476{
477 struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
478
479 gpiochip_remove(&p->gpio_chip);
480
481 pm_runtime_put(&pdev->dev);
482 pm_runtime_disable(&pdev->dev);
483 return 0;
484}
485
486static struct platform_driver gpio_rcar_device_driver = {
487 .probe = gpio_rcar_probe,
488 .remove = gpio_rcar_remove,
489 .driver = {
490 .name = "gpio_rcar",
491 .of_match_table = of_match_ptr(gpio_rcar_of_table),
492 }
493};
494
495module_platform_driver(gpio_rcar_device_driver);
496
497MODULE_AUTHOR("Magnus Damm");
498MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
499MODULE_LICENSE("GPL v2");