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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org)
7 */
8#ifndef __ASM_CMPXCHG_H
9#define __ASM_CMPXCHG_H
10
11#include <linux/bug.h>
12#include <linux/irqflags.h>
13#include <asm/war.h>
14
15static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
16{
17 __u32 retval;
18
19 smp_mb__before_llsc();
20
21 if (kernel_uses_llsc && R10000_LLSC_WAR) {
22 unsigned long dummy;
23
24 __asm__ __volatile__(
25 " .set arch=r4000 \n"
26 "1: ll %0, %3 # xchg_u32 \n"
27 " .set mips0 \n"
28 " move %2, %z4 \n"
29 " .set arch=r4000 \n"
30 " sc %2, %1 \n"
31 " beqzl %2, 1b \n"
32 " .set mips0 \n"
33 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
34 : "R" (*m), "Jr" (val)
35 : "memory");
36 } else if (kernel_uses_llsc) {
37 unsigned long dummy;
38
39 do {
40 __asm__ __volatile__(
41 " .set arch=r4000 \n"
42 " ll %0, %3 # xchg_u32 \n"
43 " .set mips0 \n"
44 " move %2, %z4 \n"
45 " .set arch=r4000 \n"
46 " sc %2, %1 \n"
47 " .set mips0 \n"
48 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
49 : "R" (*m), "Jr" (val)
50 : "memory");
51 } while (unlikely(!dummy));
52 } else {
53 unsigned long flags;
54
55 raw_local_irq_save(flags);
56 retval = *m;
57 *m = val;
58 raw_local_irq_restore(flags); /* implies memory barrier */
59 }
60
61 smp_llsc_mb();
62
63 return retval;
64}
65
66#ifdef CONFIG_64BIT
67static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
68{
69 __u64 retval;
70
71 smp_mb__before_llsc();
72
73 if (kernel_uses_llsc && R10000_LLSC_WAR) {
74 unsigned long dummy;
75
76 __asm__ __volatile__(
77 " .set arch=r4000 \n"
78 "1: lld %0, %3 # xchg_u64 \n"
79 " move %2, %z4 \n"
80 " scd %2, %1 \n"
81 " beqzl %2, 1b \n"
82 " .set mips0 \n"
83 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
84 : "R" (*m), "Jr" (val)
85 : "memory");
86 } else if (kernel_uses_llsc) {
87 unsigned long dummy;
88
89 do {
90 __asm__ __volatile__(
91 " .set arch=r4000 \n"
92 " lld %0, %3 # xchg_u64 \n"
93 " move %2, %z4 \n"
94 " scd %2, %1 \n"
95 " .set mips0 \n"
96 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
97 : "R" (*m), "Jr" (val)
98 : "memory");
99 } while (unlikely(!dummy));
100 } else {
101 unsigned long flags;
102
103 raw_local_irq_save(flags);
104 retval = *m;
105 *m = val;
106 raw_local_irq_restore(flags); /* implies memory barrier */
107 }
108
109 smp_llsc_mb();
110
111 return retval;
112}
113#else
114extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
115#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
116#endif
117
118static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
119{
120 switch (size) {
121 case 4:
122 return __xchg_u32(ptr, x);
123 case 8:
124 return __xchg_u64(ptr, x);
125 }
126
127 return x;
128}
129
130#define xchg(ptr, x) \
131({ \
132 BUILD_BUG_ON(sizeof(*(ptr)) & ~0xc); \
133 \
134 ((__typeof__(*(ptr))) \
135 __xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))); \
136})
137
138#define __HAVE_ARCH_CMPXCHG 1
139
140#define __cmpxchg_asm(ld, st, m, old, new) \
141({ \
142 __typeof(*(m)) __ret; \
143 \
144 if (kernel_uses_llsc && R10000_LLSC_WAR) { \
145 __asm__ __volatile__( \
146 " .set push \n" \
147 " .set noat \n" \
148 " .set arch=r4000 \n" \
149 "1: " ld " %0, %2 # __cmpxchg_asm \n" \
150 " bne %0, %z3, 2f \n" \
151 " .set mips0 \n" \
152 " move $1, %z4 \n" \
153 " .set arch=r4000 \n" \
154 " " st " $1, %1 \n" \
155 " beqzl $1, 1b \n" \
156 "2: \n" \
157 " .set pop \n" \
158 : "=&r" (__ret), "=R" (*m) \
159 : "R" (*m), "Jr" (old), "Jr" (new) \
160 : "memory"); \
161 } else if (kernel_uses_llsc) { \
162 __asm__ __volatile__( \
163 " .set push \n" \
164 " .set noat \n" \
165 " .set arch=r4000 \n" \
166 "1: " ld " %0, %2 # __cmpxchg_asm \n" \
167 " bne %0, %z3, 2f \n" \
168 " .set mips0 \n" \
169 " move $1, %z4 \n" \
170 " .set arch=r4000 \n" \
171 " " st " $1, %1 \n" \
172 " beqz $1, 1b \n" \
173 " .set pop \n" \
174 "2: \n" \
175 : "=&r" (__ret), "=R" (*m) \
176 : "R" (*m), "Jr" (old), "Jr" (new) \
177 : "memory"); \
178 } else { \
179 unsigned long __flags; \
180 \
181 raw_local_irq_save(__flags); \
182 __ret = *m; \
183 if (__ret == old) \
184 *m = new; \
185 raw_local_irq_restore(__flags); \
186 } \
187 \
188 __ret; \
189})
190
191/*
192 * This function doesn't exist, so you'll get a linker error
193 * if something tries to do an invalid cmpxchg().
194 */
195extern void __cmpxchg_called_with_bad_pointer(void);
196
197#define __cmpxchg(ptr, old, new, pre_barrier, post_barrier) \
198({ \
199 __typeof__(ptr) __ptr = (ptr); \
200 __typeof__(*(ptr)) __old = (old); \
201 __typeof__(*(ptr)) __new = (new); \
202 __typeof__(*(ptr)) __res = 0; \
203 \
204 pre_barrier; \
205 \
206 switch (sizeof(*(__ptr))) { \
207 case 4: \
208 __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); \
209 break; \
210 case 8: \
211 if (sizeof(long) == 8) { \
212 __res = __cmpxchg_asm("lld", "scd", __ptr, \
213 __old, __new); \
214 break; \
215 } \
216 default: \
217 __cmpxchg_called_with_bad_pointer(); \
218 break; \
219 } \
220 \
221 post_barrier; \
222 \
223 __res; \
224})
225
226#define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_mb__before_llsc(), smp_llsc_mb())
227#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new, , )
228
229#define cmpxchg64(ptr, o, n) \
230 ({ \
231 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
232 cmpxchg((ptr), (o), (n)); \
233 })
234
235#ifdef CONFIG_64BIT
236#define cmpxchg64_local(ptr, o, n) \
237 ({ \
238 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
239 cmpxchg_local((ptr), (o), (n)); \
240 })
241#else
242#include <asm-generic/cmpxchg-local.h>
243#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
244#endif
245
246#endif /* __ASM_CMPXCHG_H */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org)
7 */
8#ifndef __ASM_CMPXCHG_H
9#define __ASM_CMPXCHG_H
10
11#include <linux/bug.h>
12#include <linux/irqflags.h>
13#include <asm/compiler.h>
14#include <asm/war.h>
15
16static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
17{
18 __u32 retval;
19
20 smp_mb__before_llsc();
21
22 if (kernel_uses_llsc && R10000_LLSC_WAR) {
23 unsigned long dummy;
24
25 __asm__ __volatile__(
26 " .set arch=r4000 \n"
27 "1: ll %0, %3 # xchg_u32 \n"
28 " .set mips0 \n"
29 " move %2, %z4 \n"
30 " .set arch=r4000 \n"
31 " sc %2, %1 \n"
32 " beqzl %2, 1b \n"
33 " .set mips0 \n"
34 : "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m), "=&r" (dummy)
35 : GCC_OFF_SMALL_ASM() (*m), "Jr" (val)
36 : "memory");
37 } else if (kernel_uses_llsc) {
38 unsigned long dummy;
39
40 do {
41 __asm__ __volatile__(
42 " .set "MIPS_ISA_ARCH_LEVEL" \n"
43 " ll %0, %3 # xchg_u32 \n"
44 " .set mips0 \n"
45 " move %2, %z4 \n"
46 " .set "MIPS_ISA_ARCH_LEVEL" \n"
47 " sc %2, %1 \n"
48 " .set mips0 \n"
49 : "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m),
50 "=&r" (dummy)
51 : GCC_OFF_SMALL_ASM() (*m), "Jr" (val)
52 : "memory");
53 } while (unlikely(!dummy));
54 } else {
55 unsigned long flags;
56
57 raw_local_irq_save(flags);
58 retval = *m;
59 *m = val;
60 raw_local_irq_restore(flags); /* implies memory barrier */
61 }
62
63 smp_llsc_mb();
64
65 return retval;
66}
67
68#ifdef CONFIG_64BIT
69static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
70{
71 __u64 retval;
72
73 smp_mb__before_llsc();
74
75 if (kernel_uses_llsc && R10000_LLSC_WAR) {
76 unsigned long dummy;
77
78 __asm__ __volatile__(
79 " .set arch=r4000 \n"
80 "1: lld %0, %3 # xchg_u64 \n"
81 " move %2, %z4 \n"
82 " scd %2, %1 \n"
83 " beqzl %2, 1b \n"
84 " .set mips0 \n"
85 : "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m), "=&r" (dummy)
86 : GCC_OFF_SMALL_ASM() (*m), "Jr" (val)
87 : "memory");
88 } else if (kernel_uses_llsc) {
89 unsigned long dummy;
90
91 do {
92 __asm__ __volatile__(
93 " .set "MIPS_ISA_ARCH_LEVEL" \n"
94 " lld %0, %3 # xchg_u64 \n"
95 " move %2, %z4 \n"
96 " scd %2, %1 \n"
97 " .set mips0 \n"
98 : "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m),
99 "=&r" (dummy)
100 : GCC_OFF_SMALL_ASM() (*m), "Jr" (val)
101 : "memory");
102 } while (unlikely(!dummy));
103 } else {
104 unsigned long flags;
105
106 raw_local_irq_save(flags);
107 retval = *m;
108 *m = val;
109 raw_local_irq_restore(flags); /* implies memory barrier */
110 }
111
112 smp_llsc_mb();
113
114 return retval;
115}
116#else
117extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
118#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
119#endif
120
121static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
122{
123 switch (size) {
124 case 4:
125 return __xchg_u32(ptr, x);
126 case 8:
127 return __xchg_u64(ptr, x);
128 }
129
130 return x;
131}
132
133#define xchg(ptr, x) \
134({ \
135 BUILD_BUG_ON(sizeof(*(ptr)) & ~0xc); \
136 \
137 ((__typeof__(*(ptr))) \
138 __xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))); \
139})
140
141#define __cmpxchg_asm(ld, st, m, old, new) \
142({ \
143 __typeof(*(m)) __ret; \
144 \
145 if (kernel_uses_llsc && R10000_LLSC_WAR) { \
146 __asm__ __volatile__( \
147 " .set push \n" \
148 " .set noat \n" \
149 " .set arch=r4000 \n" \
150 "1: " ld " %0, %2 # __cmpxchg_asm \n" \
151 " bne %0, %z3, 2f \n" \
152 " .set mips0 \n" \
153 " move $1, %z4 \n" \
154 " .set arch=r4000 \n" \
155 " " st " $1, %1 \n" \
156 " beqzl $1, 1b \n" \
157 "2: \n" \
158 " .set pop \n" \
159 : "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \
160 : GCC_OFF_SMALL_ASM() (*m), "Jr" (old), "Jr" (new) \
161 : "memory"); \
162 } else if (kernel_uses_llsc) { \
163 __asm__ __volatile__( \
164 " .set push \n" \
165 " .set noat \n" \
166 " .set "MIPS_ISA_ARCH_LEVEL" \n" \
167 "1: " ld " %0, %2 # __cmpxchg_asm \n" \
168 " bne %0, %z3, 2f \n" \
169 " .set mips0 \n" \
170 " move $1, %z4 \n" \
171 " .set "MIPS_ISA_ARCH_LEVEL" \n" \
172 " " st " $1, %1 \n" \
173 " beqz $1, 1b \n" \
174 " .set pop \n" \
175 "2: \n" \
176 : "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \
177 : GCC_OFF_SMALL_ASM() (*m), "Jr" (old), "Jr" (new) \
178 : "memory"); \
179 } else { \
180 unsigned long __flags; \
181 \
182 raw_local_irq_save(__flags); \
183 __ret = *m; \
184 if (__ret == old) \
185 *m = new; \
186 raw_local_irq_restore(__flags); \
187 } \
188 \
189 __ret; \
190})
191
192/*
193 * This function doesn't exist, so you'll get a linker error
194 * if something tries to do an invalid cmpxchg().
195 */
196extern void __cmpxchg_called_with_bad_pointer(void);
197
198#define __cmpxchg(ptr, old, new, pre_barrier, post_barrier) \
199({ \
200 __typeof__(ptr) __ptr = (ptr); \
201 __typeof__(*(ptr)) __old = (old); \
202 __typeof__(*(ptr)) __new = (new); \
203 __typeof__(*(ptr)) __res = 0; \
204 \
205 pre_barrier; \
206 \
207 switch (sizeof(*(__ptr))) { \
208 case 4: \
209 __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); \
210 break; \
211 case 8: \
212 if (sizeof(long) == 8) { \
213 __res = __cmpxchg_asm("lld", "scd", __ptr, \
214 __old, __new); \
215 break; \
216 } \
217 default: \
218 __cmpxchg_called_with_bad_pointer(); \
219 break; \
220 } \
221 \
222 post_barrier; \
223 \
224 __res; \
225})
226
227#define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_mb__before_llsc(), smp_llsc_mb())
228#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new, , )
229
230#ifdef CONFIG_64BIT
231#define cmpxchg64_local(ptr, o, n) \
232 ({ \
233 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
234 cmpxchg_local((ptr), (o), (n)); \
235 })
236
237#define cmpxchg64(ptr, o, n) \
238 ({ \
239 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
240 cmpxchg((ptr), (o), (n)); \
241 })
242#else
243#include <asm-generic/cmpxchg-local.h>
244#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
245#define cmpxchg64(ptr, o, n) cmpxchg64_local((ptr), (o), (n))
246#endif
247
248#endif /* __ASM_CMPXCHG_H */