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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org)
7 */
8#ifndef __ASM_CMPXCHG_H
9#define __ASM_CMPXCHG_H
10
11#include <linux/bug.h>
12#include <linux/irqflags.h>
13#include <asm/war.h>
14
15static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
16{
17 __u32 retval;
18
19 smp_mb__before_llsc();
20
21 if (kernel_uses_llsc && R10000_LLSC_WAR) {
22 unsigned long dummy;
23
24 __asm__ __volatile__(
25 " .set arch=r4000 \n"
26 "1: ll %0, %3 # xchg_u32 \n"
27 " .set mips0 \n"
28 " move %2, %z4 \n"
29 " .set arch=r4000 \n"
30 " sc %2, %1 \n"
31 " beqzl %2, 1b \n"
32 " .set mips0 \n"
33 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
34 : "R" (*m), "Jr" (val)
35 : "memory");
36 } else if (kernel_uses_llsc) {
37 unsigned long dummy;
38
39 do {
40 __asm__ __volatile__(
41 " .set arch=r4000 \n"
42 " ll %0, %3 # xchg_u32 \n"
43 " .set mips0 \n"
44 " move %2, %z4 \n"
45 " .set arch=r4000 \n"
46 " sc %2, %1 \n"
47 " .set mips0 \n"
48 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
49 : "R" (*m), "Jr" (val)
50 : "memory");
51 } while (unlikely(!dummy));
52 } else {
53 unsigned long flags;
54
55 raw_local_irq_save(flags);
56 retval = *m;
57 *m = val;
58 raw_local_irq_restore(flags); /* implies memory barrier */
59 }
60
61 smp_llsc_mb();
62
63 return retval;
64}
65
66#ifdef CONFIG_64BIT
67static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
68{
69 __u64 retval;
70
71 smp_mb__before_llsc();
72
73 if (kernel_uses_llsc && R10000_LLSC_WAR) {
74 unsigned long dummy;
75
76 __asm__ __volatile__(
77 " .set arch=r4000 \n"
78 "1: lld %0, %3 # xchg_u64 \n"
79 " move %2, %z4 \n"
80 " scd %2, %1 \n"
81 " beqzl %2, 1b \n"
82 " .set mips0 \n"
83 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
84 : "R" (*m), "Jr" (val)
85 : "memory");
86 } else if (kernel_uses_llsc) {
87 unsigned long dummy;
88
89 do {
90 __asm__ __volatile__(
91 " .set arch=r4000 \n"
92 " lld %0, %3 # xchg_u64 \n"
93 " move %2, %z4 \n"
94 " scd %2, %1 \n"
95 " .set mips0 \n"
96 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
97 : "R" (*m), "Jr" (val)
98 : "memory");
99 } while (unlikely(!dummy));
100 } else {
101 unsigned long flags;
102
103 raw_local_irq_save(flags);
104 retval = *m;
105 *m = val;
106 raw_local_irq_restore(flags); /* implies memory barrier */
107 }
108
109 smp_llsc_mb();
110
111 return retval;
112}
113#else
114extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
115#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
116#endif
117
118static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
119{
120 switch (size) {
121 case 4:
122 return __xchg_u32(ptr, x);
123 case 8:
124 return __xchg_u64(ptr, x);
125 }
126
127 return x;
128}
129
130#define xchg(ptr, x) \
131({ \
132 BUILD_BUG_ON(sizeof(*(ptr)) & ~0xc); \
133 \
134 ((__typeof__(*(ptr))) \
135 __xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))); \
136})
137
138#define __HAVE_ARCH_CMPXCHG 1
139
140#define __cmpxchg_asm(ld, st, m, old, new) \
141({ \
142 __typeof(*(m)) __ret; \
143 \
144 if (kernel_uses_llsc && R10000_LLSC_WAR) { \
145 __asm__ __volatile__( \
146 " .set push \n" \
147 " .set noat \n" \
148 " .set arch=r4000 \n" \
149 "1: " ld " %0, %2 # __cmpxchg_asm \n" \
150 " bne %0, %z3, 2f \n" \
151 " .set mips0 \n" \
152 " move $1, %z4 \n" \
153 " .set arch=r4000 \n" \
154 " " st " $1, %1 \n" \
155 " beqzl $1, 1b \n" \
156 "2: \n" \
157 " .set pop \n" \
158 : "=&r" (__ret), "=R" (*m) \
159 : "R" (*m), "Jr" (old), "Jr" (new) \
160 : "memory"); \
161 } else if (kernel_uses_llsc) { \
162 __asm__ __volatile__( \
163 " .set push \n" \
164 " .set noat \n" \
165 " .set arch=r4000 \n" \
166 "1: " ld " %0, %2 # __cmpxchg_asm \n" \
167 " bne %0, %z3, 2f \n" \
168 " .set mips0 \n" \
169 " move $1, %z4 \n" \
170 " .set arch=r4000 \n" \
171 " " st " $1, %1 \n" \
172 " beqz $1, 1b \n" \
173 " .set pop \n" \
174 "2: \n" \
175 : "=&r" (__ret), "=R" (*m) \
176 : "R" (*m), "Jr" (old), "Jr" (new) \
177 : "memory"); \
178 } else { \
179 unsigned long __flags; \
180 \
181 raw_local_irq_save(__flags); \
182 __ret = *m; \
183 if (__ret == old) \
184 *m = new; \
185 raw_local_irq_restore(__flags); \
186 } \
187 \
188 __ret; \
189})
190
191/*
192 * This function doesn't exist, so you'll get a linker error
193 * if something tries to do an invalid cmpxchg().
194 */
195extern void __cmpxchg_called_with_bad_pointer(void);
196
197#define __cmpxchg(ptr, old, new, pre_barrier, post_barrier) \
198({ \
199 __typeof__(ptr) __ptr = (ptr); \
200 __typeof__(*(ptr)) __old = (old); \
201 __typeof__(*(ptr)) __new = (new); \
202 __typeof__(*(ptr)) __res = 0; \
203 \
204 pre_barrier; \
205 \
206 switch (sizeof(*(__ptr))) { \
207 case 4: \
208 __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); \
209 break; \
210 case 8: \
211 if (sizeof(long) == 8) { \
212 __res = __cmpxchg_asm("lld", "scd", __ptr, \
213 __old, __new); \
214 break; \
215 } \
216 default: \
217 __cmpxchg_called_with_bad_pointer(); \
218 break; \
219 } \
220 \
221 post_barrier; \
222 \
223 __res; \
224})
225
226#define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_mb__before_llsc(), smp_llsc_mb())
227#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new, , )
228
229#define cmpxchg64(ptr, o, n) \
230 ({ \
231 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
232 cmpxchg((ptr), (o), (n)); \
233 })
234
235#ifdef CONFIG_64BIT
236#define cmpxchg64_local(ptr, o, n) \
237 ({ \
238 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
239 cmpxchg_local((ptr), (o), (n)); \
240 })
241#else
242#include <asm-generic/cmpxchg-local.h>
243#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
244#endif
245
246#endif /* __ASM_CMPXCHG_H */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org)
7 */
8#ifndef __ASM_CMPXCHG_H
9#define __ASM_CMPXCHG_H
10
11#include <linux/bug.h>
12#include <linux/irqflags.h>
13#include <asm/compiler.h>
14#include <asm/war.h>
15
16/*
17 * Using a branch-likely instruction to check the result of an sc instruction
18 * works around a bug present in R10000 CPUs prior to revision 3.0 that could
19 * cause ll-sc sequences to execute non-atomically.
20 */
21#if R10000_LLSC_WAR
22# define __scbeqz "beqzl"
23#else
24# define __scbeqz "beqz"
25#endif
26
27/*
28 * These functions doesn't exist, so if they are called you'll either:
29 *
30 * - Get an error at compile-time due to __compiletime_error, if supported by
31 * your compiler.
32 *
33 * or:
34 *
35 * - Get an error at link-time due to the call to the missing function.
36 */
37extern unsigned long __cmpxchg_called_with_bad_pointer(void)
38 __compiletime_error("Bad argument size for cmpxchg");
39extern unsigned long __xchg_called_with_bad_pointer(void)
40 __compiletime_error("Bad argument size for xchg");
41
42#define __xchg_asm(ld, st, m, val) \
43({ \
44 __typeof(*(m)) __ret; \
45 \
46 if (kernel_uses_llsc) { \
47 __asm__ __volatile__( \
48 " .set push \n" \
49 " .set noat \n" \
50 " .set " MIPS_ISA_ARCH_LEVEL " \n" \
51 "1: " ld " %0, %2 # __xchg_asm \n" \
52 " .set mips0 \n" \
53 " move $1, %z3 \n" \
54 " .set " MIPS_ISA_ARCH_LEVEL " \n" \
55 " " st " $1, %1 \n" \
56 "\t" __scbeqz " $1, 1b \n" \
57 " .set pop \n" \
58 : "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \
59 : GCC_OFF_SMALL_ASM() (*m), "Jr" (val) \
60 : "memory"); \
61 } else { \
62 unsigned long __flags; \
63 \
64 raw_local_irq_save(__flags); \
65 __ret = *m; \
66 *m = val; \
67 raw_local_irq_restore(__flags); \
68 } \
69 \
70 __ret; \
71})
72
73extern unsigned long __xchg_small(volatile void *ptr, unsigned long val,
74 unsigned int size);
75
76static inline unsigned long __xchg(volatile void *ptr, unsigned long x,
77 int size)
78{
79 switch (size) {
80 case 1:
81 case 2:
82 return __xchg_small(ptr, x, size);
83
84 case 4:
85 return __xchg_asm("ll", "sc", (volatile u32 *)ptr, x);
86
87 case 8:
88 if (!IS_ENABLED(CONFIG_64BIT))
89 return __xchg_called_with_bad_pointer();
90
91 return __xchg_asm("lld", "scd", (volatile u64 *)ptr, x);
92
93 default:
94 return __xchg_called_with_bad_pointer();
95 }
96}
97
98#define xchg(ptr, x) \
99({ \
100 __typeof__(*(ptr)) __res; \
101 \
102 smp_mb__before_llsc(); \
103 \
104 __res = (__typeof__(*(ptr))) \
105 __xchg((ptr), (unsigned long)(x), sizeof(*(ptr))); \
106 \
107 smp_llsc_mb(); \
108 \
109 __res; \
110})
111
112#define __cmpxchg_asm(ld, st, m, old, new) \
113({ \
114 __typeof(*(m)) __ret; \
115 \
116 if (kernel_uses_llsc) { \
117 __asm__ __volatile__( \
118 " .set push \n" \
119 " .set noat \n" \
120 " .set "MIPS_ISA_ARCH_LEVEL" \n" \
121 "1: " ld " %0, %2 # __cmpxchg_asm \n" \
122 " bne %0, %z3, 2f \n" \
123 " .set mips0 \n" \
124 " move $1, %z4 \n" \
125 " .set "MIPS_ISA_ARCH_LEVEL" \n" \
126 " " st " $1, %1 \n" \
127 "\t" __scbeqz " $1, 1b \n" \
128 " .set pop \n" \
129 "2: \n" \
130 : "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \
131 : GCC_OFF_SMALL_ASM() (*m), "Jr" (old), "Jr" (new) \
132 : "memory"); \
133 } else { \
134 unsigned long __flags; \
135 \
136 raw_local_irq_save(__flags); \
137 __ret = *m; \
138 if (__ret == old) \
139 *m = new; \
140 raw_local_irq_restore(__flags); \
141 } \
142 \
143 __ret; \
144})
145
146extern unsigned long __cmpxchg_small(volatile void *ptr, unsigned long old,
147 unsigned long new, unsigned int size);
148
149static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
150 unsigned long new, unsigned int size)
151{
152 switch (size) {
153 case 1:
154 case 2:
155 return __cmpxchg_small(ptr, old, new, size);
156
157 case 4:
158 return __cmpxchg_asm("ll", "sc", (volatile u32 *)ptr,
159 (u32)old, new);
160
161 case 8:
162 /* lld/scd are only available for MIPS64 */
163 if (!IS_ENABLED(CONFIG_64BIT))
164 return __cmpxchg_called_with_bad_pointer();
165
166 return __cmpxchg_asm("lld", "scd", (volatile u64 *)ptr,
167 (u64)old, new);
168
169 default:
170 return __cmpxchg_called_with_bad_pointer();
171 }
172}
173
174#define cmpxchg_local(ptr, old, new) \
175 ((__typeof__(*(ptr))) \
176 __cmpxchg((ptr), \
177 (unsigned long)(__typeof__(*(ptr)))(old), \
178 (unsigned long)(__typeof__(*(ptr)))(new), \
179 sizeof(*(ptr))))
180
181#define cmpxchg(ptr, old, new) \
182({ \
183 __typeof__(*(ptr)) __res; \
184 \
185 smp_mb__before_llsc(); \
186 __res = cmpxchg_local((ptr), (old), (new)); \
187 smp_llsc_mb(); \
188 \
189 __res; \
190})
191
192#ifdef CONFIG_64BIT
193#define cmpxchg64_local(ptr, o, n) \
194 ({ \
195 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
196 cmpxchg_local((ptr), (o), (n)); \
197 })
198
199#define cmpxchg64(ptr, o, n) \
200 ({ \
201 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
202 cmpxchg((ptr), (o), (n)); \
203 })
204#else
205#include <asm-generic/cmpxchg-local.h>
206#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
207#ifndef CONFIG_SMP
208#define cmpxchg64(ptr, o, n) cmpxchg64_local((ptr), (o), (n))
209#endif
210#endif
211
212#undef __scbeqz
213
214#endif /* __ASM_CMPXCHG_H */