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1/*
2 * DMA Engine test module
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 * Copyright (C) 2013 Intel Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13#include <linux/delay.h>
14#include <linux/dma-mapping.h>
15#include <linux/dmaengine.h>
16#include <linux/freezer.h>
17#include <linux/init.h>
18#include <linux/kthread.h>
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/random.h>
22#include <linux/slab.h>
23#include <linux/wait.h>
24
25static unsigned int test_buf_size = 16384;
26module_param(test_buf_size, uint, S_IRUGO | S_IWUSR);
27MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
28
29static char test_channel[20];
30module_param_string(channel, test_channel, sizeof(test_channel),
31 S_IRUGO | S_IWUSR);
32MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)");
33
34static char test_device[32];
35module_param_string(device, test_device, sizeof(test_device),
36 S_IRUGO | S_IWUSR);
37MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
38
39static unsigned int threads_per_chan = 1;
40module_param(threads_per_chan, uint, S_IRUGO | S_IWUSR);
41MODULE_PARM_DESC(threads_per_chan,
42 "Number of threads to start per channel (default: 1)");
43
44static unsigned int max_channels;
45module_param(max_channels, uint, S_IRUGO | S_IWUSR);
46MODULE_PARM_DESC(max_channels,
47 "Maximum number of channels to use (default: all)");
48
49static unsigned int iterations;
50module_param(iterations, uint, S_IRUGO | S_IWUSR);
51MODULE_PARM_DESC(iterations,
52 "Iterations before stopping test (default: infinite)");
53
54static unsigned int xor_sources = 3;
55module_param(xor_sources, uint, S_IRUGO | S_IWUSR);
56MODULE_PARM_DESC(xor_sources,
57 "Number of xor source buffers (default: 3)");
58
59static unsigned int pq_sources = 3;
60module_param(pq_sources, uint, S_IRUGO | S_IWUSR);
61MODULE_PARM_DESC(pq_sources,
62 "Number of p+q source buffers (default: 3)");
63
64static int timeout = 3000;
65module_param(timeout, uint, S_IRUGO | S_IWUSR);
66MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
67 "Pass -1 for infinite timeout");
68
69static bool noverify;
70module_param(noverify, bool, S_IRUGO | S_IWUSR);
71MODULE_PARM_DESC(noverify, "Disable random data setup and verification");
72
73static bool verbose;
74module_param(verbose, bool, S_IRUGO | S_IWUSR);
75MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)");
76
77/**
78 * struct dmatest_params - test parameters.
79 * @buf_size: size of the memcpy test buffer
80 * @channel: bus ID of the channel to test
81 * @device: bus ID of the DMA Engine to test
82 * @threads_per_chan: number of threads to start per channel
83 * @max_channels: maximum number of channels to use
84 * @iterations: iterations before stopping test
85 * @xor_sources: number of xor source buffers
86 * @pq_sources: number of p+q source buffers
87 * @timeout: transfer timeout in msec, -1 for infinite timeout
88 */
89struct dmatest_params {
90 unsigned int buf_size;
91 char channel[20];
92 char device[32];
93 unsigned int threads_per_chan;
94 unsigned int max_channels;
95 unsigned int iterations;
96 unsigned int xor_sources;
97 unsigned int pq_sources;
98 int timeout;
99 bool noverify;
100};
101
102/**
103 * struct dmatest_info - test information.
104 * @params: test parameters
105 * @lock: access protection to the fields of this structure
106 */
107static struct dmatest_info {
108 /* Test parameters */
109 struct dmatest_params params;
110
111 /* Internal state */
112 struct list_head channels;
113 unsigned int nr_channels;
114 struct mutex lock;
115 bool did_init;
116} test_info = {
117 .channels = LIST_HEAD_INIT(test_info.channels),
118 .lock = __MUTEX_INITIALIZER(test_info.lock),
119};
120
121static int dmatest_run_set(const char *val, const struct kernel_param *kp);
122static int dmatest_run_get(char *val, const struct kernel_param *kp);
123static struct kernel_param_ops run_ops = {
124 .set = dmatest_run_set,
125 .get = dmatest_run_get,
126};
127static bool dmatest_run;
128module_param_cb(run, &run_ops, &dmatest_run, S_IRUGO | S_IWUSR);
129MODULE_PARM_DESC(run, "Run the test (default: false)");
130
131/* Maximum amount of mismatched bytes in buffer to print */
132#define MAX_ERROR_COUNT 32
133
134/*
135 * Initialization patterns. All bytes in the source buffer has bit 7
136 * set, all bytes in the destination buffer has bit 7 cleared.
137 *
138 * Bit 6 is set for all bytes which are to be copied by the DMA
139 * engine. Bit 5 is set for all bytes which are to be overwritten by
140 * the DMA engine.
141 *
142 * The remaining bits are the inverse of a counter which increments by
143 * one for each byte address.
144 */
145#define PATTERN_SRC 0x80
146#define PATTERN_DST 0x00
147#define PATTERN_COPY 0x40
148#define PATTERN_OVERWRITE 0x20
149#define PATTERN_COUNT_MASK 0x1f
150
151struct dmatest_thread {
152 struct list_head node;
153 struct dmatest_info *info;
154 struct task_struct *task;
155 struct dma_chan *chan;
156 u8 **srcs;
157 u8 **dsts;
158 enum dma_transaction_type type;
159 bool done;
160};
161
162struct dmatest_chan {
163 struct list_head node;
164 struct dma_chan *chan;
165 struct list_head threads;
166};
167
168static DECLARE_WAIT_QUEUE_HEAD(thread_wait);
169static bool wait;
170
171static bool is_threaded_test_run(struct dmatest_info *info)
172{
173 struct dmatest_chan *dtc;
174
175 list_for_each_entry(dtc, &info->channels, node) {
176 struct dmatest_thread *thread;
177
178 list_for_each_entry(thread, &dtc->threads, node) {
179 if (!thread->done)
180 return true;
181 }
182 }
183
184 return false;
185}
186
187static int dmatest_wait_get(char *val, const struct kernel_param *kp)
188{
189 struct dmatest_info *info = &test_info;
190 struct dmatest_params *params = &info->params;
191
192 if (params->iterations)
193 wait_event(thread_wait, !is_threaded_test_run(info));
194 wait = true;
195 return param_get_bool(val, kp);
196}
197
198static struct kernel_param_ops wait_ops = {
199 .get = dmatest_wait_get,
200 .set = param_set_bool,
201};
202module_param_cb(wait, &wait_ops, &wait, S_IRUGO);
203MODULE_PARM_DESC(wait, "Wait for tests to complete (default: false)");
204
205static bool dmatest_match_channel(struct dmatest_params *params,
206 struct dma_chan *chan)
207{
208 if (params->channel[0] == '\0')
209 return true;
210 return strcmp(dma_chan_name(chan), params->channel) == 0;
211}
212
213static bool dmatest_match_device(struct dmatest_params *params,
214 struct dma_device *device)
215{
216 if (params->device[0] == '\0')
217 return true;
218 return strcmp(dev_name(device->dev), params->device) == 0;
219}
220
221static unsigned long dmatest_random(void)
222{
223 unsigned long buf;
224
225 prandom_bytes(&buf, sizeof(buf));
226 return buf;
227}
228
229static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len,
230 unsigned int buf_size)
231{
232 unsigned int i;
233 u8 *buf;
234
235 for (; (buf = *bufs); bufs++) {
236 for (i = 0; i < start; i++)
237 buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
238 for ( ; i < start + len; i++)
239 buf[i] = PATTERN_SRC | PATTERN_COPY
240 | (~i & PATTERN_COUNT_MASK);
241 for ( ; i < buf_size; i++)
242 buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
243 buf++;
244 }
245}
246
247static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len,
248 unsigned int buf_size)
249{
250 unsigned int i;
251 u8 *buf;
252
253 for (; (buf = *bufs); bufs++) {
254 for (i = 0; i < start; i++)
255 buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
256 for ( ; i < start + len; i++)
257 buf[i] = PATTERN_DST | PATTERN_OVERWRITE
258 | (~i & PATTERN_COUNT_MASK);
259 for ( ; i < buf_size; i++)
260 buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
261 }
262}
263
264static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
265 unsigned int counter, bool is_srcbuf)
266{
267 u8 diff = actual ^ pattern;
268 u8 expected = pattern | (~counter & PATTERN_COUNT_MASK);
269 const char *thread_name = current->comm;
270
271 if (is_srcbuf)
272 pr_warn("%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n",
273 thread_name, index, expected, actual);
274 else if ((pattern & PATTERN_COPY)
275 && (diff & (PATTERN_COPY | PATTERN_OVERWRITE)))
276 pr_warn("%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n",
277 thread_name, index, expected, actual);
278 else if (diff & PATTERN_SRC)
279 pr_warn("%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n",
280 thread_name, index, expected, actual);
281 else
282 pr_warn("%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n",
283 thread_name, index, expected, actual);
284}
285
286static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
287 unsigned int end, unsigned int counter, u8 pattern,
288 bool is_srcbuf)
289{
290 unsigned int i;
291 unsigned int error_count = 0;
292 u8 actual;
293 u8 expected;
294 u8 *buf;
295 unsigned int counter_orig = counter;
296
297 for (; (buf = *bufs); bufs++) {
298 counter = counter_orig;
299 for (i = start; i < end; i++) {
300 actual = buf[i];
301 expected = pattern | (~counter & PATTERN_COUNT_MASK);
302 if (actual != expected) {
303 if (error_count < MAX_ERROR_COUNT)
304 dmatest_mismatch(actual, pattern, i,
305 counter, is_srcbuf);
306 error_count++;
307 }
308 counter++;
309 }
310 }
311
312 if (error_count > MAX_ERROR_COUNT)
313 pr_warn("%s: %u errors suppressed\n",
314 current->comm, error_count - MAX_ERROR_COUNT);
315
316 return error_count;
317}
318
319/* poor man's completion - we want to use wait_event_freezable() on it */
320struct dmatest_done {
321 bool done;
322 wait_queue_head_t *wait;
323};
324
325static void dmatest_callback(void *arg)
326{
327 struct dmatest_done *done = arg;
328
329 done->done = true;
330 wake_up_all(done->wait);
331}
332
333static unsigned int min_odd(unsigned int x, unsigned int y)
334{
335 unsigned int val = min(x, y);
336
337 return val % 2 ? val : val - 1;
338}
339
340static void result(const char *err, unsigned int n, unsigned int src_off,
341 unsigned int dst_off, unsigned int len, unsigned long data)
342{
343 pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
344 current->comm, n, err, src_off, dst_off, len, data);
345}
346
347static void dbg_result(const char *err, unsigned int n, unsigned int src_off,
348 unsigned int dst_off, unsigned int len,
349 unsigned long data)
350{
351 pr_debug("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
352 current->comm, n, err, src_off, dst_off, len, data);
353}
354
355#define verbose_result(err, n, src_off, dst_off, len, data) ({ \
356 if (verbose) \
357 result(err, n, src_off, dst_off, len, data); \
358 else \
359 dbg_result(err, n, src_off, dst_off, len, data); \
360})
361
362static unsigned long long dmatest_persec(s64 runtime, unsigned int val)
363{
364 unsigned long long per_sec = 1000000;
365
366 if (runtime <= 0)
367 return 0;
368
369 /* drop precision until runtime is 32-bits */
370 while (runtime > UINT_MAX) {
371 runtime >>= 1;
372 per_sec <<= 1;
373 }
374
375 per_sec *= val;
376 do_div(per_sec, runtime);
377 return per_sec;
378}
379
380static unsigned long long dmatest_KBs(s64 runtime, unsigned long long len)
381{
382 return dmatest_persec(runtime, len >> 10);
383}
384
385/*
386 * This function repeatedly tests DMA transfers of various lengths and
387 * offsets for a given operation type until it is told to exit by
388 * kthread_stop(). There may be multiple threads running this function
389 * in parallel for a single channel, and there may be multiple channels
390 * being tested in parallel.
391 *
392 * Before each test, the source and destination buffer is initialized
393 * with a known pattern. This pattern is different depending on
394 * whether it's in an area which is supposed to be copied or
395 * overwritten, and different in the source and destination buffers.
396 * So if the DMA engine doesn't copy exactly what we tell it to copy,
397 * we'll notice.
398 */
399static int dmatest_func(void *data)
400{
401 DECLARE_WAIT_QUEUE_HEAD_ONSTACK(done_wait);
402 struct dmatest_thread *thread = data;
403 struct dmatest_done done = { .wait = &done_wait };
404 struct dmatest_info *info;
405 struct dmatest_params *params;
406 struct dma_chan *chan;
407 struct dma_device *dev;
408 unsigned int src_off, dst_off, len;
409 unsigned int error_count;
410 unsigned int failed_tests = 0;
411 unsigned int total_tests = 0;
412 dma_cookie_t cookie;
413 enum dma_status status;
414 enum dma_ctrl_flags flags;
415 u8 *pq_coefs = NULL;
416 int ret;
417 int src_cnt;
418 int dst_cnt;
419 int i;
420 ktime_t ktime;
421 s64 runtime = 0;
422 unsigned long long total_len = 0;
423
424 set_freezable();
425
426 ret = -ENOMEM;
427
428 smp_rmb();
429 info = thread->info;
430 params = &info->params;
431 chan = thread->chan;
432 dev = chan->device;
433 if (thread->type == DMA_MEMCPY)
434 src_cnt = dst_cnt = 1;
435 else if (thread->type == DMA_XOR) {
436 /* force odd to ensure dst = src */
437 src_cnt = min_odd(params->xor_sources | 1, dev->max_xor);
438 dst_cnt = 1;
439 } else if (thread->type == DMA_PQ) {
440 /* force odd to ensure dst = src */
441 src_cnt = min_odd(params->pq_sources | 1, dma_maxpq(dev, 0));
442 dst_cnt = 2;
443
444 pq_coefs = kmalloc(params->pq_sources+1, GFP_KERNEL);
445 if (!pq_coefs)
446 goto err_thread_type;
447
448 for (i = 0; i < src_cnt; i++)
449 pq_coefs[i] = 1;
450 } else
451 goto err_thread_type;
452
453 thread->srcs = kcalloc(src_cnt+1, sizeof(u8 *), GFP_KERNEL);
454 if (!thread->srcs)
455 goto err_srcs;
456 for (i = 0; i < src_cnt; i++) {
457 thread->srcs[i] = kmalloc(params->buf_size, GFP_KERNEL);
458 if (!thread->srcs[i])
459 goto err_srcbuf;
460 }
461 thread->srcs[i] = NULL;
462
463 thread->dsts = kcalloc(dst_cnt+1, sizeof(u8 *), GFP_KERNEL);
464 if (!thread->dsts)
465 goto err_dsts;
466 for (i = 0; i < dst_cnt; i++) {
467 thread->dsts[i] = kmalloc(params->buf_size, GFP_KERNEL);
468 if (!thread->dsts[i])
469 goto err_dstbuf;
470 }
471 thread->dsts[i] = NULL;
472
473 set_user_nice(current, 10);
474
475 /*
476 * src and dst buffers are freed by ourselves below
477 */
478 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
479
480 ktime = ktime_get();
481 while (!kthread_should_stop()
482 && !(params->iterations && total_tests >= params->iterations)) {
483 struct dma_async_tx_descriptor *tx = NULL;
484 struct dmaengine_unmap_data *um;
485 dma_addr_t srcs[src_cnt];
486 dma_addr_t *dsts;
487 u8 align = 0;
488
489 total_tests++;
490
491 /* honor alignment restrictions */
492 if (thread->type == DMA_MEMCPY)
493 align = dev->copy_align;
494 else if (thread->type == DMA_XOR)
495 align = dev->xor_align;
496 else if (thread->type == DMA_PQ)
497 align = dev->pq_align;
498
499 if (1 << align > params->buf_size) {
500 pr_err("%u-byte buffer too small for %d-byte alignment\n",
501 params->buf_size, 1 << align);
502 break;
503 }
504
505 if (params->noverify) {
506 len = params->buf_size;
507 src_off = 0;
508 dst_off = 0;
509 } else {
510 len = dmatest_random() % params->buf_size + 1;
511 len = (len >> align) << align;
512 if (!len)
513 len = 1 << align;
514 src_off = dmatest_random() % (params->buf_size - len + 1);
515 dst_off = dmatest_random() % (params->buf_size - len + 1);
516
517 src_off = (src_off >> align) << align;
518 dst_off = (dst_off >> align) << align;
519
520 dmatest_init_srcs(thread->srcs, src_off, len,
521 params->buf_size);
522 dmatest_init_dsts(thread->dsts, dst_off, len,
523 params->buf_size);
524 }
525
526 len = (len >> align) << align;
527 if (!len)
528 len = 1 << align;
529 total_len += len;
530
531 um = dmaengine_get_unmap_data(dev->dev, src_cnt+dst_cnt,
532 GFP_KERNEL);
533 if (!um) {
534 failed_tests++;
535 result("unmap data NULL", total_tests,
536 src_off, dst_off, len, ret);
537 continue;
538 }
539
540 um->len = params->buf_size;
541 for (i = 0; i < src_cnt; i++) {
542 void *buf = thread->srcs[i];
543 struct page *pg = virt_to_page(buf);
544 unsigned pg_off = (unsigned long) buf & ~PAGE_MASK;
545
546 um->addr[i] = dma_map_page(dev->dev, pg, pg_off,
547 um->len, DMA_TO_DEVICE);
548 srcs[i] = um->addr[i] + src_off;
549 ret = dma_mapping_error(dev->dev, um->addr[i]);
550 if (ret) {
551 dmaengine_unmap_put(um);
552 result("src mapping error", total_tests,
553 src_off, dst_off, len, ret);
554 failed_tests++;
555 continue;
556 }
557 um->to_cnt++;
558 }
559 /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
560 dsts = &um->addr[src_cnt];
561 for (i = 0; i < dst_cnt; i++) {
562 void *buf = thread->dsts[i];
563 struct page *pg = virt_to_page(buf);
564 unsigned pg_off = (unsigned long) buf & ~PAGE_MASK;
565
566 dsts[i] = dma_map_page(dev->dev, pg, pg_off, um->len,
567 DMA_BIDIRECTIONAL);
568 ret = dma_mapping_error(dev->dev, dsts[i]);
569 if (ret) {
570 dmaengine_unmap_put(um);
571 result("dst mapping error", total_tests,
572 src_off, dst_off, len, ret);
573 failed_tests++;
574 continue;
575 }
576 um->bidi_cnt++;
577 }
578
579 if (thread->type == DMA_MEMCPY)
580 tx = dev->device_prep_dma_memcpy(chan,
581 dsts[0] + dst_off,
582 srcs[0], len, flags);
583 else if (thread->type == DMA_XOR)
584 tx = dev->device_prep_dma_xor(chan,
585 dsts[0] + dst_off,
586 srcs, src_cnt,
587 len, flags);
588 else if (thread->type == DMA_PQ) {
589 dma_addr_t dma_pq[dst_cnt];
590
591 for (i = 0; i < dst_cnt; i++)
592 dma_pq[i] = dsts[i] + dst_off;
593 tx = dev->device_prep_dma_pq(chan, dma_pq, srcs,
594 src_cnt, pq_coefs,
595 len, flags);
596 }
597
598 if (!tx) {
599 dmaengine_unmap_put(um);
600 result("prep error", total_tests, src_off,
601 dst_off, len, ret);
602 msleep(100);
603 failed_tests++;
604 continue;
605 }
606
607 done.done = false;
608 tx->callback = dmatest_callback;
609 tx->callback_param = &done;
610 cookie = tx->tx_submit(tx);
611
612 if (dma_submit_error(cookie)) {
613 dmaengine_unmap_put(um);
614 result("submit error", total_tests, src_off,
615 dst_off, len, ret);
616 msleep(100);
617 failed_tests++;
618 continue;
619 }
620 dma_async_issue_pending(chan);
621
622 wait_event_freezable_timeout(done_wait, done.done,
623 msecs_to_jiffies(params->timeout));
624
625 status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
626
627 if (!done.done) {
628 /*
629 * We're leaving the timed out dma operation with
630 * dangling pointer to done_wait. To make this
631 * correct, we'll need to allocate wait_done for
632 * each test iteration and perform "who's gonna
633 * free it this time?" dancing. For now, just
634 * leave it dangling.
635 */
636 dmaengine_unmap_put(um);
637 result("test timed out", total_tests, src_off, dst_off,
638 len, 0);
639 failed_tests++;
640 continue;
641 } else if (status != DMA_COMPLETE) {
642 dmaengine_unmap_put(um);
643 result(status == DMA_ERROR ?
644 "completion error status" :
645 "completion busy status", total_tests, src_off,
646 dst_off, len, ret);
647 failed_tests++;
648 continue;
649 }
650
651 dmaengine_unmap_put(um);
652
653 if (params->noverify) {
654 verbose_result("test passed", total_tests, src_off,
655 dst_off, len, 0);
656 continue;
657 }
658
659 pr_debug("%s: verifying source buffer...\n", current->comm);
660 error_count = dmatest_verify(thread->srcs, 0, src_off,
661 0, PATTERN_SRC, true);
662 error_count += dmatest_verify(thread->srcs, src_off,
663 src_off + len, src_off,
664 PATTERN_SRC | PATTERN_COPY, true);
665 error_count += dmatest_verify(thread->srcs, src_off + len,
666 params->buf_size, src_off + len,
667 PATTERN_SRC, true);
668
669 pr_debug("%s: verifying dest buffer...\n", current->comm);
670 error_count += dmatest_verify(thread->dsts, 0, dst_off,
671 0, PATTERN_DST, false);
672 error_count += dmatest_verify(thread->dsts, dst_off,
673 dst_off + len, src_off,
674 PATTERN_SRC | PATTERN_COPY, false);
675 error_count += dmatest_verify(thread->dsts, dst_off + len,
676 params->buf_size, dst_off + len,
677 PATTERN_DST, false);
678
679 if (error_count) {
680 result("data error", total_tests, src_off, dst_off,
681 len, error_count);
682 failed_tests++;
683 } else {
684 verbose_result("test passed", total_tests, src_off,
685 dst_off, len, 0);
686 }
687 }
688 runtime = ktime_us_delta(ktime_get(), ktime);
689
690 ret = 0;
691 for (i = 0; thread->dsts[i]; i++)
692 kfree(thread->dsts[i]);
693err_dstbuf:
694 kfree(thread->dsts);
695err_dsts:
696 for (i = 0; thread->srcs[i]; i++)
697 kfree(thread->srcs[i]);
698err_srcbuf:
699 kfree(thread->srcs);
700err_srcs:
701 kfree(pq_coefs);
702err_thread_type:
703 pr_info("%s: summary %u tests, %u failures %llu iops %llu KB/s (%d)\n",
704 current->comm, total_tests, failed_tests,
705 dmatest_persec(runtime, total_tests),
706 dmatest_KBs(runtime, total_len), ret);
707
708 /* terminate all transfers on specified channels */
709 if (ret)
710 dmaengine_terminate_all(chan);
711
712 thread->done = true;
713 wake_up(&thread_wait);
714
715 return ret;
716}
717
718static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
719{
720 struct dmatest_thread *thread;
721 struct dmatest_thread *_thread;
722 int ret;
723
724 list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
725 ret = kthread_stop(thread->task);
726 pr_debug("thread %s exited with status %d\n",
727 thread->task->comm, ret);
728 list_del(&thread->node);
729 put_task_struct(thread->task);
730 kfree(thread);
731 }
732
733 /* terminate all transfers on specified channels */
734 dmaengine_terminate_all(dtc->chan);
735
736 kfree(dtc);
737}
738
739static int dmatest_add_threads(struct dmatest_info *info,
740 struct dmatest_chan *dtc, enum dma_transaction_type type)
741{
742 struct dmatest_params *params = &info->params;
743 struct dmatest_thread *thread;
744 struct dma_chan *chan = dtc->chan;
745 char *op;
746 unsigned int i;
747
748 if (type == DMA_MEMCPY)
749 op = "copy";
750 else if (type == DMA_XOR)
751 op = "xor";
752 else if (type == DMA_PQ)
753 op = "pq";
754 else
755 return -EINVAL;
756
757 for (i = 0; i < params->threads_per_chan; i++) {
758 thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
759 if (!thread) {
760 pr_warn("No memory for %s-%s%u\n",
761 dma_chan_name(chan), op, i);
762 break;
763 }
764 thread->info = info;
765 thread->chan = dtc->chan;
766 thread->type = type;
767 smp_wmb();
768 thread->task = kthread_create(dmatest_func, thread, "%s-%s%u",
769 dma_chan_name(chan), op, i);
770 if (IS_ERR(thread->task)) {
771 pr_warn("Failed to create thread %s-%s%u\n",
772 dma_chan_name(chan), op, i);
773 kfree(thread);
774 break;
775 }
776
777 /* srcbuf and dstbuf are allocated by the thread itself */
778 get_task_struct(thread->task);
779 list_add_tail(&thread->node, &dtc->threads);
780 wake_up_process(thread->task);
781 }
782
783 return i;
784}
785
786static int dmatest_add_channel(struct dmatest_info *info,
787 struct dma_chan *chan)
788{
789 struct dmatest_chan *dtc;
790 struct dma_device *dma_dev = chan->device;
791 unsigned int thread_count = 0;
792 int cnt;
793
794 dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL);
795 if (!dtc) {
796 pr_warn("No memory for %s\n", dma_chan_name(chan));
797 return -ENOMEM;
798 }
799
800 dtc->chan = chan;
801 INIT_LIST_HEAD(&dtc->threads);
802
803 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
804 cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY);
805 thread_count += cnt > 0 ? cnt : 0;
806 }
807 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
808 cnt = dmatest_add_threads(info, dtc, DMA_XOR);
809 thread_count += cnt > 0 ? cnt : 0;
810 }
811 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
812 cnt = dmatest_add_threads(info, dtc, DMA_PQ);
813 thread_count += cnt > 0 ? cnt : 0;
814 }
815
816 pr_info("Started %u threads using %s\n",
817 thread_count, dma_chan_name(chan));
818
819 list_add_tail(&dtc->node, &info->channels);
820 info->nr_channels++;
821
822 return 0;
823}
824
825static bool filter(struct dma_chan *chan, void *param)
826{
827 struct dmatest_params *params = param;
828
829 if (!dmatest_match_channel(params, chan) ||
830 !dmatest_match_device(params, chan->device))
831 return false;
832 else
833 return true;
834}
835
836static void request_channels(struct dmatest_info *info,
837 enum dma_transaction_type type)
838{
839 dma_cap_mask_t mask;
840
841 dma_cap_zero(mask);
842 dma_cap_set(type, mask);
843 for (;;) {
844 struct dmatest_params *params = &info->params;
845 struct dma_chan *chan;
846
847 chan = dma_request_channel(mask, filter, params);
848 if (chan) {
849 if (dmatest_add_channel(info, chan)) {
850 dma_release_channel(chan);
851 break; /* add_channel failed, punt */
852 }
853 } else
854 break; /* no more channels available */
855 if (params->max_channels &&
856 info->nr_channels >= params->max_channels)
857 break; /* we have all we need */
858 }
859}
860
861static void run_threaded_test(struct dmatest_info *info)
862{
863 struct dmatest_params *params = &info->params;
864
865 /* Copy test parameters */
866 params->buf_size = test_buf_size;
867 strlcpy(params->channel, strim(test_channel), sizeof(params->channel));
868 strlcpy(params->device, strim(test_device), sizeof(params->device));
869 params->threads_per_chan = threads_per_chan;
870 params->max_channels = max_channels;
871 params->iterations = iterations;
872 params->xor_sources = xor_sources;
873 params->pq_sources = pq_sources;
874 params->timeout = timeout;
875 params->noverify = noverify;
876
877 request_channels(info, DMA_MEMCPY);
878 request_channels(info, DMA_XOR);
879 request_channels(info, DMA_PQ);
880}
881
882static void stop_threaded_test(struct dmatest_info *info)
883{
884 struct dmatest_chan *dtc, *_dtc;
885 struct dma_chan *chan;
886
887 list_for_each_entry_safe(dtc, _dtc, &info->channels, node) {
888 list_del(&dtc->node);
889 chan = dtc->chan;
890 dmatest_cleanup_channel(dtc);
891 pr_debug("dropped channel %s\n", dma_chan_name(chan));
892 dma_release_channel(chan);
893 }
894
895 info->nr_channels = 0;
896}
897
898static void restart_threaded_test(struct dmatest_info *info, bool run)
899{
900 /* we might be called early to set run=, defer running until all
901 * parameters have been evaluated
902 */
903 if (!info->did_init)
904 return;
905
906 /* Stop any running test first */
907 stop_threaded_test(info);
908
909 /* Run test with new parameters */
910 run_threaded_test(info);
911}
912
913static int dmatest_run_get(char *val, const struct kernel_param *kp)
914{
915 struct dmatest_info *info = &test_info;
916
917 mutex_lock(&info->lock);
918 if (is_threaded_test_run(info)) {
919 dmatest_run = true;
920 } else {
921 stop_threaded_test(info);
922 dmatest_run = false;
923 }
924 mutex_unlock(&info->lock);
925
926 return param_get_bool(val, kp);
927}
928
929static int dmatest_run_set(const char *val, const struct kernel_param *kp)
930{
931 struct dmatest_info *info = &test_info;
932 int ret;
933
934 mutex_lock(&info->lock);
935 ret = param_set_bool(val, kp);
936 if (ret) {
937 mutex_unlock(&info->lock);
938 return ret;
939 }
940
941 if (is_threaded_test_run(info))
942 ret = -EBUSY;
943 else if (dmatest_run)
944 restart_threaded_test(info, dmatest_run);
945
946 mutex_unlock(&info->lock);
947
948 return ret;
949}
950
951static int __init dmatest_init(void)
952{
953 struct dmatest_info *info = &test_info;
954 struct dmatest_params *params = &info->params;
955
956 if (dmatest_run) {
957 mutex_lock(&info->lock);
958 run_threaded_test(info);
959 mutex_unlock(&info->lock);
960 }
961
962 if (params->iterations && wait)
963 wait_event(thread_wait, !is_threaded_test_run(info));
964
965 /* module parameters are stable, inittime tests are started,
966 * let userspace take over 'run' control
967 */
968 info->did_init = true;
969
970 return 0;
971}
972/* when compiled-in wait for drivers to load first */
973late_initcall(dmatest_init);
974
975static void __exit dmatest_exit(void)
976{
977 struct dmatest_info *info = &test_info;
978
979 mutex_lock(&info->lock);
980 stop_threaded_test(info);
981 mutex_unlock(&info->lock);
982}
983module_exit(dmatest_exit);
984
985MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
986MODULE_LICENSE("GPL v2");
1/*
2 * DMA Engine test module
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 * Copyright (C) 2013 Intel Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13#include <linux/delay.h>
14#include <linux/dma-mapping.h>
15#include <linux/dmaengine.h>
16#include <linux/freezer.h>
17#include <linux/init.h>
18#include <linux/kthread.h>
19#include <linux/sched/task.h>
20#include <linux/module.h>
21#include <linux/moduleparam.h>
22#include <linux/random.h>
23#include <linux/slab.h>
24#include <linux/wait.h>
25
26static unsigned int test_buf_size = 16384;
27module_param(test_buf_size, uint, S_IRUGO | S_IWUSR);
28MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
29
30static char test_channel[20];
31module_param_string(channel, test_channel, sizeof(test_channel),
32 S_IRUGO | S_IWUSR);
33MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)");
34
35static char test_device[32];
36module_param_string(device, test_device, sizeof(test_device),
37 S_IRUGO | S_IWUSR);
38MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
39
40static unsigned int threads_per_chan = 1;
41module_param(threads_per_chan, uint, S_IRUGO | S_IWUSR);
42MODULE_PARM_DESC(threads_per_chan,
43 "Number of threads to start per channel (default: 1)");
44
45static unsigned int max_channels;
46module_param(max_channels, uint, S_IRUGO | S_IWUSR);
47MODULE_PARM_DESC(max_channels,
48 "Maximum number of channels to use (default: all)");
49
50static unsigned int iterations;
51module_param(iterations, uint, S_IRUGO | S_IWUSR);
52MODULE_PARM_DESC(iterations,
53 "Iterations before stopping test (default: infinite)");
54
55static unsigned int dmatest;
56module_param(dmatest, uint, S_IRUGO | S_IWUSR);
57MODULE_PARM_DESC(dmatest,
58 "dmatest 0-memcpy 1-memset (default: 0)");
59
60static unsigned int xor_sources = 3;
61module_param(xor_sources, uint, S_IRUGO | S_IWUSR);
62MODULE_PARM_DESC(xor_sources,
63 "Number of xor source buffers (default: 3)");
64
65static unsigned int pq_sources = 3;
66module_param(pq_sources, uint, S_IRUGO | S_IWUSR);
67MODULE_PARM_DESC(pq_sources,
68 "Number of p+q source buffers (default: 3)");
69
70static int timeout = 3000;
71module_param(timeout, uint, S_IRUGO | S_IWUSR);
72MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
73 "Pass -1 for infinite timeout");
74
75static bool noverify;
76module_param(noverify, bool, S_IRUGO | S_IWUSR);
77MODULE_PARM_DESC(noverify, "Disable data verification (default: verify)");
78
79static bool norandom;
80module_param(norandom, bool, 0644);
81MODULE_PARM_DESC(norandom, "Disable random offset setup (default: random)");
82
83static bool verbose;
84module_param(verbose, bool, S_IRUGO | S_IWUSR);
85MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)");
86
87/**
88 * struct dmatest_params - test parameters.
89 * @buf_size: size of the memcpy test buffer
90 * @channel: bus ID of the channel to test
91 * @device: bus ID of the DMA Engine to test
92 * @threads_per_chan: number of threads to start per channel
93 * @max_channels: maximum number of channels to use
94 * @iterations: iterations before stopping test
95 * @xor_sources: number of xor source buffers
96 * @pq_sources: number of p+q source buffers
97 * @timeout: transfer timeout in msec, -1 for infinite timeout
98 */
99struct dmatest_params {
100 unsigned int buf_size;
101 char channel[20];
102 char device[32];
103 unsigned int threads_per_chan;
104 unsigned int max_channels;
105 unsigned int iterations;
106 unsigned int xor_sources;
107 unsigned int pq_sources;
108 int timeout;
109 bool noverify;
110 bool norandom;
111};
112
113/**
114 * struct dmatest_info - test information.
115 * @params: test parameters
116 * @lock: access protection to the fields of this structure
117 */
118static struct dmatest_info {
119 /* Test parameters */
120 struct dmatest_params params;
121
122 /* Internal state */
123 struct list_head channels;
124 unsigned int nr_channels;
125 struct mutex lock;
126 bool did_init;
127} test_info = {
128 .channels = LIST_HEAD_INIT(test_info.channels),
129 .lock = __MUTEX_INITIALIZER(test_info.lock),
130};
131
132static int dmatest_run_set(const char *val, const struct kernel_param *kp);
133static int dmatest_run_get(char *val, const struct kernel_param *kp);
134static const struct kernel_param_ops run_ops = {
135 .set = dmatest_run_set,
136 .get = dmatest_run_get,
137};
138static bool dmatest_run;
139module_param_cb(run, &run_ops, &dmatest_run, S_IRUGO | S_IWUSR);
140MODULE_PARM_DESC(run, "Run the test (default: false)");
141
142/* Maximum amount of mismatched bytes in buffer to print */
143#define MAX_ERROR_COUNT 32
144
145/*
146 * Initialization patterns. All bytes in the source buffer has bit 7
147 * set, all bytes in the destination buffer has bit 7 cleared.
148 *
149 * Bit 6 is set for all bytes which are to be copied by the DMA
150 * engine. Bit 5 is set for all bytes which are to be overwritten by
151 * the DMA engine.
152 *
153 * The remaining bits are the inverse of a counter which increments by
154 * one for each byte address.
155 */
156#define PATTERN_SRC 0x80
157#define PATTERN_DST 0x00
158#define PATTERN_COPY 0x40
159#define PATTERN_OVERWRITE 0x20
160#define PATTERN_COUNT_MASK 0x1f
161#define PATTERN_MEMSET_IDX 0x01
162
163/* poor man's completion - we want to use wait_event_freezable() on it */
164struct dmatest_done {
165 bool done;
166 wait_queue_head_t *wait;
167};
168
169struct dmatest_thread {
170 struct list_head node;
171 struct dmatest_info *info;
172 struct task_struct *task;
173 struct dma_chan *chan;
174 u8 **srcs;
175 u8 **usrcs;
176 u8 **dsts;
177 u8 **udsts;
178 enum dma_transaction_type type;
179 wait_queue_head_t done_wait;
180 struct dmatest_done test_done;
181 bool done;
182};
183
184struct dmatest_chan {
185 struct list_head node;
186 struct dma_chan *chan;
187 struct list_head threads;
188};
189
190static DECLARE_WAIT_QUEUE_HEAD(thread_wait);
191static bool wait;
192
193static bool is_threaded_test_run(struct dmatest_info *info)
194{
195 struct dmatest_chan *dtc;
196
197 list_for_each_entry(dtc, &info->channels, node) {
198 struct dmatest_thread *thread;
199
200 list_for_each_entry(thread, &dtc->threads, node) {
201 if (!thread->done)
202 return true;
203 }
204 }
205
206 return false;
207}
208
209static int dmatest_wait_get(char *val, const struct kernel_param *kp)
210{
211 struct dmatest_info *info = &test_info;
212 struct dmatest_params *params = &info->params;
213
214 if (params->iterations)
215 wait_event(thread_wait, !is_threaded_test_run(info));
216 wait = true;
217 return param_get_bool(val, kp);
218}
219
220static const struct kernel_param_ops wait_ops = {
221 .get = dmatest_wait_get,
222 .set = param_set_bool,
223};
224module_param_cb(wait, &wait_ops, &wait, S_IRUGO);
225MODULE_PARM_DESC(wait, "Wait for tests to complete (default: false)");
226
227static bool dmatest_match_channel(struct dmatest_params *params,
228 struct dma_chan *chan)
229{
230 if (params->channel[0] == '\0')
231 return true;
232 return strcmp(dma_chan_name(chan), params->channel) == 0;
233}
234
235static bool dmatest_match_device(struct dmatest_params *params,
236 struct dma_device *device)
237{
238 if (params->device[0] == '\0')
239 return true;
240 return strcmp(dev_name(device->dev), params->device) == 0;
241}
242
243static unsigned long dmatest_random(void)
244{
245 unsigned long buf;
246
247 prandom_bytes(&buf, sizeof(buf));
248 return buf;
249}
250
251static inline u8 gen_inv_idx(u8 index, bool is_memset)
252{
253 u8 val = is_memset ? PATTERN_MEMSET_IDX : index;
254
255 return ~val & PATTERN_COUNT_MASK;
256}
257
258static inline u8 gen_src_value(u8 index, bool is_memset)
259{
260 return PATTERN_SRC | gen_inv_idx(index, is_memset);
261}
262
263static inline u8 gen_dst_value(u8 index, bool is_memset)
264{
265 return PATTERN_DST | gen_inv_idx(index, is_memset);
266}
267
268static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len,
269 unsigned int buf_size, bool is_memset)
270{
271 unsigned int i;
272 u8 *buf;
273
274 for (; (buf = *bufs); bufs++) {
275 for (i = 0; i < start; i++)
276 buf[i] = gen_src_value(i, is_memset);
277 for ( ; i < start + len; i++)
278 buf[i] = gen_src_value(i, is_memset) | PATTERN_COPY;
279 for ( ; i < buf_size; i++)
280 buf[i] = gen_src_value(i, is_memset);
281 buf++;
282 }
283}
284
285static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len,
286 unsigned int buf_size, bool is_memset)
287{
288 unsigned int i;
289 u8 *buf;
290
291 for (; (buf = *bufs); bufs++) {
292 for (i = 0; i < start; i++)
293 buf[i] = gen_dst_value(i, is_memset);
294 for ( ; i < start + len; i++)
295 buf[i] = gen_dst_value(i, is_memset) |
296 PATTERN_OVERWRITE;
297 for ( ; i < buf_size; i++)
298 buf[i] = gen_dst_value(i, is_memset);
299 }
300}
301
302static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
303 unsigned int counter, bool is_srcbuf, bool is_memset)
304{
305 u8 diff = actual ^ pattern;
306 u8 expected = pattern | gen_inv_idx(counter, is_memset);
307 const char *thread_name = current->comm;
308
309 if (is_srcbuf)
310 pr_warn("%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n",
311 thread_name, index, expected, actual);
312 else if ((pattern & PATTERN_COPY)
313 && (diff & (PATTERN_COPY | PATTERN_OVERWRITE)))
314 pr_warn("%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n",
315 thread_name, index, expected, actual);
316 else if (diff & PATTERN_SRC)
317 pr_warn("%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n",
318 thread_name, index, expected, actual);
319 else
320 pr_warn("%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n",
321 thread_name, index, expected, actual);
322}
323
324static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
325 unsigned int end, unsigned int counter, u8 pattern,
326 bool is_srcbuf, bool is_memset)
327{
328 unsigned int i;
329 unsigned int error_count = 0;
330 u8 actual;
331 u8 expected;
332 u8 *buf;
333 unsigned int counter_orig = counter;
334
335 for (; (buf = *bufs); bufs++) {
336 counter = counter_orig;
337 for (i = start; i < end; i++) {
338 actual = buf[i];
339 expected = pattern | gen_inv_idx(counter, is_memset);
340 if (actual != expected) {
341 if (error_count < MAX_ERROR_COUNT)
342 dmatest_mismatch(actual, pattern, i,
343 counter, is_srcbuf,
344 is_memset);
345 error_count++;
346 }
347 counter++;
348 }
349 }
350
351 if (error_count > MAX_ERROR_COUNT)
352 pr_warn("%s: %u errors suppressed\n",
353 current->comm, error_count - MAX_ERROR_COUNT);
354
355 return error_count;
356}
357
358
359static void dmatest_callback(void *arg)
360{
361 struct dmatest_done *done = arg;
362 struct dmatest_thread *thread =
363 container_of(done, struct dmatest_thread, test_done);
364 if (!thread->done) {
365 done->done = true;
366 wake_up_all(done->wait);
367 } else {
368 /*
369 * If thread->done, it means that this callback occurred
370 * after the parent thread has cleaned up. This can
371 * happen in the case that driver doesn't implement
372 * the terminate_all() functionality and a dma operation
373 * did not occur within the timeout period
374 */
375 WARN(1, "dmatest: Kernel memory may be corrupted!!\n");
376 }
377}
378
379static unsigned int min_odd(unsigned int x, unsigned int y)
380{
381 unsigned int val = min(x, y);
382
383 return val % 2 ? val : val - 1;
384}
385
386static void result(const char *err, unsigned int n, unsigned int src_off,
387 unsigned int dst_off, unsigned int len, unsigned long data)
388{
389 pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
390 current->comm, n, err, src_off, dst_off, len, data);
391}
392
393static void dbg_result(const char *err, unsigned int n, unsigned int src_off,
394 unsigned int dst_off, unsigned int len,
395 unsigned long data)
396{
397 pr_debug("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
398 current->comm, n, err, src_off, dst_off, len, data);
399}
400
401#define verbose_result(err, n, src_off, dst_off, len, data) ({ \
402 if (verbose) \
403 result(err, n, src_off, dst_off, len, data); \
404 else \
405 dbg_result(err, n, src_off, dst_off, len, data);\
406})
407
408static unsigned long long dmatest_persec(s64 runtime, unsigned int val)
409{
410 unsigned long long per_sec = 1000000;
411
412 if (runtime <= 0)
413 return 0;
414
415 /* drop precision until runtime is 32-bits */
416 while (runtime > UINT_MAX) {
417 runtime >>= 1;
418 per_sec <<= 1;
419 }
420
421 per_sec *= val;
422 do_div(per_sec, runtime);
423 return per_sec;
424}
425
426static unsigned long long dmatest_KBs(s64 runtime, unsigned long long len)
427{
428 return dmatest_persec(runtime, len >> 10);
429}
430
431/*
432 * This function repeatedly tests DMA transfers of various lengths and
433 * offsets for a given operation type until it is told to exit by
434 * kthread_stop(). There may be multiple threads running this function
435 * in parallel for a single channel, and there may be multiple channels
436 * being tested in parallel.
437 *
438 * Before each test, the source and destination buffer is initialized
439 * with a known pattern. This pattern is different depending on
440 * whether it's in an area which is supposed to be copied or
441 * overwritten, and different in the source and destination buffers.
442 * So if the DMA engine doesn't copy exactly what we tell it to copy,
443 * we'll notice.
444 */
445static int dmatest_func(void *data)
446{
447 struct dmatest_thread *thread = data;
448 struct dmatest_done *done = &thread->test_done;
449 struct dmatest_info *info;
450 struct dmatest_params *params;
451 struct dma_chan *chan;
452 struct dma_device *dev;
453 unsigned int error_count;
454 unsigned int failed_tests = 0;
455 unsigned int total_tests = 0;
456 dma_cookie_t cookie;
457 enum dma_status status;
458 enum dma_ctrl_flags flags;
459 u8 *pq_coefs = NULL;
460 int ret;
461 int src_cnt;
462 int dst_cnt;
463 int i;
464 ktime_t ktime, start, diff;
465 ktime_t filltime = 0;
466 ktime_t comparetime = 0;
467 s64 runtime = 0;
468 unsigned long long total_len = 0;
469 u8 align = 0;
470 bool is_memset = false;
471
472 set_freezable();
473
474 ret = -ENOMEM;
475
476 smp_rmb();
477 info = thread->info;
478 params = &info->params;
479 chan = thread->chan;
480 dev = chan->device;
481 if (thread->type == DMA_MEMCPY) {
482 align = dev->copy_align;
483 src_cnt = dst_cnt = 1;
484 } else if (thread->type == DMA_MEMSET) {
485 align = dev->fill_align;
486 src_cnt = dst_cnt = 1;
487 is_memset = true;
488 } else if (thread->type == DMA_XOR) {
489 /* force odd to ensure dst = src */
490 src_cnt = min_odd(params->xor_sources | 1, dev->max_xor);
491 dst_cnt = 1;
492 align = dev->xor_align;
493 } else if (thread->type == DMA_PQ) {
494 /* force odd to ensure dst = src */
495 src_cnt = min_odd(params->pq_sources | 1, dma_maxpq(dev, 0));
496 dst_cnt = 2;
497 align = dev->pq_align;
498
499 pq_coefs = kmalloc(params->pq_sources + 1, GFP_KERNEL);
500 if (!pq_coefs)
501 goto err_thread_type;
502
503 for (i = 0; i < src_cnt; i++)
504 pq_coefs[i] = 1;
505 } else
506 goto err_thread_type;
507
508 thread->srcs = kcalloc(src_cnt + 1, sizeof(u8 *), GFP_KERNEL);
509 if (!thread->srcs)
510 goto err_srcs;
511
512 thread->usrcs = kcalloc(src_cnt + 1, sizeof(u8 *), GFP_KERNEL);
513 if (!thread->usrcs)
514 goto err_usrcs;
515
516 for (i = 0; i < src_cnt; i++) {
517 thread->usrcs[i] = kmalloc(params->buf_size + align,
518 GFP_KERNEL);
519 if (!thread->usrcs[i])
520 goto err_srcbuf;
521
522 /* align srcs to alignment restriction */
523 if (align)
524 thread->srcs[i] = PTR_ALIGN(thread->usrcs[i], align);
525 else
526 thread->srcs[i] = thread->usrcs[i];
527 }
528 thread->srcs[i] = NULL;
529
530 thread->dsts = kcalloc(dst_cnt + 1, sizeof(u8 *), GFP_KERNEL);
531 if (!thread->dsts)
532 goto err_dsts;
533
534 thread->udsts = kcalloc(dst_cnt + 1, sizeof(u8 *), GFP_KERNEL);
535 if (!thread->udsts)
536 goto err_udsts;
537
538 for (i = 0; i < dst_cnt; i++) {
539 thread->udsts[i] = kmalloc(params->buf_size + align,
540 GFP_KERNEL);
541 if (!thread->udsts[i])
542 goto err_dstbuf;
543
544 /* align dsts to alignment restriction */
545 if (align)
546 thread->dsts[i] = PTR_ALIGN(thread->udsts[i], align);
547 else
548 thread->dsts[i] = thread->udsts[i];
549 }
550 thread->dsts[i] = NULL;
551
552 set_user_nice(current, 10);
553
554 /*
555 * src and dst buffers are freed by ourselves below
556 */
557 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
558
559 ktime = ktime_get();
560 while (!kthread_should_stop()
561 && !(params->iterations && total_tests >= params->iterations)) {
562 struct dma_async_tx_descriptor *tx = NULL;
563 struct dmaengine_unmap_data *um;
564 dma_addr_t srcs[src_cnt];
565 dma_addr_t *dsts;
566 unsigned int src_off, dst_off, len;
567
568 total_tests++;
569
570 /* Check if buffer count fits into map count variable (u8) */
571 if ((src_cnt + dst_cnt) >= 255) {
572 pr_err("too many buffers (%d of 255 supported)\n",
573 src_cnt + dst_cnt);
574 break;
575 }
576
577 if (1 << align > params->buf_size) {
578 pr_err("%u-byte buffer too small for %d-byte alignment\n",
579 params->buf_size, 1 << align);
580 break;
581 }
582
583 if (params->norandom)
584 len = params->buf_size;
585 else
586 len = dmatest_random() % params->buf_size + 1;
587
588 len = (len >> align) << align;
589 if (!len)
590 len = 1 << align;
591
592 total_len += len;
593
594 if (params->norandom) {
595 src_off = 0;
596 dst_off = 0;
597 } else {
598 src_off = dmatest_random() % (params->buf_size - len + 1);
599 dst_off = dmatest_random() % (params->buf_size - len + 1);
600
601 src_off = (src_off >> align) << align;
602 dst_off = (dst_off >> align) << align;
603 }
604
605 if (!params->noverify) {
606 start = ktime_get();
607 dmatest_init_srcs(thread->srcs, src_off, len,
608 params->buf_size, is_memset);
609 dmatest_init_dsts(thread->dsts, dst_off, len,
610 params->buf_size, is_memset);
611
612 diff = ktime_sub(ktime_get(), start);
613 filltime = ktime_add(filltime, diff);
614 }
615
616 um = dmaengine_get_unmap_data(dev->dev, src_cnt + dst_cnt,
617 GFP_KERNEL);
618 if (!um) {
619 failed_tests++;
620 result("unmap data NULL", total_tests,
621 src_off, dst_off, len, ret);
622 continue;
623 }
624
625 um->len = params->buf_size;
626 for (i = 0; i < src_cnt; i++) {
627 void *buf = thread->srcs[i];
628 struct page *pg = virt_to_page(buf);
629 unsigned long pg_off = offset_in_page(buf);
630
631 um->addr[i] = dma_map_page(dev->dev, pg, pg_off,
632 um->len, DMA_TO_DEVICE);
633 srcs[i] = um->addr[i] + src_off;
634 ret = dma_mapping_error(dev->dev, um->addr[i]);
635 if (ret) {
636 dmaengine_unmap_put(um);
637 result("src mapping error", total_tests,
638 src_off, dst_off, len, ret);
639 failed_tests++;
640 continue;
641 }
642 um->to_cnt++;
643 }
644 /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
645 dsts = &um->addr[src_cnt];
646 for (i = 0; i < dst_cnt; i++) {
647 void *buf = thread->dsts[i];
648 struct page *pg = virt_to_page(buf);
649 unsigned long pg_off = offset_in_page(buf);
650
651 dsts[i] = dma_map_page(dev->dev, pg, pg_off, um->len,
652 DMA_BIDIRECTIONAL);
653 ret = dma_mapping_error(dev->dev, dsts[i]);
654 if (ret) {
655 dmaengine_unmap_put(um);
656 result("dst mapping error", total_tests,
657 src_off, dst_off, len, ret);
658 failed_tests++;
659 continue;
660 }
661 um->bidi_cnt++;
662 }
663
664 if (thread->type == DMA_MEMCPY)
665 tx = dev->device_prep_dma_memcpy(chan,
666 dsts[0] + dst_off,
667 srcs[0], len, flags);
668 else if (thread->type == DMA_MEMSET)
669 tx = dev->device_prep_dma_memset(chan,
670 dsts[0] + dst_off,
671 *(thread->srcs[0] + src_off),
672 len, flags);
673 else if (thread->type == DMA_XOR)
674 tx = dev->device_prep_dma_xor(chan,
675 dsts[0] + dst_off,
676 srcs, src_cnt,
677 len, flags);
678 else if (thread->type == DMA_PQ) {
679 dma_addr_t dma_pq[dst_cnt];
680
681 for (i = 0; i < dst_cnt; i++)
682 dma_pq[i] = dsts[i] + dst_off;
683 tx = dev->device_prep_dma_pq(chan, dma_pq, srcs,
684 src_cnt, pq_coefs,
685 len, flags);
686 }
687
688 if (!tx) {
689 dmaengine_unmap_put(um);
690 result("prep error", total_tests, src_off,
691 dst_off, len, ret);
692 msleep(100);
693 failed_tests++;
694 continue;
695 }
696
697 done->done = false;
698 tx->callback = dmatest_callback;
699 tx->callback_param = done;
700 cookie = tx->tx_submit(tx);
701
702 if (dma_submit_error(cookie)) {
703 dmaengine_unmap_put(um);
704 result("submit error", total_tests, src_off,
705 dst_off, len, ret);
706 msleep(100);
707 failed_tests++;
708 continue;
709 }
710 dma_async_issue_pending(chan);
711
712 wait_event_freezable_timeout(thread->done_wait, done->done,
713 msecs_to_jiffies(params->timeout));
714
715 status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
716
717 if (!done->done) {
718 dmaengine_unmap_put(um);
719 result("test timed out", total_tests, src_off, dst_off,
720 len, 0);
721 failed_tests++;
722 continue;
723 } else if (status != DMA_COMPLETE) {
724 dmaengine_unmap_put(um);
725 result(status == DMA_ERROR ?
726 "completion error status" :
727 "completion busy status", total_tests, src_off,
728 dst_off, len, ret);
729 failed_tests++;
730 continue;
731 }
732
733 dmaengine_unmap_put(um);
734
735 if (params->noverify) {
736 verbose_result("test passed", total_tests, src_off,
737 dst_off, len, 0);
738 continue;
739 }
740
741 start = ktime_get();
742 pr_debug("%s: verifying source buffer...\n", current->comm);
743 error_count = dmatest_verify(thread->srcs, 0, src_off,
744 0, PATTERN_SRC, true, is_memset);
745 error_count += dmatest_verify(thread->srcs, src_off,
746 src_off + len, src_off,
747 PATTERN_SRC | PATTERN_COPY, true, is_memset);
748 error_count += dmatest_verify(thread->srcs, src_off + len,
749 params->buf_size, src_off + len,
750 PATTERN_SRC, true, is_memset);
751
752 pr_debug("%s: verifying dest buffer...\n", current->comm);
753 error_count += dmatest_verify(thread->dsts, 0, dst_off,
754 0, PATTERN_DST, false, is_memset);
755
756 error_count += dmatest_verify(thread->dsts, dst_off,
757 dst_off + len, src_off,
758 PATTERN_SRC | PATTERN_COPY, false, is_memset);
759
760 error_count += dmatest_verify(thread->dsts, dst_off + len,
761 params->buf_size, dst_off + len,
762 PATTERN_DST, false, is_memset);
763
764 diff = ktime_sub(ktime_get(), start);
765 comparetime = ktime_add(comparetime, diff);
766
767 if (error_count) {
768 result("data error", total_tests, src_off, dst_off,
769 len, error_count);
770 failed_tests++;
771 } else {
772 verbose_result("test passed", total_tests, src_off,
773 dst_off, len, 0);
774 }
775 }
776 ktime = ktime_sub(ktime_get(), ktime);
777 ktime = ktime_sub(ktime, comparetime);
778 ktime = ktime_sub(ktime, filltime);
779 runtime = ktime_to_us(ktime);
780
781 ret = 0;
782err_dstbuf:
783 for (i = 0; thread->udsts[i]; i++)
784 kfree(thread->udsts[i]);
785 kfree(thread->udsts);
786err_udsts:
787 kfree(thread->dsts);
788err_dsts:
789err_srcbuf:
790 for (i = 0; thread->usrcs[i]; i++)
791 kfree(thread->usrcs[i]);
792 kfree(thread->usrcs);
793err_usrcs:
794 kfree(thread->srcs);
795err_srcs:
796 kfree(pq_coefs);
797err_thread_type:
798 pr_info("%s: summary %u tests, %u failures %llu iops %llu KB/s (%d)\n",
799 current->comm, total_tests, failed_tests,
800 dmatest_persec(runtime, total_tests),
801 dmatest_KBs(runtime, total_len), ret);
802
803 /* terminate all transfers on specified channels */
804 if (ret || failed_tests)
805 dmaengine_terminate_all(chan);
806
807 thread->done = true;
808 wake_up(&thread_wait);
809
810 return ret;
811}
812
813static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
814{
815 struct dmatest_thread *thread;
816 struct dmatest_thread *_thread;
817 int ret;
818
819 list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
820 ret = kthread_stop(thread->task);
821 pr_debug("thread %s exited with status %d\n",
822 thread->task->comm, ret);
823 list_del(&thread->node);
824 put_task_struct(thread->task);
825 kfree(thread);
826 }
827
828 /* terminate all transfers on specified channels */
829 dmaengine_terminate_all(dtc->chan);
830
831 kfree(dtc);
832}
833
834static int dmatest_add_threads(struct dmatest_info *info,
835 struct dmatest_chan *dtc, enum dma_transaction_type type)
836{
837 struct dmatest_params *params = &info->params;
838 struct dmatest_thread *thread;
839 struct dma_chan *chan = dtc->chan;
840 char *op;
841 unsigned int i;
842
843 if (type == DMA_MEMCPY)
844 op = "copy";
845 else if (type == DMA_MEMSET)
846 op = "set";
847 else if (type == DMA_XOR)
848 op = "xor";
849 else if (type == DMA_PQ)
850 op = "pq";
851 else
852 return -EINVAL;
853
854 for (i = 0; i < params->threads_per_chan; i++) {
855 thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
856 if (!thread) {
857 pr_warn("No memory for %s-%s%u\n",
858 dma_chan_name(chan), op, i);
859 break;
860 }
861 thread->info = info;
862 thread->chan = dtc->chan;
863 thread->type = type;
864 thread->test_done.wait = &thread->done_wait;
865 init_waitqueue_head(&thread->done_wait);
866 smp_wmb();
867 thread->task = kthread_create(dmatest_func, thread, "%s-%s%u",
868 dma_chan_name(chan), op, i);
869 if (IS_ERR(thread->task)) {
870 pr_warn("Failed to create thread %s-%s%u\n",
871 dma_chan_name(chan), op, i);
872 kfree(thread);
873 break;
874 }
875
876 /* srcbuf and dstbuf are allocated by the thread itself */
877 get_task_struct(thread->task);
878 list_add_tail(&thread->node, &dtc->threads);
879 wake_up_process(thread->task);
880 }
881
882 return i;
883}
884
885static int dmatest_add_channel(struct dmatest_info *info,
886 struct dma_chan *chan)
887{
888 struct dmatest_chan *dtc;
889 struct dma_device *dma_dev = chan->device;
890 unsigned int thread_count = 0;
891 int cnt;
892
893 dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL);
894 if (!dtc) {
895 pr_warn("No memory for %s\n", dma_chan_name(chan));
896 return -ENOMEM;
897 }
898
899 dtc->chan = chan;
900 INIT_LIST_HEAD(&dtc->threads);
901
902 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
903 if (dmatest == 0) {
904 cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY);
905 thread_count += cnt > 0 ? cnt : 0;
906 }
907 }
908
909 if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
910 if (dmatest == 1) {
911 cnt = dmatest_add_threads(info, dtc, DMA_MEMSET);
912 thread_count += cnt > 0 ? cnt : 0;
913 }
914 }
915
916 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
917 cnt = dmatest_add_threads(info, dtc, DMA_XOR);
918 thread_count += cnt > 0 ? cnt : 0;
919 }
920 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
921 cnt = dmatest_add_threads(info, dtc, DMA_PQ);
922 thread_count += cnt > 0 ? cnt : 0;
923 }
924
925 pr_info("Started %u threads using %s\n",
926 thread_count, dma_chan_name(chan));
927
928 list_add_tail(&dtc->node, &info->channels);
929 info->nr_channels++;
930
931 return 0;
932}
933
934static bool filter(struct dma_chan *chan, void *param)
935{
936 struct dmatest_params *params = param;
937
938 if (!dmatest_match_channel(params, chan) ||
939 !dmatest_match_device(params, chan->device))
940 return false;
941 else
942 return true;
943}
944
945static void request_channels(struct dmatest_info *info,
946 enum dma_transaction_type type)
947{
948 dma_cap_mask_t mask;
949
950 dma_cap_zero(mask);
951 dma_cap_set(type, mask);
952 for (;;) {
953 struct dmatest_params *params = &info->params;
954 struct dma_chan *chan;
955
956 chan = dma_request_channel(mask, filter, params);
957 if (chan) {
958 if (dmatest_add_channel(info, chan)) {
959 dma_release_channel(chan);
960 break; /* add_channel failed, punt */
961 }
962 } else
963 break; /* no more channels available */
964 if (params->max_channels &&
965 info->nr_channels >= params->max_channels)
966 break; /* we have all we need */
967 }
968}
969
970static void run_threaded_test(struct dmatest_info *info)
971{
972 struct dmatest_params *params = &info->params;
973
974 /* Copy test parameters */
975 params->buf_size = test_buf_size;
976 strlcpy(params->channel, strim(test_channel), sizeof(params->channel));
977 strlcpy(params->device, strim(test_device), sizeof(params->device));
978 params->threads_per_chan = threads_per_chan;
979 params->max_channels = max_channels;
980 params->iterations = iterations;
981 params->xor_sources = xor_sources;
982 params->pq_sources = pq_sources;
983 params->timeout = timeout;
984 params->noverify = noverify;
985 params->norandom = norandom;
986
987 request_channels(info, DMA_MEMCPY);
988 request_channels(info, DMA_MEMSET);
989 request_channels(info, DMA_XOR);
990 request_channels(info, DMA_PQ);
991}
992
993static void stop_threaded_test(struct dmatest_info *info)
994{
995 struct dmatest_chan *dtc, *_dtc;
996 struct dma_chan *chan;
997
998 list_for_each_entry_safe(dtc, _dtc, &info->channels, node) {
999 list_del(&dtc->node);
1000 chan = dtc->chan;
1001 dmatest_cleanup_channel(dtc);
1002 pr_debug("dropped channel %s\n", dma_chan_name(chan));
1003 dma_release_channel(chan);
1004 }
1005
1006 info->nr_channels = 0;
1007}
1008
1009static void restart_threaded_test(struct dmatest_info *info, bool run)
1010{
1011 /* we might be called early to set run=, defer running until all
1012 * parameters have been evaluated
1013 */
1014 if (!info->did_init)
1015 return;
1016
1017 /* Stop any running test first */
1018 stop_threaded_test(info);
1019
1020 /* Run test with new parameters */
1021 run_threaded_test(info);
1022}
1023
1024static int dmatest_run_get(char *val, const struct kernel_param *kp)
1025{
1026 struct dmatest_info *info = &test_info;
1027
1028 mutex_lock(&info->lock);
1029 if (is_threaded_test_run(info)) {
1030 dmatest_run = true;
1031 } else {
1032 stop_threaded_test(info);
1033 dmatest_run = false;
1034 }
1035 mutex_unlock(&info->lock);
1036
1037 return param_get_bool(val, kp);
1038}
1039
1040static int dmatest_run_set(const char *val, const struct kernel_param *kp)
1041{
1042 struct dmatest_info *info = &test_info;
1043 int ret;
1044
1045 mutex_lock(&info->lock);
1046 ret = param_set_bool(val, kp);
1047 if (ret) {
1048 mutex_unlock(&info->lock);
1049 return ret;
1050 }
1051
1052 if (is_threaded_test_run(info))
1053 ret = -EBUSY;
1054 else if (dmatest_run)
1055 restart_threaded_test(info, dmatest_run);
1056
1057 mutex_unlock(&info->lock);
1058
1059 return ret;
1060}
1061
1062static int __init dmatest_init(void)
1063{
1064 struct dmatest_info *info = &test_info;
1065 struct dmatest_params *params = &info->params;
1066
1067 if (dmatest_run) {
1068 mutex_lock(&info->lock);
1069 run_threaded_test(info);
1070 mutex_unlock(&info->lock);
1071 }
1072
1073 if (params->iterations && wait)
1074 wait_event(thread_wait, !is_threaded_test_run(info));
1075
1076 /* module parameters are stable, inittime tests are started,
1077 * let userspace take over 'run' control
1078 */
1079 info->did_init = true;
1080
1081 return 0;
1082}
1083/* when compiled-in wait for drivers to load first */
1084late_initcall(dmatest_init);
1085
1086static void __exit dmatest_exit(void)
1087{
1088 struct dmatest_info *info = &test_info;
1089
1090 mutex_lock(&info->lock);
1091 stop_threaded_test(info);
1092 mutex_unlock(&info->lock);
1093}
1094module_exit(dmatest_exit);
1095
1096MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1097MODULE_LICENSE("GPL v2");