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1/*
2 * DMA Engine test module
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 * Copyright (C) 2013 Intel Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13#include <linux/delay.h>
14#include <linux/dma-mapping.h>
15#include <linux/dmaengine.h>
16#include <linux/freezer.h>
17#include <linux/init.h>
18#include <linux/kthread.h>
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/random.h>
22#include <linux/slab.h>
23#include <linux/wait.h>
24
25static unsigned int test_buf_size = 16384;
26module_param(test_buf_size, uint, S_IRUGO | S_IWUSR);
27MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
28
29static char test_channel[20];
30module_param_string(channel, test_channel, sizeof(test_channel),
31 S_IRUGO | S_IWUSR);
32MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)");
33
34static char test_device[32];
35module_param_string(device, test_device, sizeof(test_device),
36 S_IRUGO | S_IWUSR);
37MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
38
39static unsigned int threads_per_chan = 1;
40module_param(threads_per_chan, uint, S_IRUGO | S_IWUSR);
41MODULE_PARM_DESC(threads_per_chan,
42 "Number of threads to start per channel (default: 1)");
43
44static unsigned int max_channels;
45module_param(max_channels, uint, S_IRUGO | S_IWUSR);
46MODULE_PARM_DESC(max_channels,
47 "Maximum number of channels to use (default: all)");
48
49static unsigned int iterations;
50module_param(iterations, uint, S_IRUGO | S_IWUSR);
51MODULE_PARM_DESC(iterations,
52 "Iterations before stopping test (default: infinite)");
53
54static unsigned int xor_sources = 3;
55module_param(xor_sources, uint, S_IRUGO | S_IWUSR);
56MODULE_PARM_DESC(xor_sources,
57 "Number of xor source buffers (default: 3)");
58
59static unsigned int pq_sources = 3;
60module_param(pq_sources, uint, S_IRUGO | S_IWUSR);
61MODULE_PARM_DESC(pq_sources,
62 "Number of p+q source buffers (default: 3)");
63
64static int timeout = 3000;
65module_param(timeout, uint, S_IRUGO | S_IWUSR);
66MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
67 "Pass -1 for infinite timeout");
68
69static bool noverify;
70module_param(noverify, bool, S_IRUGO | S_IWUSR);
71MODULE_PARM_DESC(noverify, "Disable random data setup and verification");
72
73static bool verbose;
74module_param(verbose, bool, S_IRUGO | S_IWUSR);
75MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)");
76
77/**
78 * struct dmatest_params - test parameters.
79 * @buf_size: size of the memcpy test buffer
80 * @channel: bus ID of the channel to test
81 * @device: bus ID of the DMA Engine to test
82 * @threads_per_chan: number of threads to start per channel
83 * @max_channels: maximum number of channels to use
84 * @iterations: iterations before stopping test
85 * @xor_sources: number of xor source buffers
86 * @pq_sources: number of p+q source buffers
87 * @timeout: transfer timeout in msec, -1 for infinite timeout
88 */
89struct dmatest_params {
90 unsigned int buf_size;
91 char channel[20];
92 char device[32];
93 unsigned int threads_per_chan;
94 unsigned int max_channels;
95 unsigned int iterations;
96 unsigned int xor_sources;
97 unsigned int pq_sources;
98 int timeout;
99 bool noverify;
100};
101
102/**
103 * struct dmatest_info - test information.
104 * @params: test parameters
105 * @lock: access protection to the fields of this structure
106 */
107static struct dmatest_info {
108 /* Test parameters */
109 struct dmatest_params params;
110
111 /* Internal state */
112 struct list_head channels;
113 unsigned int nr_channels;
114 struct mutex lock;
115 bool did_init;
116} test_info = {
117 .channels = LIST_HEAD_INIT(test_info.channels),
118 .lock = __MUTEX_INITIALIZER(test_info.lock),
119};
120
121static int dmatest_run_set(const char *val, const struct kernel_param *kp);
122static int dmatest_run_get(char *val, const struct kernel_param *kp);
123static struct kernel_param_ops run_ops = {
124 .set = dmatest_run_set,
125 .get = dmatest_run_get,
126};
127static bool dmatest_run;
128module_param_cb(run, &run_ops, &dmatest_run, S_IRUGO | S_IWUSR);
129MODULE_PARM_DESC(run, "Run the test (default: false)");
130
131/* Maximum amount of mismatched bytes in buffer to print */
132#define MAX_ERROR_COUNT 32
133
134/*
135 * Initialization patterns. All bytes in the source buffer has bit 7
136 * set, all bytes in the destination buffer has bit 7 cleared.
137 *
138 * Bit 6 is set for all bytes which are to be copied by the DMA
139 * engine. Bit 5 is set for all bytes which are to be overwritten by
140 * the DMA engine.
141 *
142 * The remaining bits are the inverse of a counter which increments by
143 * one for each byte address.
144 */
145#define PATTERN_SRC 0x80
146#define PATTERN_DST 0x00
147#define PATTERN_COPY 0x40
148#define PATTERN_OVERWRITE 0x20
149#define PATTERN_COUNT_MASK 0x1f
150
151struct dmatest_thread {
152 struct list_head node;
153 struct dmatest_info *info;
154 struct task_struct *task;
155 struct dma_chan *chan;
156 u8 **srcs;
157 u8 **dsts;
158 enum dma_transaction_type type;
159 bool done;
160};
161
162struct dmatest_chan {
163 struct list_head node;
164 struct dma_chan *chan;
165 struct list_head threads;
166};
167
168static DECLARE_WAIT_QUEUE_HEAD(thread_wait);
169static bool wait;
170
171static bool is_threaded_test_run(struct dmatest_info *info)
172{
173 struct dmatest_chan *dtc;
174
175 list_for_each_entry(dtc, &info->channels, node) {
176 struct dmatest_thread *thread;
177
178 list_for_each_entry(thread, &dtc->threads, node) {
179 if (!thread->done)
180 return true;
181 }
182 }
183
184 return false;
185}
186
187static int dmatest_wait_get(char *val, const struct kernel_param *kp)
188{
189 struct dmatest_info *info = &test_info;
190 struct dmatest_params *params = &info->params;
191
192 if (params->iterations)
193 wait_event(thread_wait, !is_threaded_test_run(info));
194 wait = true;
195 return param_get_bool(val, kp);
196}
197
198static struct kernel_param_ops wait_ops = {
199 .get = dmatest_wait_get,
200 .set = param_set_bool,
201};
202module_param_cb(wait, &wait_ops, &wait, S_IRUGO);
203MODULE_PARM_DESC(wait, "Wait for tests to complete (default: false)");
204
205static bool dmatest_match_channel(struct dmatest_params *params,
206 struct dma_chan *chan)
207{
208 if (params->channel[0] == '\0')
209 return true;
210 return strcmp(dma_chan_name(chan), params->channel) == 0;
211}
212
213static bool dmatest_match_device(struct dmatest_params *params,
214 struct dma_device *device)
215{
216 if (params->device[0] == '\0')
217 return true;
218 return strcmp(dev_name(device->dev), params->device) == 0;
219}
220
221static unsigned long dmatest_random(void)
222{
223 unsigned long buf;
224
225 prandom_bytes(&buf, sizeof(buf));
226 return buf;
227}
228
229static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len,
230 unsigned int buf_size)
231{
232 unsigned int i;
233 u8 *buf;
234
235 for (; (buf = *bufs); bufs++) {
236 for (i = 0; i < start; i++)
237 buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
238 for ( ; i < start + len; i++)
239 buf[i] = PATTERN_SRC | PATTERN_COPY
240 | (~i & PATTERN_COUNT_MASK);
241 for ( ; i < buf_size; i++)
242 buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
243 buf++;
244 }
245}
246
247static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len,
248 unsigned int buf_size)
249{
250 unsigned int i;
251 u8 *buf;
252
253 for (; (buf = *bufs); bufs++) {
254 for (i = 0; i < start; i++)
255 buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
256 for ( ; i < start + len; i++)
257 buf[i] = PATTERN_DST | PATTERN_OVERWRITE
258 | (~i & PATTERN_COUNT_MASK);
259 for ( ; i < buf_size; i++)
260 buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
261 }
262}
263
264static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
265 unsigned int counter, bool is_srcbuf)
266{
267 u8 diff = actual ^ pattern;
268 u8 expected = pattern | (~counter & PATTERN_COUNT_MASK);
269 const char *thread_name = current->comm;
270
271 if (is_srcbuf)
272 pr_warn("%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n",
273 thread_name, index, expected, actual);
274 else if ((pattern & PATTERN_COPY)
275 && (diff & (PATTERN_COPY | PATTERN_OVERWRITE)))
276 pr_warn("%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n",
277 thread_name, index, expected, actual);
278 else if (diff & PATTERN_SRC)
279 pr_warn("%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n",
280 thread_name, index, expected, actual);
281 else
282 pr_warn("%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n",
283 thread_name, index, expected, actual);
284}
285
286static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
287 unsigned int end, unsigned int counter, u8 pattern,
288 bool is_srcbuf)
289{
290 unsigned int i;
291 unsigned int error_count = 0;
292 u8 actual;
293 u8 expected;
294 u8 *buf;
295 unsigned int counter_orig = counter;
296
297 for (; (buf = *bufs); bufs++) {
298 counter = counter_orig;
299 for (i = start; i < end; i++) {
300 actual = buf[i];
301 expected = pattern | (~counter & PATTERN_COUNT_MASK);
302 if (actual != expected) {
303 if (error_count < MAX_ERROR_COUNT)
304 dmatest_mismatch(actual, pattern, i,
305 counter, is_srcbuf);
306 error_count++;
307 }
308 counter++;
309 }
310 }
311
312 if (error_count > MAX_ERROR_COUNT)
313 pr_warn("%s: %u errors suppressed\n",
314 current->comm, error_count - MAX_ERROR_COUNT);
315
316 return error_count;
317}
318
319/* poor man's completion - we want to use wait_event_freezable() on it */
320struct dmatest_done {
321 bool done;
322 wait_queue_head_t *wait;
323};
324
325static void dmatest_callback(void *arg)
326{
327 struct dmatest_done *done = arg;
328
329 done->done = true;
330 wake_up_all(done->wait);
331}
332
333static unsigned int min_odd(unsigned int x, unsigned int y)
334{
335 unsigned int val = min(x, y);
336
337 return val % 2 ? val : val - 1;
338}
339
340static void result(const char *err, unsigned int n, unsigned int src_off,
341 unsigned int dst_off, unsigned int len, unsigned long data)
342{
343 pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
344 current->comm, n, err, src_off, dst_off, len, data);
345}
346
347static void dbg_result(const char *err, unsigned int n, unsigned int src_off,
348 unsigned int dst_off, unsigned int len,
349 unsigned long data)
350{
351 pr_debug("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
352 current->comm, n, err, src_off, dst_off, len, data);
353}
354
355#define verbose_result(err, n, src_off, dst_off, len, data) ({ \
356 if (verbose) \
357 result(err, n, src_off, dst_off, len, data); \
358 else \
359 dbg_result(err, n, src_off, dst_off, len, data); \
360})
361
362static unsigned long long dmatest_persec(s64 runtime, unsigned int val)
363{
364 unsigned long long per_sec = 1000000;
365
366 if (runtime <= 0)
367 return 0;
368
369 /* drop precision until runtime is 32-bits */
370 while (runtime > UINT_MAX) {
371 runtime >>= 1;
372 per_sec <<= 1;
373 }
374
375 per_sec *= val;
376 do_div(per_sec, runtime);
377 return per_sec;
378}
379
380static unsigned long long dmatest_KBs(s64 runtime, unsigned long long len)
381{
382 return dmatest_persec(runtime, len >> 10);
383}
384
385/*
386 * This function repeatedly tests DMA transfers of various lengths and
387 * offsets for a given operation type until it is told to exit by
388 * kthread_stop(). There may be multiple threads running this function
389 * in parallel for a single channel, and there may be multiple channels
390 * being tested in parallel.
391 *
392 * Before each test, the source and destination buffer is initialized
393 * with a known pattern. This pattern is different depending on
394 * whether it's in an area which is supposed to be copied or
395 * overwritten, and different in the source and destination buffers.
396 * So if the DMA engine doesn't copy exactly what we tell it to copy,
397 * we'll notice.
398 */
399static int dmatest_func(void *data)
400{
401 DECLARE_WAIT_QUEUE_HEAD_ONSTACK(done_wait);
402 struct dmatest_thread *thread = data;
403 struct dmatest_done done = { .wait = &done_wait };
404 struct dmatest_info *info;
405 struct dmatest_params *params;
406 struct dma_chan *chan;
407 struct dma_device *dev;
408 unsigned int src_off, dst_off, len;
409 unsigned int error_count;
410 unsigned int failed_tests = 0;
411 unsigned int total_tests = 0;
412 dma_cookie_t cookie;
413 enum dma_status status;
414 enum dma_ctrl_flags flags;
415 u8 *pq_coefs = NULL;
416 int ret;
417 int src_cnt;
418 int dst_cnt;
419 int i;
420 ktime_t ktime;
421 s64 runtime = 0;
422 unsigned long long total_len = 0;
423
424 set_freezable();
425
426 ret = -ENOMEM;
427
428 smp_rmb();
429 info = thread->info;
430 params = &info->params;
431 chan = thread->chan;
432 dev = chan->device;
433 if (thread->type == DMA_MEMCPY)
434 src_cnt = dst_cnt = 1;
435 else if (thread->type == DMA_XOR) {
436 /* force odd to ensure dst = src */
437 src_cnt = min_odd(params->xor_sources | 1, dev->max_xor);
438 dst_cnt = 1;
439 } else if (thread->type == DMA_PQ) {
440 /* force odd to ensure dst = src */
441 src_cnt = min_odd(params->pq_sources | 1, dma_maxpq(dev, 0));
442 dst_cnt = 2;
443
444 pq_coefs = kmalloc(params->pq_sources+1, GFP_KERNEL);
445 if (!pq_coefs)
446 goto err_thread_type;
447
448 for (i = 0; i < src_cnt; i++)
449 pq_coefs[i] = 1;
450 } else
451 goto err_thread_type;
452
453 thread->srcs = kcalloc(src_cnt+1, sizeof(u8 *), GFP_KERNEL);
454 if (!thread->srcs)
455 goto err_srcs;
456 for (i = 0; i < src_cnt; i++) {
457 thread->srcs[i] = kmalloc(params->buf_size, GFP_KERNEL);
458 if (!thread->srcs[i])
459 goto err_srcbuf;
460 }
461 thread->srcs[i] = NULL;
462
463 thread->dsts = kcalloc(dst_cnt+1, sizeof(u8 *), GFP_KERNEL);
464 if (!thread->dsts)
465 goto err_dsts;
466 for (i = 0; i < dst_cnt; i++) {
467 thread->dsts[i] = kmalloc(params->buf_size, GFP_KERNEL);
468 if (!thread->dsts[i])
469 goto err_dstbuf;
470 }
471 thread->dsts[i] = NULL;
472
473 set_user_nice(current, 10);
474
475 /*
476 * src and dst buffers are freed by ourselves below
477 */
478 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
479
480 ktime = ktime_get();
481 while (!kthread_should_stop()
482 && !(params->iterations && total_tests >= params->iterations)) {
483 struct dma_async_tx_descriptor *tx = NULL;
484 struct dmaengine_unmap_data *um;
485 dma_addr_t srcs[src_cnt];
486 dma_addr_t *dsts;
487 u8 align = 0;
488
489 total_tests++;
490
491 /* honor alignment restrictions */
492 if (thread->type == DMA_MEMCPY)
493 align = dev->copy_align;
494 else if (thread->type == DMA_XOR)
495 align = dev->xor_align;
496 else if (thread->type == DMA_PQ)
497 align = dev->pq_align;
498
499 if (1 << align > params->buf_size) {
500 pr_err("%u-byte buffer too small for %d-byte alignment\n",
501 params->buf_size, 1 << align);
502 break;
503 }
504
505 if (params->noverify) {
506 len = params->buf_size;
507 src_off = 0;
508 dst_off = 0;
509 } else {
510 len = dmatest_random() % params->buf_size + 1;
511 len = (len >> align) << align;
512 if (!len)
513 len = 1 << align;
514 src_off = dmatest_random() % (params->buf_size - len + 1);
515 dst_off = dmatest_random() % (params->buf_size - len + 1);
516
517 src_off = (src_off >> align) << align;
518 dst_off = (dst_off >> align) << align;
519
520 dmatest_init_srcs(thread->srcs, src_off, len,
521 params->buf_size);
522 dmatest_init_dsts(thread->dsts, dst_off, len,
523 params->buf_size);
524 }
525
526 len = (len >> align) << align;
527 if (!len)
528 len = 1 << align;
529 total_len += len;
530
531 um = dmaengine_get_unmap_data(dev->dev, src_cnt+dst_cnt,
532 GFP_KERNEL);
533 if (!um) {
534 failed_tests++;
535 result("unmap data NULL", total_tests,
536 src_off, dst_off, len, ret);
537 continue;
538 }
539
540 um->len = params->buf_size;
541 for (i = 0; i < src_cnt; i++) {
542 void *buf = thread->srcs[i];
543 struct page *pg = virt_to_page(buf);
544 unsigned pg_off = (unsigned long) buf & ~PAGE_MASK;
545
546 um->addr[i] = dma_map_page(dev->dev, pg, pg_off,
547 um->len, DMA_TO_DEVICE);
548 srcs[i] = um->addr[i] + src_off;
549 ret = dma_mapping_error(dev->dev, um->addr[i]);
550 if (ret) {
551 dmaengine_unmap_put(um);
552 result("src mapping error", total_tests,
553 src_off, dst_off, len, ret);
554 failed_tests++;
555 continue;
556 }
557 um->to_cnt++;
558 }
559 /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
560 dsts = &um->addr[src_cnt];
561 for (i = 0; i < dst_cnt; i++) {
562 void *buf = thread->dsts[i];
563 struct page *pg = virt_to_page(buf);
564 unsigned pg_off = (unsigned long) buf & ~PAGE_MASK;
565
566 dsts[i] = dma_map_page(dev->dev, pg, pg_off, um->len,
567 DMA_BIDIRECTIONAL);
568 ret = dma_mapping_error(dev->dev, dsts[i]);
569 if (ret) {
570 dmaengine_unmap_put(um);
571 result("dst mapping error", total_tests,
572 src_off, dst_off, len, ret);
573 failed_tests++;
574 continue;
575 }
576 um->bidi_cnt++;
577 }
578
579 if (thread->type == DMA_MEMCPY)
580 tx = dev->device_prep_dma_memcpy(chan,
581 dsts[0] + dst_off,
582 srcs[0], len, flags);
583 else if (thread->type == DMA_XOR)
584 tx = dev->device_prep_dma_xor(chan,
585 dsts[0] + dst_off,
586 srcs, src_cnt,
587 len, flags);
588 else if (thread->type == DMA_PQ) {
589 dma_addr_t dma_pq[dst_cnt];
590
591 for (i = 0; i < dst_cnt; i++)
592 dma_pq[i] = dsts[i] + dst_off;
593 tx = dev->device_prep_dma_pq(chan, dma_pq, srcs,
594 src_cnt, pq_coefs,
595 len, flags);
596 }
597
598 if (!tx) {
599 dmaengine_unmap_put(um);
600 result("prep error", total_tests, src_off,
601 dst_off, len, ret);
602 msleep(100);
603 failed_tests++;
604 continue;
605 }
606
607 done.done = false;
608 tx->callback = dmatest_callback;
609 tx->callback_param = &done;
610 cookie = tx->tx_submit(tx);
611
612 if (dma_submit_error(cookie)) {
613 dmaengine_unmap_put(um);
614 result("submit error", total_tests, src_off,
615 dst_off, len, ret);
616 msleep(100);
617 failed_tests++;
618 continue;
619 }
620 dma_async_issue_pending(chan);
621
622 wait_event_freezable_timeout(done_wait, done.done,
623 msecs_to_jiffies(params->timeout));
624
625 status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
626
627 if (!done.done) {
628 /*
629 * We're leaving the timed out dma operation with
630 * dangling pointer to done_wait. To make this
631 * correct, we'll need to allocate wait_done for
632 * each test iteration and perform "who's gonna
633 * free it this time?" dancing. For now, just
634 * leave it dangling.
635 */
636 dmaengine_unmap_put(um);
637 result("test timed out", total_tests, src_off, dst_off,
638 len, 0);
639 failed_tests++;
640 continue;
641 } else if (status != DMA_COMPLETE) {
642 dmaengine_unmap_put(um);
643 result(status == DMA_ERROR ?
644 "completion error status" :
645 "completion busy status", total_tests, src_off,
646 dst_off, len, ret);
647 failed_tests++;
648 continue;
649 }
650
651 dmaengine_unmap_put(um);
652
653 if (params->noverify) {
654 verbose_result("test passed", total_tests, src_off,
655 dst_off, len, 0);
656 continue;
657 }
658
659 pr_debug("%s: verifying source buffer...\n", current->comm);
660 error_count = dmatest_verify(thread->srcs, 0, src_off,
661 0, PATTERN_SRC, true);
662 error_count += dmatest_verify(thread->srcs, src_off,
663 src_off + len, src_off,
664 PATTERN_SRC | PATTERN_COPY, true);
665 error_count += dmatest_verify(thread->srcs, src_off + len,
666 params->buf_size, src_off + len,
667 PATTERN_SRC, true);
668
669 pr_debug("%s: verifying dest buffer...\n", current->comm);
670 error_count += dmatest_verify(thread->dsts, 0, dst_off,
671 0, PATTERN_DST, false);
672 error_count += dmatest_verify(thread->dsts, dst_off,
673 dst_off + len, src_off,
674 PATTERN_SRC | PATTERN_COPY, false);
675 error_count += dmatest_verify(thread->dsts, dst_off + len,
676 params->buf_size, dst_off + len,
677 PATTERN_DST, false);
678
679 if (error_count) {
680 result("data error", total_tests, src_off, dst_off,
681 len, error_count);
682 failed_tests++;
683 } else {
684 verbose_result("test passed", total_tests, src_off,
685 dst_off, len, 0);
686 }
687 }
688 runtime = ktime_us_delta(ktime_get(), ktime);
689
690 ret = 0;
691 for (i = 0; thread->dsts[i]; i++)
692 kfree(thread->dsts[i]);
693err_dstbuf:
694 kfree(thread->dsts);
695err_dsts:
696 for (i = 0; thread->srcs[i]; i++)
697 kfree(thread->srcs[i]);
698err_srcbuf:
699 kfree(thread->srcs);
700err_srcs:
701 kfree(pq_coefs);
702err_thread_type:
703 pr_info("%s: summary %u tests, %u failures %llu iops %llu KB/s (%d)\n",
704 current->comm, total_tests, failed_tests,
705 dmatest_persec(runtime, total_tests),
706 dmatest_KBs(runtime, total_len), ret);
707
708 /* terminate all transfers on specified channels */
709 if (ret)
710 dmaengine_terminate_all(chan);
711
712 thread->done = true;
713 wake_up(&thread_wait);
714
715 return ret;
716}
717
718static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
719{
720 struct dmatest_thread *thread;
721 struct dmatest_thread *_thread;
722 int ret;
723
724 list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
725 ret = kthread_stop(thread->task);
726 pr_debug("thread %s exited with status %d\n",
727 thread->task->comm, ret);
728 list_del(&thread->node);
729 put_task_struct(thread->task);
730 kfree(thread);
731 }
732
733 /* terminate all transfers on specified channels */
734 dmaengine_terminate_all(dtc->chan);
735
736 kfree(dtc);
737}
738
739static int dmatest_add_threads(struct dmatest_info *info,
740 struct dmatest_chan *dtc, enum dma_transaction_type type)
741{
742 struct dmatest_params *params = &info->params;
743 struct dmatest_thread *thread;
744 struct dma_chan *chan = dtc->chan;
745 char *op;
746 unsigned int i;
747
748 if (type == DMA_MEMCPY)
749 op = "copy";
750 else if (type == DMA_XOR)
751 op = "xor";
752 else if (type == DMA_PQ)
753 op = "pq";
754 else
755 return -EINVAL;
756
757 for (i = 0; i < params->threads_per_chan; i++) {
758 thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
759 if (!thread) {
760 pr_warn("No memory for %s-%s%u\n",
761 dma_chan_name(chan), op, i);
762 break;
763 }
764 thread->info = info;
765 thread->chan = dtc->chan;
766 thread->type = type;
767 smp_wmb();
768 thread->task = kthread_create(dmatest_func, thread, "%s-%s%u",
769 dma_chan_name(chan), op, i);
770 if (IS_ERR(thread->task)) {
771 pr_warn("Failed to create thread %s-%s%u\n",
772 dma_chan_name(chan), op, i);
773 kfree(thread);
774 break;
775 }
776
777 /* srcbuf and dstbuf are allocated by the thread itself */
778 get_task_struct(thread->task);
779 list_add_tail(&thread->node, &dtc->threads);
780 wake_up_process(thread->task);
781 }
782
783 return i;
784}
785
786static int dmatest_add_channel(struct dmatest_info *info,
787 struct dma_chan *chan)
788{
789 struct dmatest_chan *dtc;
790 struct dma_device *dma_dev = chan->device;
791 unsigned int thread_count = 0;
792 int cnt;
793
794 dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL);
795 if (!dtc) {
796 pr_warn("No memory for %s\n", dma_chan_name(chan));
797 return -ENOMEM;
798 }
799
800 dtc->chan = chan;
801 INIT_LIST_HEAD(&dtc->threads);
802
803 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
804 cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY);
805 thread_count += cnt > 0 ? cnt : 0;
806 }
807 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
808 cnt = dmatest_add_threads(info, dtc, DMA_XOR);
809 thread_count += cnt > 0 ? cnt : 0;
810 }
811 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
812 cnt = dmatest_add_threads(info, dtc, DMA_PQ);
813 thread_count += cnt > 0 ? cnt : 0;
814 }
815
816 pr_info("Started %u threads using %s\n",
817 thread_count, dma_chan_name(chan));
818
819 list_add_tail(&dtc->node, &info->channels);
820 info->nr_channels++;
821
822 return 0;
823}
824
825static bool filter(struct dma_chan *chan, void *param)
826{
827 struct dmatest_params *params = param;
828
829 if (!dmatest_match_channel(params, chan) ||
830 !dmatest_match_device(params, chan->device))
831 return false;
832 else
833 return true;
834}
835
836static void request_channels(struct dmatest_info *info,
837 enum dma_transaction_type type)
838{
839 dma_cap_mask_t mask;
840
841 dma_cap_zero(mask);
842 dma_cap_set(type, mask);
843 for (;;) {
844 struct dmatest_params *params = &info->params;
845 struct dma_chan *chan;
846
847 chan = dma_request_channel(mask, filter, params);
848 if (chan) {
849 if (dmatest_add_channel(info, chan)) {
850 dma_release_channel(chan);
851 break; /* add_channel failed, punt */
852 }
853 } else
854 break; /* no more channels available */
855 if (params->max_channels &&
856 info->nr_channels >= params->max_channels)
857 break; /* we have all we need */
858 }
859}
860
861static void run_threaded_test(struct dmatest_info *info)
862{
863 struct dmatest_params *params = &info->params;
864
865 /* Copy test parameters */
866 params->buf_size = test_buf_size;
867 strlcpy(params->channel, strim(test_channel), sizeof(params->channel));
868 strlcpy(params->device, strim(test_device), sizeof(params->device));
869 params->threads_per_chan = threads_per_chan;
870 params->max_channels = max_channels;
871 params->iterations = iterations;
872 params->xor_sources = xor_sources;
873 params->pq_sources = pq_sources;
874 params->timeout = timeout;
875 params->noverify = noverify;
876
877 request_channels(info, DMA_MEMCPY);
878 request_channels(info, DMA_XOR);
879 request_channels(info, DMA_PQ);
880}
881
882static void stop_threaded_test(struct dmatest_info *info)
883{
884 struct dmatest_chan *dtc, *_dtc;
885 struct dma_chan *chan;
886
887 list_for_each_entry_safe(dtc, _dtc, &info->channels, node) {
888 list_del(&dtc->node);
889 chan = dtc->chan;
890 dmatest_cleanup_channel(dtc);
891 pr_debug("dropped channel %s\n", dma_chan_name(chan));
892 dma_release_channel(chan);
893 }
894
895 info->nr_channels = 0;
896}
897
898static void restart_threaded_test(struct dmatest_info *info, bool run)
899{
900 /* we might be called early to set run=, defer running until all
901 * parameters have been evaluated
902 */
903 if (!info->did_init)
904 return;
905
906 /* Stop any running test first */
907 stop_threaded_test(info);
908
909 /* Run test with new parameters */
910 run_threaded_test(info);
911}
912
913static int dmatest_run_get(char *val, const struct kernel_param *kp)
914{
915 struct dmatest_info *info = &test_info;
916
917 mutex_lock(&info->lock);
918 if (is_threaded_test_run(info)) {
919 dmatest_run = true;
920 } else {
921 stop_threaded_test(info);
922 dmatest_run = false;
923 }
924 mutex_unlock(&info->lock);
925
926 return param_get_bool(val, kp);
927}
928
929static int dmatest_run_set(const char *val, const struct kernel_param *kp)
930{
931 struct dmatest_info *info = &test_info;
932 int ret;
933
934 mutex_lock(&info->lock);
935 ret = param_set_bool(val, kp);
936 if (ret) {
937 mutex_unlock(&info->lock);
938 return ret;
939 }
940
941 if (is_threaded_test_run(info))
942 ret = -EBUSY;
943 else if (dmatest_run)
944 restart_threaded_test(info, dmatest_run);
945
946 mutex_unlock(&info->lock);
947
948 return ret;
949}
950
951static int __init dmatest_init(void)
952{
953 struct dmatest_info *info = &test_info;
954 struct dmatest_params *params = &info->params;
955
956 if (dmatest_run) {
957 mutex_lock(&info->lock);
958 run_threaded_test(info);
959 mutex_unlock(&info->lock);
960 }
961
962 if (params->iterations && wait)
963 wait_event(thread_wait, !is_threaded_test_run(info));
964
965 /* module parameters are stable, inittime tests are started,
966 * let userspace take over 'run' control
967 */
968 info->did_init = true;
969
970 return 0;
971}
972/* when compiled-in wait for drivers to load first */
973late_initcall(dmatest_init);
974
975static void __exit dmatest_exit(void)
976{
977 struct dmatest_info *info = &test_info;
978
979 mutex_lock(&info->lock);
980 stop_threaded_test(info);
981 mutex_unlock(&info->lock);
982}
983module_exit(dmatest_exit);
984
985MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
986MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * DMA Engine test module
4 *
5 * Copyright (C) 2007 Atmel Corporation
6 * Copyright (C) 2013 Intel Corporation
7 */
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/delay.h>
11#include <linux/dma-mapping.h>
12#include <linux/dmaengine.h>
13#include <linux/freezer.h>
14#include <linux/init.h>
15#include <linux/kthread.h>
16#include <linux/sched/task.h>
17#include <linux/module.h>
18#include <linux/moduleparam.h>
19#include <linux/random.h>
20#include <linux/slab.h>
21#include <linux/wait.h>
22
23static unsigned int test_buf_size = 16384;
24module_param(test_buf_size, uint, S_IRUGO | S_IWUSR);
25MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
26
27static char test_device[32];
28module_param_string(device, test_device, sizeof(test_device),
29 S_IRUGO | S_IWUSR);
30MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
31
32static unsigned int threads_per_chan = 1;
33module_param(threads_per_chan, uint, S_IRUGO | S_IWUSR);
34MODULE_PARM_DESC(threads_per_chan,
35 "Number of threads to start per channel (default: 1)");
36
37static unsigned int max_channels;
38module_param(max_channels, uint, S_IRUGO | S_IWUSR);
39MODULE_PARM_DESC(max_channels,
40 "Maximum number of channels to use (default: all)");
41
42static unsigned int iterations;
43module_param(iterations, uint, S_IRUGO | S_IWUSR);
44MODULE_PARM_DESC(iterations,
45 "Iterations before stopping test (default: infinite)");
46
47static unsigned int dmatest;
48module_param(dmatest, uint, S_IRUGO | S_IWUSR);
49MODULE_PARM_DESC(dmatest,
50 "dmatest 0-memcpy 1-memset (default: 0)");
51
52static unsigned int xor_sources = 3;
53module_param(xor_sources, uint, S_IRUGO | S_IWUSR);
54MODULE_PARM_DESC(xor_sources,
55 "Number of xor source buffers (default: 3)");
56
57static unsigned int pq_sources = 3;
58module_param(pq_sources, uint, S_IRUGO | S_IWUSR);
59MODULE_PARM_DESC(pq_sources,
60 "Number of p+q source buffers (default: 3)");
61
62static int timeout = 3000;
63module_param(timeout, int, S_IRUGO | S_IWUSR);
64MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
65 "Pass -1 for infinite timeout");
66
67static bool noverify;
68module_param(noverify, bool, S_IRUGO | S_IWUSR);
69MODULE_PARM_DESC(noverify, "Disable data verification (default: verify)");
70
71static bool norandom;
72module_param(norandom, bool, 0644);
73MODULE_PARM_DESC(norandom, "Disable random offset setup (default: random)");
74
75static bool verbose;
76module_param(verbose, bool, S_IRUGO | S_IWUSR);
77MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)");
78
79static int alignment = -1;
80module_param(alignment, int, 0644);
81MODULE_PARM_DESC(alignment, "Custom data address alignment taken as 2^(alignment) (default: not used (-1))");
82
83static unsigned int transfer_size;
84module_param(transfer_size, uint, 0644);
85MODULE_PARM_DESC(transfer_size, "Optional custom transfer size in bytes (default: not used (0))");
86
87static bool polled;
88module_param(polled, bool, S_IRUGO | S_IWUSR);
89MODULE_PARM_DESC(polled, "Use polling for completion instead of interrupts");
90
91/**
92 * struct dmatest_params - test parameters.
93 * @buf_size: size of the memcpy test buffer
94 * @channel: bus ID of the channel to test
95 * @device: bus ID of the DMA Engine to test
96 * @threads_per_chan: number of threads to start per channel
97 * @max_channels: maximum number of channels to use
98 * @iterations: iterations before stopping test
99 * @xor_sources: number of xor source buffers
100 * @pq_sources: number of p+q source buffers
101 * @timeout: transfer timeout in msec, -1 for infinite timeout
102 * @noverify: disable data verification
103 * @norandom: disable random offset setup
104 * @alignment: custom data address alignment taken as 2^alignment
105 * @transfer_size: custom transfer size in bytes
106 * @polled: use polling for completion instead of interrupts
107 */
108struct dmatest_params {
109 unsigned int buf_size;
110 char channel[20];
111 char device[32];
112 unsigned int threads_per_chan;
113 unsigned int max_channels;
114 unsigned int iterations;
115 unsigned int xor_sources;
116 unsigned int pq_sources;
117 int timeout;
118 bool noverify;
119 bool norandom;
120 int alignment;
121 unsigned int transfer_size;
122 bool polled;
123};
124
125/**
126 * struct dmatest_info - test information.
127 * @params: test parameters
128 * @channels: channels under test
129 * @nr_channels: number of channels under test
130 * @lock: access protection to the fields of this structure
131 * @did_init: module has been initialized completely
132 * @last_error: test has faced configuration issues
133 */
134static struct dmatest_info {
135 /* Test parameters */
136 struct dmatest_params params;
137
138 /* Internal state */
139 struct list_head channels;
140 unsigned int nr_channels;
141 int last_error;
142 struct mutex lock;
143 bool did_init;
144} test_info = {
145 .channels = LIST_HEAD_INIT(test_info.channels),
146 .lock = __MUTEX_INITIALIZER(test_info.lock),
147};
148
149static int dmatest_run_set(const char *val, const struct kernel_param *kp);
150static int dmatest_run_get(char *val, const struct kernel_param *kp);
151static const struct kernel_param_ops run_ops = {
152 .set = dmatest_run_set,
153 .get = dmatest_run_get,
154};
155static bool dmatest_run;
156module_param_cb(run, &run_ops, &dmatest_run, S_IRUGO | S_IWUSR);
157MODULE_PARM_DESC(run, "Run the test (default: false)");
158
159static int dmatest_chan_set(const char *val, const struct kernel_param *kp);
160static int dmatest_chan_get(char *val, const struct kernel_param *kp);
161static const struct kernel_param_ops multi_chan_ops = {
162 .set = dmatest_chan_set,
163 .get = dmatest_chan_get,
164};
165
166static char test_channel[20];
167static struct kparam_string newchan_kps = {
168 .string = test_channel,
169 .maxlen = 20,
170};
171module_param_cb(channel, &multi_chan_ops, &newchan_kps, 0644);
172MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)");
173
174static int dmatest_test_list_get(char *val, const struct kernel_param *kp);
175static const struct kernel_param_ops test_list_ops = {
176 .get = dmatest_test_list_get,
177};
178module_param_cb(test_list, &test_list_ops, NULL, 0444);
179MODULE_PARM_DESC(test_list, "Print current test list");
180
181/* Maximum amount of mismatched bytes in buffer to print */
182#define MAX_ERROR_COUNT 32
183
184/*
185 * Initialization patterns. All bytes in the source buffer has bit 7
186 * set, all bytes in the destination buffer has bit 7 cleared.
187 *
188 * Bit 6 is set for all bytes which are to be copied by the DMA
189 * engine. Bit 5 is set for all bytes which are to be overwritten by
190 * the DMA engine.
191 *
192 * The remaining bits are the inverse of a counter which increments by
193 * one for each byte address.
194 */
195#define PATTERN_SRC 0x80
196#define PATTERN_DST 0x00
197#define PATTERN_COPY 0x40
198#define PATTERN_OVERWRITE 0x20
199#define PATTERN_COUNT_MASK 0x1f
200#define PATTERN_MEMSET_IDX 0x01
201
202/* Fixed point arithmetic ops */
203#define FIXPT_SHIFT 8
204#define FIXPNT_MASK 0xFF
205#define FIXPT_TO_INT(a) ((a) >> FIXPT_SHIFT)
206#define INT_TO_FIXPT(a) ((a) << FIXPT_SHIFT)
207#define FIXPT_GET_FRAC(a) ((((a) & FIXPNT_MASK) * 100) >> FIXPT_SHIFT)
208
209/* poor man's completion - we want to use wait_event_freezable() on it */
210struct dmatest_done {
211 bool done;
212 wait_queue_head_t *wait;
213};
214
215struct dmatest_data {
216 u8 **raw;
217 u8 **aligned;
218 unsigned int cnt;
219 unsigned int off;
220};
221
222struct dmatest_thread {
223 struct list_head node;
224 struct dmatest_info *info;
225 struct task_struct *task;
226 struct dma_chan *chan;
227 struct dmatest_data src;
228 struct dmatest_data dst;
229 enum dma_transaction_type type;
230 wait_queue_head_t done_wait;
231 struct dmatest_done test_done;
232 bool done;
233 bool pending;
234};
235
236struct dmatest_chan {
237 struct list_head node;
238 struct dma_chan *chan;
239 struct list_head threads;
240};
241
242static DECLARE_WAIT_QUEUE_HEAD(thread_wait);
243static bool wait;
244
245static bool is_threaded_test_run(struct dmatest_info *info)
246{
247 struct dmatest_chan *dtc;
248
249 list_for_each_entry(dtc, &info->channels, node) {
250 struct dmatest_thread *thread;
251
252 list_for_each_entry(thread, &dtc->threads, node) {
253 if (!thread->done && !thread->pending)
254 return true;
255 }
256 }
257
258 return false;
259}
260
261static bool is_threaded_test_pending(struct dmatest_info *info)
262{
263 struct dmatest_chan *dtc;
264
265 list_for_each_entry(dtc, &info->channels, node) {
266 struct dmatest_thread *thread;
267
268 list_for_each_entry(thread, &dtc->threads, node) {
269 if (thread->pending)
270 return true;
271 }
272 }
273
274 return false;
275}
276
277static int dmatest_wait_get(char *val, const struct kernel_param *kp)
278{
279 struct dmatest_info *info = &test_info;
280 struct dmatest_params *params = &info->params;
281
282 if (params->iterations)
283 wait_event(thread_wait, !is_threaded_test_run(info));
284 wait = true;
285 return param_get_bool(val, kp);
286}
287
288static const struct kernel_param_ops wait_ops = {
289 .get = dmatest_wait_get,
290 .set = param_set_bool,
291};
292module_param_cb(wait, &wait_ops, &wait, S_IRUGO);
293MODULE_PARM_DESC(wait, "Wait for tests to complete (default: false)");
294
295static bool dmatest_match_channel(struct dmatest_params *params,
296 struct dma_chan *chan)
297{
298 if (params->channel[0] == '\0')
299 return true;
300 return strcmp(dma_chan_name(chan), params->channel) == 0;
301}
302
303static bool dmatest_match_device(struct dmatest_params *params,
304 struct dma_device *device)
305{
306 if (params->device[0] == '\0')
307 return true;
308 return strcmp(dev_name(device->dev), params->device) == 0;
309}
310
311static unsigned long dmatest_random(void)
312{
313 unsigned long buf;
314
315 prandom_bytes(&buf, sizeof(buf));
316 return buf;
317}
318
319static inline u8 gen_inv_idx(u8 index, bool is_memset)
320{
321 u8 val = is_memset ? PATTERN_MEMSET_IDX : index;
322
323 return ~val & PATTERN_COUNT_MASK;
324}
325
326static inline u8 gen_src_value(u8 index, bool is_memset)
327{
328 return PATTERN_SRC | gen_inv_idx(index, is_memset);
329}
330
331static inline u8 gen_dst_value(u8 index, bool is_memset)
332{
333 return PATTERN_DST | gen_inv_idx(index, is_memset);
334}
335
336static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len,
337 unsigned int buf_size, bool is_memset)
338{
339 unsigned int i;
340 u8 *buf;
341
342 for (; (buf = *bufs); bufs++) {
343 for (i = 0; i < start; i++)
344 buf[i] = gen_src_value(i, is_memset);
345 for ( ; i < start + len; i++)
346 buf[i] = gen_src_value(i, is_memset) | PATTERN_COPY;
347 for ( ; i < buf_size; i++)
348 buf[i] = gen_src_value(i, is_memset);
349 buf++;
350 }
351}
352
353static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len,
354 unsigned int buf_size, bool is_memset)
355{
356 unsigned int i;
357 u8 *buf;
358
359 for (; (buf = *bufs); bufs++) {
360 for (i = 0; i < start; i++)
361 buf[i] = gen_dst_value(i, is_memset);
362 for ( ; i < start + len; i++)
363 buf[i] = gen_dst_value(i, is_memset) |
364 PATTERN_OVERWRITE;
365 for ( ; i < buf_size; i++)
366 buf[i] = gen_dst_value(i, is_memset);
367 }
368}
369
370static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
371 unsigned int counter, bool is_srcbuf, bool is_memset)
372{
373 u8 diff = actual ^ pattern;
374 u8 expected = pattern | gen_inv_idx(counter, is_memset);
375 const char *thread_name = current->comm;
376
377 if (is_srcbuf)
378 pr_warn("%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n",
379 thread_name, index, expected, actual);
380 else if ((pattern & PATTERN_COPY)
381 && (diff & (PATTERN_COPY | PATTERN_OVERWRITE)))
382 pr_warn("%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n",
383 thread_name, index, expected, actual);
384 else if (diff & PATTERN_SRC)
385 pr_warn("%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n",
386 thread_name, index, expected, actual);
387 else
388 pr_warn("%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n",
389 thread_name, index, expected, actual);
390}
391
392static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
393 unsigned int end, unsigned int counter, u8 pattern,
394 bool is_srcbuf, bool is_memset)
395{
396 unsigned int i;
397 unsigned int error_count = 0;
398 u8 actual;
399 u8 expected;
400 u8 *buf;
401 unsigned int counter_orig = counter;
402
403 for (; (buf = *bufs); bufs++) {
404 counter = counter_orig;
405 for (i = start; i < end; i++) {
406 actual = buf[i];
407 expected = pattern | gen_inv_idx(counter, is_memset);
408 if (actual != expected) {
409 if (error_count < MAX_ERROR_COUNT)
410 dmatest_mismatch(actual, pattern, i,
411 counter, is_srcbuf,
412 is_memset);
413 error_count++;
414 }
415 counter++;
416 }
417 }
418
419 if (error_count > MAX_ERROR_COUNT)
420 pr_warn("%s: %u errors suppressed\n",
421 current->comm, error_count - MAX_ERROR_COUNT);
422
423 return error_count;
424}
425
426
427static void dmatest_callback(void *arg)
428{
429 struct dmatest_done *done = arg;
430 struct dmatest_thread *thread =
431 container_of(done, struct dmatest_thread, test_done);
432 if (!thread->done) {
433 done->done = true;
434 wake_up_all(done->wait);
435 } else {
436 /*
437 * If thread->done, it means that this callback occurred
438 * after the parent thread has cleaned up. This can
439 * happen in the case that driver doesn't implement
440 * the terminate_all() functionality and a dma operation
441 * did not occur within the timeout period
442 */
443 WARN(1, "dmatest: Kernel memory may be corrupted!!\n");
444 }
445}
446
447static unsigned int min_odd(unsigned int x, unsigned int y)
448{
449 unsigned int val = min(x, y);
450
451 return val % 2 ? val : val - 1;
452}
453
454static void result(const char *err, unsigned int n, unsigned int src_off,
455 unsigned int dst_off, unsigned int len, unsigned long data)
456{
457 pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
458 current->comm, n, err, src_off, dst_off, len, data);
459}
460
461static void dbg_result(const char *err, unsigned int n, unsigned int src_off,
462 unsigned int dst_off, unsigned int len,
463 unsigned long data)
464{
465 pr_debug("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
466 current->comm, n, err, src_off, dst_off, len, data);
467}
468
469#define verbose_result(err, n, src_off, dst_off, len, data) ({ \
470 if (verbose) \
471 result(err, n, src_off, dst_off, len, data); \
472 else \
473 dbg_result(err, n, src_off, dst_off, len, data);\
474})
475
476static unsigned long long dmatest_persec(s64 runtime, unsigned int val)
477{
478 unsigned long long per_sec = 1000000;
479
480 if (runtime <= 0)
481 return 0;
482
483 /* drop precision until runtime is 32-bits */
484 while (runtime > UINT_MAX) {
485 runtime >>= 1;
486 per_sec <<= 1;
487 }
488
489 per_sec *= val;
490 per_sec = INT_TO_FIXPT(per_sec);
491 do_div(per_sec, runtime);
492
493 return per_sec;
494}
495
496static unsigned long long dmatest_KBs(s64 runtime, unsigned long long len)
497{
498 return FIXPT_TO_INT(dmatest_persec(runtime, len >> 10));
499}
500
501static void __dmatest_free_test_data(struct dmatest_data *d, unsigned int cnt)
502{
503 unsigned int i;
504
505 for (i = 0; i < cnt; i++)
506 kfree(d->raw[i]);
507
508 kfree(d->aligned);
509 kfree(d->raw);
510}
511
512static void dmatest_free_test_data(struct dmatest_data *d)
513{
514 __dmatest_free_test_data(d, d->cnt);
515}
516
517static int dmatest_alloc_test_data(struct dmatest_data *d,
518 unsigned int buf_size, u8 align)
519{
520 unsigned int i = 0;
521
522 d->raw = kcalloc(d->cnt + 1, sizeof(u8 *), GFP_KERNEL);
523 if (!d->raw)
524 return -ENOMEM;
525
526 d->aligned = kcalloc(d->cnt + 1, sizeof(u8 *), GFP_KERNEL);
527 if (!d->aligned)
528 goto err;
529
530 for (i = 0; i < d->cnt; i++) {
531 d->raw[i] = kmalloc(buf_size + align, GFP_KERNEL);
532 if (!d->raw[i])
533 goto err;
534
535 /* align to alignment restriction */
536 if (align)
537 d->aligned[i] = PTR_ALIGN(d->raw[i], align);
538 else
539 d->aligned[i] = d->raw[i];
540 }
541
542 return 0;
543err:
544 __dmatest_free_test_data(d, i);
545 return -ENOMEM;
546}
547
548/*
549 * This function repeatedly tests DMA transfers of various lengths and
550 * offsets for a given operation type until it is told to exit by
551 * kthread_stop(). There may be multiple threads running this function
552 * in parallel for a single channel, and there may be multiple channels
553 * being tested in parallel.
554 *
555 * Before each test, the source and destination buffer is initialized
556 * with a known pattern. This pattern is different depending on
557 * whether it's in an area which is supposed to be copied or
558 * overwritten, and different in the source and destination buffers.
559 * So if the DMA engine doesn't copy exactly what we tell it to copy,
560 * we'll notice.
561 */
562static int dmatest_func(void *data)
563{
564 struct dmatest_thread *thread = data;
565 struct dmatest_done *done = &thread->test_done;
566 struct dmatest_info *info;
567 struct dmatest_params *params;
568 struct dma_chan *chan;
569 struct dma_device *dev;
570 unsigned int error_count;
571 unsigned int failed_tests = 0;
572 unsigned int total_tests = 0;
573 dma_cookie_t cookie;
574 enum dma_status status;
575 enum dma_ctrl_flags flags;
576 u8 *pq_coefs = NULL;
577 int ret;
578 unsigned int buf_size;
579 struct dmatest_data *src;
580 struct dmatest_data *dst;
581 int i;
582 ktime_t ktime, start, diff;
583 ktime_t filltime = 0;
584 ktime_t comparetime = 0;
585 s64 runtime = 0;
586 unsigned long long total_len = 0;
587 unsigned long long iops = 0;
588 u8 align = 0;
589 bool is_memset = false;
590 dma_addr_t *srcs;
591 dma_addr_t *dma_pq;
592
593 set_freezable();
594
595 ret = -ENOMEM;
596
597 smp_rmb();
598 thread->pending = false;
599 info = thread->info;
600 params = &info->params;
601 chan = thread->chan;
602 dev = chan->device;
603 src = &thread->src;
604 dst = &thread->dst;
605 if (thread->type == DMA_MEMCPY) {
606 align = params->alignment < 0 ? dev->copy_align :
607 params->alignment;
608 src->cnt = dst->cnt = 1;
609 } else if (thread->type == DMA_MEMSET) {
610 align = params->alignment < 0 ? dev->fill_align :
611 params->alignment;
612 src->cnt = dst->cnt = 1;
613 is_memset = true;
614 } else if (thread->type == DMA_XOR) {
615 /* force odd to ensure dst = src */
616 src->cnt = min_odd(params->xor_sources | 1, dev->max_xor);
617 dst->cnt = 1;
618 align = params->alignment < 0 ? dev->xor_align :
619 params->alignment;
620 } else if (thread->type == DMA_PQ) {
621 /* force odd to ensure dst = src */
622 src->cnt = min_odd(params->pq_sources | 1, dma_maxpq(dev, 0));
623 dst->cnt = 2;
624 align = params->alignment < 0 ? dev->pq_align :
625 params->alignment;
626
627 pq_coefs = kmalloc(params->pq_sources + 1, GFP_KERNEL);
628 if (!pq_coefs)
629 goto err_thread_type;
630
631 for (i = 0; i < src->cnt; i++)
632 pq_coefs[i] = 1;
633 } else
634 goto err_thread_type;
635
636 /* Check if buffer count fits into map count variable (u8) */
637 if ((src->cnt + dst->cnt) >= 255) {
638 pr_err("too many buffers (%d of 255 supported)\n",
639 src->cnt + dst->cnt);
640 goto err_free_coefs;
641 }
642
643 buf_size = params->buf_size;
644 if (1 << align > buf_size) {
645 pr_err("%u-byte buffer too small for %d-byte alignment\n",
646 buf_size, 1 << align);
647 goto err_free_coefs;
648 }
649
650 if (dmatest_alloc_test_data(src, buf_size, align) < 0)
651 goto err_free_coefs;
652
653 if (dmatest_alloc_test_data(dst, buf_size, align) < 0)
654 goto err_src;
655
656 set_user_nice(current, 10);
657
658 srcs = kcalloc(src->cnt, sizeof(dma_addr_t), GFP_KERNEL);
659 if (!srcs)
660 goto err_dst;
661
662 dma_pq = kcalloc(dst->cnt, sizeof(dma_addr_t), GFP_KERNEL);
663 if (!dma_pq)
664 goto err_srcs_array;
665
666 /*
667 * src and dst buffers are freed by ourselves below
668 */
669 if (params->polled)
670 flags = DMA_CTRL_ACK;
671 else
672 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
673
674 ktime = ktime_get();
675 while (!(kthread_should_stop() ||
676 (params->iterations && total_tests >= params->iterations))) {
677 struct dma_async_tx_descriptor *tx = NULL;
678 struct dmaengine_unmap_data *um;
679 dma_addr_t *dsts;
680 unsigned int len;
681
682 total_tests++;
683
684 if (params->transfer_size) {
685 if (params->transfer_size >= buf_size) {
686 pr_err("%u-byte transfer size must be lower than %u-buffer size\n",
687 params->transfer_size, buf_size);
688 break;
689 }
690 len = params->transfer_size;
691 } else if (params->norandom) {
692 len = buf_size;
693 } else {
694 len = dmatest_random() % buf_size + 1;
695 }
696
697 /* Do not alter transfer size explicitly defined by user */
698 if (!params->transfer_size) {
699 len = (len >> align) << align;
700 if (!len)
701 len = 1 << align;
702 }
703 total_len += len;
704
705 if (params->norandom) {
706 src->off = 0;
707 dst->off = 0;
708 } else {
709 src->off = dmatest_random() % (buf_size - len + 1);
710 dst->off = dmatest_random() % (buf_size - len + 1);
711
712 src->off = (src->off >> align) << align;
713 dst->off = (dst->off >> align) << align;
714 }
715
716 if (!params->noverify) {
717 start = ktime_get();
718 dmatest_init_srcs(src->aligned, src->off, len,
719 buf_size, is_memset);
720 dmatest_init_dsts(dst->aligned, dst->off, len,
721 buf_size, is_memset);
722
723 diff = ktime_sub(ktime_get(), start);
724 filltime = ktime_add(filltime, diff);
725 }
726
727 um = dmaengine_get_unmap_data(dev->dev, src->cnt + dst->cnt,
728 GFP_KERNEL);
729 if (!um) {
730 failed_tests++;
731 result("unmap data NULL", total_tests,
732 src->off, dst->off, len, ret);
733 continue;
734 }
735
736 um->len = buf_size;
737 for (i = 0; i < src->cnt; i++) {
738 void *buf = src->aligned[i];
739 struct page *pg = virt_to_page(buf);
740 unsigned long pg_off = offset_in_page(buf);
741
742 um->addr[i] = dma_map_page(dev->dev, pg, pg_off,
743 um->len, DMA_TO_DEVICE);
744 srcs[i] = um->addr[i] + src->off;
745 ret = dma_mapping_error(dev->dev, um->addr[i]);
746 if (ret) {
747 result("src mapping error", total_tests,
748 src->off, dst->off, len, ret);
749 goto error_unmap_continue;
750 }
751 um->to_cnt++;
752 }
753 /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
754 dsts = &um->addr[src->cnt];
755 for (i = 0; i < dst->cnt; i++) {
756 void *buf = dst->aligned[i];
757 struct page *pg = virt_to_page(buf);
758 unsigned long pg_off = offset_in_page(buf);
759
760 dsts[i] = dma_map_page(dev->dev, pg, pg_off, um->len,
761 DMA_BIDIRECTIONAL);
762 ret = dma_mapping_error(dev->dev, dsts[i]);
763 if (ret) {
764 result("dst mapping error", total_tests,
765 src->off, dst->off, len, ret);
766 goto error_unmap_continue;
767 }
768 um->bidi_cnt++;
769 }
770
771 if (thread->type == DMA_MEMCPY)
772 tx = dev->device_prep_dma_memcpy(chan,
773 dsts[0] + dst->off,
774 srcs[0], len, flags);
775 else if (thread->type == DMA_MEMSET)
776 tx = dev->device_prep_dma_memset(chan,
777 dsts[0] + dst->off,
778 *(src->aligned[0] + src->off),
779 len, flags);
780 else if (thread->type == DMA_XOR)
781 tx = dev->device_prep_dma_xor(chan,
782 dsts[0] + dst->off,
783 srcs, src->cnt,
784 len, flags);
785 else if (thread->type == DMA_PQ) {
786 for (i = 0; i < dst->cnt; i++)
787 dma_pq[i] = dsts[i] + dst->off;
788 tx = dev->device_prep_dma_pq(chan, dma_pq, srcs,
789 src->cnt, pq_coefs,
790 len, flags);
791 }
792
793 if (!tx) {
794 result("prep error", total_tests, src->off,
795 dst->off, len, ret);
796 msleep(100);
797 goto error_unmap_continue;
798 }
799
800 done->done = false;
801 if (!params->polled) {
802 tx->callback = dmatest_callback;
803 tx->callback_param = done;
804 }
805 cookie = tx->tx_submit(tx);
806
807 if (dma_submit_error(cookie)) {
808 result("submit error", total_tests, src->off,
809 dst->off, len, ret);
810 msleep(100);
811 goto error_unmap_continue;
812 }
813
814 if (params->polled) {
815 status = dma_sync_wait(chan, cookie);
816 dmaengine_terminate_sync(chan);
817 if (status == DMA_COMPLETE)
818 done->done = true;
819 } else {
820 dma_async_issue_pending(chan);
821
822 wait_event_freezable_timeout(thread->done_wait,
823 done->done,
824 msecs_to_jiffies(params->timeout));
825
826 status = dma_async_is_tx_complete(chan, cookie, NULL,
827 NULL);
828 }
829
830 if (!done->done) {
831 result("test timed out", total_tests, src->off, dst->off,
832 len, 0);
833 goto error_unmap_continue;
834 } else if (status != DMA_COMPLETE &&
835 !(dma_has_cap(DMA_COMPLETION_NO_ORDER,
836 dev->cap_mask) &&
837 status == DMA_OUT_OF_ORDER)) {
838 result(status == DMA_ERROR ?
839 "completion error status" :
840 "completion busy status", total_tests, src->off,
841 dst->off, len, ret);
842 goto error_unmap_continue;
843 }
844
845 dmaengine_unmap_put(um);
846
847 if (params->noverify) {
848 verbose_result("test passed", total_tests, src->off,
849 dst->off, len, 0);
850 continue;
851 }
852
853 start = ktime_get();
854 pr_debug("%s: verifying source buffer...\n", current->comm);
855 error_count = dmatest_verify(src->aligned, 0, src->off,
856 0, PATTERN_SRC, true, is_memset);
857 error_count += dmatest_verify(src->aligned, src->off,
858 src->off + len, src->off,
859 PATTERN_SRC | PATTERN_COPY, true, is_memset);
860 error_count += dmatest_verify(src->aligned, src->off + len,
861 buf_size, src->off + len,
862 PATTERN_SRC, true, is_memset);
863
864 pr_debug("%s: verifying dest buffer...\n", current->comm);
865 error_count += dmatest_verify(dst->aligned, 0, dst->off,
866 0, PATTERN_DST, false, is_memset);
867
868 error_count += dmatest_verify(dst->aligned, dst->off,
869 dst->off + len, src->off,
870 PATTERN_SRC | PATTERN_COPY, false, is_memset);
871
872 error_count += dmatest_verify(dst->aligned, dst->off + len,
873 buf_size, dst->off + len,
874 PATTERN_DST, false, is_memset);
875
876 diff = ktime_sub(ktime_get(), start);
877 comparetime = ktime_add(comparetime, diff);
878
879 if (error_count) {
880 result("data error", total_tests, src->off, dst->off,
881 len, error_count);
882 failed_tests++;
883 } else {
884 verbose_result("test passed", total_tests, src->off,
885 dst->off, len, 0);
886 }
887
888 continue;
889
890error_unmap_continue:
891 dmaengine_unmap_put(um);
892 failed_tests++;
893 }
894 ktime = ktime_sub(ktime_get(), ktime);
895 ktime = ktime_sub(ktime, comparetime);
896 ktime = ktime_sub(ktime, filltime);
897 runtime = ktime_to_us(ktime);
898
899 ret = 0;
900 kfree(dma_pq);
901err_srcs_array:
902 kfree(srcs);
903err_dst:
904 dmatest_free_test_data(dst);
905err_src:
906 dmatest_free_test_data(src);
907err_free_coefs:
908 kfree(pq_coefs);
909err_thread_type:
910 iops = dmatest_persec(runtime, total_tests);
911 pr_info("%s: summary %u tests, %u failures %llu.%02llu iops %llu KB/s (%d)\n",
912 current->comm, total_tests, failed_tests,
913 FIXPT_TO_INT(iops), FIXPT_GET_FRAC(iops),
914 dmatest_KBs(runtime, total_len), ret);
915
916 /* terminate all transfers on specified channels */
917 if (ret || failed_tests)
918 dmaengine_terminate_sync(chan);
919
920 thread->done = true;
921 wake_up(&thread_wait);
922
923 return ret;
924}
925
926static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
927{
928 struct dmatest_thread *thread;
929 struct dmatest_thread *_thread;
930 int ret;
931
932 list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
933 ret = kthread_stop(thread->task);
934 pr_debug("thread %s exited with status %d\n",
935 thread->task->comm, ret);
936 list_del(&thread->node);
937 put_task_struct(thread->task);
938 kfree(thread);
939 }
940
941 /* terminate all transfers on specified channels */
942 dmaengine_terminate_sync(dtc->chan);
943
944 kfree(dtc);
945}
946
947static int dmatest_add_threads(struct dmatest_info *info,
948 struct dmatest_chan *dtc, enum dma_transaction_type type)
949{
950 struct dmatest_params *params = &info->params;
951 struct dmatest_thread *thread;
952 struct dma_chan *chan = dtc->chan;
953 char *op;
954 unsigned int i;
955
956 if (type == DMA_MEMCPY)
957 op = "copy";
958 else if (type == DMA_MEMSET)
959 op = "set";
960 else if (type == DMA_XOR)
961 op = "xor";
962 else if (type == DMA_PQ)
963 op = "pq";
964 else
965 return -EINVAL;
966
967 for (i = 0; i < params->threads_per_chan; i++) {
968 thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
969 if (!thread) {
970 pr_warn("No memory for %s-%s%u\n",
971 dma_chan_name(chan), op, i);
972 break;
973 }
974 thread->info = info;
975 thread->chan = dtc->chan;
976 thread->type = type;
977 thread->test_done.wait = &thread->done_wait;
978 init_waitqueue_head(&thread->done_wait);
979 smp_wmb();
980 thread->task = kthread_create(dmatest_func, thread, "%s-%s%u",
981 dma_chan_name(chan), op, i);
982 if (IS_ERR(thread->task)) {
983 pr_warn("Failed to create thread %s-%s%u\n",
984 dma_chan_name(chan), op, i);
985 kfree(thread);
986 break;
987 }
988
989 /* srcbuf and dstbuf are allocated by the thread itself */
990 get_task_struct(thread->task);
991 list_add_tail(&thread->node, &dtc->threads);
992 thread->pending = true;
993 }
994
995 return i;
996}
997
998static int dmatest_add_channel(struct dmatest_info *info,
999 struct dma_chan *chan)
1000{
1001 struct dmatest_chan *dtc;
1002 struct dma_device *dma_dev = chan->device;
1003 unsigned int thread_count = 0;
1004 int cnt;
1005
1006 dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL);
1007 if (!dtc) {
1008 pr_warn("No memory for %s\n", dma_chan_name(chan));
1009 return -ENOMEM;
1010 }
1011
1012 dtc->chan = chan;
1013 INIT_LIST_HEAD(&dtc->threads);
1014
1015 if (dma_has_cap(DMA_COMPLETION_NO_ORDER, dma_dev->cap_mask) &&
1016 info->params.polled) {
1017 info->params.polled = false;
1018 pr_warn("DMA_COMPLETION_NO_ORDER, polled disabled\n");
1019 }
1020
1021 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1022 if (dmatest == 0) {
1023 cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY);
1024 thread_count += cnt > 0 ? cnt : 0;
1025 }
1026 }
1027
1028 if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
1029 if (dmatest == 1) {
1030 cnt = dmatest_add_threads(info, dtc, DMA_MEMSET);
1031 thread_count += cnt > 0 ? cnt : 0;
1032 }
1033 }
1034
1035 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1036 cnt = dmatest_add_threads(info, dtc, DMA_XOR);
1037 thread_count += cnt > 0 ? cnt : 0;
1038 }
1039 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
1040 cnt = dmatest_add_threads(info, dtc, DMA_PQ);
1041 thread_count += cnt > 0 ? cnt : 0;
1042 }
1043
1044 pr_info("Added %u threads using %s\n",
1045 thread_count, dma_chan_name(chan));
1046
1047 list_add_tail(&dtc->node, &info->channels);
1048 info->nr_channels++;
1049
1050 return 0;
1051}
1052
1053static bool filter(struct dma_chan *chan, void *param)
1054{
1055 struct dmatest_params *params = param;
1056
1057 if (!dmatest_match_channel(params, chan) ||
1058 !dmatest_match_device(params, chan->device))
1059 return false;
1060 else
1061 return true;
1062}
1063
1064static void request_channels(struct dmatest_info *info,
1065 enum dma_transaction_type type)
1066{
1067 dma_cap_mask_t mask;
1068
1069 dma_cap_zero(mask);
1070 dma_cap_set(type, mask);
1071 for (;;) {
1072 struct dmatest_params *params = &info->params;
1073 struct dma_chan *chan;
1074
1075 chan = dma_request_channel(mask, filter, params);
1076 if (chan) {
1077 if (dmatest_add_channel(info, chan)) {
1078 dma_release_channel(chan);
1079 break; /* add_channel failed, punt */
1080 }
1081 } else
1082 break; /* no more channels available */
1083 if (params->max_channels &&
1084 info->nr_channels >= params->max_channels)
1085 break; /* we have all we need */
1086 }
1087}
1088
1089static void add_threaded_test(struct dmatest_info *info)
1090{
1091 struct dmatest_params *params = &info->params;
1092
1093 /* Copy test parameters */
1094 params->buf_size = test_buf_size;
1095 strlcpy(params->channel, strim(test_channel), sizeof(params->channel));
1096 strlcpy(params->device, strim(test_device), sizeof(params->device));
1097 params->threads_per_chan = threads_per_chan;
1098 params->max_channels = max_channels;
1099 params->iterations = iterations;
1100 params->xor_sources = xor_sources;
1101 params->pq_sources = pq_sources;
1102 params->timeout = timeout;
1103 params->noverify = noverify;
1104 params->norandom = norandom;
1105 params->alignment = alignment;
1106 params->transfer_size = transfer_size;
1107 params->polled = polled;
1108
1109 request_channels(info, DMA_MEMCPY);
1110 request_channels(info, DMA_MEMSET);
1111 request_channels(info, DMA_XOR);
1112 request_channels(info, DMA_PQ);
1113}
1114
1115static void run_pending_tests(struct dmatest_info *info)
1116{
1117 struct dmatest_chan *dtc;
1118 unsigned int thread_count = 0;
1119
1120 list_for_each_entry(dtc, &info->channels, node) {
1121 struct dmatest_thread *thread;
1122
1123 thread_count = 0;
1124 list_for_each_entry(thread, &dtc->threads, node) {
1125 wake_up_process(thread->task);
1126 thread_count++;
1127 }
1128 pr_info("Started %u threads using %s\n",
1129 thread_count, dma_chan_name(dtc->chan));
1130 }
1131}
1132
1133static void stop_threaded_test(struct dmatest_info *info)
1134{
1135 struct dmatest_chan *dtc, *_dtc;
1136 struct dma_chan *chan;
1137
1138 list_for_each_entry_safe(dtc, _dtc, &info->channels, node) {
1139 list_del(&dtc->node);
1140 chan = dtc->chan;
1141 dmatest_cleanup_channel(dtc);
1142 pr_debug("dropped channel %s\n", dma_chan_name(chan));
1143 dma_release_channel(chan);
1144 }
1145
1146 info->nr_channels = 0;
1147}
1148
1149static void start_threaded_tests(struct dmatest_info *info)
1150{
1151 /* we might be called early to set run=, defer running until all
1152 * parameters have been evaluated
1153 */
1154 if (!info->did_init)
1155 return;
1156
1157 run_pending_tests(info);
1158}
1159
1160static int dmatest_run_get(char *val, const struct kernel_param *kp)
1161{
1162 struct dmatest_info *info = &test_info;
1163
1164 mutex_lock(&info->lock);
1165 if (is_threaded_test_run(info)) {
1166 dmatest_run = true;
1167 } else {
1168 if (!is_threaded_test_pending(info))
1169 stop_threaded_test(info);
1170 dmatest_run = false;
1171 }
1172 mutex_unlock(&info->lock);
1173
1174 return param_get_bool(val, kp);
1175}
1176
1177static int dmatest_run_set(const char *val, const struct kernel_param *kp)
1178{
1179 struct dmatest_info *info = &test_info;
1180 int ret;
1181
1182 mutex_lock(&info->lock);
1183 ret = param_set_bool(val, kp);
1184 if (ret) {
1185 mutex_unlock(&info->lock);
1186 return ret;
1187 } else if (dmatest_run) {
1188 if (!is_threaded_test_pending(info)) {
1189 /*
1190 * We have nothing to run. This can be due to:
1191 */
1192 ret = info->last_error;
1193 if (ret) {
1194 /* 1) Misconfiguration */
1195 pr_err("Channel misconfigured, can't continue\n");
1196 mutex_unlock(&info->lock);
1197 return ret;
1198 } else {
1199 /* 2) We rely on defaults */
1200 pr_info("No channels configured, continue with any\n");
1201 if (!is_threaded_test_run(info))
1202 stop_threaded_test(info);
1203 add_threaded_test(info);
1204 }
1205 }
1206 start_threaded_tests(info);
1207 } else {
1208 stop_threaded_test(info);
1209 }
1210
1211 mutex_unlock(&info->lock);
1212
1213 return ret;
1214}
1215
1216static int dmatest_chan_set(const char *val, const struct kernel_param *kp)
1217{
1218 struct dmatest_info *info = &test_info;
1219 struct dmatest_chan *dtc;
1220 char chan_reset_val[20];
1221 int ret;
1222
1223 mutex_lock(&info->lock);
1224 ret = param_set_copystring(val, kp);
1225 if (ret) {
1226 mutex_unlock(&info->lock);
1227 return ret;
1228 }
1229 /*Clear any previously run threads */
1230 if (!is_threaded_test_run(info) && !is_threaded_test_pending(info))
1231 stop_threaded_test(info);
1232 /* Reject channels that are already registered */
1233 if (is_threaded_test_pending(info)) {
1234 list_for_each_entry(dtc, &info->channels, node) {
1235 if (strcmp(dma_chan_name(dtc->chan),
1236 strim(test_channel)) == 0) {
1237 dtc = list_last_entry(&info->channels,
1238 struct dmatest_chan,
1239 node);
1240 strlcpy(chan_reset_val,
1241 dma_chan_name(dtc->chan),
1242 sizeof(chan_reset_val));
1243 ret = -EBUSY;
1244 goto add_chan_err;
1245 }
1246 }
1247 }
1248
1249 add_threaded_test(info);
1250
1251 /* Check if channel was added successfully */
1252 dtc = list_last_entry(&info->channels, struct dmatest_chan, node);
1253
1254 if (dtc->chan) {
1255 /*
1256 * if new channel was not successfully added, revert the
1257 * "test_channel" string to the name of the last successfully
1258 * added channel. exception for when users issues empty string
1259 * to channel parameter.
1260 */
1261 if ((strcmp(dma_chan_name(dtc->chan), strim(test_channel)) != 0)
1262 && (strcmp("", strim(test_channel)) != 0)) {
1263 ret = -EINVAL;
1264 strlcpy(chan_reset_val, dma_chan_name(dtc->chan),
1265 sizeof(chan_reset_val));
1266 goto add_chan_err;
1267 }
1268
1269 } else {
1270 /* Clear test_channel if no channels were added successfully */
1271 strlcpy(chan_reset_val, "", sizeof(chan_reset_val));
1272 ret = -EBUSY;
1273 goto add_chan_err;
1274 }
1275
1276 info->last_error = ret;
1277 mutex_unlock(&info->lock);
1278
1279 return ret;
1280
1281add_chan_err:
1282 param_set_copystring(chan_reset_val, kp);
1283 info->last_error = ret;
1284 mutex_unlock(&info->lock);
1285
1286 return ret;
1287}
1288
1289static int dmatest_chan_get(char *val, const struct kernel_param *kp)
1290{
1291 struct dmatest_info *info = &test_info;
1292
1293 mutex_lock(&info->lock);
1294 if (!is_threaded_test_run(info) && !is_threaded_test_pending(info)) {
1295 stop_threaded_test(info);
1296 strlcpy(test_channel, "", sizeof(test_channel));
1297 }
1298 mutex_unlock(&info->lock);
1299
1300 return param_get_string(val, kp);
1301}
1302
1303static int dmatest_test_list_get(char *val, const struct kernel_param *kp)
1304{
1305 struct dmatest_info *info = &test_info;
1306 struct dmatest_chan *dtc;
1307 unsigned int thread_count = 0;
1308
1309 list_for_each_entry(dtc, &info->channels, node) {
1310 struct dmatest_thread *thread;
1311
1312 thread_count = 0;
1313 list_for_each_entry(thread, &dtc->threads, node) {
1314 thread_count++;
1315 }
1316 pr_info("%u threads using %s\n",
1317 thread_count, dma_chan_name(dtc->chan));
1318 }
1319
1320 return 0;
1321}
1322
1323static int __init dmatest_init(void)
1324{
1325 struct dmatest_info *info = &test_info;
1326 struct dmatest_params *params = &info->params;
1327
1328 if (dmatest_run) {
1329 mutex_lock(&info->lock);
1330 add_threaded_test(info);
1331 run_pending_tests(info);
1332 mutex_unlock(&info->lock);
1333 }
1334
1335 if (params->iterations && wait)
1336 wait_event(thread_wait, !is_threaded_test_run(info));
1337
1338 /* module parameters are stable, inittime tests are started,
1339 * let userspace take over 'run' control
1340 */
1341 info->did_init = true;
1342
1343 return 0;
1344}
1345/* when compiled-in wait for drivers to load first */
1346late_initcall(dmatest_init);
1347
1348static void __exit dmatest_exit(void)
1349{
1350 struct dmatest_info *info = &test_info;
1351
1352 mutex_lock(&info->lock);
1353 stop_threaded_test(info);
1354 mutex_unlock(&info->lock);
1355}
1356module_exit(dmatest_exit);
1357
1358MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1359MODULE_LICENSE("GPL v2");