Loading...
1/*
2 * TLB Management (flush/create/diagnostics) for ARC700
3 *
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * vineetg: Aug 2011
11 * -Reintroduce duplicate PD fixup - some customer chips still have the issue
12 *
13 * vineetg: May 2011
14 * -No need to flush_cache_page( ) for each call to update_mmu_cache()
15 * some of the LMBench tests improved amazingly
16 * = page-fault thrice as fast (75 usec to 28 usec)
17 * = mmap twice as fast (9.6 msec to 4.6 msec),
18 * = fork (5.3 msec to 3.7 msec)
19 *
20 * vineetg: April 2011 :
21 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
22 * helps avoid a shift when preparing PD0 from PTE
23 *
24 * vineetg: April 2011 : Preparing for MMU V3
25 * -MMU v2/v3 BCRs decoded differently
26 * -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
27 * -tlb_entry_erase( ) can be void
28 * -local_flush_tlb_range( ):
29 * = need not "ceil" @end
30 * = walks MMU only if range spans < 32 entries, as opposed to 256
31 *
32 * Vineetg: Sept 10th 2008
33 * -Changes related to MMU v2 (Rel 4.8)
34 *
35 * Vineetg: Aug 29th 2008
36 * -In TLB Flush operations (Metal Fix MMU) there is a explict command to
37 * flush Micro-TLBS. If TLB Index Reg is invalid prior to TLBIVUTLB cmd,
38 * it fails. Thus need to load it with ANY valid value before invoking
39 * TLBIVUTLB cmd
40 *
41 * Vineetg: Aug 21th 2008:
42 * -Reduced the duration of IRQ lockouts in TLB Flush routines
43 * -Multiple copies of TLB erase code seperated into a "single" function
44 * -In TLB Flush routines, interrupt disabling moved UP to retrieve ASID
45 * in interrupt-safe region.
46 *
47 * Vineetg: April 23rd Bug #93131
48 * Problem: tlb_flush_kernel_range() doesnt do anything if the range to
49 * flush is more than the size of TLB itself.
50 *
51 * Rahul Trivedi : Codito Technologies 2004
52 */
53
54#include <linux/module.h>
55#include <linux/bug.h>
56#include <asm/arcregs.h>
57#include <asm/setup.h>
58#include <asm/mmu_context.h>
59#include <asm/mmu.h>
60
61/* Need for ARC MMU v2
62 *
63 * ARC700 MMU-v1 had a Joint-TLB for Code and Data and is 2 way set-assoc.
64 * For a memcpy operation with 3 players (src/dst/code) such that all 3 pages
65 * map into same set, there would be contention for the 2 ways causing severe
66 * Thrashing.
67 *
68 * Although J-TLB is 2 way set assoc, ARC700 caches J-TLB into uTLBS which has
69 * much higher associativity. u-D-TLB is 8 ways, u-I-TLB is 4 ways.
70 * Given this, the thrasing problem should never happen because once the 3
71 * J-TLB entries are created (even though 3rd will knock out one of the prev
72 * two), the u-D-TLB and u-I-TLB will have what is required to accomplish memcpy
73 *
74 * Yet we still see the Thrashing because a J-TLB Write cause flush of u-TLBs.
75 * This is a simple design for keeping them in sync. So what do we do?
76 * The solution which James came up was pretty neat. It utilised the assoc
77 * of uTLBs by not invalidating always but only when absolutely necessary.
78 *
79 * - Existing TLB commands work as before
80 * - New command (TLBWriteNI) for TLB write without clearing uTLBs
81 * - New command (TLBIVUTLB) to invalidate uTLBs.
82 *
83 * The uTLBs need only be invalidated when pages are being removed from the
84 * OS page table. If a 'victim' TLB entry is being overwritten in the main TLB
85 * as a result of a miss, the removed entry is still allowed to exist in the
86 * uTLBs as it is still valid and present in the OS page table. This allows the
87 * full associativity of the uTLBs to hide the limited associativity of the main
88 * TLB.
89 *
90 * During a miss handler, the new "TLBWriteNI" command is used to load
91 * entries without clearing the uTLBs.
92 *
93 * When the OS page table is updated, TLB entries that may be associated with a
94 * removed page are removed (flushed) from the TLB using TLBWrite. In this
95 * circumstance, the uTLBs must also be cleared. This is done by using the
96 * existing TLBWrite command. An explicit IVUTLB is also required for those
97 * corner cases when TLBWrite was not executed at all because the corresp
98 * J-TLB entry got evicted/replaced.
99 */
100
101
102/* A copy of the ASID from the PID reg is kept in asid_cache */
103DEFINE_PER_CPU(unsigned int, asid_cache) = MM_CTXT_FIRST_CYCLE;
104
105/*
106 * Utility Routine to erase a J-TLB entry
107 * Caller needs to setup Index Reg (manually or via getIndex)
108 */
109static inline void __tlb_entry_erase(void)
110{
111 write_aux_reg(ARC_REG_TLBPD1, 0);
112 write_aux_reg(ARC_REG_TLBPD0, 0);
113 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
114}
115
116static inline unsigned int tlb_entry_lkup(unsigned long vaddr_n_asid)
117{
118 unsigned int idx;
119
120 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid);
121
122 write_aux_reg(ARC_REG_TLBCOMMAND, TLBProbe);
123 idx = read_aux_reg(ARC_REG_TLBINDEX);
124
125 return idx;
126}
127
128static void tlb_entry_erase(unsigned int vaddr_n_asid)
129{
130 unsigned int idx;
131
132 /* Locate the TLB entry for this vaddr + ASID */
133 idx = tlb_entry_lkup(vaddr_n_asid);
134
135 /* No error means entry found, zero it out */
136 if (likely(!(idx & TLB_LKUP_ERR))) {
137 __tlb_entry_erase();
138 } else {
139 /* Duplicate entry error */
140 WARN(idx == TLB_DUP_ERR, "Probe returned Dup PD for %x\n",
141 vaddr_n_asid);
142 }
143}
144
145/****************************************************************************
146 * ARC700 MMU caches recently used J-TLB entries (RAM) as uTLBs (FLOPs)
147 *
148 * New IVUTLB cmd in MMU v2 explictly invalidates the uTLB
149 *
150 * utlb_invalidate ( )
151 * -For v2 MMU calls Flush uTLB Cmd
152 * -For v1 MMU does nothing (except for Metal Fix v1 MMU)
153 * This is because in v1 TLBWrite itself invalidate uTLBs
154 ***************************************************************************/
155
156static void utlb_invalidate(void)
157{
158#if (CONFIG_ARC_MMU_VER >= 2)
159
160#if (CONFIG_ARC_MMU_VER == 2)
161 /* MMU v2 introduced the uTLB Flush command.
162 * There was however an obscure hardware bug, where uTLB flush would
163 * fail when a prior probe for J-TLB (both totally unrelated) would
164 * return lkup err - because the entry didnt exist in MMU.
165 * The Workround was to set Index reg with some valid value, prior to
166 * flush. This was fixed in MMU v3 hence not needed any more
167 */
168 unsigned int idx;
169
170 /* make sure INDEX Reg is valid */
171 idx = read_aux_reg(ARC_REG_TLBINDEX);
172
173 /* If not write some dummy val */
174 if (unlikely(idx & TLB_LKUP_ERR))
175 write_aux_reg(ARC_REG_TLBINDEX, 0xa);
176#endif
177
178 write_aux_reg(ARC_REG_TLBCOMMAND, TLBIVUTLB);
179#endif
180
181}
182
183static void tlb_entry_insert(unsigned int pd0, unsigned int pd1)
184{
185 unsigned int idx;
186
187 /*
188 * First verify if entry for this vaddr+ASID already exists
189 * This also sets up PD0 (vaddr, ASID..) for final commit
190 */
191 idx = tlb_entry_lkup(pd0);
192
193 /*
194 * If Not already present get a free slot from MMU.
195 * Otherwise, Probe would have located the entry and set INDEX Reg
196 * with existing location. This will cause Write CMD to over-write
197 * existing entry with new PD0 and PD1
198 */
199 if (likely(idx & TLB_LKUP_ERR))
200 write_aux_reg(ARC_REG_TLBCOMMAND, TLBGetIndex);
201
202 /* setup the other half of TLB entry (pfn, rwx..) */
203 write_aux_reg(ARC_REG_TLBPD1, pd1);
204
205 /*
206 * Commit the Entry to MMU
207 * It doesnt sound safe to use the TLBWriteNI cmd here
208 * which doesn't flush uTLBs. I'd rather be safe than sorry.
209 */
210 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
211}
212
213/*
214 * Un-conditionally (without lookup) erase the entire MMU contents
215 */
216
217noinline void local_flush_tlb_all(void)
218{
219 unsigned long flags;
220 unsigned int entry;
221 struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
222
223 local_irq_save(flags);
224
225 /* Load PD0 and PD1 with template for a Blank Entry */
226 write_aux_reg(ARC_REG_TLBPD1, 0);
227 write_aux_reg(ARC_REG_TLBPD0, 0);
228
229 for (entry = 0; entry < mmu->num_tlb; entry++) {
230 /* write this entry to the TLB */
231 write_aux_reg(ARC_REG_TLBINDEX, entry);
232 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
233 }
234
235 utlb_invalidate();
236
237 local_irq_restore(flags);
238}
239
240/*
241 * Flush the entrie MM for userland. The fastest way is to move to Next ASID
242 */
243noinline void local_flush_tlb_mm(struct mm_struct *mm)
244{
245 /*
246 * Small optimisation courtesy IA64
247 * flush_mm called during fork,exit,munmap etc, multiple times as well.
248 * Only for fork( ) do we need to move parent to a new MMU ctxt,
249 * all other cases are NOPs, hence this check.
250 */
251 if (atomic_read(&mm->mm_users) == 0)
252 return;
253
254 /*
255 * - Move to a new ASID, but only if the mm is still wired in
256 * (Android Binder ended up calling this for vma->mm != tsk->mm,
257 * causing h/w - s/w ASID to get out of sync)
258 * - Also get_new_mmu_context() new implementation allocates a new
259 * ASID only if it is not allocated already - so unallocate first
260 */
261 destroy_context(mm);
262 if (current->mm == mm)
263 get_new_mmu_context(mm);
264}
265
266/*
267 * Flush a Range of TLB entries for userland.
268 * @start is inclusive, while @end is exclusive
269 * Difference between this and Kernel Range Flush is
270 * -Here the fastest way (if range is too large) is to move to next ASID
271 * without doing any explicit Shootdown
272 * -In case of kernel Flush, entry has to be shot down explictly
273 */
274void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
275 unsigned long end)
276{
277 const unsigned int cpu = smp_processor_id();
278 unsigned long flags;
279
280 /* If range @start to @end is more than 32 TLB entries deep,
281 * its better to move to a new ASID rather than searching for
282 * individual entries and then shooting them down
283 *
284 * The calc above is rough, doesn't account for unaligned parts,
285 * since this is heuristics based anyways
286 */
287 if (unlikely((end - start) >= PAGE_SIZE * 32)) {
288 local_flush_tlb_mm(vma->vm_mm);
289 return;
290 }
291
292 /*
293 * @start moved to page start: this alone suffices for checking
294 * loop end condition below, w/o need for aligning @end to end
295 * e.g. 2000 to 4001 will anyhow loop twice
296 */
297 start &= PAGE_MASK;
298
299 local_irq_save(flags);
300
301 if (asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID) {
302 while (start < end) {
303 tlb_entry_erase(start | hw_pid(vma->vm_mm, cpu));
304 start += PAGE_SIZE;
305 }
306 }
307
308 utlb_invalidate();
309
310 local_irq_restore(flags);
311}
312
313/* Flush the kernel TLB entries - vmalloc/modules (Global from MMU perspective)
314 * @start, @end interpreted as kvaddr
315 * Interestingly, shared TLB entries can also be flushed using just
316 * @start,@end alone (interpreted as user vaddr), although technically SASID
317 * is also needed. However our smart TLbProbe lookup takes care of that.
318 */
319void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
320{
321 unsigned long flags;
322
323 /* exactly same as above, except for TLB entry not taking ASID */
324
325 if (unlikely((end - start) >= PAGE_SIZE * 32)) {
326 local_flush_tlb_all();
327 return;
328 }
329
330 start &= PAGE_MASK;
331
332 local_irq_save(flags);
333 while (start < end) {
334 tlb_entry_erase(start);
335 start += PAGE_SIZE;
336 }
337
338 utlb_invalidate();
339
340 local_irq_restore(flags);
341}
342
343/*
344 * Delete TLB entry in MMU for a given page (??? address)
345 * NOTE One TLB entry contains translation for single PAGE
346 */
347
348void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
349{
350 const unsigned int cpu = smp_processor_id();
351 unsigned long flags;
352
353 /* Note that it is critical that interrupts are DISABLED between
354 * checking the ASID and using it flush the TLB entry
355 */
356 local_irq_save(flags);
357
358 if (asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID) {
359 tlb_entry_erase((page & PAGE_MASK) | hw_pid(vma->vm_mm, cpu));
360 utlb_invalidate();
361 }
362
363 local_irq_restore(flags);
364}
365
366#ifdef CONFIG_SMP
367
368struct tlb_args {
369 struct vm_area_struct *ta_vma;
370 unsigned long ta_start;
371 unsigned long ta_end;
372};
373
374static inline void ipi_flush_tlb_page(void *arg)
375{
376 struct tlb_args *ta = arg;
377
378 local_flush_tlb_page(ta->ta_vma, ta->ta_start);
379}
380
381static inline void ipi_flush_tlb_range(void *arg)
382{
383 struct tlb_args *ta = arg;
384
385 local_flush_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end);
386}
387
388static inline void ipi_flush_tlb_kernel_range(void *arg)
389{
390 struct tlb_args *ta = (struct tlb_args *)arg;
391
392 local_flush_tlb_kernel_range(ta->ta_start, ta->ta_end);
393}
394
395void flush_tlb_all(void)
396{
397 on_each_cpu((smp_call_func_t)local_flush_tlb_all, NULL, 1);
398}
399
400void flush_tlb_mm(struct mm_struct *mm)
401{
402 on_each_cpu_mask(mm_cpumask(mm), (smp_call_func_t)local_flush_tlb_mm,
403 mm, 1);
404}
405
406void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
407{
408 struct tlb_args ta = {
409 .ta_vma = vma,
410 .ta_start = uaddr
411 };
412
413 on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_page, &ta, 1);
414}
415
416void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
417 unsigned long end)
418{
419 struct tlb_args ta = {
420 .ta_vma = vma,
421 .ta_start = start,
422 .ta_end = end
423 };
424
425 on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_range, &ta, 1);
426}
427
428void flush_tlb_kernel_range(unsigned long start, unsigned long end)
429{
430 struct tlb_args ta = {
431 .ta_start = start,
432 .ta_end = end
433 };
434
435 on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
436}
437#endif
438
439/*
440 * Routine to create a TLB entry
441 */
442void create_tlb(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
443{
444 unsigned long flags;
445 unsigned int asid_or_sasid, rwx;
446 unsigned long pd0, pd1;
447
448 /*
449 * create_tlb() assumes that current->mm == vma->mm, since
450 * -it ASID for TLB entry is fetched from MMU ASID reg (valid for curr)
451 * -completes the lazy write to SASID reg (again valid for curr tsk)
452 *
453 * Removing the assumption involves
454 * -Using vma->mm->context{ASID,SASID}, as opposed to MMU reg.
455 * -Fix the TLB paranoid debug code to not trigger false negatives.
456 * -More importantly it makes this handler inconsistent with fast-path
457 * TLB Refill handler which always deals with "current"
458 *
459 * Lets see the use cases when current->mm != vma->mm and we land here
460 * 1. execve->copy_strings()->__get_user_pages->handle_mm_fault
461 * Here VM wants to pre-install a TLB entry for user stack while
462 * current->mm still points to pre-execve mm (hence the condition).
463 * However the stack vaddr is soon relocated (randomization) and
464 * move_page_tables() tries to undo that TLB entry.
465 * Thus not creating TLB entry is not any worse.
466 *
467 * 2. ptrace(POKETEXT) causes a CoW - debugger(current) inserting a
468 * breakpoint in debugged task. Not creating a TLB now is not
469 * performance critical.
470 *
471 * Both the cases above are not good enough for code churn.
472 */
473 if (current->active_mm != vma->vm_mm)
474 return;
475
476 local_irq_save(flags);
477
478 tlb_paranoid_check(asid_mm(vma->vm_mm, smp_processor_id()), address);
479
480 address &= PAGE_MASK;
481
482 /* update this PTE credentials */
483 pte_val(*ptep) |= (_PAGE_PRESENT | _PAGE_ACCESSED);
484
485 /* Create HW TLB(PD0,PD1) from PTE */
486
487 /* ASID for this task */
488 asid_or_sasid = read_aux_reg(ARC_REG_PID) & 0xff;
489
490 pd0 = address | asid_or_sasid | (pte_val(*ptep) & PTE_BITS_IN_PD0);
491
492 /*
493 * ARC MMU provides fully orthogonal access bits for K/U mode,
494 * however Linux only saves 1 set to save PTE real-estate
495 * Here we convert 3 PTE bits into 6 MMU bits:
496 * -Kernel only entries have Kr Kw Kx 0 0 0
497 * -User entries have mirrored K and U bits
498 */
499 rwx = pte_val(*ptep) & PTE_BITS_RWX;
500
501 if (pte_val(*ptep) & _PAGE_GLOBAL)
502 rwx <<= 3; /* r w x => Kr Kw Kx 0 0 0 */
503 else
504 rwx |= (rwx << 3); /* r w x => Kr Kw Kx Ur Uw Ux */
505
506 pd1 = rwx | (pte_val(*ptep) & PTE_BITS_NON_RWX_IN_PD1);
507
508 tlb_entry_insert(pd0, pd1);
509
510 local_irq_restore(flags);
511}
512
513/*
514 * Called at the end of pagefault, for a userspace mapped page
515 * -pre-install the corresponding TLB entry into MMU
516 * -Finalize the delayed D-cache flush of kernel mapping of page due to
517 * flush_dcache_page(), copy_user_page()
518 *
519 * Note that flush (when done) involves both WBACK - so physical page is
520 * in sync as well as INV - so any non-congruent aliases don't remain
521 */
522void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
523 pte_t *ptep)
524{
525 unsigned long vaddr = vaddr_unaligned & PAGE_MASK;
526 unsigned long paddr = pte_val(*ptep) & PAGE_MASK;
527 struct page *page = pfn_to_page(pte_pfn(*ptep));
528
529 create_tlb(vma, vaddr, ptep);
530
531 if (page == ZERO_PAGE(0)) {
532 return;
533 }
534
535 /*
536 * Exec page : Independent of aliasing/page-color considerations,
537 * since icache doesn't snoop dcache on ARC, any dirty
538 * K-mapping of a code page needs to be wback+inv so that
539 * icache fetch by userspace sees code correctly.
540 * !EXEC page: If K-mapping is NOT congruent to U-mapping, flush it
541 * so userspace sees the right data.
542 * (Avoids the flush for Non-exec + congruent mapping case)
543 */
544 if ((vma->vm_flags & VM_EXEC) ||
545 addr_not_cache_congruent(paddr, vaddr)) {
546
547 int dirty = !test_and_set_bit(PG_dc_clean, &page->flags);
548 if (dirty) {
549 /* wback + inv dcache lines */
550 __flush_dcache_page(paddr, paddr);
551
552 /* invalidate any existing icache lines */
553 if (vma->vm_flags & VM_EXEC)
554 __inv_icache_page(paddr, vaddr);
555 }
556 }
557}
558
559/* Read the Cache Build Confuration Registers, Decode them and save into
560 * the cpuinfo structure for later use.
561 * No Validation is done here, simply read/convert the BCRs
562 */
563void read_decode_mmu_bcr(void)
564{
565 struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
566 unsigned int tmp;
567 struct bcr_mmu_1_2 {
568#ifdef CONFIG_CPU_BIG_ENDIAN
569 unsigned int ver:8, ways:4, sets:4, u_itlb:8, u_dtlb:8;
570#else
571 unsigned int u_dtlb:8, u_itlb:8, sets:4, ways:4, ver:8;
572#endif
573 } *mmu2;
574
575 struct bcr_mmu_3 {
576#ifdef CONFIG_CPU_BIG_ENDIAN
577 unsigned int ver:8, ways:4, sets:4, osm:1, reserv:3, pg_sz:4,
578 u_itlb:4, u_dtlb:4;
579#else
580 unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, reserv:3, osm:1, sets:4,
581 ways:4, ver:8;
582#endif
583 } *mmu3;
584
585 tmp = read_aux_reg(ARC_REG_MMU_BCR);
586 mmu->ver = (tmp >> 24);
587
588 if (mmu->ver <= 2) {
589 mmu2 = (struct bcr_mmu_1_2 *)&tmp;
590 mmu->pg_sz = PAGE_SIZE;
591 mmu->sets = 1 << mmu2->sets;
592 mmu->ways = 1 << mmu2->ways;
593 mmu->u_dtlb = mmu2->u_dtlb;
594 mmu->u_itlb = mmu2->u_itlb;
595 } else {
596 mmu3 = (struct bcr_mmu_3 *)&tmp;
597 mmu->pg_sz = 512 << mmu3->pg_sz;
598 mmu->sets = 1 << mmu3->sets;
599 mmu->ways = 1 << mmu3->ways;
600 mmu->u_dtlb = mmu3->u_dtlb;
601 mmu->u_itlb = mmu3->u_itlb;
602 }
603
604 mmu->num_tlb = mmu->sets * mmu->ways;
605}
606
607char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len)
608{
609 int n = 0;
610 struct cpuinfo_arc_mmu *p_mmu = &cpuinfo_arc700[cpu_id].mmu;
611
612 n += scnprintf(buf + n, len - n, "ARC700 MMU [v%x]\t: %dk PAGE, ",
613 p_mmu->ver, TO_KB(p_mmu->pg_sz));
614
615 n += scnprintf(buf + n, len - n,
616 "J-TLB %d (%dx%d), uDTLB %d, uITLB %d, %s\n",
617 p_mmu->num_tlb, p_mmu->sets, p_mmu->ways,
618 p_mmu->u_dtlb, p_mmu->u_itlb,
619 IS_ENABLED(CONFIG_ARC_MMU_SASID) ? "SASID" : "");
620
621 return buf;
622}
623
624void arc_mmu_init(void)
625{
626 char str[256];
627 struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
628
629 printk(arc_mmu_mumbojumbo(0, str, sizeof(str)));
630
631 /* For efficiency sake, kernel is compile time built for a MMU ver
632 * This must match the hardware it is running on.
633 * Linux built for MMU V2, if run on MMU V1 will break down because V1
634 * hardware doesn't understand cmds such as WriteNI, or IVUTLB
635 * On the other hand, Linux built for V1 if run on MMU V2 will do
636 * un-needed workarounds to prevent memcpy thrashing.
637 * Similarly MMU V3 has new features which won't work on older MMU
638 */
639 if (mmu->ver != CONFIG_ARC_MMU_VER) {
640 panic("MMU ver %d doesn't match kernel built for %d...\n",
641 mmu->ver, CONFIG_ARC_MMU_VER);
642 }
643
644 if (mmu->pg_sz != PAGE_SIZE)
645 panic("MMU pg size != PAGE_SIZE (%luk)\n", TO_KB(PAGE_SIZE));
646
647 /* Enable the MMU */
648 write_aux_reg(ARC_REG_PID, MMU_ENABLE);
649
650 /* In smp we use this reg for interrupt 1 scratch */
651#ifndef CONFIG_SMP
652 /* swapper_pg_dir is the pgd for the kernel, used by vmalloc */
653 write_aux_reg(ARC_REG_SCRATCH_DATA0, swapper_pg_dir);
654#endif
655}
656
657/*
658 * TLB Programmer's Model uses Linear Indexes: 0 to {255, 511} for 128 x {2,4}
659 * The mapping is Column-first.
660 * --------------------- -----------
661 * |way0|way1|way2|way3| |way0|way1|
662 * --------------------- -----------
663 * [set0] | 0 | 1 | 2 | 3 | | 0 | 1 |
664 * [set1] | 4 | 5 | 6 | 7 | | 2 | 3 |
665 * ~ ~ ~ ~
666 * [set127] | 508| 509| 510| 511| | 254| 255|
667 * --------------------- -----------
668 * For normal operations we don't(must not) care how above works since
669 * MMU cmd getIndex(vaddr) abstracts that out.
670 * However for walking WAYS of a SET, we need to know this
671 */
672#define SET_WAY_TO_IDX(mmu, set, way) ((set) * mmu->ways + (way))
673
674/* Handling of Duplicate PD (TLB entry) in MMU.
675 * -Could be due to buggy customer tapeouts or obscure kernel bugs
676 * -MMU complaints not at the time of duplicate PD installation, but at the
677 * time of lookup matching multiple ways.
678 * -Ideally these should never happen - but if they do - workaround by deleting
679 * the duplicate one.
680 * -Knob to be verbose abt it.(TODO: hook them up to debugfs)
681 */
682volatile int dup_pd_verbose = 1;/* Be slient abt it or complain (default) */
683
684void do_tlb_overlap_fault(unsigned long cause, unsigned long address,
685 struct pt_regs *regs)
686{
687 int set, way, n;
688 unsigned long flags, is_valid;
689 struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
690 unsigned int pd0[mmu->ways], pd1[mmu->ways];
691
692 local_irq_save(flags);
693
694 /* re-enable the MMU */
695 write_aux_reg(ARC_REG_PID, MMU_ENABLE | read_aux_reg(ARC_REG_PID));
696
697 /* loop thru all sets of TLB */
698 for (set = 0; set < mmu->sets; set++) {
699
700 /* read out all the ways of current set */
701 for (way = 0, is_valid = 0; way < mmu->ways; way++) {
702 write_aux_reg(ARC_REG_TLBINDEX,
703 SET_WAY_TO_IDX(mmu, set, way));
704 write_aux_reg(ARC_REG_TLBCOMMAND, TLBRead);
705 pd0[way] = read_aux_reg(ARC_REG_TLBPD0);
706 pd1[way] = read_aux_reg(ARC_REG_TLBPD1);
707 is_valid |= pd0[way] & _PAGE_PRESENT;
708 }
709
710 /* If all the WAYS in SET are empty, skip to next SET */
711 if (!is_valid)
712 continue;
713
714 /* Scan the set for duplicate ways: needs a nested loop */
715 for (way = 0; way < mmu->ways - 1; way++) {
716 if (!pd0[way])
717 continue;
718
719 for (n = way + 1; n < mmu->ways; n++) {
720 if ((pd0[way] & PAGE_MASK) ==
721 (pd0[n] & PAGE_MASK)) {
722
723 if (dup_pd_verbose) {
724 pr_info("Duplicate PD's @"
725 "[%d:%d]/[%d:%d]\n",
726 set, way, set, n);
727 pr_info("TLBPD0[%u]: %08x\n",
728 way, pd0[way]);
729 }
730
731 /*
732 * clear entry @way and not @n. This is
733 * critical to our optimised loop
734 */
735 pd0[way] = pd1[way] = 0;
736 write_aux_reg(ARC_REG_TLBINDEX,
737 SET_WAY_TO_IDX(mmu, set, way));
738 __tlb_entry_erase();
739 }
740 }
741 }
742 }
743
744 local_irq_restore(flags);
745}
746
747/***********************************************************************
748 * Diagnostic Routines
749 * -Called from Low Level TLB Hanlders if things don;t look good
750 **********************************************************************/
751
752#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
753
754/*
755 * Low Level ASM TLB handler calls this if it finds that HW and SW ASIDS
756 * don't match
757 */
758void print_asid_mismatch(int mm_asid, int mmu_asid, int is_fast_path)
759{
760 pr_emerg("ASID Mismatch in %s Path Handler: sw-pid=0x%x hw-pid=0x%x\n",
761 is_fast_path ? "Fast" : "Slow", mm_asid, mmu_asid);
762
763 __asm__ __volatile__("flag 1");
764}
765
766void tlb_paranoid_check(unsigned int mm_asid, unsigned long addr)
767{
768 unsigned int mmu_asid;
769
770 mmu_asid = read_aux_reg(ARC_REG_PID) & 0xff;
771
772 /*
773 * At the time of a TLB miss/installation
774 * - HW version needs to match SW version
775 * - SW needs to have a valid ASID
776 */
777 if (addr < 0x70000000 &&
778 ((mm_asid == MM_CTXT_NO_ASID) ||
779 (mmu_asid != (mm_asid & MM_CTXT_ASID_MASK))))
780 print_asid_mismatch(mm_asid, mmu_asid, 0);
781}
782#endif
1/*
2 * TLB Management (flush/create/diagnostics) for ARC700
3 *
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * vineetg: Aug 2011
11 * -Reintroduce duplicate PD fixup - some customer chips still have the issue
12 *
13 * vineetg: May 2011
14 * -No need to flush_cache_page( ) for each call to update_mmu_cache()
15 * some of the LMBench tests improved amazingly
16 * = page-fault thrice as fast (75 usec to 28 usec)
17 * = mmap twice as fast (9.6 msec to 4.6 msec),
18 * = fork (5.3 msec to 3.7 msec)
19 *
20 * vineetg: April 2011 :
21 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
22 * helps avoid a shift when preparing PD0 from PTE
23 *
24 * vineetg: April 2011 : Preparing for MMU V3
25 * -MMU v2/v3 BCRs decoded differently
26 * -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
27 * -tlb_entry_erase( ) can be void
28 * -local_flush_tlb_range( ):
29 * = need not "ceil" @end
30 * = walks MMU only if range spans < 32 entries, as opposed to 256
31 *
32 * Vineetg: Sept 10th 2008
33 * -Changes related to MMU v2 (Rel 4.8)
34 *
35 * Vineetg: Aug 29th 2008
36 * -In TLB Flush operations (Metal Fix MMU) there is a explict command to
37 * flush Micro-TLBS. If TLB Index Reg is invalid prior to TLBIVUTLB cmd,
38 * it fails. Thus need to load it with ANY valid value before invoking
39 * TLBIVUTLB cmd
40 *
41 * Vineetg: Aug 21th 2008:
42 * -Reduced the duration of IRQ lockouts in TLB Flush routines
43 * -Multiple copies of TLB erase code seperated into a "single" function
44 * -In TLB Flush routines, interrupt disabling moved UP to retrieve ASID
45 * in interrupt-safe region.
46 *
47 * Vineetg: April 23rd Bug #93131
48 * Problem: tlb_flush_kernel_range() doesn't do anything if the range to
49 * flush is more than the size of TLB itself.
50 *
51 * Rahul Trivedi : Codito Technologies 2004
52 */
53
54#include <linux/module.h>
55#include <linux/bug.h>
56#include <linux/mm_types.h>
57
58#include <asm/arcregs.h>
59#include <asm/setup.h>
60#include <asm/mmu_context.h>
61#include <asm/mmu.h>
62
63/* Need for ARC MMU v2
64 *
65 * ARC700 MMU-v1 had a Joint-TLB for Code and Data and is 2 way set-assoc.
66 * For a memcpy operation with 3 players (src/dst/code) such that all 3 pages
67 * map into same set, there would be contention for the 2 ways causing severe
68 * Thrashing.
69 *
70 * Although J-TLB is 2 way set assoc, ARC700 caches J-TLB into uTLBS which has
71 * much higher associativity. u-D-TLB is 8 ways, u-I-TLB is 4 ways.
72 * Given this, the thrasing problem should never happen because once the 3
73 * J-TLB entries are created (even though 3rd will knock out one of the prev
74 * two), the u-D-TLB and u-I-TLB will have what is required to accomplish memcpy
75 *
76 * Yet we still see the Thrashing because a J-TLB Write cause flush of u-TLBs.
77 * This is a simple design for keeping them in sync. So what do we do?
78 * The solution which James came up was pretty neat. It utilised the assoc
79 * of uTLBs by not invalidating always but only when absolutely necessary.
80 *
81 * - Existing TLB commands work as before
82 * - New command (TLBWriteNI) for TLB write without clearing uTLBs
83 * - New command (TLBIVUTLB) to invalidate uTLBs.
84 *
85 * The uTLBs need only be invalidated when pages are being removed from the
86 * OS page table. If a 'victim' TLB entry is being overwritten in the main TLB
87 * as a result of a miss, the removed entry is still allowed to exist in the
88 * uTLBs as it is still valid and present in the OS page table. This allows the
89 * full associativity of the uTLBs to hide the limited associativity of the main
90 * TLB.
91 *
92 * During a miss handler, the new "TLBWriteNI" command is used to load
93 * entries without clearing the uTLBs.
94 *
95 * When the OS page table is updated, TLB entries that may be associated with a
96 * removed page are removed (flushed) from the TLB using TLBWrite. In this
97 * circumstance, the uTLBs must also be cleared. This is done by using the
98 * existing TLBWrite command. An explicit IVUTLB is also required for those
99 * corner cases when TLBWrite was not executed at all because the corresp
100 * J-TLB entry got evicted/replaced.
101 */
102
103
104/* A copy of the ASID from the PID reg is kept in asid_cache */
105DEFINE_PER_CPU(unsigned int, asid_cache) = MM_CTXT_FIRST_CYCLE;
106
107static int __read_mostly pae_exists;
108
109/*
110 * Utility Routine to erase a J-TLB entry
111 * Caller needs to setup Index Reg (manually or via getIndex)
112 */
113static inline void __tlb_entry_erase(void)
114{
115 write_aux_reg(ARC_REG_TLBPD1, 0);
116
117 if (is_pae40_enabled())
118 write_aux_reg(ARC_REG_TLBPD1HI, 0);
119
120 write_aux_reg(ARC_REG_TLBPD0, 0);
121 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
122}
123
124#if (CONFIG_ARC_MMU_VER < 4)
125
126static inline unsigned int tlb_entry_lkup(unsigned long vaddr_n_asid)
127{
128 unsigned int idx;
129
130 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid);
131
132 write_aux_reg(ARC_REG_TLBCOMMAND, TLBProbe);
133 idx = read_aux_reg(ARC_REG_TLBINDEX);
134
135 return idx;
136}
137
138static void tlb_entry_erase(unsigned int vaddr_n_asid)
139{
140 unsigned int idx;
141
142 /* Locate the TLB entry for this vaddr + ASID */
143 idx = tlb_entry_lkup(vaddr_n_asid);
144
145 /* No error means entry found, zero it out */
146 if (likely(!(idx & TLB_LKUP_ERR))) {
147 __tlb_entry_erase();
148 } else {
149 /* Duplicate entry error */
150 WARN(idx == TLB_DUP_ERR, "Probe returned Dup PD for %x\n",
151 vaddr_n_asid);
152 }
153}
154
155/****************************************************************************
156 * ARC700 MMU caches recently used J-TLB entries (RAM) as uTLBs (FLOPs)
157 *
158 * New IVUTLB cmd in MMU v2 explictly invalidates the uTLB
159 *
160 * utlb_invalidate ( )
161 * -For v2 MMU calls Flush uTLB Cmd
162 * -For v1 MMU does nothing (except for Metal Fix v1 MMU)
163 * This is because in v1 TLBWrite itself invalidate uTLBs
164 ***************************************************************************/
165
166static void utlb_invalidate(void)
167{
168#if (CONFIG_ARC_MMU_VER >= 2)
169
170#if (CONFIG_ARC_MMU_VER == 2)
171 /* MMU v2 introduced the uTLB Flush command.
172 * There was however an obscure hardware bug, where uTLB flush would
173 * fail when a prior probe for J-TLB (both totally unrelated) would
174 * return lkup err - because the entry didn't exist in MMU.
175 * The Workround was to set Index reg with some valid value, prior to
176 * flush. This was fixed in MMU v3 hence not needed any more
177 */
178 unsigned int idx;
179
180 /* make sure INDEX Reg is valid */
181 idx = read_aux_reg(ARC_REG_TLBINDEX);
182
183 /* If not write some dummy val */
184 if (unlikely(idx & TLB_LKUP_ERR))
185 write_aux_reg(ARC_REG_TLBINDEX, 0xa);
186#endif
187
188 write_aux_reg(ARC_REG_TLBCOMMAND, TLBIVUTLB);
189#endif
190
191}
192
193static void tlb_entry_insert(unsigned int pd0, pte_t pd1)
194{
195 unsigned int idx;
196
197 /*
198 * First verify if entry for this vaddr+ASID already exists
199 * This also sets up PD0 (vaddr, ASID..) for final commit
200 */
201 idx = tlb_entry_lkup(pd0);
202
203 /*
204 * If Not already present get a free slot from MMU.
205 * Otherwise, Probe would have located the entry and set INDEX Reg
206 * with existing location. This will cause Write CMD to over-write
207 * existing entry with new PD0 and PD1
208 */
209 if (likely(idx & TLB_LKUP_ERR))
210 write_aux_reg(ARC_REG_TLBCOMMAND, TLBGetIndex);
211
212 /* setup the other half of TLB entry (pfn, rwx..) */
213 write_aux_reg(ARC_REG_TLBPD1, pd1);
214
215 /*
216 * Commit the Entry to MMU
217 * It doesn't sound safe to use the TLBWriteNI cmd here
218 * which doesn't flush uTLBs. I'd rather be safe than sorry.
219 */
220 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
221}
222
223#else /* CONFIG_ARC_MMU_VER >= 4) */
224
225static void utlb_invalidate(void)
226{
227 /* No need since uTLB is always in sync with JTLB */
228}
229
230static void tlb_entry_erase(unsigned int vaddr_n_asid)
231{
232 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid | _PAGE_PRESENT);
233 write_aux_reg(ARC_REG_TLBCOMMAND, TLBDeleteEntry);
234}
235
236static void tlb_entry_insert(unsigned int pd0, pte_t pd1)
237{
238 write_aux_reg(ARC_REG_TLBPD0, pd0);
239 write_aux_reg(ARC_REG_TLBPD1, pd1);
240
241 if (is_pae40_enabled())
242 write_aux_reg(ARC_REG_TLBPD1HI, (u64)pd1 >> 32);
243
244 write_aux_reg(ARC_REG_TLBCOMMAND, TLBInsertEntry);
245}
246
247#endif
248
249/*
250 * Un-conditionally (without lookup) erase the entire MMU contents
251 */
252
253noinline void local_flush_tlb_all(void)
254{
255 struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
256 unsigned long flags;
257 unsigned int entry;
258 int num_tlb = mmu->sets * mmu->ways;
259
260 local_irq_save(flags);
261
262 /* Load PD0 and PD1 with template for a Blank Entry */
263 write_aux_reg(ARC_REG_TLBPD1, 0);
264
265 if (is_pae40_enabled())
266 write_aux_reg(ARC_REG_TLBPD1HI, 0);
267
268 write_aux_reg(ARC_REG_TLBPD0, 0);
269
270 for (entry = 0; entry < num_tlb; entry++) {
271 /* write this entry to the TLB */
272 write_aux_reg(ARC_REG_TLBINDEX, entry);
273 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
274 }
275
276 if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE)) {
277 const int stlb_idx = 0x800;
278
279 /* Blank sTLB entry */
280 write_aux_reg(ARC_REG_TLBPD0, _PAGE_HW_SZ);
281
282 for (entry = stlb_idx; entry < stlb_idx + 16; entry++) {
283 write_aux_reg(ARC_REG_TLBINDEX, entry);
284 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
285 }
286 }
287
288 utlb_invalidate();
289
290 local_irq_restore(flags);
291}
292
293/*
294 * Flush the entrie MM for userland. The fastest way is to move to Next ASID
295 */
296noinline void local_flush_tlb_mm(struct mm_struct *mm)
297{
298 /*
299 * Small optimisation courtesy IA64
300 * flush_mm called during fork,exit,munmap etc, multiple times as well.
301 * Only for fork( ) do we need to move parent to a new MMU ctxt,
302 * all other cases are NOPs, hence this check.
303 */
304 if (atomic_read(&mm->mm_users) == 0)
305 return;
306
307 /*
308 * - Move to a new ASID, but only if the mm is still wired in
309 * (Android Binder ended up calling this for vma->mm != tsk->mm,
310 * causing h/w - s/w ASID to get out of sync)
311 * - Also get_new_mmu_context() new implementation allocates a new
312 * ASID only if it is not allocated already - so unallocate first
313 */
314 destroy_context(mm);
315 if (current->mm == mm)
316 get_new_mmu_context(mm);
317}
318
319/*
320 * Flush a Range of TLB entries for userland.
321 * @start is inclusive, while @end is exclusive
322 * Difference between this and Kernel Range Flush is
323 * -Here the fastest way (if range is too large) is to move to next ASID
324 * without doing any explicit Shootdown
325 * -In case of kernel Flush, entry has to be shot down explictly
326 */
327void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
328 unsigned long end)
329{
330 const unsigned int cpu = smp_processor_id();
331 unsigned long flags;
332
333 /* If range @start to @end is more than 32 TLB entries deep,
334 * its better to move to a new ASID rather than searching for
335 * individual entries and then shooting them down
336 *
337 * The calc above is rough, doesn't account for unaligned parts,
338 * since this is heuristics based anyways
339 */
340 if (unlikely((end - start) >= PAGE_SIZE * 32)) {
341 local_flush_tlb_mm(vma->vm_mm);
342 return;
343 }
344
345 /*
346 * @start moved to page start: this alone suffices for checking
347 * loop end condition below, w/o need for aligning @end to end
348 * e.g. 2000 to 4001 will anyhow loop twice
349 */
350 start &= PAGE_MASK;
351
352 local_irq_save(flags);
353
354 if (asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID) {
355 while (start < end) {
356 tlb_entry_erase(start | hw_pid(vma->vm_mm, cpu));
357 start += PAGE_SIZE;
358 }
359 }
360
361 utlb_invalidate();
362
363 local_irq_restore(flags);
364}
365
366/* Flush the kernel TLB entries - vmalloc/modules (Global from MMU perspective)
367 * @start, @end interpreted as kvaddr
368 * Interestingly, shared TLB entries can also be flushed using just
369 * @start,@end alone (interpreted as user vaddr), although technically SASID
370 * is also needed. However our smart TLbProbe lookup takes care of that.
371 */
372void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
373{
374 unsigned long flags;
375
376 /* exactly same as above, except for TLB entry not taking ASID */
377
378 if (unlikely((end - start) >= PAGE_SIZE * 32)) {
379 local_flush_tlb_all();
380 return;
381 }
382
383 start &= PAGE_MASK;
384
385 local_irq_save(flags);
386 while (start < end) {
387 tlb_entry_erase(start);
388 start += PAGE_SIZE;
389 }
390
391 utlb_invalidate();
392
393 local_irq_restore(flags);
394}
395
396/*
397 * Delete TLB entry in MMU for a given page (??? address)
398 * NOTE One TLB entry contains translation for single PAGE
399 */
400
401void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
402{
403 const unsigned int cpu = smp_processor_id();
404 unsigned long flags;
405
406 /* Note that it is critical that interrupts are DISABLED between
407 * checking the ASID and using it flush the TLB entry
408 */
409 local_irq_save(flags);
410
411 if (asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID) {
412 tlb_entry_erase((page & PAGE_MASK) | hw_pid(vma->vm_mm, cpu));
413 utlb_invalidate();
414 }
415
416 local_irq_restore(flags);
417}
418
419#ifdef CONFIG_SMP
420
421struct tlb_args {
422 struct vm_area_struct *ta_vma;
423 unsigned long ta_start;
424 unsigned long ta_end;
425};
426
427static inline void ipi_flush_tlb_page(void *arg)
428{
429 struct tlb_args *ta = arg;
430
431 local_flush_tlb_page(ta->ta_vma, ta->ta_start);
432}
433
434static inline void ipi_flush_tlb_range(void *arg)
435{
436 struct tlb_args *ta = arg;
437
438 local_flush_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end);
439}
440
441#ifdef CONFIG_TRANSPARENT_HUGEPAGE
442static inline void ipi_flush_pmd_tlb_range(void *arg)
443{
444 struct tlb_args *ta = arg;
445
446 local_flush_pmd_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end);
447}
448#endif
449
450static inline void ipi_flush_tlb_kernel_range(void *arg)
451{
452 struct tlb_args *ta = (struct tlb_args *)arg;
453
454 local_flush_tlb_kernel_range(ta->ta_start, ta->ta_end);
455}
456
457void flush_tlb_all(void)
458{
459 on_each_cpu((smp_call_func_t)local_flush_tlb_all, NULL, 1);
460}
461
462void flush_tlb_mm(struct mm_struct *mm)
463{
464 on_each_cpu_mask(mm_cpumask(mm), (smp_call_func_t)local_flush_tlb_mm,
465 mm, 1);
466}
467
468void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
469{
470 struct tlb_args ta = {
471 .ta_vma = vma,
472 .ta_start = uaddr
473 };
474
475 on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_page, &ta, 1);
476}
477
478void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
479 unsigned long end)
480{
481 struct tlb_args ta = {
482 .ta_vma = vma,
483 .ta_start = start,
484 .ta_end = end
485 };
486
487 on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_range, &ta, 1);
488}
489
490#ifdef CONFIG_TRANSPARENT_HUGEPAGE
491void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
492 unsigned long end)
493{
494 struct tlb_args ta = {
495 .ta_vma = vma,
496 .ta_start = start,
497 .ta_end = end
498 };
499
500 on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_pmd_tlb_range, &ta, 1);
501}
502#endif
503
504void flush_tlb_kernel_range(unsigned long start, unsigned long end)
505{
506 struct tlb_args ta = {
507 .ta_start = start,
508 .ta_end = end
509 };
510
511 on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
512}
513#endif
514
515/*
516 * Routine to create a TLB entry
517 */
518void create_tlb(struct vm_area_struct *vma, unsigned long vaddr, pte_t *ptep)
519{
520 unsigned long flags;
521 unsigned int asid_or_sasid, rwx;
522 unsigned long pd0;
523 pte_t pd1;
524
525 /*
526 * create_tlb() assumes that current->mm == vma->mm, since
527 * -it ASID for TLB entry is fetched from MMU ASID reg (valid for curr)
528 * -completes the lazy write to SASID reg (again valid for curr tsk)
529 *
530 * Removing the assumption involves
531 * -Using vma->mm->context{ASID,SASID}, as opposed to MMU reg.
532 * -Fix the TLB paranoid debug code to not trigger false negatives.
533 * -More importantly it makes this handler inconsistent with fast-path
534 * TLB Refill handler which always deals with "current"
535 *
536 * Lets see the use cases when current->mm != vma->mm and we land here
537 * 1. execve->copy_strings()->__get_user_pages->handle_mm_fault
538 * Here VM wants to pre-install a TLB entry for user stack while
539 * current->mm still points to pre-execve mm (hence the condition).
540 * However the stack vaddr is soon relocated (randomization) and
541 * move_page_tables() tries to undo that TLB entry.
542 * Thus not creating TLB entry is not any worse.
543 *
544 * 2. ptrace(POKETEXT) causes a CoW - debugger(current) inserting a
545 * breakpoint in debugged task. Not creating a TLB now is not
546 * performance critical.
547 *
548 * Both the cases above are not good enough for code churn.
549 */
550 if (current->active_mm != vma->vm_mm)
551 return;
552
553 local_irq_save(flags);
554
555 tlb_paranoid_check(asid_mm(vma->vm_mm, smp_processor_id()), vaddr);
556
557 vaddr &= PAGE_MASK;
558
559 /* update this PTE credentials */
560 pte_val(*ptep) |= (_PAGE_PRESENT | _PAGE_ACCESSED);
561
562 /* Create HW TLB(PD0,PD1) from PTE */
563
564 /* ASID for this task */
565 asid_or_sasid = read_aux_reg(ARC_REG_PID) & 0xff;
566
567 pd0 = vaddr | asid_or_sasid | (pte_val(*ptep) & PTE_BITS_IN_PD0);
568
569 /*
570 * ARC MMU provides fully orthogonal access bits for K/U mode,
571 * however Linux only saves 1 set to save PTE real-estate
572 * Here we convert 3 PTE bits into 6 MMU bits:
573 * -Kernel only entries have Kr Kw Kx 0 0 0
574 * -User entries have mirrored K and U bits
575 */
576 rwx = pte_val(*ptep) & PTE_BITS_RWX;
577
578 if (pte_val(*ptep) & _PAGE_GLOBAL)
579 rwx <<= 3; /* r w x => Kr Kw Kx 0 0 0 */
580 else
581 rwx |= (rwx << 3); /* r w x => Kr Kw Kx Ur Uw Ux */
582
583 pd1 = rwx | (pte_val(*ptep) & PTE_BITS_NON_RWX_IN_PD1);
584
585 tlb_entry_insert(pd0, pd1);
586
587 local_irq_restore(flags);
588}
589
590/*
591 * Called at the end of pagefault, for a userspace mapped page
592 * -pre-install the corresponding TLB entry into MMU
593 * -Finalize the delayed D-cache flush of kernel mapping of page due to
594 * flush_dcache_page(), copy_user_page()
595 *
596 * Note that flush (when done) involves both WBACK - so physical page is
597 * in sync as well as INV - so any non-congruent aliases don't remain
598 */
599void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
600 pte_t *ptep)
601{
602 unsigned long vaddr = vaddr_unaligned & PAGE_MASK;
603 phys_addr_t paddr = pte_val(*ptep) & PAGE_MASK;
604 struct page *page = pfn_to_page(pte_pfn(*ptep));
605
606 create_tlb(vma, vaddr, ptep);
607
608 if (page == ZERO_PAGE(0)) {
609 return;
610 }
611
612 /*
613 * Exec page : Independent of aliasing/page-color considerations,
614 * since icache doesn't snoop dcache on ARC, any dirty
615 * K-mapping of a code page needs to be wback+inv so that
616 * icache fetch by userspace sees code correctly.
617 * !EXEC page: If K-mapping is NOT congruent to U-mapping, flush it
618 * so userspace sees the right data.
619 * (Avoids the flush for Non-exec + congruent mapping case)
620 */
621 if ((vma->vm_flags & VM_EXEC) ||
622 addr_not_cache_congruent(paddr, vaddr)) {
623
624 int dirty = !test_and_set_bit(PG_dc_clean, &page->flags);
625 if (dirty) {
626 /* wback + inv dcache lines (K-mapping) */
627 __flush_dcache_page(paddr, paddr);
628
629 /* invalidate any existing icache lines (U-mapping) */
630 if (vma->vm_flags & VM_EXEC)
631 __inv_icache_page(paddr, vaddr);
632 }
633 }
634}
635
636#ifdef CONFIG_TRANSPARENT_HUGEPAGE
637
638/*
639 * MMUv4 in HS38x cores supports Super Pages which are basis for Linux THP
640 * support.
641 *
642 * Normal and Super pages can co-exist (ofcourse not overlap) in TLB with a
643 * new bit "SZ" in TLB page descriptor to distinguish between them.
644 * Super Page size is configurable in hardware (4K to 16M), but fixed once
645 * RTL builds.
646 *
647 * The exact THP size a Linx configuration will support is a function of:
648 * - MMU page size (typical 8K, RTL fixed)
649 * - software page walker address split between PGD:PTE:PFN (typical
650 * 11:8:13, but can be changed with 1 line)
651 * So for above default, THP size supported is 8K * (2^8) = 2M
652 *
653 * Default Page Walker is 2 levels, PGD:PTE:PFN, which in THP regime
654 * reduces to 1 level (as PTE is folded into PGD and canonically referred
655 * to as PMD).
656 * Thus THP PMD accessors are implemented in terms of PTE (just like sparc)
657 */
658
659void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
660 pmd_t *pmd)
661{
662 pte_t pte = __pte(pmd_val(*pmd));
663 update_mmu_cache(vma, addr, &pte);
664}
665
666void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
667 pgtable_t pgtable)
668{
669 struct list_head *lh = (struct list_head *) pgtable;
670
671 assert_spin_locked(&mm->page_table_lock);
672
673 /* FIFO */
674 if (!pmd_huge_pte(mm, pmdp))
675 INIT_LIST_HEAD(lh);
676 else
677 list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
678 pmd_huge_pte(mm, pmdp) = pgtable;
679}
680
681pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
682{
683 struct list_head *lh;
684 pgtable_t pgtable;
685
686 assert_spin_locked(&mm->page_table_lock);
687
688 pgtable = pmd_huge_pte(mm, pmdp);
689 lh = (struct list_head *) pgtable;
690 if (list_empty(lh))
691 pmd_huge_pte(mm, pmdp) = NULL;
692 else {
693 pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
694 list_del(lh);
695 }
696
697 pte_val(pgtable[0]) = 0;
698 pte_val(pgtable[1]) = 0;
699
700 return pgtable;
701}
702
703void local_flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
704 unsigned long end)
705{
706 unsigned int cpu;
707 unsigned long flags;
708
709 local_irq_save(flags);
710
711 cpu = smp_processor_id();
712
713 if (likely(asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID)) {
714 unsigned int asid = hw_pid(vma->vm_mm, cpu);
715
716 /* No need to loop here: this will always be for 1 Huge Page */
717 tlb_entry_erase(start | _PAGE_HW_SZ | asid);
718 }
719
720 local_irq_restore(flags);
721}
722
723#endif
724
725/* Read the Cache Build Confuration Registers, Decode them and save into
726 * the cpuinfo structure for later use.
727 * No Validation is done here, simply read/convert the BCRs
728 */
729void read_decode_mmu_bcr(void)
730{
731 struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
732 unsigned int tmp;
733 struct bcr_mmu_1_2 {
734#ifdef CONFIG_CPU_BIG_ENDIAN
735 unsigned int ver:8, ways:4, sets:4, u_itlb:8, u_dtlb:8;
736#else
737 unsigned int u_dtlb:8, u_itlb:8, sets:4, ways:4, ver:8;
738#endif
739 } *mmu2;
740
741 struct bcr_mmu_3 {
742#ifdef CONFIG_CPU_BIG_ENDIAN
743 unsigned int ver:8, ways:4, sets:4, res:3, sasid:1, pg_sz:4,
744 u_itlb:4, u_dtlb:4;
745#else
746 unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, sasid:1, res:3, sets:4,
747 ways:4, ver:8;
748#endif
749 } *mmu3;
750
751 struct bcr_mmu_4 {
752#ifdef CONFIG_CPU_BIG_ENDIAN
753 unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
754 n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
755#else
756 /* DTLB ITLB JES JE JA */
757 unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
758 pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
759#endif
760 } *mmu4;
761
762 tmp = read_aux_reg(ARC_REG_MMU_BCR);
763 mmu->ver = (tmp >> 24);
764
765 if (is_isa_arcompact()) {
766 if (mmu->ver <= 2) {
767 mmu2 = (struct bcr_mmu_1_2 *)&tmp;
768 mmu->pg_sz_k = TO_KB(0x2000);
769 mmu->sets = 1 << mmu2->sets;
770 mmu->ways = 1 << mmu2->ways;
771 mmu->u_dtlb = mmu2->u_dtlb;
772 mmu->u_itlb = mmu2->u_itlb;
773 } else {
774 mmu3 = (struct bcr_mmu_3 *)&tmp;
775 mmu->pg_sz_k = 1 << (mmu3->pg_sz - 1);
776 mmu->sets = 1 << mmu3->sets;
777 mmu->ways = 1 << mmu3->ways;
778 mmu->u_dtlb = mmu3->u_dtlb;
779 mmu->u_itlb = mmu3->u_itlb;
780 mmu->sasid = mmu3->sasid;
781 }
782 } else {
783 mmu4 = (struct bcr_mmu_4 *)&tmp;
784 mmu->pg_sz_k = 1 << (mmu4->sz0 - 1);
785 mmu->s_pg_sz_m = 1 << (mmu4->sz1 - 11);
786 mmu->sets = 64 << mmu4->n_entry;
787 mmu->ways = mmu4->n_ways * 2;
788 mmu->u_dtlb = mmu4->u_dtlb * 4;
789 mmu->u_itlb = mmu4->u_itlb * 4;
790 mmu->sasid = mmu4->sasid;
791 pae_exists = mmu->pae = mmu4->pae;
792 }
793}
794
795char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len)
796{
797 int n = 0;
798 struct cpuinfo_arc_mmu *p_mmu = &cpuinfo_arc700[cpu_id].mmu;
799 char super_pg[64] = "";
800
801 if (p_mmu->s_pg_sz_m)
802 scnprintf(super_pg, 64, "%dM Super Page %s",
803 p_mmu->s_pg_sz_m,
804 IS_USED_CFG(CONFIG_TRANSPARENT_HUGEPAGE));
805
806 n += scnprintf(buf + n, len - n,
807 "MMU [v%x]\t: %dk PAGE, %sJTLB %d (%dx%d), uDTLB %d, uITLB %d%s%s\n",
808 p_mmu->ver, p_mmu->pg_sz_k, super_pg,
809 p_mmu->sets * p_mmu->ways, p_mmu->sets, p_mmu->ways,
810 p_mmu->u_dtlb, p_mmu->u_itlb,
811 IS_AVAIL2(p_mmu->pae, ", PAE40 ", CONFIG_ARC_HAS_PAE40));
812
813 return buf;
814}
815
816int pae40_exist_but_not_enab(void)
817{
818 return pae_exists && !is_pae40_enabled();
819}
820
821void arc_mmu_init(void)
822{
823 struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
824 char str[256];
825 int compat = 0;
826
827 pr_info("%s", arc_mmu_mumbojumbo(0, str, sizeof(str)));
828
829 /*
830 * Can't be done in processor.h due to header include depenedencies
831 */
832 BUILD_BUG_ON(!IS_ALIGNED((CONFIG_ARC_KVADDR_SIZE << 20), PMD_SIZE));
833
834 /*
835 * stack top size sanity check,
836 * Can't be done in processor.h due to header include depenedencies
837 */
838 BUILD_BUG_ON(!IS_ALIGNED(STACK_TOP, PMD_SIZE));
839
840 /*
841 * Ensure that MMU features assumed by kernel exist in hardware.
842 * For older ARC700 cpus, it has to be exact match, since the MMU
843 * revisions were not backwards compatible (MMUv3 TLB layout changed
844 * so even if kernel for v2 didn't use any new cmds of v3, it would
845 * still not work.
846 * For HS cpus, MMUv4 was baseline and v5 is backwards compatible
847 * (will run older software).
848 */
849 if (is_isa_arcompact() && mmu->ver == CONFIG_ARC_MMU_VER)
850 compat = 1;
851 else if (is_isa_arcv2() && mmu->ver >= CONFIG_ARC_MMU_VER)
852 compat = 1;
853
854 if (!compat) {
855 panic("MMU ver %d doesn't match kernel built for %d...\n",
856 mmu->ver, CONFIG_ARC_MMU_VER);
857 }
858
859 if (mmu->pg_sz_k != TO_KB(PAGE_SIZE))
860 panic("MMU pg size != PAGE_SIZE (%luk)\n", TO_KB(PAGE_SIZE));
861
862 if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE) &&
863 mmu->s_pg_sz_m != TO_MB(HPAGE_PMD_SIZE))
864 panic("MMU Super pg size != Linux HPAGE_PMD_SIZE (%luM)\n",
865 (unsigned long)TO_MB(HPAGE_PMD_SIZE));
866
867 if (IS_ENABLED(CONFIG_ARC_HAS_PAE40) && !mmu->pae)
868 panic("Hardware doesn't support PAE40\n");
869
870 /* Enable the MMU */
871 write_aux_reg(ARC_REG_PID, MMU_ENABLE);
872
873 /* In smp we use this reg for interrupt 1 scratch */
874#ifndef CONFIG_SMP
875 /* swapper_pg_dir is the pgd for the kernel, used by vmalloc */
876 write_aux_reg(ARC_REG_SCRATCH_DATA0, swapper_pg_dir);
877#endif
878
879 if (pae40_exist_but_not_enab())
880 write_aux_reg(ARC_REG_TLBPD1HI, 0);
881}
882
883/*
884 * TLB Programmer's Model uses Linear Indexes: 0 to {255, 511} for 128 x {2,4}
885 * The mapping is Column-first.
886 * --------------------- -----------
887 * |way0|way1|way2|way3| |way0|way1|
888 * --------------------- -----------
889 * [set0] | 0 | 1 | 2 | 3 | | 0 | 1 |
890 * [set1] | 4 | 5 | 6 | 7 | | 2 | 3 |
891 * ~ ~ ~ ~
892 * [set127] | 508| 509| 510| 511| | 254| 255|
893 * --------------------- -----------
894 * For normal operations we don't(must not) care how above works since
895 * MMU cmd getIndex(vaddr) abstracts that out.
896 * However for walking WAYS of a SET, we need to know this
897 */
898#define SET_WAY_TO_IDX(mmu, set, way) ((set) * mmu->ways + (way))
899
900/* Handling of Duplicate PD (TLB entry) in MMU.
901 * -Could be due to buggy customer tapeouts or obscure kernel bugs
902 * -MMU complaints not at the time of duplicate PD installation, but at the
903 * time of lookup matching multiple ways.
904 * -Ideally these should never happen - but if they do - workaround by deleting
905 * the duplicate one.
906 * -Knob to be verbose abt it.(TODO: hook them up to debugfs)
907 */
908volatile int dup_pd_silent; /* Be slient abt it or complain (default) */
909
910void do_tlb_overlap_fault(unsigned long cause, unsigned long address,
911 struct pt_regs *regs)
912{
913 struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
914 unsigned int pd0[mmu->ways];
915 unsigned long flags;
916 int set;
917
918 local_irq_save(flags);
919
920 /* loop thru all sets of TLB */
921 for (set = 0; set < mmu->sets; set++) {
922
923 int is_valid, way;
924
925 /* read out all the ways of current set */
926 for (way = 0, is_valid = 0; way < mmu->ways; way++) {
927 write_aux_reg(ARC_REG_TLBINDEX,
928 SET_WAY_TO_IDX(mmu, set, way));
929 write_aux_reg(ARC_REG_TLBCOMMAND, TLBRead);
930 pd0[way] = read_aux_reg(ARC_REG_TLBPD0);
931 is_valid |= pd0[way] & _PAGE_PRESENT;
932 pd0[way] &= PAGE_MASK;
933 }
934
935 /* If all the WAYS in SET are empty, skip to next SET */
936 if (!is_valid)
937 continue;
938
939 /* Scan the set for duplicate ways: needs a nested loop */
940 for (way = 0; way < mmu->ways - 1; way++) {
941
942 int n;
943
944 if (!pd0[way])
945 continue;
946
947 for (n = way + 1; n < mmu->ways; n++) {
948 if (pd0[way] != pd0[n])
949 continue;
950
951 if (!dup_pd_silent)
952 pr_info("Dup TLB PD0 %08x @ set %d ways %d,%d\n",
953 pd0[way], set, way, n);
954
955 /*
956 * clear entry @way and not @n.
957 * This is critical to our optimised loop
958 */
959 pd0[way] = 0;
960 write_aux_reg(ARC_REG_TLBINDEX,
961 SET_WAY_TO_IDX(mmu, set, way));
962 __tlb_entry_erase();
963 }
964 }
965 }
966
967 local_irq_restore(flags);
968}
969
970/***********************************************************************
971 * Diagnostic Routines
972 * -Called from Low Level TLB Hanlders if things don;t look good
973 **********************************************************************/
974
975#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
976
977/*
978 * Low Level ASM TLB handler calls this if it finds that HW and SW ASIDS
979 * don't match
980 */
981void print_asid_mismatch(int mm_asid, int mmu_asid, int is_fast_path)
982{
983 pr_emerg("ASID Mismatch in %s Path Handler: sw-pid=0x%x hw-pid=0x%x\n",
984 is_fast_path ? "Fast" : "Slow", mm_asid, mmu_asid);
985
986 __asm__ __volatile__("flag 1");
987}
988
989void tlb_paranoid_check(unsigned int mm_asid, unsigned long addr)
990{
991 unsigned int mmu_asid;
992
993 mmu_asid = read_aux_reg(ARC_REG_PID) & 0xff;
994
995 /*
996 * At the time of a TLB miss/installation
997 * - HW version needs to match SW version
998 * - SW needs to have a valid ASID
999 */
1000 if (addr < 0x70000000 &&
1001 ((mm_asid == MM_CTXT_NO_ASID) ||
1002 (mmu_asid != (mm_asid & MM_CTXT_ASID_MASK))))
1003 print_asid_mismatch(mm_asid, mmu_asid, 0);
1004}
1005#endif