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1/*
2 * OMAP2+ common Power & Reset Management (PRM) IP block functions
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Tero Kristo <t-kristo@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 *
12 * For historical purposes, the API used to configure the PRM
13 * interrupt handler refers to it as the "PRCM interrupt." The
14 * underlying registers are located in the PRM on OMAP3/4.
15 *
16 * XXX This code should eventually be moved to a PRM driver.
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/io.h>
23#include <linux/irq.h>
24#include <linux/interrupt.h>
25#include <linux/slab.h>
26#include <linux/of.h>
27#include <linux/of_address.h>
28#include <linux/clk-provider.h>
29#include <linux/clk/ti.h>
30
31#include "soc.h"
32#include "prm2xxx_3xxx.h"
33#include "prm2xxx.h"
34#include "prm3xxx.h"
35#include "prm44xx.h"
36#include "common.h"
37#include "clock.h"
38
39/*
40 * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
41 * XXX this is technically not needed, since
42 * omap_prcm_register_chain_handler() could allocate this based on the
43 * actual amount of memory needed for the SoC
44 */
45#define OMAP_PRCM_MAX_NR_PENDING_REG 2
46
47/*
48 * prcm_irq_chips: an array of all of the "generic IRQ chips" in use
49 * by the PRCM interrupt handler code. There will be one 'chip' per
50 * PRM_{IRQSTATUS,IRQENABLE}_MPU register pair. (So OMAP3 will have
51 * one "chip" and OMAP4 will have two.)
52 */
53static struct irq_chip_generic **prcm_irq_chips;
54
55/*
56 * prcm_irq_setup: the PRCM IRQ parameters for the hardware the code
57 * is currently running on. Defined and passed by initialization code
58 * that calls omap_prcm_register_chain_handler().
59 */
60static struct omap_prcm_irq_setup *prcm_irq_setup;
61
62/* prm_base: base virtual address of the PRM IP block */
63void __iomem *prm_base;
64
65/*
66 * prm_ll_data: function pointers to SoC-specific implementations of
67 * common PRM functions
68 */
69static struct prm_ll_data null_prm_ll_data;
70static struct prm_ll_data *prm_ll_data = &null_prm_ll_data;
71
72/* Private functions */
73
74/*
75 * Move priority events from events to priority_events array
76 */
77static void omap_prcm_events_filter_priority(unsigned long *events,
78 unsigned long *priority_events)
79{
80 int i;
81
82 for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
83 priority_events[i] =
84 events[i] & prcm_irq_setup->priority_mask[i];
85 events[i] ^= priority_events[i];
86 }
87}
88
89/*
90 * PRCM Interrupt Handler
91 *
92 * This is a common handler for the OMAP PRCM interrupts. Pending
93 * interrupts are detected by a call to prcm_pending_events and
94 * dispatched accordingly. Clearing of the wakeup events should be
95 * done by the SoC specific individual handlers.
96 */
97static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
98{
99 unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
100 unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
101 struct irq_chip *chip = irq_desc_get_chip(desc);
102 unsigned int virtirq;
103 int nr_irq = prcm_irq_setup->nr_regs * 32;
104
105 /*
106 * If we are suspended, mask all interrupts from PRCM level,
107 * this does not ack them, and they will be pending until we
108 * re-enable the interrupts, at which point the
109 * omap_prcm_irq_handler will be executed again. The
110 * _save_and_clear_irqen() function must ensure that the PRM
111 * write to disable all IRQs has reached the PRM before
112 * returning, or spurious PRCM interrupts may occur during
113 * suspend.
114 */
115 if (prcm_irq_setup->suspended) {
116 prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask);
117 prcm_irq_setup->suspend_save_flag = true;
118 }
119
120 /*
121 * Loop until all pending irqs are handled, since
122 * generic_handle_irq() can cause new irqs to come
123 */
124 while (!prcm_irq_setup->suspended) {
125 prcm_irq_setup->read_pending_irqs(pending);
126
127 /* No bit set, then all IRQs are handled */
128 if (find_first_bit(pending, nr_irq) >= nr_irq)
129 break;
130
131 omap_prcm_events_filter_priority(pending, priority_pending);
132
133 /*
134 * Loop on all currently pending irqs so that new irqs
135 * cannot starve previously pending irqs
136 */
137
138 /* Serve priority events first */
139 for_each_set_bit(virtirq, priority_pending, nr_irq)
140 generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
141
142 /* Serve normal events next */
143 for_each_set_bit(virtirq, pending, nr_irq)
144 generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
145 }
146 if (chip->irq_ack)
147 chip->irq_ack(&desc->irq_data);
148 if (chip->irq_eoi)
149 chip->irq_eoi(&desc->irq_data);
150 chip->irq_unmask(&desc->irq_data);
151
152 prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */
153}
154
155/* Public functions */
156
157/**
158 * omap_prcm_event_to_irq - given a PRCM event name, returns the
159 * corresponding IRQ on which the handler should be registered
160 * @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq
161 *
162 * Returns the Linux internal IRQ ID corresponding to @name upon success,
163 * or -ENOENT upon failure.
164 */
165int omap_prcm_event_to_irq(const char *name)
166{
167 int i;
168
169 if (!prcm_irq_setup || !name)
170 return -ENOENT;
171
172 for (i = 0; i < prcm_irq_setup->nr_irqs; i++)
173 if (!strcmp(prcm_irq_setup->irqs[i].name, name))
174 return prcm_irq_setup->base_irq +
175 prcm_irq_setup->irqs[i].offset;
176
177 return -ENOENT;
178}
179
180/**
181 * omap_prcm_irq_cleanup - reverses memory allocated and other steps
182 * done by omap_prcm_register_chain_handler()
183 *
184 * No return value.
185 */
186void omap_prcm_irq_cleanup(void)
187{
188 int i;
189
190 if (!prcm_irq_setup) {
191 pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n");
192 return;
193 }
194
195 if (prcm_irq_chips) {
196 for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
197 if (prcm_irq_chips[i])
198 irq_remove_generic_chip(prcm_irq_chips[i],
199 0xffffffff, 0, 0);
200 prcm_irq_chips[i] = NULL;
201 }
202 kfree(prcm_irq_chips);
203 prcm_irq_chips = NULL;
204 }
205
206 kfree(prcm_irq_setup->saved_mask);
207 prcm_irq_setup->saved_mask = NULL;
208
209 kfree(prcm_irq_setup->priority_mask);
210 prcm_irq_setup->priority_mask = NULL;
211
212 irq_set_chained_handler(prcm_irq_setup->irq, NULL);
213
214 if (prcm_irq_setup->base_irq > 0)
215 irq_free_descs(prcm_irq_setup->base_irq,
216 prcm_irq_setup->nr_regs * 32);
217 prcm_irq_setup->base_irq = 0;
218}
219
220void omap_prcm_irq_prepare(void)
221{
222 prcm_irq_setup->suspended = true;
223}
224
225void omap_prcm_irq_complete(void)
226{
227 prcm_irq_setup->suspended = false;
228
229 /* If we have not saved the masks, do not attempt to restore */
230 if (!prcm_irq_setup->suspend_save_flag)
231 return;
232
233 prcm_irq_setup->suspend_save_flag = false;
234
235 /*
236 * Re-enable all masked PRCM irq sources, this causes the PRCM
237 * interrupt to fire immediately if the events were masked
238 * previously in the chain handler
239 */
240 prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask);
241}
242
243/**
244 * omap_prcm_register_chain_handler - initializes the prcm chained interrupt
245 * handler based on provided parameters
246 * @irq_setup: hardware data about the underlying PRM/PRCM
247 *
248 * Set up the PRCM chained interrupt handler on the PRCM IRQ. Sets up
249 * one generic IRQ chip per PRM interrupt status/enable register pair.
250 * Returns 0 upon success, -EINVAL if called twice or if invalid
251 * arguments are passed, or -ENOMEM on any other error.
252 */
253int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
254{
255 int nr_regs;
256 u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
257 int offset, i;
258 struct irq_chip_generic *gc;
259 struct irq_chip_type *ct;
260
261 if (!irq_setup)
262 return -EINVAL;
263
264 nr_regs = irq_setup->nr_regs;
265
266 if (prcm_irq_setup) {
267 pr_err("PRCM: already initialized; won't reinitialize\n");
268 return -EINVAL;
269 }
270
271 if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) {
272 pr_err("PRCM: nr_regs too large\n");
273 return -EINVAL;
274 }
275
276 prcm_irq_setup = irq_setup;
277
278 prcm_irq_chips = kzalloc(sizeof(void *) * nr_regs, GFP_KERNEL);
279 prcm_irq_setup->saved_mask = kzalloc(sizeof(u32) * nr_regs, GFP_KERNEL);
280 prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs,
281 GFP_KERNEL);
282
283 if (!prcm_irq_chips || !prcm_irq_setup->saved_mask ||
284 !prcm_irq_setup->priority_mask) {
285 pr_err("PRCM: kzalloc failed\n");
286 goto err;
287 }
288
289 memset(mask, 0, sizeof(mask));
290
291 for (i = 0; i < irq_setup->nr_irqs; i++) {
292 offset = irq_setup->irqs[i].offset;
293 mask[offset >> 5] |= 1 << (offset & 0x1f);
294 if (irq_setup->irqs[i].priority)
295 irq_setup->priority_mask[offset >> 5] |=
296 1 << (offset & 0x1f);
297 }
298
299 irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler);
300
301 irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
302 0);
303
304 if (irq_setup->base_irq < 0) {
305 pr_err("PRCM: failed to allocate irq descs: %d\n",
306 irq_setup->base_irq);
307 goto err;
308 }
309
310 for (i = 0; i < irq_setup->nr_regs; i++) {
311 gc = irq_alloc_generic_chip("PRCM", 1,
312 irq_setup->base_irq + i * 32, prm_base,
313 handle_level_irq);
314
315 if (!gc) {
316 pr_err("PRCM: failed to allocate generic chip\n");
317 goto err;
318 }
319 ct = gc->chip_types;
320 ct->chip.irq_ack = irq_gc_ack_set_bit;
321 ct->chip.irq_mask = irq_gc_mask_clr_bit;
322 ct->chip.irq_unmask = irq_gc_mask_set_bit;
323
324 ct->regs.ack = irq_setup->ack + i * 4;
325 ct->regs.mask = irq_setup->mask + i * 4;
326
327 irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0);
328 prcm_irq_chips[i] = gc;
329 }
330
331 if (of_have_populated_dt()) {
332 int irq = omap_prcm_event_to_irq("io");
333 if (cpu_is_omap34xx())
334 omap_pcs_legacy_init(irq,
335 omap3xxx_prm_reconfigure_io_chain);
336 else
337 omap_pcs_legacy_init(irq,
338 omap44xx_prm_reconfigure_io_chain);
339 }
340
341 return 0;
342
343err:
344 omap_prcm_irq_cleanup();
345 return -ENOMEM;
346}
347
348/**
349 * omap2_set_globals_prm - set the PRM base address (for early use)
350 * @prm: PRM base virtual address
351 *
352 * XXX Will be replaced when the PRM/CM drivers are completed.
353 */
354void __init omap2_set_globals_prm(void __iomem *prm)
355{
356 prm_base = prm;
357}
358
359/**
360 * prm_read_reset_sources - return the sources of the SoC's last reset
361 *
362 * Return a u32 bitmask representing the reset sources that caused the
363 * SoC to reset. The low-level per-SoC functions called by this
364 * function remap the SoC-specific reset source bits into an
365 * OMAP-common set of reset source bits, defined in
366 * arch/arm/mach-omap2/prm.h. Returns the standardized reset source
367 * u32 bitmask from the hardware upon success, or returns (1 <<
368 * OMAP_UNKNOWN_RST_SRC_ID_SHIFT) if no low-level read_reset_sources()
369 * function was registered.
370 */
371u32 prm_read_reset_sources(void)
372{
373 u32 ret = 1 << OMAP_UNKNOWN_RST_SRC_ID_SHIFT;
374
375 if (prm_ll_data->read_reset_sources)
376 ret = prm_ll_data->read_reset_sources();
377 else
378 WARN_ONCE(1, "prm: %s: no mapping function defined for reset sources\n", __func__);
379
380 return ret;
381}
382
383/**
384 * prm_was_any_context_lost_old - was device context lost? (old API)
385 * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
386 * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
387 * @idx: CONTEXT register offset
388 *
389 * Return 1 if any bits were set in the *_CONTEXT_* register
390 * identified by (@part, @inst, @idx), which means that some context
391 * was lost for that module; otherwise, return 0. XXX Deprecated;
392 * callers need to use a less-SoC-dependent way to identify hardware
393 * IP blocks.
394 */
395bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx)
396{
397 bool ret = true;
398
399 if (prm_ll_data->was_any_context_lost_old)
400 ret = prm_ll_data->was_any_context_lost_old(part, inst, idx);
401 else
402 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
403 __func__);
404
405 return ret;
406}
407
408/**
409 * prm_clear_context_lost_flags_old - clear context loss flags (old API)
410 * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
411 * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
412 * @idx: CONTEXT register offset
413 *
414 * Clear hardware context loss bits for the module identified by
415 * (@part, @inst, @idx). No return value. XXX Deprecated; callers
416 * need to use a less-SoC-dependent way to identify hardware IP
417 * blocks.
418 */
419void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx)
420{
421 if (prm_ll_data->clear_context_loss_flags_old)
422 prm_ll_data->clear_context_loss_flags_old(part, inst, idx);
423 else
424 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
425 __func__);
426}
427
428/**
429 * prm_register - register per-SoC low-level data with the PRM
430 * @pld: low-level per-SoC OMAP PRM data & function pointers to register
431 *
432 * Register per-SoC low-level OMAP PRM data and function pointers with
433 * the OMAP PRM common interface. The caller must keep the data
434 * pointed to by @pld valid until it calls prm_unregister() and
435 * it returns successfully. Returns 0 upon success, -EINVAL if @pld
436 * is NULL, or -EEXIST if prm_register() has already been called
437 * without an intervening prm_unregister().
438 */
439int prm_register(struct prm_ll_data *pld)
440{
441 if (!pld)
442 return -EINVAL;
443
444 if (prm_ll_data != &null_prm_ll_data)
445 return -EEXIST;
446
447 prm_ll_data = pld;
448
449 return 0;
450}
451
452/**
453 * prm_unregister - unregister per-SoC low-level data & function pointers
454 * @pld: low-level per-SoC OMAP PRM data & function pointers to unregister
455 *
456 * Unregister per-SoC low-level OMAP PRM data and function pointers
457 * that were previously registered with prm_register(). The
458 * caller may not destroy any of the data pointed to by @pld until
459 * this function returns successfully. Returns 0 upon success, or
460 * -EINVAL if @pld is NULL or if @pld does not match the struct
461 * prm_ll_data * previously registered by prm_register().
462 */
463int prm_unregister(struct prm_ll_data *pld)
464{
465 if (!pld || prm_ll_data != pld)
466 return -EINVAL;
467
468 prm_ll_data = &null_prm_ll_data;
469
470 return 0;
471}
472
473static struct of_device_id omap_prcm_dt_match_table[] = {
474 { .compatible = "ti,am3-prcm" },
475 { .compatible = "ti,am3-scrm" },
476 { .compatible = "ti,am4-prcm" },
477 { .compatible = "ti,am4-scrm" },
478 { .compatible = "ti,omap3-prm" },
479 { .compatible = "ti,omap3-cm" },
480 { .compatible = "ti,omap3-scrm" },
481 { .compatible = "ti,omap4-cm1" },
482 { .compatible = "ti,omap4-prm" },
483 { .compatible = "ti,omap4-cm2" },
484 { .compatible = "ti,omap4-scrm" },
485 { .compatible = "ti,omap5-prm" },
486 { .compatible = "ti,omap5-cm-core-aon" },
487 { .compatible = "ti,omap5-scrm" },
488 { .compatible = "ti,omap5-cm-core" },
489 { .compatible = "ti,dra7-prm" },
490 { .compatible = "ti,dra7-cm-core-aon" },
491 { .compatible = "ti,dra7-cm-core" },
492 { }
493};
494
495static struct clk_hw_omap memmap_dummy_ck = {
496 .flags = MEMMAP_ADDRESSING,
497};
498
499static u32 prm_clk_readl(void __iomem *reg)
500{
501 return omap2_clk_readl(&memmap_dummy_ck, reg);
502}
503
504static void prm_clk_writel(u32 val, void __iomem *reg)
505{
506 omap2_clk_writel(val, &memmap_dummy_ck, reg);
507}
508
509static struct ti_clk_ll_ops omap_clk_ll_ops = {
510 .clk_readl = prm_clk_readl,
511 .clk_writel = prm_clk_writel,
512};
513
514int __init of_prcm_init(void)
515{
516 struct device_node *np;
517 void __iomem *mem;
518 int memmap_index = 0;
519
520 ti_clk_ll_ops = &omap_clk_ll_ops;
521
522 for_each_matching_node(np, omap_prcm_dt_match_table) {
523 mem = of_iomap(np, 0);
524 clk_memmaps[memmap_index] = mem;
525 ti_dt_clk_init_provider(np, memmap_index);
526 memmap_index++;
527 }
528
529 ti_dt_clockdomains_setup();
530
531 return 0;
532}
1/*
2 * OMAP2+ common Power & Reset Management (PRM) IP block functions
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Tero Kristo <t-kristo@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 *
12 * For historical purposes, the API used to configure the PRM
13 * interrupt handler refers to it as the "PRCM interrupt." The
14 * underlying registers are located in the PRM on OMAP3/4.
15 *
16 * XXX This code should eventually be moved to a PRM driver.
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/io.h>
23#include <linux/irq.h>
24#include <linux/interrupt.h>
25#include <linux/slab.h>
26#include <linux/of.h>
27#include <linux/of_address.h>
28#include <linux/clk-provider.h>
29#include <linux/clk/ti.h>
30
31#include "soc.h"
32#include "prm2xxx_3xxx.h"
33#include "prm2xxx.h"
34#include "prm3xxx.h"
35#include "prm33xx.h"
36#include "prm44xx.h"
37#include "prm54xx.h"
38#include "prm7xx.h"
39#include "prcm43xx.h"
40#include "common.h"
41#include "clock.h"
42#include "cm.h"
43#include "control.h"
44
45/*
46 * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
47 * XXX this is technically not needed, since
48 * omap_prcm_register_chain_handler() could allocate this based on the
49 * actual amount of memory needed for the SoC
50 */
51#define OMAP_PRCM_MAX_NR_PENDING_REG 2
52
53/*
54 * prcm_irq_chips: an array of all of the "generic IRQ chips" in use
55 * by the PRCM interrupt handler code. There will be one 'chip' per
56 * PRM_{IRQSTATUS,IRQENABLE}_MPU register pair. (So OMAP3 will have
57 * one "chip" and OMAP4 will have two.)
58 */
59static struct irq_chip_generic **prcm_irq_chips;
60
61/*
62 * prcm_irq_setup: the PRCM IRQ parameters for the hardware the code
63 * is currently running on. Defined and passed by initialization code
64 * that calls omap_prcm_register_chain_handler().
65 */
66static struct omap_prcm_irq_setup *prcm_irq_setup;
67
68/* prm_base: base virtual address of the PRM IP block */
69struct omap_domain_base prm_base;
70
71u16 prm_features;
72
73/*
74 * prm_ll_data: function pointers to SoC-specific implementations of
75 * common PRM functions
76 */
77static struct prm_ll_data null_prm_ll_data;
78static struct prm_ll_data *prm_ll_data = &null_prm_ll_data;
79
80/* Private functions */
81
82/*
83 * Move priority events from events to priority_events array
84 */
85static void omap_prcm_events_filter_priority(unsigned long *events,
86 unsigned long *priority_events)
87{
88 int i;
89
90 for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
91 priority_events[i] =
92 events[i] & prcm_irq_setup->priority_mask[i];
93 events[i] ^= priority_events[i];
94 }
95}
96
97/*
98 * PRCM Interrupt Handler
99 *
100 * This is a common handler for the OMAP PRCM interrupts. Pending
101 * interrupts are detected by a call to prcm_pending_events and
102 * dispatched accordingly. Clearing of the wakeup events should be
103 * done by the SoC specific individual handlers.
104 */
105static void omap_prcm_irq_handler(struct irq_desc *desc)
106{
107 unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
108 unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
109 struct irq_chip *chip = irq_desc_get_chip(desc);
110 unsigned int virtirq;
111 int nr_irq = prcm_irq_setup->nr_regs * 32;
112
113 /*
114 * If we are suspended, mask all interrupts from PRCM level,
115 * this does not ack them, and they will be pending until we
116 * re-enable the interrupts, at which point the
117 * omap_prcm_irq_handler will be executed again. The
118 * _save_and_clear_irqen() function must ensure that the PRM
119 * write to disable all IRQs has reached the PRM before
120 * returning, or spurious PRCM interrupts may occur during
121 * suspend.
122 */
123 if (prcm_irq_setup->suspended) {
124 prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask);
125 prcm_irq_setup->suspend_save_flag = true;
126 }
127
128 /*
129 * Loop until all pending irqs are handled, since
130 * generic_handle_irq() can cause new irqs to come
131 */
132 while (!prcm_irq_setup->suspended) {
133 prcm_irq_setup->read_pending_irqs(pending);
134
135 /* No bit set, then all IRQs are handled */
136 if (find_first_bit(pending, nr_irq) >= nr_irq)
137 break;
138
139 omap_prcm_events_filter_priority(pending, priority_pending);
140
141 /*
142 * Loop on all currently pending irqs so that new irqs
143 * cannot starve previously pending irqs
144 */
145
146 /* Serve priority events first */
147 for_each_set_bit(virtirq, priority_pending, nr_irq)
148 generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
149
150 /* Serve normal events next */
151 for_each_set_bit(virtirq, pending, nr_irq)
152 generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
153 }
154 if (chip->irq_ack)
155 chip->irq_ack(&desc->irq_data);
156 if (chip->irq_eoi)
157 chip->irq_eoi(&desc->irq_data);
158 chip->irq_unmask(&desc->irq_data);
159
160 prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */
161}
162
163/* Public functions */
164
165/**
166 * omap_prcm_event_to_irq - given a PRCM event name, returns the
167 * corresponding IRQ on which the handler should be registered
168 * @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq
169 *
170 * Returns the Linux internal IRQ ID corresponding to @name upon success,
171 * or -ENOENT upon failure.
172 */
173int omap_prcm_event_to_irq(const char *name)
174{
175 int i;
176
177 if (!prcm_irq_setup || !name)
178 return -ENOENT;
179
180 for (i = 0; i < prcm_irq_setup->nr_irqs; i++)
181 if (!strcmp(prcm_irq_setup->irqs[i].name, name))
182 return prcm_irq_setup->base_irq +
183 prcm_irq_setup->irqs[i].offset;
184
185 return -ENOENT;
186}
187
188/**
189 * omap_prcm_irq_cleanup - reverses memory allocated and other steps
190 * done by omap_prcm_register_chain_handler()
191 *
192 * No return value.
193 */
194void omap_prcm_irq_cleanup(void)
195{
196 unsigned int irq;
197 int i;
198
199 if (!prcm_irq_setup) {
200 pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n");
201 return;
202 }
203
204 if (prcm_irq_chips) {
205 for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
206 if (prcm_irq_chips[i])
207 irq_remove_generic_chip(prcm_irq_chips[i],
208 0xffffffff, 0, 0);
209 prcm_irq_chips[i] = NULL;
210 }
211 kfree(prcm_irq_chips);
212 prcm_irq_chips = NULL;
213 }
214
215 kfree(prcm_irq_setup->saved_mask);
216 prcm_irq_setup->saved_mask = NULL;
217
218 kfree(prcm_irq_setup->priority_mask);
219 prcm_irq_setup->priority_mask = NULL;
220
221 irq = prcm_irq_setup->irq;
222 irq_set_chained_handler(irq, NULL);
223
224 if (prcm_irq_setup->base_irq > 0)
225 irq_free_descs(prcm_irq_setup->base_irq,
226 prcm_irq_setup->nr_regs * 32);
227 prcm_irq_setup->base_irq = 0;
228}
229
230void omap_prcm_irq_prepare(void)
231{
232 prcm_irq_setup->suspended = true;
233}
234
235void omap_prcm_irq_complete(void)
236{
237 prcm_irq_setup->suspended = false;
238
239 /* If we have not saved the masks, do not attempt to restore */
240 if (!prcm_irq_setup->suspend_save_flag)
241 return;
242
243 prcm_irq_setup->suspend_save_flag = false;
244
245 /*
246 * Re-enable all masked PRCM irq sources, this causes the PRCM
247 * interrupt to fire immediately if the events were masked
248 * previously in the chain handler
249 */
250 prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask);
251}
252
253/**
254 * omap_prcm_register_chain_handler - initializes the prcm chained interrupt
255 * handler based on provided parameters
256 * @irq_setup: hardware data about the underlying PRM/PRCM
257 *
258 * Set up the PRCM chained interrupt handler on the PRCM IRQ. Sets up
259 * one generic IRQ chip per PRM interrupt status/enable register pair.
260 * Returns 0 upon success, -EINVAL if called twice or if invalid
261 * arguments are passed, or -ENOMEM on any other error.
262 */
263int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
264{
265 int nr_regs;
266 u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
267 int offset, i, irq;
268 struct irq_chip_generic *gc;
269 struct irq_chip_type *ct;
270
271 if (!irq_setup)
272 return -EINVAL;
273
274 nr_regs = irq_setup->nr_regs;
275
276 if (prcm_irq_setup) {
277 pr_err("PRCM: already initialized; won't reinitialize\n");
278 return -EINVAL;
279 }
280
281 if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) {
282 pr_err("PRCM: nr_regs too large\n");
283 return -EINVAL;
284 }
285
286 prcm_irq_setup = irq_setup;
287
288 prcm_irq_chips = kzalloc(sizeof(void *) * nr_regs, GFP_KERNEL);
289 prcm_irq_setup->saved_mask = kzalloc(sizeof(u32) * nr_regs, GFP_KERNEL);
290 prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs,
291 GFP_KERNEL);
292
293 if (!prcm_irq_chips || !prcm_irq_setup->saved_mask ||
294 !prcm_irq_setup->priority_mask)
295 goto err;
296
297 memset(mask, 0, sizeof(mask));
298
299 for (i = 0; i < irq_setup->nr_irqs; i++) {
300 offset = irq_setup->irqs[i].offset;
301 mask[offset >> 5] |= 1 << (offset & 0x1f);
302 if (irq_setup->irqs[i].priority)
303 irq_setup->priority_mask[offset >> 5] |=
304 1 << (offset & 0x1f);
305 }
306
307 irq = irq_setup->irq;
308 irq_set_chained_handler(irq, omap_prcm_irq_handler);
309
310 irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
311 0);
312
313 if (irq_setup->base_irq < 0) {
314 pr_err("PRCM: failed to allocate irq descs: %d\n",
315 irq_setup->base_irq);
316 goto err;
317 }
318
319 for (i = 0; i < irq_setup->nr_regs; i++) {
320 gc = irq_alloc_generic_chip("PRCM", 1,
321 irq_setup->base_irq + i * 32, prm_base.va,
322 handle_level_irq);
323
324 if (!gc) {
325 pr_err("PRCM: failed to allocate generic chip\n");
326 goto err;
327 }
328 ct = gc->chip_types;
329 ct->chip.irq_ack = irq_gc_ack_set_bit;
330 ct->chip.irq_mask = irq_gc_mask_clr_bit;
331 ct->chip.irq_unmask = irq_gc_mask_set_bit;
332
333 ct->regs.ack = irq_setup->ack + i * 4;
334 ct->regs.mask = irq_setup->mask + i * 4;
335
336 irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0);
337 prcm_irq_chips[i] = gc;
338 }
339
340 irq = omap_prcm_event_to_irq("io");
341 omap_pcs_legacy_init(irq, irq_setup->reconfigure_io_chain);
342
343 return 0;
344
345err:
346 omap_prcm_irq_cleanup();
347 return -ENOMEM;
348}
349
350/**
351 * omap2_set_globals_prm - set the PRM base address (for early use)
352 * @prm: PRM base virtual address
353 *
354 * XXX Will be replaced when the PRM/CM drivers are completed.
355 */
356void __init omap2_set_globals_prm(void __iomem *prm)
357{
358 prm_base.va = prm;
359}
360
361/**
362 * prm_read_reset_sources - return the sources of the SoC's last reset
363 *
364 * Return a u32 bitmask representing the reset sources that caused the
365 * SoC to reset. The low-level per-SoC functions called by this
366 * function remap the SoC-specific reset source bits into an
367 * OMAP-common set of reset source bits, defined in
368 * arch/arm/mach-omap2/prm.h. Returns the standardized reset source
369 * u32 bitmask from the hardware upon success, or returns (1 <<
370 * OMAP_UNKNOWN_RST_SRC_ID_SHIFT) if no low-level read_reset_sources()
371 * function was registered.
372 */
373u32 prm_read_reset_sources(void)
374{
375 u32 ret = 1 << OMAP_UNKNOWN_RST_SRC_ID_SHIFT;
376
377 if (prm_ll_data->read_reset_sources)
378 ret = prm_ll_data->read_reset_sources();
379 else
380 WARN_ONCE(1, "prm: %s: no mapping function defined for reset sources\n", __func__);
381
382 return ret;
383}
384
385/**
386 * prm_was_any_context_lost_old - was device context lost? (old API)
387 * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
388 * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
389 * @idx: CONTEXT register offset
390 *
391 * Return 1 if any bits were set in the *_CONTEXT_* register
392 * identified by (@part, @inst, @idx), which means that some context
393 * was lost for that module; otherwise, return 0. XXX Deprecated;
394 * callers need to use a less-SoC-dependent way to identify hardware
395 * IP blocks.
396 */
397bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx)
398{
399 bool ret = true;
400
401 if (prm_ll_data->was_any_context_lost_old)
402 ret = prm_ll_data->was_any_context_lost_old(part, inst, idx);
403 else
404 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
405 __func__);
406
407 return ret;
408}
409
410/**
411 * prm_clear_context_lost_flags_old - clear context loss flags (old API)
412 * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
413 * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
414 * @idx: CONTEXT register offset
415 *
416 * Clear hardware context loss bits for the module identified by
417 * (@part, @inst, @idx). No return value. XXX Deprecated; callers
418 * need to use a less-SoC-dependent way to identify hardware IP
419 * blocks.
420 */
421void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx)
422{
423 if (prm_ll_data->clear_context_loss_flags_old)
424 prm_ll_data->clear_context_loss_flags_old(part, inst, idx);
425 else
426 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
427 __func__);
428}
429
430/**
431 * omap_prm_assert_hardreset - assert hardreset for an IP block
432 * @shift: register bit shift corresponding to the reset line
433 * @part: PRM partition
434 * @prm_mod: PRM submodule base or instance offset
435 * @offset: register offset
436 *
437 * Asserts a hardware reset line for an IP block.
438 */
439int omap_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset)
440{
441 if (!prm_ll_data->assert_hardreset) {
442 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
443 __func__);
444 return -EINVAL;
445 }
446
447 return prm_ll_data->assert_hardreset(shift, part, prm_mod, offset);
448}
449
450/**
451 * omap_prm_deassert_hardreset - deassert hardreset for an IP block
452 * @shift: register bit shift corresponding to the reset line
453 * @st_shift: reset status bit shift corresponding to the reset line
454 * @part: PRM partition
455 * @prm_mod: PRM submodule base or instance offset
456 * @offset: register offset
457 * @st_offset: status register offset
458 *
459 * Deasserts a hardware reset line for an IP block.
460 */
461int omap_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 prm_mod,
462 u16 offset, u16 st_offset)
463{
464 if (!prm_ll_data->deassert_hardreset) {
465 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
466 __func__);
467 return -EINVAL;
468 }
469
470 return prm_ll_data->deassert_hardreset(shift, st_shift, part, prm_mod,
471 offset, st_offset);
472}
473
474/**
475 * omap_prm_is_hardreset_asserted - check the hardreset status for an IP block
476 * @shift: register bit shift corresponding to the reset line
477 * @part: PRM partition
478 * @prm_mod: PRM submodule base or instance offset
479 * @offset: register offset
480 *
481 * Checks if a hardware reset line for an IP block is enabled or not.
482 */
483int omap_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset)
484{
485 if (!prm_ll_data->is_hardreset_asserted) {
486 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
487 __func__);
488 return -EINVAL;
489 }
490
491 return prm_ll_data->is_hardreset_asserted(shift, part, prm_mod, offset);
492}
493
494/**
495 * omap_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
496 *
497 * Clear any previously-latched I/O wakeup events and ensure that the
498 * I/O wakeup gates are aligned with the current mux settings.
499 * Calls SoC specific I/O chain reconfigure function if available,
500 * otherwise does nothing.
501 */
502void omap_prm_reconfigure_io_chain(void)
503{
504 if (!prcm_irq_setup || !prcm_irq_setup->reconfigure_io_chain)
505 return;
506
507 prcm_irq_setup->reconfigure_io_chain();
508}
509
510/**
511 * omap_prm_reset_system - trigger global SW reset
512 *
513 * Triggers SoC specific global warm reset to reboot the device.
514 */
515void omap_prm_reset_system(void)
516{
517 if (!prm_ll_data->reset_system) {
518 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
519 __func__);
520 return;
521 }
522
523 prm_ll_data->reset_system();
524
525 while (1)
526 cpu_relax();
527}
528
529/**
530 * omap_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt
531 * @module: PRM module to clear wakeups from
532 * @regs: register to clear
533 * @wkst_mask: wkst bits to clear
534 *
535 * Clears any wakeup events for the module and register set defined.
536 * Uses SoC specific implementation to do the actual wakeup status
537 * clearing.
538 */
539int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
540{
541 if (!prm_ll_data->clear_mod_irqs) {
542 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
543 __func__);
544 return -EINVAL;
545 }
546
547 return prm_ll_data->clear_mod_irqs(module, regs, wkst_mask);
548}
549
550/**
551 * omap_prm_vp_check_txdone - check voltage processor TX done status
552 *
553 * Checks if voltage processor transmission has been completed.
554 * Returns non-zero if a transmission has completed, 0 otherwise.
555 */
556u32 omap_prm_vp_check_txdone(u8 vp_id)
557{
558 if (!prm_ll_data->vp_check_txdone) {
559 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
560 __func__);
561 return 0;
562 }
563
564 return prm_ll_data->vp_check_txdone(vp_id);
565}
566
567/**
568 * omap_prm_vp_clear_txdone - clears voltage processor TX done status
569 *
570 * Clears the status bit for completed voltage processor transmission
571 * returned by prm_vp_check_txdone.
572 */
573void omap_prm_vp_clear_txdone(u8 vp_id)
574{
575 if (!prm_ll_data->vp_clear_txdone) {
576 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
577 __func__);
578 return;
579 }
580
581 prm_ll_data->vp_clear_txdone(vp_id);
582}
583
584/**
585 * prm_register - register per-SoC low-level data with the PRM
586 * @pld: low-level per-SoC OMAP PRM data & function pointers to register
587 *
588 * Register per-SoC low-level OMAP PRM data and function pointers with
589 * the OMAP PRM common interface. The caller must keep the data
590 * pointed to by @pld valid until it calls prm_unregister() and
591 * it returns successfully. Returns 0 upon success, -EINVAL if @pld
592 * is NULL, or -EEXIST if prm_register() has already been called
593 * without an intervening prm_unregister().
594 */
595int prm_register(struct prm_ll_data *pld)
596{
597 if (!pld)
598 return -EINVAL;
599
600 if (prm_ll_data != &null_prm_ll_data)
601 return -EEXIST;
602
603 prm_ll_data = pld;
604
605 return 0;
606}
607
608/**
609 * prm_unregister - unregister per-SoC low-level data & function pointers
610 * @pld: low-level per-SoC OMAP PRM data & function pointers to unregister
611 *
612 * Unregister per-SoC low-level OMAP PRM data and function pointers
613 * that were previously registered with prm_register(). The
614 * caller may not destroy any of the data pointed to by @pld until
615 * this function returns successfully. Returns 0 upon success, or
616 * -EINVAL if @pld is NULL or if @pld does not match the struct
617 * prm_ll_data * previously registered by prm_register().
618 */
619int prm_unregister(struct prm_ll_data *pld)
620{
621 if (!pld || prm_ll_data != pld)
622 return -EINVAL;
623
624 prm_ll_data = &null_prm_ll_data;
625
626 return 0;
627}
628
629#ifdef CONFIG_ARCH_OMAP2
630static struct omap_prcm_init_data omap2_prm_data __initdata = {
631 .index = TI_CLKM_PRM,
632 .init = omap2xxx_prm_init,
633};
634#endif
635
636#ifdef CONFIG_ARCH_OMAP3
637static struct omap_prcm_init_data omap3_prm_data __initdata = {
638 .index = TI_CLKM_PRM,
639 .init = omap3xxx_prm_init,
640
641 /*
642 * IVA2 offset is a negative value, must offset the prm_base
643 * address by this to get it to positive
644 */
645 .offset = -OMAP3430_IVA2_MOD,
646};
647#endif
648
649#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_TI81XX)
650static struct omap_prcm_init_data am3_prm_data __initdata = {
651 .index = TI_CLKM_PRM,
652 .init = am33xx_prm_init,
653};
654#endif
655
656#ifdef CONFIG_SOC_TI81XX
657static struct omap_prcm_init_data dm814_pllss_data __initdata = {
658 .index = TI_CLKM_PLLSS,
659 .init = am33xx_prm_init,
660};
661#endif
662
663#ifdef CONFIG_ARCH_OMAP4
664static struct omap_prcm_init_data omap4_prm_data __initdata = {
665 .index = TI_CLKM_PRM,
666 .init = omap44xx_prm_init,
667 .device_inst_offset = OMAP4430_PRM_DEVICE_INST,
668 .flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE,
669};
670#endif
671
672#ifdef CONFIG_SOC_OMAP5
673static struct omap_prcm_init_data omap5_prm_data __initdata = {
674 .index = TI_CLKM_PRM,
675 .init = omap44xx_prm_init,
676 .device_inst_offset = OMAP54XX_PRM_DEVICE_INST,
677 .flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE,
678};
679#endif
680
681#ifdef CONFIG_SOC_DRA7XX
682static struct omap_prcm_init_data dra7_prm_data __initdata = {
683 .index = TI_CLKM_PRM,
684 .init = omap44xx_prm_init,
685 .device_inst_offset = DRA7XX_PRM_DEVICE_INST,
686 .flags = PRM_HAS_IO_WAKEUP,
687};
688#endif
689
690#ifdef CONFIG_SOC_AM43XX
691static struct omap_prcm_init_data am4_prm_data __initdata = {
692 .index = TI_CLKM_PRM,
693 .init = omap44xx_prm_init,
694 .device_inst_offset = AM43XX_PRM_DEVICE_INST,
695 .flags = PRM_HAS_IO_WAKEUP,
696};
697#endif
698
699#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
700static struct omap_prcm_init_data scrm_data __initdata = {
701 .index = TI_CLKM_SCRM,
702};
703#endif
704
705static const struct of_device_id omap_prcm_dt_match_table[] __initconst = {
706#ifdef CONFIG_SOC_AM33XX
707 { .compatible = "ti,am3-prcm", .data = &am3_prm_data },
708#endif
709#ifdef CONFIG_SOC_AM43XX
710 { .compatible = "ti,am4-prcm", .data = &am4_prm_data },
711#endif
712#ifdef CONFIG_SOC_TI81XX
713 { .compatible = "ti,dm814-prcm", .data = &am3_prm_data },
714 { .compatible = "ti,dm814-pllss", .data = &dm814_pllss_data },
715 { .compatible = "ti,dm816-prcm", .data = &am3_prm_data },
716#endif
717#ifdef CONFIG_ARCH_OMAP2
718 { .compatible = "ti,omap2-prcm", .data = &omap2_prm_data },
719#endif
720#ifdef CONFIG_ARCH_OMAP3
721 { .compatible = "ti,omap3-prm", .data = &omap3_prm_data },
722#endif
723#ifdef CONFIG_ARCH_OMAP4
724 { .compatible = "ti,omap4-prm", .data = &omap4_prm_data },
725 { .compatible = "ti,omap4-scrm", .data = &scrm_data },
726#endif
727#ifdef CONFIG_SOC_OMAP5
728 { .compatible = "ti,omap5-prm", .data = &omap5_prm_data },
729 { .compatible = "ti,omap5-scrm", .data = &scrm_data },
730#endif
731#ifdef CONFIG_SOC_DRA7XX
732 { .compatible = "ti,dra7-prm", .data = &dra7_prm_data },
733#endif
734 { }
735};
736
737/**
738 * omap2_prm_base_init - initialize iomappings for the PRM driver
739 *
740 * Detects and initializes the iomappings for the PRM driver, based
741 * on the DT data. Returns 0 in success, negative error value
742 * otherwise.
743 */
744int __init omap2_prm_base_init(void)
745{
746 struct device_node *np;
747 const struct of_device_id *match;
748 struct omap_prcm_init_data *data;
749 struct resource res;
750 int ret;
751
752 for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) {
753 data = (struct omap_prcm_init_data *)match->data;
754
755 ret = of_address_to_resource(np, 0, &res);
756 if (ret)
757 return ret;
758
759 data->mem = ioremap(res.start, resource_size(&res));
760
761 if (data->index == TI_CLKM_PRM) {
762 prm_base.va = data->mem + data->offset;
763 prm_base.pa = res.start + data->offset;
764 }
765
766 data->np = np;
767
768 if (data->init)
769 data->init(data);
770 }
771
772 return 0;
773}
774
775int __init omap2_prcm_base_init(void)
776{
777 int ret;
778
779 ret = omap2_prm_base_init();
780 if (ret)
781 return ret;
782
783 return omap2_cm_base_init();
784}
785
786/**
787 * omap_prcm_init - low level init for the PRCM drivers
788 *
789 * Initializes the low level clock infrastructure for PRCM drivers.
790 * Returns 0 in success, negative error value in failure.
791 */
792int __init omap_prcm_init(void)
793{
794 struct device_node *np;
795 const struct of_device_id *match;
796 const struct omap_prcm_init_data *data;
797 int ret;
798
799 for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) {
800 data = match->data;
801
802 ret = omap2_clk_provider_init(np, data->index, NULL, data->mem);
803 if (ret)
804 return ret;
805 }
806
807 omap_cm_init();
808
809 return 0;
810}
811
812static int __init prm_late_init(void)
813{
814 if (prm_ll_data->late_init)
815 return prm_ll_data->late_init();
816 return 0;
817}
818subsys_initcall(prm_late_init);