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1/*
2 * CAN bus driver for Microchip 251x CAN Controller with SPI Interface
3 *
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
6 *
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
8 *
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
12 *
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
15 *
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
19 * Copyright 2007
20 *
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the version 2 of the GNU General Public License
23 * as published by the Free Software Foundation
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see <http://www.gnu.org/licenses/>.
32 *
33 *
34 *
35 * Your platform definition file should specify something like:
36 *
37 * static struct mcp251x_platform_data mcp251x_info = {
38 * .oscillator_frequency = 8000000,
39 * };
40 *
41 * static struct spi_board_info spi_board_info[] = {
42 * {
43 * .modalias = "mcp2510",
44 * // or "mcp2515" depending on your controller
45 * .platform_data = &mcp251x_info,
46 * .irq = IRQ_EINT13,
47 * .max_speed_hz = 2*1000*1000,
48 * .chip_select = 2,
49 * },
50 * };
51 *
52 * Please see mcp251x.h for a description of the fields in
53 * struct mcp251x_platform_data.
54 *
55 */
56
57#include <linux/can/core.h>
58#include <linux/can/dev.h>
59#include <linux/can/led.h>
60#include <linux/can/platform/mcp251x.h>
61#include <linux/clk.h>
62#include <linux/completion.h>
63#include <linux/delay.h>
64#include <linux/device.h>
65#include <linux/dma-mapping.h>
66#include <linux/freezer.h>
67#include <linux/interrupt.h>
68#include <linux/io.h>
69#include <linux/kernel.h>
70#include <linux/module.h>
71#include <linux/netdevice.h>
72#include <linux/of.h>
73#include <linux/of_device.h>
74#include <linux/platform_device.h>
75#include <linux/slab.h>
76#include <linux/spi/spi.h>
77#include <linux/uaccess.h>
78#include <linux/regulator/consumer.h>
79
80/* SPI interface instruction set */
81#define INSTRUCTION_WRITE 0x02
82#define INSTRUCTION_READ 0x03
83#define INSTRUCTION_BIT_MODIFY 0x05
84#define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
85#define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
86#define INSTRUCTION_RESET 0xC0
87#define RTS_TXB0 0x01
88#define RTS_TXB1 0x02
89#define RTS_TXB2 0x04
90#define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07))
91
92
93/* MPC251x registers */
94#define CANSTAT 0x0e
95#define CANCTRL 0x0f
96# define CANCTRL_REQOP_MASK 0xe0
97# define CANCTRL_REQOP_CONF 0x80
98# define CANCTRL_REQOP_LISTEN_ONLY 0x60
99# define CANCTRL_REQOP_LOOPBACK 0x40
100# define CANCTRL_REQOP_SLEEP 0x20
101# define CANCTRL_REQOP_NORMAL 0x00
102# define CANCTRL_OSM 0x08
103# define CANCTRL_ABAT 0x10
104#define TEC 0x1c
105#define REC 0x1d
106#define CNF1 0x2a
107# define CNF1_SJW_SHIFT 6
108#define CNF2 0x29
109# define CNF2_BTLMODE 0x80
110# define CNF2_SAM 0x40
111# define CNF2_PS1_SHIFT 3
112#define CNF3 0x28
113# define CNF3_SOF 0x08
114# define CNF3_WAKFIL 0x04
115# define CNF3_PHSEG2_MASK 0x07
116#define CANINTE 0x2b
117# define CANINTE_MERRE 0x80
118# define CANINTE_WAKIE 0x40
119# define CANINTE_ERRIE 0x20
120# define CANINTE_TX2IE 0x10
121# define CANINTE_TX1IE 0x08
122# define CANINTE_TX0IE 0x04
123# define CANINTE_RX1IE 0x02
124# define CANINTE_RX0IE 0x01
125#define CANINTF 0x2c
126# define CANINTF_MERRF 0x80
127# define CANINTF_WAKIF 0x40
128# define CANINTF_ERRIF 0x20
129# define CANINTF_TX2IF 0x10
130# define CANINTF_TX1IF 0x08
131# define CANINTF_TX0IF 0x04
132# define CANINTF_RX1IF 0x02
133# define CANINTF_RX0IF 0x01
134# define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF)
135# define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
136# define CANINTF_ERR (CANINTF_ERRIF)
137#define EFLG 0x2d
138# define EFLG_EWARN 0x01
139# define EFLG_RXWAR 0x02
140# define EFLG_TXWAR 0x04
141# define EFLG_RXEP 0x08
142# define EFLG_TXEP 0x10
143# define EFLG_TXBO 0x20
144# define EFLG_RX0OVR 0x40
145# define EFLG_RX1OVR 0x80
146#define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
147# define TXBCTRL_ABTF 0x40
148# define TXBCTRL_MLOA 0x20
149# define TXBCTRL_TXERR 0x10
150# define TXBCTRL_TXREQ 0x08
151#define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
152# define SIDH_SHIFT 3
153#define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
154# define SIDL_SID_MASK 7
155# define SIDL_SID_SHIFT 5
156# define SIDL_EXIDE_SHIFT 3
157# define SIDL_EID_SHIFT 16
158# define SIDL_EID_MASK 3
159#define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
160#define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
161#define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
162# define DLC_RTR_SHIFT 6
163#define TXBCTRL_OFF 0
164#define TXBSIDH_OFF 1
165#define TXBSIDL_OFF 2
166#define TXBEID8_OFF 3
167#define TXBEID0_OFF 4
168#define TXBDLC_OFF 5
169#define TXBDAT_OFF 6
170#define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
171# define RXBCTRL_BUKT 0x04
172# define RXBCTRL_RXM0 0x20
173# define RXBCTRL_RXM1 0x40
174#define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
175# define RXBSIDH_SHIFT 3
176#define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
177# define RXBSIDL_IDE 0x08
178# define RXBSIDL_SRR 0x10
179# define RXBSIDL_EID 3
180# define RXBSIDL_SHIFT 5
181#define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
182#define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
183#define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
184# define RXBDLC_LEN_MASK 0x0f
185# define RXBDLC_RTR 0x40
186#define RXBCTRL_OFF 0
187#define RXBSIDH_OFF 1
188#define RXBSIDL_OFF 2
189#define RXBEID8_OFF 3
190#define RXBEID0_OFF 4
191#define RXBDLC_OFF 5
192#define RXBDAT_OFF 6
193#define RXFSID(n) ((n < 3) ? 0 : 4)
194#define RXFSIDH(n) ((n) * 4 + RXFSID(n))
195#define RXFSIDL(n) ((n) * 4 + 1 + RXFSID(n))
196#define RXFEID8(n) ((n) * 4 + 2 + RXFSID(n))
197#define RXFEID0(n) ((n) * 4 + 3 + RXFSID(n))
198#define RXMSIDH(n) ((n) * 4 + 0x20)
199#define RXMSIDL(n) ((n) * 4 + 0x21)
200#define RXMEID8(n) ((n) * 4 + 0x22)
201#define RXMEID0(n) ((n) * 4 + 0x23)
202
203#define GET_BYTE(val, byte) \
204 (((val) >> ((byte) * 8)) & 0xff)
205#define SET_BYTE(val, byte) \
206 (((val) & 0xff) << ((byte) * 8))
207
208/*
209 * Buffer size required for the largest SPI transfer (i.e., reading a
210 * frame)
211 */
212#define CAN_FRAME_MAX_DATA_LEN 8
213#define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
214#define CAN_FRAME_MAX_BITS 128
215
216#define TX_ECHO_SKB_MAX 1
217
218#define MCP251X_OST_DELAY_MS (5)
219
220#define DEVICE_NAME "mcp251x"
221
222static int mcp251x_enable_dma; /* Enable SPI DMA. Default: 0 (Off) */
223module_param(mcp251x_enable_dma, int, S_IRUGO);
224MODULE_PARM_DESC(mcp251x_enable_dma, "Enable SPI DMA. Default: 0 (Off)");
225
226static const struct can_bittiming_const mcp251x_bittiming_const = {
227 .name = DEVICE_NAME,
228 .tseg1_min = 3,
229 .tseg1_max = 16,
230 .tseg2_min = 2,
231 .tseg2_max = 8,
232 .sjw_max = 4,
233 .brp_min = 1,
234 .brp_max = 64,
235 .brp_inc = 1,
236};
237
238enum mcp251x_model {
239 CAN_MCP251X_MCP2510 = 0x2510,
240 CAN_MCP251X_MCP2515 = 0x2515,
241};
242
243struct mcp251x_priv {
244 struct can_priv can;
245 struct net_device *net;
246 struct spi_device *spi;
247 enum mcp251x_model model;
248
249 struct mutex mcp_lock; /* SPI device lock */
250
251 u8 *spi_tx_buf;
252 u8 *spi_rx_buf;
253 dma_addr_t spi_tx_dma;
254 dma_addr_t spi_rx_dma;
255
256 struct sk_buff *tx_skb;
257 int tx_len;
258
259 struct workqueue_struct *wq;
260 struct work_struct tx_work;
261 struct work_struct restart_work;
262
263 int force_quit;
264 int after_suspend;
265#define AFTER_SUSPEND_UP 1
266#define AFTER_SUSPEND_DOWN 2
267#define AFTER_SUSPEND_POWER 4
268#define AFTER_SUSPEND_RESTART 8
269 int restart_tx;
270 struct regulator *power;
271 struct regulator *transceiver;
272 struct clk *clk;
273};
274
275#define MCP251X_IS(_model) \
276static inline int mcp251x_is_##_model(struct spi_device *spi) \
277{ \
278 struct mcp251x_priv *priv = spi_get_drvdata(spi); \
279 return priv->model == CAN_MCP251X_MCP##_model; \
280}
281
282MCP251X_IS(2510);
283MCP251X_IS(2515);
284
285static void mcp251x_clean(struct net_device *net)
286{
287 struct mcp251x_priv *priv = netdev_priv(net);
288
289 if (priv->tx_skb || priv->tx_len)
290 net->stats.tx_errors++;
291 if (priv->tx_skb)
292 dev_kfree_skb(priv->tx_skb);
293 if (priv->tx_len)
294 can_free_echo_skb(priv->net, 0);
295 priv->tx_skb = NULL;
296 priv->tx_len = 0;
297}
298
299/*
300 * Note about handling of error return of mcp251x_spi_trans: accessing
301 * registers via SPI is not really different conceptually than using
302 * normal I/O assembler instructions, although it's much more
303 * complicated from a practical POV. So it's not advisable to always
304 * check the return value of this function. Imagine that every
305 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
306 * error();", it would be a great mess (well there are some situation
307 * when exception handling C++ like could be useful after all). So we
308 * just check that transfers are OK at the beginning of our
309 * conversation with the chip and to avoid doing really nasty things
310 * (like injecting bogus packets in the network stack).
311 */
312static int mcp251x_spi_trans(struct spi_device *spi, int len)
313{
314 struct mcp251x_priv *priv = spi_get_drvdata(spi);
315 struct spi_transfer t = {
316 .tx_buf = priv->spi_tx_buf,
317 .rx_buf = priv->spi_rx_buf,
318 .len = len,
319 .cs_change = 0,
320 };
321 struct spi_message m;
322 int ret;
323
324 spi_message_init(&m);
325
326 if (mcp251x_enable_dma) {
327 t.tx_dma = priv->spi_tx_dma;
328 t.rx_dma = priv->spi_rx_dma;
329 m.is_dma_mapped = 1;
330 }
331
332 spi_message_add_tail(&t, &m);
333
334 ret = spi_sync(spi, &m);
335 if (ret)
336 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
337 return ret;
338}
339
340static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg)
341{
342 struct mcp251x_priv *priv = spi_get_drvdata(spi);
343 u8 val = 0;
344
345 priv->spi_tx_buf[0] = INSTRUCTION_READ;
346 priv->spi_tx_buf[1] = reg;
347
348 mcp251x_spi_trans(spi, 3);
349 val = priv->spi_rx_buf[2];
350
351 return val;
352}
353
354static void mcp251x_read_2regs(struct spi_device *spi, uint8_t reg,
355 uint8_t *v1, uint8_t *v2)
356{
357 struct mcp251x_priv *priv = spi_get_drvdata(spi);
358
359 priv->spi_tx_buf[0] = INSTRUCTION_READ;
360 priv->spi_tx_buf[1] = reg;
361
362 mcp251x_spi_trans(spi, 4);
363
364 *v1 = priv->spi_rx_buf[2];
365 *v2 = priv->spi_rx_buf[3];
366}
367
368static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val)
369{
370 struct mcp251x_priv *priv = spi_get_drvdata(spi);
371
372 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
373 priv->spi_tx_buf[1] = reg;
374 priv->spi_tx_buf[2] = val;
375
376 mcp251x_spi_trans(spi, 3);
377}
378
379static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
380 u8 mask, uint8_t val)
381{
382 struct mcp251x_priv *priv = spi_get_drvdata(spi);
383
384 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
385 priv->spi_tx_buf[1] = reg;
386 priv->spi_tx_buf[2] = mask;
387 priv->spi_tx_buf[3] = val;
388
389 mcp251x_spi_trans(spi, 4);
390}
391
392static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
393 int len, int tx_buf_idx)
394{
395 struct mcp251x_priv *priv = spi_get_drvdata(spi);
396
397 if (mcp251x_is_2510(spi)) {
398 int i;
399
400 for (i = 1; i < TXBDAT_OFF + len; i++)
401 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
402 buf[i]);
403 } else {
404 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
405 mcp251x_spi_trans(spi, TXBDAT_OFF + len);
406 }
407}
408
409static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
410 int tx_buf_idx)
411{
412 struct mcp251x_priv *priv = spi_get_drvdata(spi);
413 u32 sid, eid, exide, rtr;
414 u8 buf[SPI_TRANSFER_BUF_LEN];
415
416 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
417 if (exide)
418 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
419 else
420 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
421 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
422 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
423
424 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
425 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
426 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
427 (exide << SIDL_EXIDE_SHIFT) |
428 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
429 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
430 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
431 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc;
432 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc);
433 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx);
434
435 /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */
436 priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx);
437 mcp251x_spi_trans(priv->spi, 1);
438}
439
440static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
441 int buf_idx)
442{
443 struct mcp251x_priv *priv = spi_get_drvdata(spi);
444
445 if (mcp251x_is_2510(spi)) {
446 int i, len;
447
448 for (i = 1; i < RXBDAT_OFF; i++)
449 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
450
451 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
452 for (; i < (RXBDAT_OFF + len); i++)
453 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
454 } else {
455 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
456 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
457 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
458 }
459}
460
461static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
462{
463 struct mcp251x_priv *priv = spi_get_drvdata(spi);
464 struct sk_buff *skb;
465 struct can_frame *frame;
466 u8 buf[SPI_TRANSFER_BUF_LEN];
467
468 skb = alloc_can_skb(priv->net, &frame);
469 if (!skb) {
470 dev_err(&spi->dev, "cannot allocate RX skb\n");
471 priv->net->stats.rx_dropped++;
472 return;
473 }
474
475 mcp251x_hw_rx_frame(spi, buf, buf_idx);
476 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
477 /* Extended ID format */
478 frame->can_id = CAN_EFF_FLAG;
479 frame->can_id |=
480 /* Extended ID part */
481 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
482 SET_BYTE(buf[RXBEID8_OFF], 1) |
483 SET_BYTE(buf[RXBEID0_OFF], 0) |
484 /* Standard ID part */
485 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
486 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
487 /* Remote transmission request */
488 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
489 frame->can_id |= CAN_RTR_FLAG;
490 } else {
491 /* Standard ID format */
492 frame->can_id =
493 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
494 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
495 if (buf[RXBSIDL_OFF] & RXBSIDL_SRR)
496 frame->can_id |= CAN_RTR_FLAG;
497 }
498 /* Data length */
499 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
500 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc);
501
502 priv->net->stats.rx_packets++;
503 priv->net->stats.rx_bytes += frame->can_dlc;
504
505 can_led_event(priv->net, CAN_LED_EVENT_RX);
506
507 netif_rx_ni(skb);
508}
509
510static void mcp251x_hw_sleep(struct spi_device *spi)
511{
512 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
513}
514
515static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
516 struct net_device *net)
517{
518 struct mcp251x_priv *priv = netdev_priv(net);
519 struct spi_device *spi = priv->spi;
520
521 if (priv->tx_skb || priv->tx_len) {
522 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
523 return NETDEV_TX_BUSY;
524 }
525
526 if (can_dropped_invalid_skb(net, skb))
527 return NETDEV_TX_OK;
528
529 netif_stop_queue(net);
530 priv->tx_skb = skb;
531 queue_work(priv->wq, &priv->tx_work);
532
533 return NETDEV_TX_OK;
534}
535
536static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
537{
538 struct mcp251x_priv *priv = netdev_priv(net);
539
540 switch (mode) {
541 case CAN_MODE_START:
542 mcp251x_clean(net);
543 /* We have to delay work since SPI I/O may sleep */
544 priv->can.state = CAN_STATE_ERROR_ACTIVE;
545 priv->restart_tx = 1;
546 if (priv->can.restart_ms == 0)
547 priv->after_suspend = AFTER_SUSPEND_RESTART;
548 queue_work(priv->wq, &priv->restart_work);
549 break;
550 default:
551 return -EOPNOTSUPP;
552 }
553
554 return 0;
555}
556
557static int mcp251x_set_normal_mode(struct spi_device *spi)
558{
559 struct mcp251x_priv *priv = spi_get_drvdata(spi);
560 unsigned long timeout;
561
562 /* Enable interrupts */
563 mcp251x_write_reg(spi, CANINTE,
564 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
565 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
566
567 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
568 /* Put device into loopback mode */
569 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
570 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
571 /* Put device into listen-only mode */
572 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
573 } else {
574 /* Put device into normal mode */
575 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
576
577 /* Wait for the device to enter normal mode */
578 timeout = jiffies + HZ;
579 while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) {
580 schedule();
581 if (time_after(jiffies, timeout)) {
582 dev_err(&spi->dev, "MCP251x didn't"
583 " enter in normal mode\n");
584 return -EBUSY;
585 }
586 }
587 }
588 priv->can.state = CAN_STATE_ERROR_ACTIVE;
589 return 0;
590}
591
592static int mcp251x_do_set_bittiming(struct net_device *net)
593{
594 struct mcp251x_priv *priv = netdev_priv(net);
595 struct can_bittiming *bt = &priv->can.bittiming;
596 struct spi_device *spi = priv->spi;
597
598 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
599 (bt->brp - 1));
600 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
601 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
602 CNF2_SAM : 0) |
603 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
604 (bt->prop_seg - 1));
605 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
606 (bt->phase_seg2 - 1));
607 dev_dbg(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
608 mcp251x_read_reg(spi, CNF1),
609 mcp251x_read_reg(spi, CNF2),
610 mcp251x_read_reg(spi, CNF3));
611
612 return 0;
613}
614
615static int mcp251x_setup(struct net_device *net, struct mcp251x_priv *priv,
616 struct spi_device *spi)
617{
618 mcp251x_do_set_bittiming(net);
619
620 mcp251x_write_reg(spi, RXBCTRL(0),
621 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
622 mcp251x_write_reg(spi, RXBCTRL(1),
623 RXBCTRL_RXM0 | RXBCTRL_RXM1);
624 return 0;
625}
626
627static int mcp251x_hw_reset(struct spi_device *spi)
628{
629 struct mcp251x_priv *priv = spi_get_drvdata(spi);
630 u8 reg;
631 int ret;
632
633 /* Wait for oscillator startup timer after power up */
634 mdelay(MCP251X_OST_DELAY_MS);
635
636 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
637 ret = mcp251x_spi_trans(spi, 1);
638 if (ret)
639 return ret;
640
641 /* Wait for oscillator startup timer after reset */
642 mdelay(MCP251X_OST_DELAY_MS);
643
644 reg = mcp251x_read_reg(spi, CANSTAT);
645 if ((reg & CANCTRL_REQOP_MASK) != CANCTRL_REQOP_CONF)
646 return -ENODEV;
647
648 return 0;
649}
650
651static int mcp251x_hw_probe(struct spi_device *spi)
652{
653 u8 ctrl;
654 int ret;
655
656 ret = mcp251x_hw_reset(spi);
657 if (ret)
658 return ret;
659
660 ctrl = mcp251x_read_reg(spi, CANCTRL);
661
662 dev_dbg(&spi->dev, "CANCTRL 0x%02x\n", ctrl);
663
664 /* Check for power up default value */
665 if ((ctrl & 0x17) != 0x07)
666 return -ENODEV;
667
668 return 0;
669}
670
671static int mcp251x_power_enable(struct regulator *reg, int enable)
672{
673 if (IS_ERR_OR_NULL(reg))
674 return 0;
675
676 if (enable)
677 return regulator_enable(reg);
678 else
679 return regulator_disable(reg);
680}
681
682static void mcp251x_open_clean(struct net_device *net)
683{
684 struct mcp251x_priv *priv = netdev_priv(net);
685 struct spi_device *spi = priv->spi;
686
687 free_irq(spi->irq, priv);
688 mcp251x_hw_sleep(spi);
689 mcp251x_power_enable(priv->transceiver, 0);
690 close_candev(net);
691}
692
693static int mcp251x_stop(struct net_device *net)
694{
695 struct mcp251x_priv *priv = netdev_priv(net);
696 struct spi_device *spi = priv->spi;
697
698 close_candev(net);
699
700 priv->force_quit = 1;
701 free_irq(spi->irq, priv);
702 destroy_workqueue(priv->wq);
703 priv->wq = NULL;
704
705 mutex_lock(&priv->mcp_lock);
706
707 /* Disable and clear pending interrupts */
708 mcp251x_write_reg(spi, CANINTE, 0x00);
709 mcp251x_write_reg(spi, CANINTF, 0x00);
710
711 mcp251x_write_reg(spi, TXBCTRL(0), 0);
712 mcp251x_clean(net);
713
714 mcp251x_hw_sleep(spi);
715
716 mcp251x_power_enable(priv->transceiver, 0);
717
718 priv->can.state = CAN_STATE_STOPPED;
719
720 mutex_unlock(&priv->mcp_lock);
721
722 can_led_event(net, CAN_LED_EVENT_STOP);
723
724 return 0;
725}
726
727static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
728{
729 struct sk_buff *skb;
730 struct can_frame *frame;
731
732 skb = alloc_can_err_skb(net, &frame);
733 if (skb) {
734 frame->can_id |= can_id;
735 frame->data[1] = data1;
736 netif_rx_ni(skb);
737 } else {
738 netdev_err(net, "cannot allocate error skb\n");
739 }
740}
741
742static void mcp251x_tx_work_handler(struct work_struct *ws)
743{
744 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
745 tx_work);
746 struct spi_device *spi = priv->spi;
747 struct net_device *net = priv->net;
748 struct can_frame *frame;
749
750 mutex_lock(&priv->mcp_lock);
751 if (priv->tx_skb) {
752 if (priv->can.state == CAN_STATE_BUS_OFF) {
753 mcp251x_clean(net);
754 } else {
755 frame = (struct can_frame *)priv->tx_skb->data;
756
757 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
758 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
759 mcp251x_hw_tx(spi, frame, 0);
760 priv->tx_len = 1 + frame->can_dlc;
761 can_put_echo_skb(priv->tx_skb, net, 0);
762 priv->tx_skb = NULL;
763 }
764 }
765 mutex_unlock(&priv->mcp_lock);
766}
767
768static void mcp251x_restart_work_handler(struct work_struct *ws)
769{
770 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
771 restart_work);
772 struct spi_device *spi = priv->spi;
773 struct net_device *net = priv->net;
774
775 mutex_lock(&priv->mcp_lock);
776 if (priv->after_suspend) {
777 mcp251x_hw_reset(spi);
778 mcp251x_setup(net, priv, spi);
779 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
780 mcp251x_set_normal_mode(spi);
781 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
782 netif_device_attach(net);
783 mcp251x_clean(net);
784 mcp251x_set_normal_mode(spi);
785 netif_wake_queue(net);
786 } else {
787 mcp251x_hw_sleep(spi);
788 }
789 priv->after_suspend = 0;
790 priv->force_quit = 0;
791 }
792
793 if (priv->restart_tx) {
794 priv->restart_tx = 0;
795 mcp251x_write_reg(spi, TXBCTRL(0), 0);
796 mcp251x_clean(net);
797 netif_wake_queue(net);
798 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
799 }
800 mutex_unlock(&priv->mcp_lock);
801}
802
803static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
804{
805 struct mcp251x_priv *priv = dev_id;
806 struct spi_device *spi = priv->spi;
807 struct net_device *net = priv->net;
808
809 mutex_lock(&priv->mcp_lock);
810 while (!priv->force_quit) {
811 enum can_state new_state;
812 u8 intf, eflag;
813 u8 clear_intf = 0;
814 int can_id = 0, data1 = 0;
815
816 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
817
818 /* mask out flags we don't care about */
819 intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR;
820
821 /* receive buffer 0 */
822 if (intf & CANINTF_RX0IF) {
823 mcp251x_hw_rx(spi, 0);
824 /*
825 * Free one buffer ASAP
826 * (The MCP2515 does this automatically.)
827 */
828 if (mcp251x_is_2510(spi))
829 mcp251x_write_bits(spi, CANINTF, CANINTF_RX0IF, 0x00);
830 }
831
832 /* receive buffer 1 */
833 if (intf & CANINTF_RX1IF) {
834 mcp251x_hw_rx(spi, 1);
835 /* the MCP2515 does this automatically */
836 if (mcp251x_is_2510(spi))
837 clear_intf |= CANINTF_RX1IF;
838 }
839
840 /* any error or tx interrupt we need to clear? */
841 if (intf & (CANINTF_ERR | CANINTF_TX))
842 clear_intf |= intf & (CANINTF_ERR | CANINTF_TX);
843 if (clear_intf)
844 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
845
846 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR))
847 mcp251x_write_bits(spi, EFLG, eflag, 0x00);
848
849 /* Update can state */
850 if (eflag & EFLG_TXBO) {
851 new_state = CAN_STATE_BUS_OFF;
852 can_id |= CAN_ERR_BUSOFF;
853 } else if (eflag & EFLG_TXEP) {
854 new_state = CAN_STATE_ERROR_PASSIVE;
855 can_id |= CAN_ERR_CRTL;
856 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
857 } else if (eflag & EFLG_RXEP) {
858 new_state = CAN_STATE_ERROR_PASSIVE;
859 can_id |= CAN_ERR_CRTL;
860 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
861 } else if (eflag & EFLG_TXWAR) {
862 new_state = CAN_STATE_ERROR_WARNING;
863 can_id |= CAN_ERR_CRTL;
864 data1 |= CAN_ERR_CRTL_TX_WARNING;
865 } else if (eflag & EFLG_RXWAR) {
866 new_state = CAN_STATE_ERROR_WARNING;
867 can_id |= CAN_ERR_CRTL;
868 data1 |= CAN_ERR_CRTL_RX_WARNING;
869 } else {
870 new_state = CAN_STATE_ERROR_ACTIVE;
871 }
872
873 /* Update can state statistics */
874 switch (priv->can.state) {
875 case CAN_STATE_ERROR_ACTIVE:
876 if (new_state >= CAN_STATE_ERROR_WARNING &&
877 new_state <= CAN_STATE_BUS_OFF)
878 priv->can.can_stats.error_warning++;
879 case CAN_STATE_ERROR_WARNING: /* fallthrough */
880 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
881 new_state <= CAN_STATE_BUS_OFF)
882 priv->can.can_stats.error_passive++;
883 break;
884 default:
885 break;
886 }
887 priv->can.state = new_state;
888
889 if (intf & CANINTF_ERRIF) {
890 /* Handle overflow counters */
891 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
892 if (eflag & EFLG_RX0OVR) {
893 net->stats.rx_over_errors++;
894 net->stats.rx_errors++;
895 }
896 if (eflag & EFLG_RX1OVR) {
897 net->stats.rx_over_errors++;
898 net->stats.rx_errors++;
899 }
900 can_id |= CAN_ERR_CRTL;
901 data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
902 }
903 mcp251x_error_skb(net, can_id, data1);
904 }
905
906 if (priv->can.state == CAN_STATE_BUS_OFF) {
907 if (priv->can.restart_ms == 0) {
908 priv->force_quit = 1;
909 priv->can.can_stats.bus_off++;
910 can_bus_off(net);
911 mcp251x_hw_sleep(spi);
912 break;
913 }
914 }
915
916 if (intf == 0)
917 break;
918
919 if (intf & CANINTF_TX) {
920 net->stats.tx_packets++;
921 net->stats.tx_bytes += priv->tx_len - 1;
922 can_led_event(net, CAN_LED_EVENT_TX);
923 if (priv->tx_len) {
924 can_get_echo_skb(net, 0);
925 priv->tx_len = 0;
926 }
927 netif_wake_queue(net);
928 }
929
930 }
931 mutex_unlock(&priv->mcp_lock);
932 return IRQ_HANDLED;
933}
934
935static int mcp251x_open(struct net_device *net)
936{
937 struct mcp251x_priv *priv = netdev_priv(net);
938 struct spi_device *spi = priv->spi;
939 unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_FALLING;
940 int ret;
941
942 ret = open_candev(net);
943 if (ret) {
944 dev_err(&spi->dev, "unable to set initial baudrate!\n");
945 return ret;
946 }
947
948 mutex_lock(&priv->mcp_lock);
949 mcp251x_power_enable(priv->transceiver, 1);
950
951 priv->force_quit = 0;
952 priv->tx_skb = NULL;
953 priv->tx_len = 0;
954
955 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
956 flags | IRQF_ONESHOT, DEVICE_NAME, priv);
957 if (ret) {
958 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
959 mcp251x_power_enable(priv->transceiver, 0);
960 close_candev(net);
961 goto open_unlock;
962 }
963
964 priv->wq = alloc_workqueue("mcp251x_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM,
965 0);
966 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
967 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
968
969 ret = mcp251x_hw_reset(spi);
970 if (ret) {
971 mcp251x_open_clean(net);
972 goto open_unlock;
973 }
974 ret = mcp251x_setup(net, priv, spi);
975 if (ret) {
976 mcp251x_open_clean(net);
977 goto open_unlock;
978 }
979 ret = mcp251x_set_normal_mode(spi);
980 if (ret) {
981 mcp251x_open_clean(net);
982 goto open_unlock;
983 }
984
985 can_led_event(net, CAN_LED_EVENT_OPEN);
986
987 netif_wake_queue(net);
988
989open_unlock:
990 mutex_unlock(&priv->mcp_lock);
991 return ret;
992}
993
994static const struct net_device_ops mcp251x_netdev_ops = {
995 .ndo_open = mcp251x_open,
996 .ndo_stop = mcp251x_stop,
997 .ndo_start_xmit = mcp251x_hard_start_xmit,
998 .ndo_change_mtu = can_change_mtu,
999};
1000
1001static const struct of_device_id mcp251x_of_match[] = {
1002 {
1003 .compatible = "microchip,mcp2510",
1004 .data = (void *)CAN_MCP251X_MCP2510,
1005 },
1006 {
1007 .compatible = "microchip,mcp2515",
1008 .data = (void *)CAN_MCP251X_MCP2515,
1009 },
1010 { }
1011};
1012MODULE_DEVICE_TABLE(of, mcp251x_of_match);
1013
1014static const struct spi_device_id mcp251x_id_table[] = {
1015 {
1016 .name = "mcp2510",
1017 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2510,
1018 },
1019 {
1020 .name = "mcp2515",
1021 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2515,
1022 },
1023 { }
1024};
1025MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
1026
1027static int mcp251x_can_probe(struct spi_device *spi)
1028{
1029 const struct of_device_id *of_id = of_match_device(mcp251x_of_match,
1030 &spi->dev);
1031 struct mcp251x_platform_data *pdata = dev_get_platdata(&spi->dev);
1032 struct net_device *net;
1033 struct mcp251x_priv *priv;
1034 struct clk *clk;
1035 int freq, ret;
1036
1037 clk = devm_clk_get(&spi->dev, NULL);
1038 if (IS_ERR(clk)) {
1039 if (pdata)
1040 freq = pdata->oscillator_frequency;
1041 else
1042 return PTR_ERR(clk);
1043 } else {
1044 freq = clk_get_rate(clk);
1045 }
1046
1047 /* Sanity check */
1048 if (freq < 1000000 || freq > 25000000)
1049 return -ERANGE;
1050
1051 /* Allocate can/net device */
1052 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
1053 if (!net)
1054 return -ENOMEM;
1055
1056 if (!IS_ERR(clk)) {
1057 ret = clk_prepare_enable(clk);
1058 if (ret)
1059 goto out_free;
1060 }
1061
1062 net->netdev_ops = &mcp251x_netdev_ops;
1063 net->flags |= IFF_ECHO;
1064
1065 priv = netdev_priv(net);
1066 priv->can.bittiming_const = &mcp251x_bittiming_const;
1067 priv->can.do_set_mode = mcp251x_do_set_mode;
1068 priv->can.clock.freq = freq / 2;
1069 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
1070 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
1071 if (of_id)
1072 priv->model = (enum mcp251x_model)of_id->data;
1073 else
1074 priv->model = spi_get_device_id(spi)->driver_data;
1075 priv->net = net;
1076 priv->clk = clk;
1077
1078 spi_set_drvdata(spi, priv);
1079
1080 /* Configure the SPI bus */
1081 spi->bits_per_word = 8;
1082 if (mcp251x_is_2510(spi))
1083 spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000;
1084 else
1085 spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000;
1086 ret = spi_setup(spi);
1087 if (ret)
1088 goto out_clk;
1089
1090 priv->power = devm_regulator_get_optional(&spi->dev, "vdd");
1091 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
1092 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
1093 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
1094 ret = -EPROBE_DEFER;
1095 goto out_clk;
1096 }
1097
1098 ret = mcp251x_power_enable(priv->power, 1);
1099 if (ret)
1100 goto out_clk;
1101
1102 priv->spi = spi;
1103 mutex_init(&priv->mcp_lock);
1104
1105 /* If requested, allocate DMA buffers */
1106 if (mcp251x_enable_dma) {
1107 spi->dev.coherent_dma_mask = ~0;
1108
1109 /*
1110 * Minimum coherent DMA allocation is PAGE_SIZE, so allocate
1111 * that much and share it between Tx and Rx DMA buffers.
1112 */
1113 priv->spi_tx_buf = dmam_alloc_coherent(&spi->dev,
1114 PAGE_SIZE,
1115 &priv->spi_tx_dma,
1116 GFP_DMA);
1117
1118 if (priv->spi_tx_buf) {
1119 priv->spi_rx_buf = (priv->spi_tx_buf + (PAGE_SIZE / 2));
1120 priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma +
1121 (PAGE_SIZE / 2));
1122 } else {
1123 /* Fall back to non-DMA */
1124 mcp251x_enable_dma = 0;
1125 }
1126 }
1127
1128 /* Allocate non-DMA buffers */
1129 if (!mcp251x_enable_dma) {
1130 priv->spi_tx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1131 GFP_KERNEL);
1132 if (!priv->spi_tx_buf) {
1133 ret = -ENOMEM;
1134 goto error_probe;
1135 }
1136 priv->spi_rx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1137 GFP_KERNEL);
1138 if (!priv->spi_rx_buf) {
1139 ret = -ENOMEM;
1140 goto error_probe;
1141 }
1142 }
1143
1144 SET_NETDEV_DEV(net, &spi->dev);
1145
1146 /* Here is OK to not lock the MCP, no one knows about it yet */
1147 ret = mcp251x_hw_probe(spi);
1148 if (ret) {
1149 if (ret == -ENODEV)
1150 dev_err(&spi->dev, "Cannot initialize MCP%x. Wrong wiring?\n", priv->model);
1151 goto error_probe;
1152 }
1153
1154 mcp251x_hw_sleep(spi);
1155
1156 ret = register_candev(net);
1157 if (ret)
1158 goto error_probe;
1159
1160 devm_can_led_init(net);
1161
1162 netdev_info(net, "MCP%x successfully initialized.\n", priv->model);
1163 return 0;
1164
1165error_probe:
1166 mcp251x_power_enable(priv->power, 0);
1167
1168out_clk:
1169 if (!IS_ERR(clk))
1170 clk_disable_unprepare(clk);
1171
1172out_free:
1173 free_candev(net);
1174
1175 dev_err(&spi->dev, "Probe failed, err=%d\n", -ret);
1176 return ret;
1177}
1178
1179static int mcp251x_can_remove(struct spi_device *spi)
1180{
1181 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1182 struct net_device *net = priv->net;
1183
1184 unregister_candev(net);
1185
1186 mcp251x_power_enable(priv->power, 0);
1187
1188 if (!IS_ERR(priv->clk))
1189 clk_disable_unprepare(priv->clk);
1190
1191 free_candev(net);
1192
1193 return 0;
1194}
1195
1196static int __maybe_unused mcp251x_can_suspend(struct device *dev)
1197{
1198 struct spi_device *spi = to_spi_device(dev);
1199 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1200 struct net_device *net = priv->net;
1201
1202 priv->force_quit = 1;
1203 disable_irq(spi->irq);
1204 /*
1205 * Note: at this point neither IST nor workqueues are running.
1206 * open/stop cannot be called anyway so locking is not needed
1207 */
1208 if (netif_running(net)) {
1209 netif_device_detach(net);
1210
1211 mcp251x_hw_sleep(spi);
1212 mcp251x_power_enable(priv->transceiver, 0);
1213 priv->after_suspend = AFTER_SUSPEND_UP;
1214 } else {
1215 priv->after_suspend = AFTER_SUSPEND_DOWN;
1216 }
1217
1218 if (!IS_ERR_OR_NULL(priv->power)) {
1219 regulator_disable(priv->power);
1220 priv->after_suspend |= AFTER_SUSPEND_POWER;
1221 }
1222
1223 return 0;
1224}
1225
1226static int __maybe_unused mcp251x_can_resume(struct device *dev)
1227{
1228 struct spi_device *spi = to_spi_device(dev);
1229 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1230
1231 if (priv->after_suspend & AFTER_SUSPEND_POWER)
1232 mcp251x_power_enable(priv->power, 1);
1233
1234 if (priv->after_suspend & AFTER_SUSPEND_UP) {
1235 mcp251x_power_enable(priv->transceiver, 1);
1236 queue_work(priv->wq, &priv->restart_work);
1237 } else {
1238 priv->after_suspend = 0;
1239 }
1240
1241 priv->force_quit = 0;
1242 enable_irq(spi->irq);
1243 return 0;
1244}
1245
1246static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend,
1247 mcp251x_can_resume);
1248
1249static struct spi_driver mcp251x_can_driver = {
1250 .driver = {
1251 .name = DEVICE_NAME,
1252 .of_match_table = mcp251x_of_match,
1253 .pm = &mcp251x_can_pm_ops,
1254 },
1255 .id_table = mcp251x_id_table,
1256 .probe = mcp251x_can_probe,
1257 .remove = mcp251x_can_remove,
1258};
1259module_spi_driver(mcp251x_can_driver);
1260
1261MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1262 "Christian Pellegrin <chripell@evolware.org>");
1263MODULE_DESCRIPTION("Microchip 251x CAN driver");
1264MODULE_LICENSE("GPL v2");