Loading...
Note: File does not exist in v3.15.
1// SPDX-License-Identifier: GPL-2.0-only
2/* CAN bus driver for Microchip 251x/25625 CAN Controller with SPI Interface
3 *
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
6 *
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
8 *
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
12 *
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
15 *
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
19 * Copyright 2007
20 */
21
22#include <linux/bitfield.h>
23#include <linux/can/core.h>
24#include <linux/can/dev.h>
25#include <linux/can/led.h>
26#include <linux/clk.h>
27#include <linux/completion.h>
28#include <linux/delay.h>
29#include <linux/device.h>
30#include <linux/freezer.h>
31#include <linux/gpio.h>
32#include <linux/gpio/driver.h>
33#include <linux/interrupt.h>
34#include <linux/io.h>
35#include <linux/iopoll.h>
36#include <linux/kernel.h>
37#include <linux/module.h>
38#include <linux/netdevice.h>
39#include <linux/platform_device.h>
40#include <linux/property.h>
41#include <linux/regulator/consumer.h>
42#include <linux/slab.h>
43#include <linux/spi/spi.h>
44#include <linux/uaccess.h>
45
46/* SPI interface instruction set */
47#define INSTRUCTION_WRITE 0x02
48#define INSTRUCTION_READ 0x03
49#define INSTRUCTION_BIT_MODIFY 0x05
50#define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
51#define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
52#define INSTRUCTION_RESET 0xC0
53#define RTS_TXB0 0x01
54#define RTS_TXB1 0x02
55#define RTS_TXB2 0x04
56#define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07))
57
58/* MPC251x registers */
59#define BFPCTRL 0x0c
60# define BFPCTRL_B0BFM BIT(0)
61# define BFPCTRL_B1BFM BIT(1)
62# define BFPCTRL_BFM(n) (BFPCTRL_B0BFM << (n))
63# define BFPCTRL_BFM_MASK GENMASK(1, 0)
64# define BFPCTRL_B0BFE BIT(2)
65# define BFPCTRL_B1BFE BIT(3)
66# define BFPCTRL_BFE(n) (BFPCTRL_B0BFE << (n))
67# define BFPCTRL_BFE_MASK GENMASK(3, 2)
68# define BFPCTRL_B0BFS BIT(4)
69# define BFPCTRL_B1BFS BIT(5)
70# define BFPCTRL_BFS(n) (BFPCTRL_B0BFS << (n))
71# define BFPCTRL_BFS_MASK GENMASK(5, 4)
72#define TXRTSCTRL 0x0d
73# define TXRTSCTRL_B0RTSM BIT(0)
74# define TXRTSCTRL_B1RTSM BIT(1)
75# define TXRTSCTRL_B2RTSM BIT(2)
76# define TXRTSCTRL_RTSM(n) (TXRTSCTRL_B0RTSM << (n))
77# define TXRTSCTRL_RTSM_MASK GENMASK(2, 0)
78# define TXRTSCTRL_B0RTS BIT(3)
79# define TXRTSCTRL_B1RTS BIT(4)
80# define TXRTSCTRL_B2RTS BIT(5)
81# define TXRTSCTRL_RTS(n) (TXRTSCTRL_B0RTS << (n))
82# define TXRTSCTRL_RTS_MASK GENMASK(5, 3)
83#define CANSTAT 0x0e
84#define CANCTRL 0x0f
85# define CANCTRL_REQOP_MASK 0xe0
86# define CANCTRL_REQOP_CONF 0x80
87# define CANCTRL_REQOP_LISTEN_ONLY 0x60
88# define CANCTRL_REQOP_LOOPBACK 0x40
89# define CANCTRL_REQOP_SLEEP 0x20
90# define CANCTRL_REQOP_NORMAL 0x00
91# define CANCTRL_OSM 0x08
92# define CANCTRL_ABAT 0x10
93#define TEC 0x1c
94#define REC 0x1d
95#define CNF1 0x2a
96# define CNF1_SJW_SHIFT 6
97#define CNF2 0x29
98# define CNF2_BTLMODE 0x80
99# define CNF2_SAM 0x40
100# define CNF2_PS1_SHIFT 3
101#define CNF3 0x28
102# define CNF3_SOF 0x08
103# define CNF3_WAKFIL 0x04
104# define CNF3_PHSEG2_MASK 0x07
105#define CANINTE 0x2b
106# define CANINTE_MERRE 0x80
107# define CANINTE_WAKIE 0x40
108# define CANINTE_ERRIE 0x20
109# define CANINTE_TX2IE 0x10
110# define CANINTE_TX1IE 0x08
111# define CANINTE_TX0IE 0x04
112# define CANINTE_RX1IE 0x02
113# define CANINTE_RX0IE 0x01
114#define CANINTF 0x2c
115# define CANINTF_MERRF 0x80
116# define CANINTF_WAKIF 0x40
117# define CANINTF_ERRIF 0x20
118# define CANINTF_TX2IF 0x10
119# define CANINTF_TX1IF 0x08
120# define CANINTF_TX0IF 0x04
121# define CANINTF_RX1IF 0x02
122# define CANINTF_RX0IF 0x01
123# define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF)
124# define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
125# define CANINTF_ERR (CANINTF_ERRIF)
126#define EFLG 0x2d
127# define EFLG_EWARN 0x01
128# define EFLG_RXWAR 0x02
129# define EFLG_TXWAR 0x04
130# define EFLG_RXEP 0x08
131# define EFLG_TXEP 0x10
132# define EFLG_TXBO 0x20
133# define EFLG_RX0OVR 0x40
134# define EFLG_RX1OVR 0x80
135#define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
136# define TXBCTRL_ABTF 0x40
137# define TXBCTRL_MLOA 0x20
138# define TXBCTRL_TXERR 0x10
139# define TXBCTRL_TXREQ 0x08
140#define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
141# define SIDH_SHIFT 3
142#define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
143# define SIDL_SID_MASK 7
144# define SIDL_SID_SHIFT 5
145# define SIDL_EXIDE_SHIFT 3
146# define SIDL_EID_SHIFT 16
147# define SIDL_EID_MASK 3
148#define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
149#define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
150#define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
151# define DLC_RTR_SHIFT 6
152#define TXBCTRL_OFF 0
153#define TXBSIDH_OFF 1
154#define TXBSIDL_OFF 2
155#define TXBEID8_OFF 3
156#define TXBEID0_OFF 4
157#define TXBDLC_OFF 5
158#define TXBDAT_OFF 6
159#define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
160# define RXBCTRL_BUKT 0x04
161# define RXBCTRL_RXM0 0x20
162# define RXBCTRL_RXM1 0x40
163#define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
164# define RXBSIDH_SHIFT 3
165#define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
166# define RXBSIDL_IDE 0x08
167# define RXBSIDL_SRR 0x10
168# define RXBSIDL_EID 3
169# define RXBSIDL_SHIFT 5
170#define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
171#define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
172#define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
173# define RXBDLC_LEN_MASK 0x0f
174# define RXBDLC_RTR 0x40
175#define RXBCTRL_OFF 0
176#define RXBSIDH_OFF 1
177#define RXBSIDL_OFF 2
178#define RXBEID8_OFF 3
179#define RXBEID0_OFF 4
180#define RXBDLC_OFF 5
181#define RXBDAT_OFF 6
182#define RXFSID(n) ((n < 3) ? 0 : 4)
183#define RXFSIDH(n) ((n) * 4 + RXFSID(n))
184#define RXFSIDL(n) ((n) * 4 + 1 + RXFSID(n))
185#define RXFEID8(n) ((n) * 4 + 2 + RXFSID(n))
186#define RXFEID0(n) ((n) * 4 + 3 + RXFSID(n))
187#define RXMSIDH(n) ((n) * 4 + 0x20)
188#define RXMSIDL(n) ((n) * 4 + 0x21)
189#define RXMEID8(n) ((n) * 4 + 0x22)
190#define RXMEID0(n) ((n) * 4 + 0x23)
191
192#define GET_BYTE(val, byte) \
193 (((val) >> ((byte) * 8)) & 0xff)
194#define SET_BYTE(val, byte) \
195 (((val) & 0xff) << ((byte) * 8))
196
197/* Buffer size required for the largest SPI transfer (i.e., reading a
198 * frame)
199 */
200#define CAN_FRAME_MAX_DATA_LEN 8
201#define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
202#define CAN_FRAME_MAX_BITS 128
203
204#define TX_ECHO_SKB_MAX 1
205
206#define MCP251X_OST_DELAY_MS (5)
207
208#define DEVICE_NAME "mcp251x"
209
210static const struct can_bittiming_const mcp251x_bittiming_const = {
211 .name = DEVICE_NAME,
212 .tseg1_min = 3,
213 .tseg1_max = 16,
214 .tseg2_min = 2,
215 .tseg2_max = 8,
216 .sjw_max = 4,
217 .brp_min = 1,
218 .brp_max = 64,
219 .brp_inc = 1,
220};
221
222enum mcp251x_model {
223 CAN_MCP251X_MCP2510 = 0x2510,
224 CAN_MCP251X_MCP2515 = 0x2515,
225 CAN_MCP251X_MCP25625 = 0x25625,
226};
227
228struct mcp251x_priv {
229 struct can_priv can;
230 struct net_device *net;
231 struct spi_device *spi;
232 enum mcp251x_model model;
233
234 struct mutex mcp_lock; /* SPI device lock */
235
236 u8 *spi_tx_buf;
237 u8 *spi_rx_buf;
238
239 struct sk_buff *tx_skb;
240 int tx_len;
241
242 struct workqueue_struct *wq;
243 struct work_struct tx_work;
244 struct work_struct restart_work;
245
246 int force_quit;
247 int after_suspend;
248#define AFTER_SUSPEND_UP 1
249#define AFTER_SUSPEND_DOWN 2
250#define AFTER_SUSPEND_POWER 4
251#define AFTER_SUSPEND_RESTART 8
252 int restart_tx;
253 struct regulator *power;
254 struct regulator *transceiver;
255 struct clk *clk;
256#ifdef CONFIG_GPIOLIB
257 struct gpio_chip gpio;
258 u8 reg_bfpctrl;
259#endif
260};
261
262#define MCP251X_IS(_model) \
263static inline int mcp251x_is_##_model(struct spi_device *spi) \
264{ \
265 struct mcp251x_priv *priv = spi_get_drvdata(spi); \
266 return priv->model == CAN_MCP251X_MCP##_model; \
267}
268
269MCP251X_IS(2510);
270
271static void mcp251x_clean(struct net_device *net)
272{
273 struct mcp251x_priv *priv = netdev_priv(net);
274
275 if (priv->tx_skb || priv->tx_len)
276 net->stats.tx_errors++;
277 dev_kfree_skb(priv->tx_skb);
278 if (priv->tx_len)
279 can_free_echo_skb(priv->net, 0, NULL);
280 priv->tx_skb = NULL;
281 priv->tx_len = 0;
282}
283
284/* Note about handling of error return of mcp251x_spi_trans: accessing
285 * registers via SPI is not really different conceptually than using
286 * normal I/O assembler instructions, although it's much more
287 * complicated from a practical POV. So it's not advisable to always
288 * check the return value of this function. Imagine that every
289 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
290 * error();", it would be a great mess (well there are some situation
291 * when exception handling C++ like could be useful after all). So we
292 * just check that transfers are OK at the beginning of our
293 * conversation with the chip and to avoid doing really nasty things
294 * (like injecting bogus packets in the network stack).
295 */
296static int mcp251x_spi_trans(struct spi_device *spi, int len)
297{
298 struct mcp251x_priv *priv = spi_get_drvdata(spi);
299 struct spi_transfer t = {
300 .tx_buf = priv->spi_tx_buf,
301 .rx_buf = priv->spi_rx_buf,
302 .len = len,
303 .cs_change = 0,
304 };
305 struct spi_message m;
306 int ret;
307
308 spi_message_init(&m);
309 spi_message_add_tail(&t, &m);
310
311 ret = spi_sync(spi, &m);
312 if (ret)
313 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
314 return ret;
315}
316
317static int mcp251x_spi_write(struct spi_device *spi, int len)
318{
319 struct mcp251x_priv *priv = spi_get_drvdata(spi);
320 int ret;
321
322 ret = spi_write(spi, priv->spi_tx_buf, len);
323 if (ret)
324 dev_err(&spi->dev, "spi write failed: ret = %d\n", ret);
325
326 return ret;
327}
328
329static u8 mcp251x_read_reg(struct spi_device *spi, u8 reg)
330{
331 struct mcp251x_priv *priv = spi_get_drvdata(spi);
332 u8 val = 0;
333
334 priv->spi_tx_buf[0] = INSTRUCTION_READ;
335 priv->spi_tx_buf[1] = reg;
336
337 if (spi->controller->flags & SPI_CONTROLLER_HALF_DUPLEX) {
338 spi_write_then_read(spi, priv->spi_tx_buf, 2, &val, 1);
339 } else {
340 mcp251x_spi_trans(spi, 3);
341 val = priv->spi_rx_buf[2];
342 }
343
344 return val;
345}
346
347static void mcp251x_read_2regs(struct spi_device *spi, u8 reg, u8 *v1, u8 *v2)
348{
349 struct mcp251x_priv *priv = spi_get_drvdata(spi);
350
351 priv->spi_tx_buf[0] = INSTRUCTION_READ;
352 priv->spi_tx_buf[1] = reg;
353
354 if (spi->controller->flags & SPI_CONTROLLER_HALF_DUPLEX) {
355 u8 val[2] = { 0 };
356
357 spi_write_then_read(spi, priv->spi_tx_buf, 2, val, 2);
358 *v1 = val[0];
359 *v2 = val[1];
360 } else {
361 mcp251x_spi_trans(spi, 4);
362
363 *v1 = priv->spi_rx_buf[2];
364 *v2 = priv->spi_rx_buf[3];
365 }
366}
367
368static void mcp251x_write_reg(struct spi_device *spi, u8 reg, u8 val)
369{
370 struct mcp251x_priv *priv = spi_get_drvdata(spi);
371
372 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
373 priv->spi_tx_buf[1] = reg;
374 priv->spi_tx_buf[2] = val;
375
376 mcp251x_spi_write(spi, 3);
377}
378
379static void mcp251x_write_2regs(struct spi_device *spi, u8 reg, u8 v1, u8 v2)
380{
381 struct mcp251x_priv *priv = spi_get_drvdata(spi);
382
383 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
384 priv->spi_tx_buf[1] = reg;
385 priv->spi_tx_buf[2] = v1;
386 priv->spi_tx_buf[3] = v2;
387
388 mcp251x_spi_write(spi, 4);
389}
390
391static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
392 u8 mask, u8 val)
393{
394 struct mcp251x_priv *priv = spi_get_drvdata(spi);
395
396 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
397 priv->spi_tx_buf[1] = reg;
398 priv->spi_tx_buf[2] = mask;
399 priv->spi_tx_buf[3] = val;
400
401 mcp251x_spi_write(spi, 4);
402}
403
404static u8 mcp251x_read_stat(struct spi_device *spi)
405{
406 return mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK;
407}
408
409#define mcp251x_read_stat_poll_timeout(addr, val, cond, delay_us, timeout_us) \
410 readx_poll_timeout(mcp251x_read_stat, addr, val, cond, \
411 delay_us, timeout_us)
412
413#ifdef CONFIG_GPIOLIB
414enum {
415 MCP251X_GPIO_TX0RTS = 0, /* inputs */
416 MCP251X_GPIO_TX1RTS,
417 MCP251X_GPIO_TX2RTS,
418 MCP251X_GPIO_RX0BF, /* outputs */
419 MCP251X_GPIO_RX1BF,
420};
421
422#define MCP251X_GPIO_INPUT_MASK \
423 GENMASK(MCP251X_GPIO_TX2RTS, MCP251X_GPIO_TX0RTS)
424#define MCP251X_GPIO_OUTPUT_MASK \
425 GENMASK(MCP251X_GPIO_RX1BF, MCP251X_GPIO_RX0BF)
426
427static const char * const mcp251x_gpio_names[] = {
428 [MCP251X_GPIO_TX0RTS] = "TX0RTS", /* inputs */
429 [MCP251X_GPIO_TX1RTS] = "TX1RTS",
430 [MCP251X_GPIO_TX2RTS] = "TX2RTS",
431 [MCP251X_GPIO_RX0BF] = "RX0BF", /* outputs */
432 [MCP251X_GPIO_RX1BF] = "RX1BF",
433};
434
435static inline bool mcp251x_gpio_is_input(unsigned int offset)
436{
437 return offset <= MCP251X_GPIO_TX2RTS;
438}
439
440static int mcp251x_gpio_request(struct gpio_chip *chip,
441 unsigned int offset)
442{
443 struct mcp251x_priv *priv = gpiochip_get_data(chip);
444 u8 val;
445
446 /* nothing to be done for inputs */
447 if (mcp251x_gpio_is_input(offset))
448 return 0;
449
450 val = BFPCTRL_BFE(offset - MCP251X_GPIO_RX0BF);
451
452 mutex_lock(&priv->mcp_lock);
453 mcp251x_write_bits(priv->spi, BFPCTRL, val, val);
454 mutex_unlock(&priv->mcp_lock);
455
456 priv->reg_bfpctrl |= val;
457
458 return 0;
459}
460
461static void mcp251x_gpio_free(struct gpio_chip *chip,
462 unsigned int offset)
463{
464 struct mcp251x_priv *priv = gpiochip_get_data(chip);
465 u8 val;
466
467 /* nothing to be done for inputs */
468 if (mcp251x_gpio_is_input(offset))
469 return;
470
471 val = BFPCTRL_BFE(offset - MCP251X_GPIO_RX0BF);
472
473 mutex_lock(&priv->mcp_lock);
474 mcp251x_write_bits(priv->spi, BFPCTRL, val, 0);
475 mutex_unlock(&priv->mcp_lock);
476
477 priv->reg_bfpctrl &= ~val;
478}
479
480static int mcp251x_gpio_get_direction(struct gpio_chip *chip,
481 unsigned int offset)
482{
483 if (mcp251x_gpio_is_input(offset))
484 return GPIOF_DIR_IN;
485
486 return GPIOF_DIR_OUT;
487}
488
489static int mcp251x_gpio_get(struct gpio_chip *chip, unsigned int offset)
490{
491 struct mcp251x_priv *priv = gpiochip_get_data(chip);
492 u8 reg, mask, val;
493
494 if (mcp251x_gpio_is_input(offset)) {
495 reg = TXRTSCTRL;
496 mask = TXRTSCTRL_RTS(offset);
497 } else {
498 reg = BFPCTRL;
499 mask = BFPCTRL_BFS(offset - MCP251X_GPIO_RX0BF);
500 }
501
502 mutex_lock(&priv->mcp_lock);
503 val = mcp251x_read_reg(priv->spi, reg);
504 mutex_unlock(&priv->mcp_lock);
505
506 return !!(val & mask);
507}
508
509static int mcp251x_gpio_get_multiple(struct gpio_chip *chip,
510 unsigned long *maskp, unsigned long *bitsp)
511{
512 struct mcp251x_priv *priv = gpiochip_get_data(chip);
513 unsigned long bits = 0;
514 u8 val;
515
516 mutex_lock(&priv->mcp_lock);
517 if (maskp[0] & MCP251X_GPIO_INPUT_MASK) {
518 val = mcp251x_read_reg(priv->spi, TXRTSCTRL);
519 val = FIELD_GET(TXRTSCTRL_RTS_MASK, val);
520 bits |= FIELD_PREP(MCP251X_GPIO_INPUT_MASK, val);
521 }
522 if (maskp[0] & MCP251X_GPIO_OUTPUT_MASK) {
523 val = mcp251x_read_reg(priv->spi, BFPCTRL);
524 val = FIELD_GET(BFPCTRL_BFS_MASK, val);
525 bits |= FIELD_PREP(MCP251X_GPIO_OUTPUT_MASK, val);
526 }
527 mutex_unlock(&priv->mcp_lock);
528
529 bitsp[0] = bits;
530 return 0;
531}
532
533static void mcp251x_gpio_set(struct gpio_chip *chip, unsigned int offset,
534 int value)
535{
536 struct mcp251x_priv *priv = gpiochip_get_data(chip);
537 u8 mask, val;
538
539 mask = BFPCTRL_BFS(offset - MCP251X_GPIO_RX0BF);
540 val = value ? mask : 0;
541
542 mutex_lock(&priv->mcp_lock);
543 mcp251x_write_bits(priv->spi, BFPCTRL, mask, val);
544 mutex_unlock(&priv->mcp_lock);
545
546 priv->reg_bfpctrl &= ~mask;
547 priv->reg_bfpctrl |= val;
548}
549
550static void
551mcp251x_gpio_set_multiple(struct gpio_chip *chip,
552 unsigned long *maskp, unsigned long *bitsp)
553{
554 struct mcp251x_priv *priv = gpiochip_get_data(chip);
555 u8 mask, val;
556
557 mask = FIELD_GET(MCP251X_GPIO_OUTPUT_MASK, maskp[0]);
558 mask = FIELD_PREP(BFPCTRL_BFS_MASK, mask);
559
560 val = FIELD_GET(MCP251X_GPIO_OUTPUT_MASK, bitsp[0]);
561 val = FIELD_PREP(BFPCTRL_BFS_MASK, val);
562
563 if (!mask)
564 return;
565
566 mutex_lock(&priv->mcp_lock);
567 mcp251x_write_bits(priv->spi, BFPCTRL, mask, val);
568 mutex_unlock(&priv->mcp_lock);
569
570 priv->reg_bfpctrl &= ~mask;
571 priv->reg_bfpctrl |= val;
572}
573
574static void mcp251x_gpio_restore(struct spi_device *spi)
575{
576 struct mcp251x_priv *priv = spi_get_drvdata(spi);
577
578 mcp251x_write_reg(spi, BFPCTRL, priv->reg_bfpctrl);
579}
580
581static int mcp251x_gpio_setup(struct mcp251x_priv *priv)
582{
583 struct gpio_chip *gpio = &priv->gpio;
584
585 if (!device_property_present(&priv->spi->dev, "gpio-controller"))
586 return 0;
587
588 /* gpiochip handles TX[0..2]RTS and RX[0..1]BF */
589 gpio->label = priv->spi->modalias;
590 gpio->parent = &priv->spi->dev;
591 gpio->owner = THIS_MODULE;
592 gpio->request = mcp251x_gpio_request;
593 gpio->free = mcp251x_gpio_free;
594 gpio->get_direction = mcp251x_gpio_get_direction;
595 gpio->get = mcp251x_gpio_get;
596 gpio->get_multiple = mcp251x_gpio_get_multiple;
597 gpio->set = mcp251x_gpio_set;
598 gpio->set_multiple = mcp251x_gpio_set_multiple;
599 gpio->base = -1;
600 gpio->ngpio = ARRAY_SIZE(mcp251x_gpio_names);
601 gpio->names = mcp251x_gpio_names;
602 gpio->can_sleep = true;
603#ifdef CONFIG_OF_GPIO
604 gpio->of_node = priv->spi->dev.of_node;
605#endif
606
607 return devm_gpiochip_add_data(&priv->spi->dev, gpio, priv);
608}
609#else
610static inline void mcp251x_gpio_restore(struct spi_device *spi)
611{
612}
613
614static inline int mcp251x_gpio_setup(struct mcp251x_priv *priv)
615{
616 return 0;
617}
618#endif
619
620static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
621 int len, int tx_buf_idx)
622{
623 struct mcp251x_priv *priv = spi_get_drvdata(spi);
624
625 if (mcp251x_is_2510(spi)) {
626 int i;
627
628 for (i = 1; i < TXBDAT_OFF + len; i++)
629 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
630 buf[i]);
631 } else {
632 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
633 mcp251x_spi_write(spi, TXBDAT_OFF + len);
634 }
635}
636
637static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
638 int tx_buf_idx)
639{
640 struct mcp251x_priv *priv = spi_get_drvdata(spi);
641 u32 sid, eid, exide, rtr;
642 u8 buf[SPI_TRANSFER_BUF_LEN];
643
644 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
645 if (exide)
646 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
647 else
648 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
649 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
650 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
651
652 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
653 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
654 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
655 (exide << SIDL_EXIDE_SHIFT) |
656 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
657 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
658 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
659 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->len;
660 memcpy(buf + TXBDAT_OFF, frame->data, frame->len);
661 mcp251x_hw_tx_frame(spi, buf, frame->len, tx_buf_idx);
662
663 /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */
664 priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx);
665 mcp251x_spi_write(priv->spi, 1);
666}
667
668static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
669 int buf_idx)
670{
671 struct mcp251x_priv *priv = spi_get_drvdata(spi);
672
673 if (mcp251x_is_2510(spi)) {
674 int i, len;
675
676 for (i = 1; i < RXBDAT_OFF; i++)
677 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
678
679 len = can_cc_dlc2len(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
680 for (; i < (RXBDAT_OFF + len); i++)
681 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
682 } else {
683 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
684 if (spi->controller->flags & SPI_CONTROLLER_HALF_DUPLEX) {
685 spi_write_then_read(spi, priv->spi_tx_buf, 1,
686 priv->spi_rx_buf,
687 SPI_TRANSFER_BUF_LEN);
688 memcpy(buf + 1, priv->spi_rx_buf,
689 SPI_TRANSFER_BUF_LEN - 1);
690 } else {
691 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
692 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
693 }
694 }
695}
696
697static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
698{
699 struct mcp251x_priv *priv = spi_get_drvdata(spi);
700 struct sk_buff *skb;
701 struct can_frame *frame;
702 u8 buf[SPI_TRANSFER_BUF_LEN];
703
704 skb = alloc_can_skb(priv->net, &frame);
705 if (!skb) {
706 dev_err(&spi->dev, "cannot allocate RX skb\n");
707 priv->net->stats.rx_dropped++;
708 return;
709 }
710
711 mcp251x_hw_rx_frame(spi, buf, buf_idx);
712 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
713 /* Extended ID format */
714 frame->can_id = CAN_EFF_FLAG;
715 frame->can_id |=
716 /* Extended ID part */
717 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
718 SET_BYTE(buf[RXBEID8_OFF], 1) |
719 SET_BYTE(buf[RXBEID0_OFF], 0) |
720 /* Standard ID part */
721 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
722 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
723 /* Remote transmission request */
724 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
725 frame->can_id |= CAN_RTR_FLAG;
726 } else {
727 /* Standard ID format */
728 frame->can_id =
729 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
730 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
731 if (buf[RXBSIDL_OFF] & RXBSIDL_SRR)
732 frame->can_id |= CAN_RTR_FLAG;
733 }
734 /* Data length */
735 frame->len = can_cc_dlc2len(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
736 memcpy(frame->data, buf + RXBDAT_OFF, frame->len);
737
738 priv->net->stats.rx_packets++;
739 priv->net->stats.rx_bytes += frame->len;
740
741 can_led_event(priv->net, CAN_LED_EVENT_RX);
742
743 netif_rx_ni(skb);
744}
745
746static void mcp251x_hw_sleep(struct spi_device *spi)
747{
748 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
749}
750
751/* May only be called when device is sleeping! */
752static int mcp251x_hw_wake(struct spi_device *spi)
753{
754 u8 value;
755 int ret;
756
757 /* Force wakeup interrupt to wake device, but don't execute IST */
758 disable_irq(spi->irq);
759 mcp251x_write_2regs(spi, CANINTE, CANINTE_WAKIE, CANINTF_WAKIF);
760
761 /* Wait for oscillator startup timer after wake up */
762 mdelay(MCP251X_OST_DELAY_MS);
763
764 /* Put device into config mode */
765 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_CONF);
766
767 /* Wait for the device to enter config mode */
768 ret = mcp251x_read_stat_poll_timeout(spi, value, value == CANCTRL_REQOP_CONF,
769 MCP251X_OST_DELAY_MS * 1000,
770 USEC_PER_SEC);
771 if (ret) {
772 dev_err(&spi->dev, "MCP251x didn't enter in config mode\n");
773 return ret;
774 }
775
776 /* Disable and clear pending interrupts */
777 mcp251x_write_2regs(spi, CANINTE, 0x00, 0x00);
778 enable_irq(spi->irq);
779
780 return 0;
781}
782
783static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
784 struct net_device *net)
785{
786 struct mcp251x_priv *priv = netdev_priv(net);
787 struct spi_device *spi = priv->spi;
788
789 if (priv->tx_skb || priv->tx_len) {
790 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
791 return NETDEV_TX_BUSY;
792 }
793
794 if (can_dropped_invalid_skb(net, skb))
795 return NETDEV_TX_OK;
796
797 netif_stop_queue(net);
798 priv->tx_skb = skb;
799 queue_work(priv->wq, &priv->tx_work);
800
801 return NETDEV_TX_OK;
802}
803
804static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
805{
806 struct mcp251x_priv *priv = netdev_priv(net);
807
808 switch (mode) {
809 case CAN_MODE_START:
810 mcp251x_clean(net);
811 /* We have to delay work since SPI I/O may sleep */
812 priv->can.state = CAN_STATE_ERROR_ACTIVE;
813 priv->restart_tx = 1;
814 if (priv->can.restart_ms == 0)
815 priv->after_suspend = AFTER_SUSPEND_RESTART;
816 queue_work(priv->wq, &priv->restart_work);
817 break;
818 default:
819 return -EOPNOTSUPP;
820 }
821
822 return 0;
823}
824
825static int mcp251x_set_normal_mode(struct spi_device *spi)
826{
827 struct mcp251x_priv *priv = spi_get_drvdata(spi);
828 u8 value;
829 int ret;
830
831 /* Enable interrupts */
832 mcp251x_write_reg(spi, CANINTE,
833 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
834 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
835
836 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
837 /* Put device into loopback mode */
838 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
839 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
840 /* Put device into listen-only mode */
841 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
842 } else {
843 /* Put device into normal mode */
844 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
845
846 /* Wait for the device to enter normal mode */
847 ret = mcp251x_read_stat_poll_timeout(spi, value, value == 0,
848 MCP251X_OST_DELAY_MS * 1000,
849 USEC_PER_SEC);
850 if (ret) {
851 dev_err(&spi->dev, "MCP251x didn't enter in normal mode\n");
852 return ret;
853 }
854 }
855 priv->can.state = CAN_STATE_ERROR_ACTIVE;
856 return 0;
857}
858
859static int mcp251x_do_set_bittiming(struct net_device *net)
860{
861 struct mcp251x_priv *priv = netdev_priv(net);
862 struct can_bittiming *bt = &priv->can.bittiming;
863 struct spi_device *spi = priv->spi;
864
865 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
866 (bt->brp - 1));
867 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
868 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
869 CNF2_SAM : 0) |
870 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
871 (bt->prop_seg - 1));
872 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
873 (bt->phase_seg2 - 1));
874 dev_dbg(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
875 mcp251x_read_reg(spi, CNF1),
876 mcp251x_read_reg(spi, CNF2),
877 mcp251x_read_reg(spi, CNF3));
878
879 return 0;
880}
881
882static int mcp251x_setup(struct net_device *net, struct spi_device *spi)
883{
884 mcp251x_do_set_bittiming(net);
885
886 mcp251x_write_reg(spi, RXBCTRL(0),
887 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
888 mcp251x_write_reg(spi, RXBCTRL(1),
889 RXBCTRL_RXM0 | RXBCTRL_RXM1);
890 return 0;
891}
892
893static int mcp251x_hw_reset(struct spi_device *spi)
894{
895 struct mcp251x_priv *priv = spi_get_drvdata(spi);
896 u8 value;
897 int ret;
898
899 /* Wait for oscillator startup timer after power up */
900 mdelay(MCP251X_OST_DELAY_MS);
901
902 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
903 ret = mcp251x_spi_write(spi, 1);
904 if (ret)
905 return ret;
906
907 /* Wait for oscillator startup timer after reset */
908 mdelay(MCP251X_OST_DELAY_MS);
909
910 /* Wait for reset to finish */
911 ret = mcp251x_read_stat_poll_timeout(spi, value, value == CANCTRL_REQOP_CONF,
912 MCP251X_OST_DELAY_MS * 1000,
913 USEC_PER_SEC);
914 if (ret)
915 dev_err(&spi->dev, "MCP251x didn't enter in conf mode after reset\n");
916 return ret;
917}
918
919static int mcp251x_hw_probe(struct spi_device *spi)
920{
921 u8 ctrl;
922 int ret;
923
924 ret = mcp251x_hw_reset(spi);
925 if (ret)
926 return ret;
927
928 ctrl = mcp251x_read_reg(spi, CANCTRL);
929
930 dev_dbg(&spi->dev, "CANCTRL 0x%02x\n", ctrl);
931
932 /* Check for power up default value */
933 if ((ctrl & 0x17) != 0x07)
934 return -ENODEV;
935
936 return 0;
937}
938
939static int mcp251x_power_enable(struct regulator *reg, int enable)
940{
941 if (IS_ERR_OR_NULL(reg))
942 return 0;
943
944 if (enable)
945 return regulator_enable(reg);
946 else
947 return regulator_disable(reg);
948}
949
950static int mcp251x_stop(struct net_device *net)
951{
952 struct mcp251x_priv *priv = netdev_priv(net);
953 struct spi_device *spi = priv->spi;
954
955 close_candev(net);
956
957 priv->force_quit = 1;
958 free_irq(spi->irq, priv);
959
960 mutex_lock(&priv->mcp_lock);
961
962 /* Disable and clear pending interrupts */
963 mcp251x_write_2regs(spi, CANINTE, 0x00, 0x00);
964
965 mcp251x_write_reg(spi, TXBCTRL(0), 0);
966 mcp251x_clean(net);
967
968 mcp251x_hw_sleep(spi);
969
970 mcp251x_power_enable(priv->transceiver, 0);
971
972 priv->can.state = CAN_STATE_STOPPED;
973
974 mutex_unlock(&priv->mcp_lock);
975
976 can_led_event(net, CAN_LED_EVENT_STOP);
977
978 return 0;
979}
980
981static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
982{
983 struct sk_buff *skb;
984 struct can_frame *frame;
985
986 skb = alloc_can_err_skb(net, &frame);
987 if (skb) {
988 frame->can_id |= can_id;
989 frame->data[1] = data1;
990 netif_rx_ni(skb);
991 } else {
992 netdev_err(net, "cannot allocate error skb\n");
993 }
994}
995
996static void mcp251x_tx_work_handler(struct work_struct *ws)
997{
998 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
999 tx_work);
1000 struct spi_device *spi = priv->spi;
1001 struct net_device *net = priv->net;
1002 struct can_frame *frame;
1003
1004 mutex_lock(&priv->mcp_lock);
1005 if (priv->tx_skb) {
1006 if (priv->can.state == CAN_STATE_BUS_OFF) {
1007 mcp251x_clean(net);
1008 } else {
1009 frame = (struct can_frame *)priv->tx_skb->data;
1010
1011 if (frame->len > CAN_FRAME_MAX_DATA_LEN)
1012 frame->len = CAN_FRAME_MAX_DATA_LEN;
1013 mcp251x_hw_tx(spi, frame, 0);
1014 priv->tx_len = 1 + frame->len;
1015 can_put_echo_skb(priv->tx_skb, net, 0, 0);
1016 priv->tx_skb = NULL;
1017 }
1018 }
1019 mutex_unlock(&priv->mcp_lock);
1020}
1021
1022static void mcp251x_restart_work_handler(struct work_struct *ws)
1023{
1024 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
1025 restart_work);
1026 struct spi_device *spi = priv->spi;
1027 struct net_device *net = priv->net;
1028
1029 mutex_lock(&priv->mcp_lock);
1030 if (priv->after_suspend) {
1031 if (priv->after_suspend & AFTER_SUSPEND_POWER) {
1032 mcp251x_hw_reset(spi);
1033 mcp251x_setup(net, spi);
1034 mcp251x_gpio_restore(spi);
1035 } else {
1036 mcp251x_hw_wake(spi);
1037 }
1038 priv->force_quit = 0;
1039 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
1040 mcp251x_set_normal_mode(spi);
1041 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
1042 netif_device_attach(net);
1043 mcp251x_clean(net);
1044 mcp251x_set_normal_mode(spi);
1045 netif_wake_queue(net);
1046 } else {
1047 mcp251x_hw_sleep(spi);
1048 }
1049 priv->after_suspend = 0;
1050 }
1051
1052 if (priv->restart_tx) {
1053 priv->restart_tx = 0;
1054 mcp251x_write_reg(spi, TXBCTRL(0), 0);
1055 mcp251x_clean(net);
1056 netif_wake_queue(net);
1057 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
1058 }
1059 mutex_unlock(&priv->mcp_lock);
1060}
1061
1062static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
1063{
1064 struct mcp251x_priv *priv = dev_id;
1065 struct spi_device *spi = priv->spi;
1066 struct net_device *net = priv->net;
1067
1068 mutex_lock(&priv->mcp_lock);
1069 while (!priv->force_quit) {
1070 enum can_state new_state;
1071 u8 intf, eflag;
1072 u8 clear_intf = 0;
1073 int can_id = 0, data1 = 0;
1074
1075 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
1076
1077 /* mask out flags we don't care about */
1078 intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR;
1079
1080 /* receive buffer 0 */
1081 if (intf & CANINTF_RX0IF) {
1082 mcp251x_hw_rx(spi, 0);
1083 /* Free one buffer ASAP
1084 * (The MCP2515/25625 does this automatically.)
1085 */
1086 if (mcp251x_is_2510(spi))
1087 mcp251x_write_bits(spi, CANINTF,
1088 CANINTF_RX0IF, 0x00);
1089 }
1090
1091 /* receive buffer 1 */
1092 if (intf & CANINTF_RX1IF) {
1093 mcp251x_hw_rx(spi, 1);
1094 /* The MCP2515/25625 does this automatically. */
1095 if (mcp251x_is_2510(spi))
1096 clear_intf |= CANINTF_RX1IF;
1097 }
1098
1099 /* any error or tx interrupt we need to clear? */
1100 if (intf & (CANINTF_ERR | CANINTF_TX))
1101 clear_intf |= intf & (CANINTF_ERR | CANINTF_TX);
1102 if (clear_intf)
1103 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
1104
1105 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR))
1106 mcp251x_write_bits(spi, EFLG, eflag, 0x00);
1107
1108 /* Update can state */
1109 if (eflag & EFLG_TXBO) {
1110 new_state = CAN_STATE_BUS_OFF;
1111 can_id |= CAN_ERR_BUSOFF;
1112 } else if (eflag & EFLG_TXEP) {
1113 new_state = CAN_STATE_ERROR_PASSIVE;
1114 can_id |= CAN_ERR_CRTL;
1115 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
1116 } else if (eflag & EFLG_RXEP) {
1117 new_state = CAN_STATE_ERROR_PASSIVE;
1118 can_id |= CAN_ERR_CRTL;
1119 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
1120 } else if (eflag & EFLG_TXWAR) {
1121 new_state = CAN_STATE_ERROR_WARNING;
1122 can_id |= CAN_ERR_CRTL;
1123 data1 |= CAN_ERR_CRTL_TX_WARNING;
1124 } else if (eflag & EFLG_RXWAR) {
1125 new_state = CAN_STATE_ERROR_WARNING;
1126 can_id |= CAN_ERR_CRTL;
1127 data1 |= CAN_ERR_CRTL_RX_WARNING;
1128 } else {
1129 new_state = CAN_STATE_ERROR_ACTIVE;
1130 }
1131
1132 /* Update can state statistics */
1133 switch (priv->can.state) {
1134 case CAN_STATE_ERROR_ACTIVE:
1135 if (new_state >= CAN_STATE_ERROR_WARNING &&
1136 new_state <= CAN_STATE_BUS_OFF)
1137 priv->can.can_stats.error_warning++;
1138 fallthrough;
1139 case CAN_STATE_ERROR_WARNING:
1140 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
1141 new_state <= CAN_STATE_BUS_OFF)
1142 priv->can.can_stats.error_passive++;
1143 break;
1144 default:
1145 break;
1146 }
1147 priv->can.state = new_state;
1148
1149 if (intf & CANINTF_ERRIF) {
1150 /* Handle overflow counters */
1151 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
1152 if (eflag & EFLG_RX0OVR) {
1153 net->stats.rx_over_errors++;
1154 net->stats.rx_errors++;
1155 }
1156 if (eflag & EFLG_RX1OVR) {
1157 net->stats.rx_over_errors++;
1158 net->stats.rx_errors++;
1159 }
1160 can_id |= CAN_ERR_CRTL;
1161 data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
1162 }
1163 mcp251x_error_skb(net, can_id, data1);
1164 }
1165
1166 if (priv->can.state == CAN_STATE_BUS_OFF) {
1167 if (priv->can.restart_ms == 0) {
1168 priv->force_quit = 1;
1169 priv->can.can_stats.bus_off++;
1170 can_bus_off(net);
1171 mcp251x_hw_sleep(spi);
1172 break;
1173 }
1174 }
1175
1176 if (intf == 0)
1177 break;
1178
1179 if (intf & CANINTF_TX) {
1180 net->stats.tx_packets++;
1181 net->stats.tx_bytes += priv->tx_len - 1;
1182 can_led_event(net, CAN_LED_EVENT_TX);
1183 if (priv->tx_len) {
1184 can_get_echo_skb(net, 0, NULL);
1185 priv->tx_len = 0;
1186 }
1187 netif_wake_queue(net);
1188 }
1189 }
1190 mutex_unlock(&priv->mcp_lock);
1191 return IRQ_HANDLED;
1192}
1193
1194static int mcp251x_open(struct net_device *net)
1195{
1196 struct mcp251x_priv *priv = netdev_priv(net);
1197 struct spi_device *spi = priv->spi;
1198 unsigned long flags = 0;
1199 int ret;
1200
1201 ret = open_candev(net);
1202 if (ret) {
1203 dev_err(&spi->dev, "unable to set initial baudrate!\n");
1204 return ret;
1205 }
1206
1207 mutex_lock(&priv->mcp_lock);
1208 mcp251x_power_enable(priv->transceiver, 1);
1209
1210 priv->force_quit = 0;
1211 priv->tx_skb = NULL;
1212 priv->tx_len = 0;
1213
1214 if (!dev_fwnode(&spi->dev))
1215 flags = IRQF_TRIGGER_FALLING;
1216
1217 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
1218 flags | IRQF_ONESHOT, dev_name(&spi->dev),
1219 priv);
1220 if (ret) {
1221 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
1222 goto out_close;
1223 }
1224
1225 ret = mcp251x_hw_wake(spi);
1226 if (ret)
1227 goto out_free_irq;
1228 ret = mcp251x_setup(net, spi);
1229 if (ret)
1230 goto out_free_irq;
1231 ret = mcp251x_set_normal_mode(spi);
1232 if (ret)
1233 goto out_free_irq;
1234
1235 can_led_event(net, CAN_LED_EVENT_OPEN);
1236
1237 netif_wake_queue(net);
1238 mutex_unlock(&priv->mcp_lock);
1239
1240 return 0;
1241
1242out_free_irq:
1243 free_irq(spi->irq, priv);
1244 mcp251x_hw_sleep(spi);
1245out_close:
1246 mcp251x_power_enable(priv->transceiver, 0);
1247 close_candev(net);
1248 mutex_unlock(&priv->mcp_lock);
1249 return ret;
1250}
1251
1252static const struct net_device_ops mcp251x_netdev_ops = {
1253 .ndo_open = mcp251x_open,
1254 .ndo_stop = mcp251x_stop,
1255 .ndo_start_xmit = mcp251x_hard_start_xmit,
1256 .ndo_change_mtu = can_change_mtu,
1257};
1258
1259static const struct of_device_id mcp251x_of_match[] = {
1260 {
1261 .compatible = "microchip,mcp2510",
1262 .data = (void *)CAN_MCP251X_MCP2510,
1263 },
1264 {
1265 .compatible = "microchip,mcp2515",
1266 .data = (void *)CAN_MCP251X_MCP2515,
1267 },
1268 {
1269 .compatible = "microchip,mcp25625",
1270 .data = (void *)CAN_MCP251X_MCP25625,
1271 },
1272 { }
1273};
1274MODULE_DEVICE_TABLE(of, mcp251x_of_match);
1275
1276static const struct spi_device_id mcp251x_id_table[] = {
1277 {
1278 .name = "mcp2510",
1279 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2510,
1280 },
1281 {
1282 .name = "mcp2515",
1283 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2515,
1284 },
1285 {
1286 .name = "mcp25625",
1287 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP25625,
1288 },
1289 { }
1290};
1291MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
1292
1293static int mcp251x_can_probe(struct spi_device *spi)
1294{
1295 const void *match = device_get_match_data(&spi->dev);
1296 struct net_device *net;
1297 struct mcp251x_priv *priv;
1298 struct clk *clk;
1299 u32 freq;
1300 int ret;
1301
1302 clk = devm_clk_get_optional(&spi->dev, NULL);
1303 if (IS_ERR(clk))
1304 return PTR_ERR(clk);
1305
1306 freq = clk_get_rate(clk);
1307 if (freq == 0)
1308 device_property_read_u32(&spi->dev, "clock-frequency", &freq);
1309
1310 /* Sanity check */
1311 if (freq < 1000000 || freq > 25000000)
1312 return -ERANGE;
1313
1314 /* Allocate can/net device */
1315 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
1316 if (!net)
1317 return -ENOMEM;
1318
1319 ret = clk_prepare_enable(clk);
1320 if (ret)
1321 goto out_free;
1322
1323 net->netdev_ops = &mcp251x_netdev_ops;
1324 net->flags |= IFF_ECHO;
1325
1326 priv = netdev_priv(net);
1327 priv->can.bittiming_const = &mcp251x_bittiming_const;
1328 priv->can.do_set_mode = mcp251x_do_set_mode;
1329 priv->can.clock.freq = freq / 2;
1330 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
1331 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
1332 if (match)
1333 priv->model = (enum mcp251x_model)(uintptr_t)match;
1334 else
1335 priv->model = spi_get_device_id(spi)->driver_data;
1336 priv->net = net;
1337 priv->clk = clk;
1338
1339 spi_set_drvdata(spi, priv);
1340
1341 /* Configure the SPI bus */
1342 spi->bits_per_word = 8;
1343 if (mcp251x_is_2510(spi))
1344 spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000;
1345 else
1346 spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000;
1347 ret = spi_setup(spi);
1348 if (ret)
1349 goto out_clk;
1350
1351 priv->power = devm_regulator_get_optional(&spi->dev, "vdd");
1352 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
1353 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
1354 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
1355 ret = -EPROBE_DEFER;
1356 goto out_clk;
1357 }
1358
1359 ret = mcp251x_power_enable(priv->power, 1);
1360 if (ret)
1361 goto out_clk;
1362
1363 priv->wq = alloc_workqueue("mcp251x_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM,
1364 0);
1365 if (!priv->wq) {
1366 ret = -ENOMEM;
1367 goto out_clk;
1368 }
1369 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
1370 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
1371
1372 priv->spi = spi;
1373 mutex_init(&priv->mcp_lock);
1374
1375 priv->spi_tx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1376 GFP_KERNEL);
1377 if (!priv->spi_tx_buf) {
1378 ret = -ENOMEM;
1379 goto error_probe;
1380 }
1381
1382 priv->spi_rx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1383 GFP_KERNEL);
1384 if (!priv->spi_rx_buf) {
1385 ret = -ENOMEM;
1386 goto error_probe;
1387 }
1388
1389 SET_NETDEV_DEV(net, &spi->dev);
1390
1391 /* Here is OK to not lock the MCP, no one knows about it yet */
1392 ret = mcp251x_hw_probe(spi);
1393 if (ret) {
1394 if (ret == -ENODEV)
1395 dev_err(&spi->dev, "Cannot initialize MCP%x. Wrong wiring?\n",
1396 priv->model);
1397 goto error_probe;
1398 }
1399
1400 mcp251x_hw_sleep(spi);
1401
1402 ret = register_candev(net);
1403 if (ret)
1404 goto error_probe;
1405
1406 devm_can_led_init(net);
1407
1408 ret = mcp251x_gpio_setup(priv);
1409 if (ret)
1410 goto error_probe;
1411
1412 netdev_info(net, "MCP%x successfully initialized.\n", priv->model);
1413 return 0;
1414
1415error_probe:
1416 destroy_workqueue(priv->wq);
1417 priv->wq = NULL;
1418 mcp251x_power_enable(priv->power, 0);
1419
1420out_clk:
1421 clk_disable_unprepare(clk);
1422
1423out_free:
1424 free_candev(net);
1425
1426 dev_err(&spi->dev, "Probe failed, err=%d\n", -ret);
1427 return ret;
1428}
1429
1430static int mcp251x_can_remove(struct spi_device *spi)
1431{
1432 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1433 struct net_device *net = priv->net;
1434
1435 unregister_candev(net);
1436
1437 mcp251x_power_enable(priv->power, 0);
1438
1439 destroy_workqueue(priv->wq);
1440 priv->wq = NULL;
1441
1442 clk_disable_unprepare(priv->clk);
1443
1444 free_candev(net);
1445
1446 return 0;
1447}
1448
1449static int __maybe_unused mcp251x_can_suspend(struct device *dev)
1450{
1451 struct spi_device *spi = to_spi_device(dev);
1452 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1453 struct net_device *net = priv->net;
1454
1455 priv->force_quit = 1;
1456 disable_irq(spi->irq);
1457 /* Note: at this point neither IST nor workqueues are running.
1458 * open/stop cannot be called anyway so locking is not needed
1459 */
1460 if (netif_running(net)) {
1461 netif_device_detach(net);
1462
1463 mcp251x_hw_sleep(spi);
1464 mcp251x_power_enable(priv->transceiver, 0);
1465 priv->after_suspend = AFTER_SUSPEND_UP;
1466 } else {
1467 priv->after_suspend = AFTER_SUSPEND_DOWN;
1468 }
1469
1470 mcp251x_power_enable(priv->power, 0);
1471 priv->after_suspend |= AFTER_SUSPEND_POWER;
1472
1473 return 0;
1474}
1475
1476static int __maybe_unused mcp251x_can_resume(struct device *dev)
1477{
1478 struct spi_device *spi = to_spi_device(dev);
1479 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1480
1481 if (priv->after_suspend & AFTER_SUSPEND_POWER)
1482 mcp251x_power_enable(priv->power, 1);
1483 if (priv->after_suspend & AFTER_SUSPEND_UP)
1484 mcp251x_power_enable(priv->transceiver, 1);
1485
1486 if (priv->after_suspend & (AFTER_SUSPEND_POWER | AFTER_SUSPEND_UP))
1487 queue_work(priv->wq, &priv->restart_work);
1488 else
1489 priv->after_suspend = 0;
1490
1491 priv->force_quit = 0;
1492 enable_irq(spi->irq);
1493 return 0;
1494}
1495
1496static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend,
1497 mcp251x_can_resume);
1498
1499static struct spi_driver mcp251x_can_driver = {
1500 .driver = {
1501 .name = DEVICE_NAME,
1502 .of_match_table = mcp251x_of_match,
1503 .pm = &mcp251x_can_pm_ops,
1504 },
1505 .id_table = mcp251x_id_table,
1506 .probe = mcp251x_can_probe,
1507 .remove = mcp251x_can_remove,
1508};
1509module_spi_driver(mcp251x_can_driver);
1510
1511MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1512 "Christian Pellegrin <chripell@evolware.org>");
1513MODULE_DESCRIPTION("Microchip 251x/25625 CAN driver");
1514MODULE_LICENSE("GPL v2");