Loading...
1/*
2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS - Power Management support
6 *
7 * Based on arch/arm/mach-s3c2410/pm.c
8 * Copyright (c) 2006 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#include <linux/init.h>
17#include <linux/suspend.h>
18#include <linux/syscore_ops.h>
19#include <linux/io.h>
20#include <linux/irqchip/arm-gic.h>
21#include <linux/err.h>
22#include <linux/clk.h>
23
24#include <asm/cacheflush.h>
25#include <asm/hardware/cache-l2x0.h>
26#include <asm/smp_scu.h>
27#include <asm/suspend.h>
28
29#include <plat/cpu.h>
30#include <plat/pm-common.h>
31#include <plat/pll.h>
32#include <plat/regs-srom.h>
33
34#include <mach/map.h>
35
36#include "common.h"
37#include "regs-pmu.h"
38
39/**
40 * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
41 * @hwirq: Hardware IRQ signal of the GIC
42 * @mask: Mask in PMU wake-up mask register
43 */
44struct exynos_wkup_irq {
45 unsigned int hwirq;
46 u32 mask;
47};
48
49static struct sleep_save exynos5_sys_save[] = {
50 SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
51};
52
53static struct sleep_save exynos_core_save[] = {
54 /* SROM side */
55 SAVE_ITEM(S5P_SROM_BW),
56 SAVE_ITEM(S5P_SROM_BC0),
57 SAVE_ITEM(S5P_SROM_BC1),
58 SAVE_ITEM(S5P_SROM_BC2),
59 SAVE_ITEM(S5P_SROM_BC3),
60};
61
62/*
63 * GIC wake-up support
64 */
65
66static u32 exynos_irqwake_intmask = 0xffffffff;
67
68static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
69 { 76, BIT(1) }, /* RTC alarm */
70 { 77, BIT(2) }, /* RTC tick */
71 { /* sentinel */ },
72};
73
74static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
75 { 75, BIT(1) }, /* RTC alarm */
76 { 76, BIT(2) }, /* RTC tick */
77 { /* sentinel */ },
78};
79
80static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
81{
82 const struct exynos_wkup_irq *wkup_irq;
83
84 if (soc_is_exynos5250())
85 wkup_irq = exynos5250_wkup_irq;
86 else
87 wkup_irq = exynos4_wkup_irq;
88
89 while (wkup_irq->mask) {
90 if (wkup_irq->hwirq == data->hwirq) {
91 if (!state)
92 exynos_irqwake_intmask |= wkup_irq->mask;
93 else
94 exynos_irqwake_intmask &= ~wkup_irq->mask;
95 return 0;
96 }
97 ++wkup_irq;
98 }
99
100 return -ENOENT;
101}
102
103/* For Cortex-A9 Diagnostic and Power control register */
104static unsigned int save_arm_register[2];
105
106static int exynos_cpu_suspend(unsigned long arg)
107{
108#ifdef CONFIG_CACHE_L2X0
109 outer_flush_all();
110#endif
111
112 if (soc_is_exynos5250())
113 flush_cache_all();
114
115 /* issue the standby signal into the pm unit. */
116 cpu_do_idle();
117
118 pr_info("Failed to suspend the system\n");
119 return 1; /* Aborting suspend */
120}
121
122static void exynos_pm_prepare(void)
123{
124 unsigned int tmp;
125
126 /* Set wake-up mask registers */
127 __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
128 __raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
129
130 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
131
132 if (soc_is_exynos5250()) {
133 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
134 /* Disable USE_RETENTION of JPEG_MEM_OPTION */
135 tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
136 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
137 __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
138 }
139
140 /* Set value of power down register for sleep mode */
141
142 exynos_sys_powerdown_conf(SYS_SLEEP);
143 __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
144
145 /* ensure at least INFORM0 has the resume address */
146
147 __raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
148}
149
150static int exynos_pm_suspend(void)
151{
152 unsigned long tmp;
153
154 /* Setting Central Sequence Register for power down mode */
155
156 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
157 tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
158 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
159
160 /* Setting SEQ_OPTION register */
161
162 tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
163 __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
164
165 if (!soc_is_exynos5250()) {
166 /* Save Power control register */
167 asm ("mrc p15, 0, %0, c15, c0, 0"
168 : "=r" (tmp) : : "cc");
169 save_arm_register[0] = tmp;
170
171 /* Save Diagnostic register */
172 asm ("mrc p15, 0, %0, c15, c0, 1"
173 : "=r" (tmp) : : "cc");
174 save_arm_register[1] = tmp;
175 }
176
177 return 0;
178}
179
180static void exynos_pm_resume(void)
181{
182 unsigned long tmp;
183
184 /*
185 * If PMU failed while entering sleep mode, WFI will be
186 * ignored by PMU and then exiting cpu_do_idle().
187 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
188 * in this situation.
189 */
190 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
191 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
192 tmp |= S5P_CENTRAL_LOWPWR_CFG;
193 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
194 /* clear the wakeup state register */
195 __raw_writel(0x0, S5P_WAKEUP_STAT);
196 /* No need to perform below restore code */
197 goto early_wakeup;
198 }
199 if (!soc_is_exynos5250()) {
200 /* Restore Power control register */
201 tmp = save_arm_register[0];
202 asm volatile ("mcr p15, 0, %0, c15, c0, 0"
203 : : "r" (tmp)
204 : "cc");
205
206 /* Restore Diagnostic register */
207 tmp = save_arm_register[1];
208 asm volatile ("mcr p15, 0, %0, c15, c0, 1"
209 : : "r" (tmp)
210 : "cc");
211 }
212
213 /* For release retention */
214
215 __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
216 __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
217 __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
218 __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
219 __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
220 __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
221 __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
222
223 if (soc_is_exynos5250())
224 s3c_pm_do_restore(exynos5_sys_save,
225 ARRAY_SIZE(exynos5_sys_save));
226
227 s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
228
229 if (IS_ENABLED(CONFIG_SMP) && !soc_is_exynos5250())
230 scu_enable(S5P_VA_SCU);
231
232early_wakeup:
233
234 /* Clear SLEEP mode set in INFORM1 */
235 __raw_writel(0x0, S5P_INFORM1);
236
237 return;
238}
239
240static struct syscore_ops exynos_pm_syscore_ops = {
241 .suspend = exynos_pm_suspend,
242 .resume = exynos_pm_resume,
243};
244
245/*
246 * Suspend Ops
247 */
248
249static int exynos_suspend_enter(suspend_state_t state)
250{
251 int ret;
252
253 s3c_pm_debug_init();
254
255 S3C_PMDBG("%s: suspending the system...\n", __func__);
256
257 S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
258 exynos_irqwake_intmask, exynos_get_eint_wake_mask());
259
260 if (exynos_irqwake_intmask == -1U
261 && exynos_get_eint_wake_mask() == -1U) {
262 pr_err("%s: No wake-up sources!\n", __func__);
263 pr_err("%s: Aborting sleep\n", __func__);
264 return -EINVAL;
265 }
266
267 s3c_pm_save_uarts();
268 exynos_pm_prepare();
269 flush_cache_all();
270 s3c_pm_check_store();
271
272 ret = cpu_suspend(0, exynos_cpu_suspend);
273 if (ret)
274 return ret;
275
276 s3c_pm_restore_uarts();
277
278 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
279 __raw_readl(S5P_WAKEUP_STAT));
280
281 s3c_pm_check_restore();
282
283 S3C_PMDBG("%s: resuming the system...\n", __func__);
284
285 return 0;
286}
287
288static int exynos_suspend_prepare(void)
289{
290 s3c_pm_check_prepare();
291
292 return 0;
293}
294
295static void exynos_suspend_finish(void)
296{
297 s3c_pm_check_cleanup();
298}
299
300static const struct platform_suspend_ops exynos_suspend_ops = {
301 .enter = exynos_suspend_enter,
302 .prepare = exynos_suspend_prepare,
303 .finish = exynos_suspend_finish,
304 .valid = suspend_valid_only_mem,
305};
306
307void __init exynos_pm_init(void)
308{
309 u32 tmp;
310
311 /* Platform-specific GIC callback */
312 gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
313
314 /* All wakeup disable */
315 tmp = __raw_readl(S5P_WAKEUP_MASK);
316 tmp |= ((0xFF << 8) | (0x1F << 1));
317 __raw_writel(tmp, S5P_WAKEUP_MASK);
318
319 register_syscore_ops(&exynos_pm_syscore_ops);
320 suspend_set_ops(&exynos_suspend_ops);
321}
1/*
2 * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS - Power Management support
6 *
7 * Based on arch/arm/mach-s3c2410/pm.c
8 * Copyright (c) 2006 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#include <linux/init.h>
17#include <linux/suspend.h>
18#include <linux/cpu_pm.h>
19#include <linux/io.h>
20#include <linux/of.h>
21#include <linux/soc/samsung/exynos-regs-pmu.h>
22#include <linux/soc/samsung/exynos-pmu.h>
23
24#include <asm/firmware.h>
25#include <asm/smp_scu.h>
26#include <asm/suspend.h>
27#include <asm/cacheflush.h>
28
29#include <mach/map.h>
30
31#include "common.h"
32
33static inline void __iomem *exynos_boot_vector_addr(void)
34{
35 if (samsung_rev() == EXYNOS4210_REV_1_1)
36 return pmu_base_addr + S5P_INFORM7;
37 else if (samsung_rev() == EXYNOS4210_REV_1_0)
38 return sysram_base_addr + 0x24;
39 return pmu_base_addr + S5P_INFORM0;
40}
41
42static inline void __iomem *exynos_boot_vector_flag(void)
43{
44 if (samsung_rev() == EXYNOS4210_REV_1_1)
45 return pmu_base_addr + S5P_INFORM6;
46 else if (samsung_rev() == EXYNOS4210_REV_1_0)
47 return sysram_base_addr + 0x20;
48 return pmu_base_addr + S5P_INFORM1;
49}
50
51#define S5P_CHECK_AFTR 0xFCBA0D10
52
53/* For Cortex-A9 Diagnostic and Power control register */
54static unsigned int save_arm_register[2];
55
56void exynos_cpu_save_register(void)
57{
58 unsigned long tmp;
59
60 /* Save Power control register */
61 asm ("mrc p15, 0, %0, c15, c0, 0"
62 : "=r" (tmp) : : "cc");
63
64 save_arm_register[0] = tmp;
65
66 /* Save Diagnostic register */
67 asm ("mrc p15, 0, %0, c15, c0, 1"
68 : "=r" (tmp) : : "cc");
69
70 save_arm_register[1] = tmp;
71}
72
73void exynos_cpu_restore_register(void)
74{
75 unsigned long tmp;
76
77 /* Restore Power control register */
78 tmp = save_arm_register[0];
79
80 asm volatile ("mcr p15, 0, %0, c15, c0, 0"
81 : : "r" (tmp)
82 : "cc");
83
84 /* Restore Diagnostic register */
85 tmp = save_arm_register[1];
86
87 asm volatile ("mcr p15, 0, %0, c15, c0, 1"
88 : : "r" (tmp)
89 : "cc");
90}
91
92void exynos_pm_central_suspend(void)
93{
94 unsigned long tmp;
95
96 /* Setting Central Sequence Register for power down mode */
97 tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
98 tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
99 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
100}
101
102int exynos_pm_central_resume(void)
103{
104 unsigned long tmp;
105
106 /*
107 * If PMU failed while entering sleep mode, WFI will be
108 * ignored by PMU and then exiting cpu_do_idle().
109 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
110 * in this situation.
111 */
112 tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
113 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
114 tmp |= S5P_CENTRAL_LOWPWR_CFG;
115 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
116 /* clear the wakeup state register */
117 pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
118 /* No need to perform below restore code */
119 return -1;
120 }
121
122 return 0;
123}
124
125/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
126static void exynos_set_wakeupmask(long mask)
127{
128 pmu_raw_writel(mask, S5P_WAKEUP_MASK);
129 if (soc_is_exynos3250())
130 pmu_raw_writel(0x0, S5P_WAKEUP_MASK2);
131}
132
133static void exynos_cpu_set_boot_vector(long flags)
134{
135 writel_relaxed(virt_to_phys(exynos_cpu_resume),
136 exynos_boot_vector_addr());
137 writel_relaxed(flags, exynos_boot_vector_flag());
138}
139
140static int exynos_aftr_finisher(unsigned long flags)
141{
142 int ret;
143
144 exynos_set_wakeupmask(soc_is_exynos3250() ? 0x40003ffe : 0x0000ff3e);
145 /* Set value of power down register for aftr mode */
146 exynos_sys_powerdown_conf(SYS_AFTR);
147
148 ret = call_firmware_op(do_idle, FW_DO_IDLE_AFTR);
149 if (ret == -ENOSYS) {
150 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
151 exynos_cpu_save_register();
152 exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
153 cpu_do_idle();
154 }
155
156 return 1;
157}
158
159void exynos_enter_aftr(void)
160{
161 unsigned int cpuid = smp_processor_id();
162
163 cpu_pm_enter();
164
165 if (soc_is_exynos3250())
166 exynos_set_boot_flag(cpuid, C2_STATE);
167
168 exynos_pm_central_suspend();
169
170 if (of_machine_is_compatible("samsung,exynos4212") ||
171 of_machine_is_compatible("samsung,exynos4412")) {
172 /* Setting SEQ_OPTION register */
173 pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
174 S5P_CENTRAL_SEQ_OPTION);
175 }
176
177 cpu_suspend(0, exynos_aftr_finisher);
178
179 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
180 scu_enable(S5P_VA_SCU);
181 if (call_firmware_op(resume) == -ENOSYS)
182 exynos_cpu_restore_register();
183 }
184
185 exynos_pm_central_resume();
186
187 if (soc_is_exynos3250())
188 exynos_clear_boot_flag(cpuid, C2_STATE);
189
190 cpu_pm_exit();
191}
192
193#if defined(CONFIG_SMP) && defined(CONFIG_ARM_EXYNOS_CPUIDLE)
194static atomic_t cpu1_wakeup = ATOMIC_INIT(0);
195
196static int exynos_cpu0_enter_aftr(void)
197{
198 int ret = -1;
199
200 /*
201 * If the other cpu is powered on, we have to power it off, because
202 * the AFTR state won't work otherwise
203 */
204 if (cpu_online(1)) {
205 /*
206 * We reach a sync point with the coupled idle state, we know
207 * the other cpu will power down itself or will abort the
208 * sequence, let's wait for one of these to happen
209 */
210 while (exynos_cpu_power_state(1)) {
211 unsigned long boot_addr;
212
213 /*
214 * The other cpu may skip idle and boot back
215 * up again
216 */
217 if (atomic_read(&cpu1_wakeup))
218 goto abort;
219
220 /*
221 * The other cpu may bounce through idle and
222 * boot back up again, getting stuck in the
223 * boot rom code
224 */
225 ret = exynos_get_boot_addr(1, &boot_addr);
226 if (ret)
227 goto fail;
228 ret = -1;
229 if (boot_addr == 0)
230 goto abort;
231
232 cpu_relax();
233 }
234 }
235
236 exynos_enter_aftr();
237 ret = 0;
238
239abort:
240 if (cpu_online(1)) {
241 unsigned long boot_addr = virt_to_phys(exynos_cpu_resume);
242
243 /*
244 * Set the boot vector to something non-zero
245 */
246 ret = exynos_set_boot_addr(1, boot_addr);
247 if (ret)
248 goto fail;
249 dsb();
250
251 /*
252 * Turn on cpu1 and wait for it to be on
253 */
254 exynos_cpu_power_up(1);
255 while (exynos_cpu_power_state(1) != S5P_CORE_LOCAL_PWR_EN)
256 cpu_relax();
257
258 if (soc_is_exynos3250()) {
259 while (!pmu_raw_readl(S5P_PMU_SPARE2) &&
260 !atomic_read(&cpu1_wakeup))
261 cpu_relax();
262
263 if (!atomic_read(&cpu1_wakeup))
264 exynos_core_restart(1);
265 }
266
267 while (!atomic_read(&cpu1_wakeup)) {
268 smp_rmb();
269
270 /*
271 * Poke cpu1 out of the boot rom
272 */
273
274 ret = exynos_set_boot_addr(1, boot_addr);
275 if (ret)
276 goto fail;
277
278 call_firmware_op(cpu_boot, 1);
279
280 if (soc_is_exynos3250())
281 dsb_sev();
282 else
283 arch_send_wakeup_ipi_mask(cpumask_of(1));
284 }
285 }
286fail:
287 return ret;
288}
289
290static int exynos_wfi_finisher(unsigned long flags)
291{
292 if (soc_is_exynos3250())
293 flush_cache_all();
294 cpu_do_idle();
295
296 return -1;
297}
298
299static int exynos_cpu1_powerdown(void)
300{
301 int ret = -1;
302
303 /*
304 * Idle sequence for cpu1
305 */
306 if (cpu_pm_enter())
307 goto cpu1_aborted;
308
309 /*
310 * Turn off cpu 1
311 */
312 exynos_cpu_power_down(1);
313
314 if (soc_is_exynos3250())
315 pmu_raw_writel(0, S5P_PMU_SPARE2);
316
317 ret = cpu_suspend(0, exynos_wfi_finisher);
318
319 cpu_pm_exit();
320
321cpu1_aborted:
322 dsb();
323 /*
324 * Notify cpu 0 that cpu 1 is awake
325 */
326 atomic_set(&cpu1_wakeup, 1);
327
328 return ret;
329}
330
331static void exynos_pre_enter_aftr(void)
332{
333 unsigned long boot_addr = virt_to_phys(exynos_cpu_resume);
334
335 (void)exynos_set_boot_addr(1, boot_addr);
336}
337
338static void exynos_post_enter_aftr(void)
339{
340 atomic_set(&cpu1_wakeup, 0);
341}
342
343struct cpuidle_exynos_data cpuidle_coupled_exynos_data = {
344 .cpu0_enter_aftr = exynos_cpu0_enter_aftr,
345 .cpu1_powerdown = exynos_cpu1_powerdown,
346 .pre_enter_aftr = exynos_pre_enter_aftr,
347 .post_enter_aftr = exynos_post_enter_aftr,
348};
349#endif /* CONFIG_SMP && CONFIG_ARM_EXYNOS_CPUIDLE */