Loading...
1/*
2 * linux/arch/arm/mach-omap1/clock_data.c
3 *
4 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * To do:
13 * - Clocks that are only available on some chips should be marked with the
14 * chips that they are present on.
15 */
16
17#include <linux/kernel.h>
18#include <linux/io.h>
19#include <linux/clk.h>
20#include <linux/cpufreq.h>
21#include <linux/delay.h>
22
23#include <asm/mach-types.h> /* for machine_is_* */
24
25#include "soc.h"
26
27#include <mach/hardware.h>
28#include <mach/usb.h> /* for OTG_BASE */
29
30#include "iomap.h"
31#include "clock.h"
32#include "sram.h"
33
34/* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
35#define IDL_CLKOUT_ARM_SHIFT 12
36#define IDLTIM_ARM_SHIFT 9
37#define IDLAPI_ARM_SHIFT 8
38#define IDLIF_ARM_SHIFT 6
39#define IDLLB_ARM_SHIFT 4 /* undocumented? */
40#define OMAP1510_IDLLCD_ARM_SHIFT 3 /* undocumented? */
41#define IDLPER_ARM_SHIFT 2
42#define IDLXORP_ARM_SHIFT 1
43#define IDLWDT_ARM_SHIFT 0
44
45/* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
46#define CONF_MOD_UART3_CLK_MODE_R 31
47#define CONF_MOD_UART2_CLK_MODE_R 30
48#define CONF_MOD_UART1_CLK_MODE_R 29
49#define CONF_MOD_MMC_SD_CLK_REQ_R 23
50#define CONF_MOD_MCBSP3_AUXON 20
51
52/* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
53#define CONF_MOD_SOSSI_CLK_EN_R 16
54
55/* Some OTG_SYSCON_2-specific bit fields */
56#define OTG_SYSCON_2_UHOST_EN_SHIFT 8
57
58/* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */
59#define SOFT_MMC2_DPLL_REQ_SHIFT 13
60#define SOFT_MMC_DPLL_REQ_SHIFT 12
61#define SOFT_UART3_DPLL_REQ_SHIFT 11
62#define SOFT_UART2_DPLL_REQ_SHIFT 10
63#define SOFT_UART1_DPLL_REQ_SHIFT 9
64#define SOFT_USB_OTG_DPLL_REQ_SHIFT 8
65#define SOFT_CAM_DPLL_REQ_SHIFT 7
66#define SOFT_COM_MCKO_REQ_SHIFT 6
67#define SOFT_PERIPH_REQ_SHIFT 5 /* sys_ck gate for UART2 ? */
68#define USB_REQ_EN_SHIFT 4
69#define SOFT_USB_REQ_SHIFT 3 /* sys_ck gate for USB host? */
70#define SOFT_SDW_REQ_SHIFT 2 /* sys_ck gate for Bluetooth? */
71#define SOFT_COM_REQ_SHIFT 1 /* sys_ck gate for com proc? */
72#define SOFT_DPLL_REQ_SHIFT 0
73
74/*
75 * Omap1 clocks
76 */
77
78static struct clk ck_ref = {
79 .name = "ck_ref",
80 .ops = &clkops_null,
81 .rate = 12000000,
82};
83
84static struct clk ck_dpll1 = {
85 .name = "ck_dpll1",
86 .ops = &clkops_null,
87 .parent = &ck_ref,
88};
89
90/*
91 * FIXME: This clock seems to be necessary but no-one has asked for its
92 * activation. [ FIX: SoSSI, SSR ]
93 */
94static struct arm_idlect1_clk ck_dpll1out = {
95 .clk = {
96 .name = "ck_dpll1out",
97 .ops = &clkops_generic,
98 .parent = &ck_dpll1,
99 .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
100 ENABLE_ON_INIT,
101 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
102 .enable_bit = EN_CKOUT_ARM,
103 .recalc = &followparent_recalc,
104 },
105 .idlect_shift = IDL_CLKOUT_ARM_SHIFT,
106};
107
108static struct clk sossi_ck = {
109 .name = "ck_sossi",
110 .ops = &clkops_generic,
111 .parent = &ck_dpll1out.clk,
112 .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
113 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
114 .enable_bit = CONF_MOD_SOSSI_CLK_EN_R,
115 .recalc = &omap1_sossi_recalc,
116 .set_rate = &omap1_set_sossi_rate,
117};
118
119static struct clk arm_ck = {
120 .name = "arm_ck",
121 .ops = &clkops_null,
122 .parent = &ck_dpll1,
123 .rate_offset = CKCTL_ARMDIV_OFFSET,
124 .recalc = &omap1_ckctl_recalc,
125 .round_rate = omap1_clk_round_rate_ckctl_arm,
126 .set_rate = omap1_clk_set_rate_ckctl_arm,
127};
128
129static struct arm_idlect1_clk armper_ck = {
130 .clk = {
131 .name = "armper_ck",
132 .ops = &clkops_generic,
133 .parent = &ck_dpll1,
134 .flags = CLOCK_IDLE_CONTROL,
135 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
136 .enable_bit = EN_PERCK,
137 .rate_offset = CKCTL_PERDIV_OFFSET,
138 .recalc = &omap1_ckctl_recalc,
139 .round_rate = omap1_clk_round_rate_ckctl_arm,
140 .set_rate = omap1_clk_set_rate_ckctl_arm,
141 },
142 .idlect_shift = IDLPER_ARM_SHIFT,
143};
144
145/*
146 * FIXME: This clock seems to be necessary but no-one has asked for its
147 * activation. [ GPIO code for 1510 ]
148 */
149static struct clk arm_gpio_ck = {
150 .name = "ick",
151 .ops = &clkops_generic,
152 .parent = &ck_dpll1,
153 .flags = ENABLE_ON_INIT,
154 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
155 .enable_bit = EN_GPIOCK,
156 .recalc = &followparent_recalc,
157};
158
159static struct arm_idlect1_clk armxor_ck = {
160 .clk = {
161 .name = "armxor_ck",
162 .ops = &clkops_generic,
163 .parent = &ck_ref,
164 .flags = CLOCK_IDLE_CONTROL,
165 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
166 .enable_bit = EN_XORPCK,
167 .recalc = &followparent_recalc,
168 },
169 .idlect_shift = IDLXORP_ARM_SHIFT,
170};
171
172static struct arm_idlect1_clk armtim_ck = {
173 .clk = {
174 .name = "armtim_ck",
175 .ops = &clkops_generic,
176 .parent = &ck_ref,
177 .flags = CLOCK_IDLE_CONTROL,
178 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
179 .enable_bit = EN_TIMCK,
180 .recalc = &followparent_recalc,
181 },
182 .idlect_shift = IDLTIM_ARM_SHIFT,
183};
184
185static struct arm_idlect1_clk armwdt_ck = {
186 .clk = {
187 .name = "armwdt_ck",
188 .ops = &clkops_generic,
189 .parent = &ck_ref,
190 .flags = CLOCK_IDLE_CONTROL,
191 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
192 .enable_bit = EN_WDTCK,
193 .fixed_div = 14,
194 .recalc = &omap_fixed_divisor_recalc,
195 },
196 .idlect_shift = IDLWDT_ARM_SHIFT,
197};
198
199static struct clk arminth_ck16xx = {
200 .name = "arminth_ck",
201 .ops = &clkops_null,
202 .parent = &arm_ck,
203 .recalc = &followparent_recalc,
204 /* Note: On 16xx the frequency can be divided by 2 by programming
205 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
206 *
207 * 1510 version is in TC clocks.
208 */
209};
210
211static struct clk dsp_ck = {
212 .name = "dsp_ck",
213 .ops = &clkops_generic,
214 .parent = &ck_dpll1,
215 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
216 .enable_bit = EN_DSPCK,
217 .rate_offset = CKCTL_DSPDIV_OFFSET,
218 .recalc = &omap1_ckctl_recalc,
219 .round_rate = omap1_clk_round_rate_ckctl_arm,
220 .set_rate = omap1_clk_set_rate_ckctl_arm,
221};
222
223static struct clk dspmmu_ck = {
224 .name = "dspmmu_ck",
225 .ops = &clkops_null,
226 .parent = &ck_dpll1,
227 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
228 .recalc = &omap1_ckctl_recalc,
229 .round_rate = omap1_clk_round_rate_ckctl_arm,
230 .set_rate = omap1_clk_set_rate_ckctl_arm,
231};
232
233static struct clk dspper_ck = {
234 .name = "dspper_ck",
235 .ops = &clkops_dspck,
236 .parent = &ck_dpll1,
237 .enable_reg = DSP_IDLECT2,
238 .enable_bit = EN_PERCK,
239 .rate_offset = CKCTL_PERDIV_OFFSET,
240 .recalc = &omap1_ckctl_recalc_dsp_domain,
241 .round_rate = omap1_clk_round_rate_ckctl_arm,
242 .set_rate = &omap1_clk_set_rate_dsp_domain,
243};
244
245static struct clk dspxor_ck = {
246 .name = "dspxor_ck",
247 .ops = &clkops_dspck,
248 .parent = &ck_ref,
249 .enable_reg = DSP_IDLECT2,
250 .enable_bit = EN_XORPCK,
251 .recalc = &followparent_recalc,
252};
253
254static struct clk dsptim_ck = {
255 .name = "dsptim_ck",
256 .ops = &clkops_dspck,
257 .parent = &ck_ref,
258 .enable_reg = DSP_IDLECT2,
259 .enable_bit = EN_DSPTIMCK,
260 .recalc = &followparent_recalc,
261};
262
263static struct arm_idlect1_clk tc_ck = {
264 .clk = {
265 .name = "tc_ck",
266 .ops = &clkops_null,
267 .parent = &ck_dpll1,
268 .flags = CLOCK_IDLE_CONTROL,
269 .rate_offset = CKCTL_TCDIV_OFFSET,
270 .recalc = &omap1_ckctl_recalc,
271 .round_rate = omap1_clk_round_rate_ckctl_arm,
272 .set_rate = omap1_clk_set_rate_ckctl_arm,
273 },
274 .idlect_shift = IDLIF_ARM_SHIFT,
275};
276
277static struct clk arminth_ck1510 = {
278 .name = "arminth_ck",
279 .ops = &clkops_null,
280 .parent = &tc_ck.clk,
281 .recalc = &followparent_recalc,
282 /* Note: On 1510 the frequency follows TC_CK
283 *
284 * 16xx version is in MPU clocks.
285 */
286};
287
288static struct clk tipb_ck = {
289 /* No-idle controlled by "tc_ck" */
290 .name = "tipb_ck",
291 .ops = &clkops_null,
292 .parent = &tc_ck.clk,
293 .recalc = &followparent_recalc,
294};
295
296static struct clk l3_ocpi_ck = {
297 /* No-idle controlled by "tc_ck" */
298 .name = "l3_ocpi_ck",
299 .ops = &clkops_generic,
300 .parent = &tc_ck.clk,
301 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
302 .enable_bit = EN_OCPI_CK,
303 .recalc = &followparent_recalc,
304};
305
306static struct clk tc1_ck = {
307 .name = "tc1_ck",
308 .ops = &clkops_generic,
309 .parent = &tc_ck.clk,
310 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
311 .enable_bit = EN_TC1_CK,
312 .recalc = &followparent_recalc,
313};
314
315/*
316 * FIXME: This clock seems to be necessary but no-one has asked for its
317 * activation. [ pm.c (SRAM), CCP, Camera ]
318 */
319static struct clk tc2_ck = {
320 .name = "tc2_ck",
321 .ops = &clkops_generic,
322 .parent = &tc_ck.clk,
323 .flags = ENABLE_ON_INIT,
324 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
325 .enable_bit = EN_TC2_CK,
326 .recalc = &followparent_recalc,
327};
328
329static struct clk dma_ck = {
330 /* No-idle controlled by "tc_ck" */
331 .name = "dma_ck",
332 .ops = &clkops_null,
333 .parent = &tc_ck.clk,
334 .recalc = &followparent_recalc,
335};
336
337static struct clk dma_lcdfree_ck = {
338 .name = "dma_lcdfree_ck",
339 .ops = &clkops_null,
340 .parent = &tc_ck.clk,
341 .recalc = &followparent_recalc,
342};
343
344static struct arm_idlect1_clk api_ck = {
345 .clk = {
346 .name = "api_ck",
347 .ops = &clkops_generic,
348 .parent = &tc_ck.clk,
349 .flags = CLOCK_IDLE_CONTROL,
350 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
351 .enable_bit = EN_APICK,
352 .recalc = &followparent_recalc,
353 },
354 .idlect_shift = IDLAPI_ARM_SHIFT,
355};
356
357static struct arm_idlect1_clk lb_ck = {
358 .clk = {
359 .name = "lb_ck",
360 .ops = &clkops_generic,
361 .parent = &tc_ck.clk,
362 .flags = CLOCK_IDLE_CONTROL,
363 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
364 .enable_bit = EN_LBCK,
365 .recalc = &followparent_recalc,
366 },
367 .idlect_shift = IDLLB_ARM_SHIFT,
368};
369
370static struct clk rhea1_ck = {
371 .name = "rhea1_ck",
372 .ops = &clkops_null,
373 .parent = &tc_ck.clk,
374 .recalc = &followparent_recalc,
375};
376
377static struct clk rhea2_ck = {
378 .name = "rhea2_ck",
379 .ops = &clkops_null,
380 .parent = &tc_ck.clk,
381 .recalc = &followparent_recalc,
382};
383
384static struct clk lcd_ck_16xx = {
385 .name = "lcd_ck",
386 .ops = &clkops_generic,
387 .parent = &ck_dpll1,
388 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
389 .enable_bit = EN_LCDCK,
390 .rate_offset = CKCTL_LCDDIV_OFFSET,
391 .recalc = &omap1_ckctl_recalc,
392 .round_rate = omap1_clk_round_rate_ckctl_arm,
393 .set_rate = omap1_clk_set_rate_ckctl_arm,
394};
395
396static struct arm_idlect1_clk lcd_ck_1510 = {
397 .clk = {
398 .name = "lcd_ck",
399 .ops = &clkops_generic,
400 .parent = &ck_dpll1,
401 .flags = CLOCK_IDLE_CONTROL,
402 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
403 .enable_bit = EN_LCDCK,
404 .rate_offset = CKCTL_LCDDIV_OFFSET,
405 .recalc = &omap1_ckctl_recalc,
406 .round_rate = omap1_clk_round_rate_ckctl_arm,
407 .set_rate = omap1_clk_set_rate_ckctl_arm,
408 },
409 .idlect_shift = OMAP1510_IDLLCD_ARM_SHIFT,
410};
411
412/*
413 * XXX The enable_bit here is misused - it simply switches between 12MHz
414 * and 48MHz. Reimplement with clksel.
415 *
416 * XXX does this need SYSC register handling?
417 */
418static struct clk uart1_1510 = {
419 .name = "uart1_ck",
420 .ops = &clkops_null,
421 /* Direct from ULPD, no real parent */
422 .parent = &armper_ck.clk,
423 .rate = 12000000,
424 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
425 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
426 .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
427 .set_rate = &omap1_set_uart_rate,
428 .recalc = &omap1_uart_recalc,
429};
430
431/*
432 * XXX The enable_bit here is misused - it simply switches between 12MHz
433 * and 48MHz. Reimplement with clksel.
434 *
435 * XXX SYSC register handling does not belong in the clock framework
436 */
437static struct uart_clk uart1_16xx = {
438 .clk = {
439 .name = "uart1_ck",
440 .ops = &clkops_uart_16xx,
441 /* Direct from ULPD, no real parent */
442 .parent = &armper_ck.clk,
443 .rate = 48000000,
444 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
445 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
446 .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
447 },
448 .sysc_addr = 0xfffb0054,
449};
450
451/*
452 * XXX The enable_bit here is misused - it simply switches between 12MHz
453 * and 48MHz. Reimplement with clksel.
454 *
455 * XXX does this need SYSC register handling?
456 */
457static struct clk uart2_ck = {
458 .name = "uart2_ck",
459 .ops = &clkops_null,
460 /* Direct from ULPD, no real parent */
461 .parent = &armper_ck.clk,
462 .rate = 12000000,
463 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
464 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
465 .enable_bit = CONF_MOD_UART2_CLK_MODE_R,
466 .set_rate = &omap1_set_uart_rate,
467 .recalc = &omap1_uart_recalc,
468};
469
470/*
471 * XXX The enable_bit here is misused - it simply switches between 12MHz
472 * and 48MHz. Reimplement with clksel.
473 *
474 * XXX does this need SYSC register handling?
475 */
476static struct clk uart3_1510 = {
477 .name = "uart3_ck",
478 .ops = &clkops_null,
479 /* Direct from ULPD, no real parent */
480 .parent = &armper_ck.clk,
481 .rate = 12000000,
482 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
483 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
484 .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
485 .set_rate = &omap1_set_uart_rate,
486 .recalc = &omap1_uart_recalc,
487};
488
489/*
490 * XXX The enable_bit here is misused - it simply switches between 12MHz
491 * and 48MHz. Reimplement with clksel.
492 *
493 * XXX SYSC register handling does not belong in the clock framework
494 */
495static struct uart_clk uart3_16xx = {
496 .clk = {
497 .name = "uart3_ck",
498 .ops = &clkops_uart_16xx,
499 /* Direct from ULPD, no real parent */
500 .parent = &armper_ck.clk,
501 .rate = 48000000,
502 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
503 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
504 .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
505 },
506 .sysc_addr = 0xfffb9854,
507};
508
509static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
510 .name = "usb_clko",
511 .ops = &clkops_generic,
512 /* Direct from ULPD, no parent */
513 .rate = 6000000,
514 .flags = ENABLE_REG_32BIT,
515 .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
516 .enable_bit = USB_MCLK_EN_BIT,
517};
518
519static struct clk usb_hhc_ck1510 = {
520 .name = "usb_hhc_ck",
521 .ops = &clkops_generic,
522 /* Direct from ULPD, no parent */
523 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
524 .flags = ENABLE_REG_32BIT,
525 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
526 .enable_bit = USB_HOST_HHC_UHOST_EN,
527};
528
529static struct clk usb_hhc_ck16xx = {
530 .name = "usb_hhc_ck",
531 .ops = &clkops_generic,
532 /* Direct from ULPD, no parent */
533 .rate = 48000000,
534 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
535 .flags = ENABLE_REG_32BIT,
536 .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
537 .enable_bit = OTG_SYSCON_2_UHOST_EN_SHIFT
538};
539
540static struct clk usb_dc_ck = {
541 .name = "usb_dc_ck",
542 .ops = &clkops_generic,
543 /* Direct from ULPD, no parent */
544 .rate = 48000000,
545 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
546 .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT,
547};
548
549static struct clk uart1_7xx = {
550 .name = "uart1_ck",
551 .ops = &clkops_generic,
552 /* Direct from ULPD, no parent */
553 .rate = 12000000,
554 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
555 .enable_bit = 9,
556};
557
558static struct clk uart2_7xx = {
559 .name = "uart2_ck",
560 .ops = &clkops_generic,
561 /* Direct from ULPD, no parent */
562 .rate = 12000000,
563 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
564 .enable_bit = 11,
565};
566
567static struct clk mclk_1510 = {
568 .name = "mclk",
569 .ops = &clkops_generic,
570 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
571 .rate = 12000000,
572 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
573 .enable_bit = SOFT_COM_MCKO_REQ_SHIFT,
574};
575
576static struct clk mclk_16xx = {
577 .name = "mclk",
578 .ops = &clkops_generic,
579 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
580 .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
581 .enable_bit = COM_ULPD_PLL_CLK_REQ,
582 .set_rate = &omap1_set_ext_clk_rate,
583 .round_rate = &omap1_round_ext_clk_rate,
584 .init = &omap1_init_ext_clk,
585};
586
587static struct clk bclk_1510 = {
588 .name = "bclk",
589 .ops = &clkops_generic,
590 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
591 .rate = 12000000,
592};
593
594static struct clk bclk_16xx = {
595 .name = "bclk",
596 .ops = &clkops_generic,
597 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
598 .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
599 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
600 .set_rate = &omap1_set_ext_clk_rate,
601 .round_rate = &omap1_round_ext_clk_rate,
602 .init = &omap1_init_ext_clk,
603};
604
605static struct clk mmc1_ck = {
606 .name = "mmc1_ck",
607 .ops = &clkops_generic,
608 /* Functional clock is direct from ULPD, interface clock is ARMPER */
609 .parent = &armper_ck.clk,
610 .rate = 48000000,
611 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
612 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
613 .enable_bit = CONF_MOD_MMC_SD_CLK_REQ_R,
614};
615
616/*
617 * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as
618 * CONF_MOD_MCBSP3_AUXON ??
619 */
620static struct clk mmc2_ck = {
621 .name = "mmc2_ck",
622 .ops = &clkops_generic,
623 /* Functional clock is direct from ULPD, interface clock is ARMPER */
624 .parent = &armper_ck.clk,
625 .rate = 48000000,
626 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
627 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
628 .enable_bit = 20,
629};
630
631static struct clk mmc3_ck = {
632 .name = "mmc3_ck",
633 .ops = &clkops_generic,
634 /* Functional clock is direct from ULPD, interface clock is ARMPER */
635 .parent = &armper_ck.clk,
636 .rate = 48000000,
637 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
638 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
639 .enable_bit = SOFT_MMC_DPLL_REQ_SHIFT,
640};
641
642static struct clk virtual_ck_mpu = {
643 .name = "mpu",
644 .ops = &clkops_null,
645 .parent = &arm_ck, /* Is smarter alias for */
646 .recalc = &followparent_recalc,
647 .set_rate = &omap1_select_table_rate,
648 .round_rate = &omap1_round_to_table_rate,
649};
650
651/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
652remains active during MPU idle whenever this is enabled */
653static struct clk i2c_fck = {
654 .name = "i2c_fck",
655 .ops = &clkops_null,
656 .flags = CLOCK_NO_IDLE_PARENT,
657 .parent = &armxor_ck.clk,
658 .recalc = &followparent_recalc,
659};
660
661static struct clk i2c_ick = {
662 .name = "i2c_ick",
663 .ops = &clkops_null,
664 .flags = CLOCK_NO_IDLE_PARENT,
665 .parent = &armper_ck.clk,
666 .recalc = &followparent_recalc,
667};
668
669/*
670 * clkdev integration
671 */
672
673static struct omap_clk omap_clks[] = {
674 /* non-ULPD clocks */
675 CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX),
676 CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310 | CK_7XX),
677 /* CK_GEN1 clocks */
678 CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
679 CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX),
680 CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310),
681 CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
682 CLK("omap_gpio.0", "ick", &arm_gpio_ck, CK_1510 | CK_310),
683 CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
684 CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
685 CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
686 CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX),
687 CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310),
688 CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310),
689 CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX),
690 /* CK_GEN2 clocks */
691 CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310),
692 CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310),
693 CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310),
694 CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
695 CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310),
696 /* CK_GEN3 clocks */
697 CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
698 CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310),
699 CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX),
700 CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX),
701 CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX),
702 CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310),
703 CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
704 CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
705 CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310),
706 CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX),
707 CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX),
708 CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX),
709 CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310),
710 /* ULPD clocks */
711 CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310),
712 CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX),
713 CLK(NULL, "uart1_ck", &uart1_7xx, CK_7XX),
714 CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310),
715 CLK(NULL, "uart2_ck", &uart2_7xx, CK_7XX),
716 CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310),
717 CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX),
718 CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310),
719 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310),
720 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX),
721 CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX | CK_7XX),
722 CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310),
723 CLK(NULL, "mclk", &mclk_16xx, CK_16XX),
724 CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310),
725 CLK(NULL, "bclk", &bclk_16xx, CK_16XX),
726 CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310),
727 CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX),
728 CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
729 CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX),
730 CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX),
731 /* Virtual clocks */
732 CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
733 CLK("omap_i2c.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX),
734 CLK("omap_i2c.1", "ick", &i2c_ick, CK_16XX),
735 CLK("omap_i2c.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX),
736 CLK("omap1_spi100k.1", "fck", &dummy_ck, CK_7XX),
737 CLK("omap1_spi100k.1", "ick", &dummy_ck, CK_7XX),
738 CLK("omap1_spi100k.2", "fck", &dummy_ck, CK_7XX),
739 CLK("omap1_spi100k.2", "ick", &dummy_ck, CK_7XX),
740 CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
741 CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX),
742 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310),
743 CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX),
744 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310),
745 CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX),
746 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310),
747 CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
748 CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
749 CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
750};
751
752/*
753 * init
754 */
755
756static void __init omap1_show_rates(void)
757{
758 pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
759 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
760 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
761 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
762}
763
764u32 cpu_mask;
765
766int __init omap1_clk_init(void)
767{
768 struct omap_clk *c;
769 int crystal_type = 0; /* Default 12 MHz */
770 u32 reg;
771
772#ifdef CONFIG_DEBUG_LL
773 /*
774 * Resets some clocks that may be left on from bootloader,
775 * but leaves serial clocks on.
776 */
777 omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
778#endif
779
780 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
781 reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
782 omap_writew(reg, SOFT_REQ_REG);
783 if (!cpu_is_omap15xx())
784 omap_writew(0, SOFT_REQ_REG2);
785
786 /* By default all idlect1 clocks are allowed to idle */
787 arm_idlect1_mask = ~0;
788
789 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
790 clk_preinit(c->lk.clk);
791
792 cpu_mask = 0;
793 if (cpu_is_omap1710())
794 cpu_mask |= CK_1710;
795 if (cpu_is_omap16xx())
796 cpu_mask |= CK_16XX;
797 if (cpu_is_omap1510())
798 cpu_mask |= CK_1510;
799 if (cpu_is_omap7xx())
800 cpu_mask |= CK_7XX;
801 if (cpu_is_omap310())
802 cpu_mask |= CK_310;
803
804 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
805 if (c->cpu & cpu_mask) {
806 clkdev_add(&c->lk);
807 clk_register(c->lk.clk);
808 }
809
810 /* Pointers to these clocks are needed by code in clock.c */
811 api_ck_p = clk_get(NULL, "api_ck");
812 ck_dpll1_p = clk_get(NULL, "ck_dpll1");
813 ck_ref_p = clk_get(NULL, "ck_ref");
814
815 if (cpu_is_omap7xx())
816 ck_ref.rate = 13000000;
817 if (cpu_is_omap16xx() && crystal_type == 2)
818 ck_ref.rate = 19200000;
819
820 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
821 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
822 omap_readw(ARM_CKCTL));
823
824 /* We want to be in syncronous scalable mode */
825 omap_writew(0x1000, ARM_SYSST);
826
827
828 /*
829 * Initially use the values set by bootloader. Determine PLL rate and
830 * recalculate dependent clocks as if kernel had changed PLL or
831 * divisors. See also omap1_clk_late_init() that can reprogram dpll1
832 * after the SRAM is initialized.
833 */
834 {
835 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
836
837 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
838 if (pll_ctl_val & 0x10) {
839 /* PLL enabled, apply multiplier and divisor */
840 if (pll_ctl_val & 0xf80)
841 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
842 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
843 } else {
844 /* PLL disabled, apply bypass divisor */
845 switch (pll_ctl_val & 0xc) {
846 case 0:
847 break;
848 case 0x4:
849 ck_dpll1.rate /= 2;
850 break;
851 default:
852 ck_dpll1.rate /= 4;
853 break;
854 }
855 }
856 }
857 propagate_rate(&ck_dpll1);
858 /* Cache rates for clocks connected to ck_ref (not dpll1) */
859 propagate_rate(&ck_ref);
860 omap1_show_rates();
861 if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
862 /* Select slicer output as OMAP input clock */
863 omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1,
864 OMAP7XX_PCC_UPLD_CTRL);
865 }
866
867 /* Amstrad Delta wants BCLK high when inactive */
868 if (machine_is_ams_delta())
869 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
870 (1 << SDW_MCLK_INV_BIT),
871 ULPD_CLOCK_CTRL);
872
873 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
874 /* (on 730, bit 13 must not be cleared) */
875 if (cpu_is_omap7xx())
876 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
877 else
878 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
879
880 /* Put DSP/MPUI into reset until needed */
881 omap_writew(0, ARM_RSTCT1);
882 omap_writew(1, ARM_RSTCT2);
883 omap_writew(0x400, ARM_IDLECT1);
884
885 /*
886 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
887 * of the ARM_IDLECT2 register must be set to zero. The power-on
888 * default value of this bit is one.
889 */
890 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
891
892 /*
893 * Only enable those clocks we will need, let the drivers
894 * enable other clocks as necessary
895 */
896 clk_enable(&armper_ck.clk);
897 clk_enable(&armxor_ck.clk);
898 clk_enable(&armtim_ck.clk); /* This should be done by timer code */
899
900 if (cpu_is_omap15xx())
901 clk_enable(&arm_gpio_ck);
902
903 return 0;
904}
905
906#define OMAP1_DPLL1_SANE_VALUE 60000000
907
908void __init omap1_clk_late_init(void)
909{
910 unsigned long rate = ck_dpll1.rate;
911
912 /* Find the highest supported frequency and enable it */
913 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
914 pr_err("System frequencies not set, using default. Check your config.\n");
915 /*
916 * Reprogramming the DPLL is tricky, it must be done from SRAM.
917 */
918 omap_sram_reprogram_clock(0x2290, 0x0005);
919 ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;
920 }
921 propagate_rate(&ck_dpll1);
922 omap1_show_rates();
923 loops_per_jiffy = cpufreq_scale(loops_per_jiffy, rate, ck_dpll1.rate);
924}
1/*
2 * linux/arch/arm/mach-omap1/clock_data.c
3 *
4 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * To do:
13 * - Clocks that are only available on some chips should be marked with the
14 * chips that they are present on.
15 */
16
17#include <linux/kernel.h>
18#include <linux/io.h>
19#include <linux/clk.h>
20#include <linux/cpufreq.h>
21#include <linux/delay.h>
22
23#include <asm/mach-types.h> /* for machine_is_* */
24
25#include <plat/clock.h>
26#include <plat/cpu.h>
27#include <plat/clkdev_omap.h>
28#include <plat/sram.h> /* for omap_sram_reprogram_clock() */
29#include <plat/usb.h> /* for OTG_BASE */
30
31#include <mach/hardware.h>
32
33#include "iomap.h"
34#include "clock.h"
35
36/* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
37#define IDL_CLKOUT_ARM_SHIFT 12
38#define IDLTIM_ARM_SHIFT 9
39#define IDLAPI_ARM_SHIFT 8
40#define IDLIF_ARM_SHIFT 6
41#define IDLLB_ARM_SHIFT 4 /* undocumented? */
42#define OMAP1510_IDLLCD_ARM_SHIFT 3 /* undocumented? */
43#define IDLPER_ARM_SHIFT 2
44#define IDLXORP_ARM_SHIFT 1
45#define IDLWDT_ARM_SHIFT 0
46
47/* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
48#define CONF_MOD_UART3_CLK_MODE_R 31
49#define CONF_MOD_UART2_CLK_MODE_R 30
50#define CONF_MOD_UART1_CLK_MODE_R 29
51#define CONF_MOD_MMC_SD_CLK_REQ_R 23
52#define CONF_MOD_MCBSP3_AUXON 20
53
54/* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
55#define CONF_MOD_SOSSI_CLK_EN_R 16
56
57/* Some OTG_SYSCON_2-specific bit fields */
58#define OTG_SYSCON_2_UHOST_EN_SHIFT 8
59
60/* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */
61#define SOFT_MMC2_DPLL_REQ_SHIFT 13
62#define SOFT_MMC_DPLL_REQ_SHIFT 12
63#define SOFT_UART3_DPLL_REQ_SHIFT 11
64#define SOFT_UART2_DPLL_REQ_SHIFT 10
65#define SOFT_UART1_DPLL_REQ_SHIFT 9
66#define SOFT_USB_OTG_DPLL_REQ_SHIFT 8
67#define SOFT_CAM_DPLL_REQ_SHIFT 7
68#define SOFT_COM_MCKO_REQ_SHIFT 6
69#define SOFT_PERIPH_REQ_SHIFT 5 /* sys_ck gate for UART2 ? */
70#define USB_REQ_EN_SHIFT 4
71#define SOFT_USB_REQ_SHIFT 3 /* sys_ck gate for USB host? */
72#define SOFT_SDW_REQ_SHIFT 2 /* sys_ck gate for Bluetooth? */
73#define SOFT_COM_REQ_SHIFT 1 /* sys_ck gate for com proc? */
74#define SOFT_DPLL_REQ_SHIFT 0
75
76/*
77 * Omap1 clocks
78 */
79
80static struct clk ck_ref = {
81 .name = "ck_ref",
82 .ops = &clkops_null,
83 .rate = 12000000,
84};
85
86static struct clk ck_dpll1 = {
87 .name = "ck_dpll1",
88 .ops = &clkops_null,
89 .parent = &ck_ref,
90};
91
92/*
93 * FIXME: This clock seems to be necessary but no-one has asked for its
94 * activation. [ FIX: SoSSI, SSR ]
95 */
96static struct arm_idlect1_clk ck_dpll1out = {
97 .clk = {
98 .name = "ck_dpll1out",
99 .ops = &clkops_generic,
100 .parent = &ck_dpll1,
101 .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
102 ENABLE_ON_INIT,
103 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
104 .enable_bit = EN_CKOUT_ARM,
105 .recalc = &followparent_recalc,
106 },
107 .idlect_shift = IDL_CLKOUT_ARM_SHIFT,
108};
109
110static struct clk sossi_ck = {
111 .name = "ck_sossi",
112 .ops = &clkops_generic,
113 .parent = &ck_dpll1out.clk,
114 .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
115 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
116 .enable_bit = CONF_MOD_SOSSI_CLK_EN_R,
117 .recalc = &omap1_sossi_recalc,
118 .set_rate = &omap1_set_sossi_rate,
119};
120
121static struct clk arm_ck = {
122 .name = "arm_ck",
123 .ops = &clkops_null,
124 .parent = &ck_dpll1,
125 .rate_offset = CKCTL_ARMDIV_OFFSET,
126 .recalc = &omap1_ckctl_recalc,
127 .round_rate = omap1_clk_round_rate_ckctl_arm,
128 .set_rate = omap1_clk_set_rate_ckctl_arm,
129};
130
131static struct arm_idlect1_clk armper_ck = {
132 .clk = {
133 .name = "armper_ck",
134 .ops = &clkops_generic,
135 .parent = &ck_dpll1,
136 .flags = CLOCK_IDLE_CONTROL,
137 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
138 .enable_bit = EN_PERCK,
139 .rate_offset = CKCTL_PERDIV_OFFSET,
140 .recalc = &omap1_ckctl_recalc,
141 .round_rate = omap1_clk_round_rate_ckctl_arm,
142 .set_rate = omap1_clk_set_rate_ckctl_arm,
143 },
144 .idlect_shift = IDLPER_ARM_SHIFT,
145};
146
147/*
148 * FIXME: This clock seems to be necessary but no-one has asked for its
149 * activation. [ GPIO code for 1510 ]
150 */
151static struct clk arm_gpio_ck = {
152 .name = "ick",
153 .ops = &clkops_generic,
154 .parent = &ck_dpll1,
155 .flags = ENABLE_ON_INIT,
156 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
157 .enable_bit = EN_GPIOCK,
158 .recalc = &followparent_recalc,
159};
160
161static struct arm_idlect1_clk armxor_ck = {
162 .clk = {
163 .name = "armxor_ck",
164 .ops = &clkops_generic,
165 .parent = &ck_ref,
166 .flags = CLOCK_IDLE_CONTROL,
167 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
168 .enable_bit = EN_XORPCK,
169 .recalc = &followparent_recalc,
170 },
171 .idlect_shift = IDLXORP_ARM_SHIFT,
172};
173
174static struct arm_idlect1_clk armtim_ck = {
175 .clk = {
176 .name = "armtim_ck",
177 .ops = &clkops_generic,
178 .parent = &ck_ref,
179 .flags = CLOCK_IDLE_CONTROL,
180 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
181 .enable_bit = EN_TIMCK,
182 .recalc = &followparent_recalc,
183 },
184 .idlect_shift = IDLTIM_ARM_SHIFT,
185};
186
187static struct arm_idlect1_clk armwdt_ck = {
188 .clk = {
189 .name = "armwdt_ck",
190 .ops = &clkops_generic,
191 .parent = &ck_ref,
192 .flags = CLOCK_IDLE_CONTROL,
193 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
194 .enable_bit = EN_WDTCK,
195 .fixed_div = 14,
196 .recalc = &omap_fixed_divisor_recalc,
197 },
198 .idlect_shift = IDLWDT_ARM_SHIFT,
199};
200
201static struct clk arminth_ck16xx = {
202 .name = "arminth_ck",
203 .ops = &clkops_null,
204 .parent = &arm_ck,
205 .recalc = &followparent_recalc,
206 /* Note: On 16xx the frequency can be divided by 2 by programming
207 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
208 *
209 * 1510 version is in TC clocks.
210 */
211};
212
213static struct clk dsp_ck = {
214 .name = "dsp_ck",
215 .ops = &clkops_generic,
216 .parent = &ck_dpll1,
217 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
218 .enable_bit = EN_DSPCK,
219 .rate_offset = CKCTL_DSPDIV_OFFSET,
220 .recalc = &omap1_ckctl_recalc,
221 .round_rate = omap1_clk_round_rate_ckctl_arm,
222 .set_rate = omap1_clk_set_rate_ckctl_arm,
223};
224
225static struct clk dspmmu_ck = {
226 .name = "dspmmu_ck",
227 .ops = &clkops_null,
228 .parent = &ck_dpll1,
229 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
230 .recalc = &omap1_ckctl_recalc,
231 .round_rate = omap1_clk_round_rate_ckctl_arm,
232 .set_rate = omap1_clk_set_rate_ckctl_arm,
233};
234
235static struct clk dspper_ck = {
236 .name = "dspper_ck",
237 .ops = &clkops_dspck,
238 .parent = &ck_dpll1,
239 .enable_reg = DSP_IDLECT2,
240 .enable_bit = EN_PERCK,
241 .rate_offset = CKCTL_PERDIV_OFFSET,
242 .recalc = &omap1_ckctl_recalc_dsp_domain,
243 .round_rate = omap1_clk_round_rate_ckctl_arm,
244 .set_rate = &omap1_clk_set_rate_dsp_domain,
245};
246
247static struct clk dspxor_ck = {
248 .name = "dspxor_ck",
249 .ops = &clkops_dspck,
250 .parent = &ck_ref,
251 .enable_reg = DSP_IDLECT2,
252 .enable_bit = EN_XORPCK,
253 .recalc = &followparent_recalc,
254};
255
256static struct clk dsptim_ck = {
257 .name = "dsptim_ck",
258 .ops = &clkops_dspck,
259 .parent = &ck_ref,
260 .enable_reg = DSP_IDLECT2,
261 .enable_bit = EN_DSPTIMCK,
262 .recalc = &followparent_recalc,
263};
264
265static struct arm_idlect1_clk tc_ck = {
266 .clk = {
267 .name = "tc_ck",
268 .ops = &clkops_null,
269 .parent = &ck_dpll1,
270 .flags = CLOCK_IDLE_CONTROL,
271 .rate_offset = CKCTL_TCDIV_OFFSET,
272 .recalc = &omap1_ckctl_recalc,
273 .round_rate = omap1_clk_round_rate_ckctl_arm,
274 .set_rate = omap1_clk_set_rate_ckctl_arm,
275 },
276 .idlect_shift = IDLIF_ARM_SHIFT,
277};
278
279static struct clk arminth_ck1510 = {
280 .name = "arminth_ck",
281 .ops = &clkops_null,
282 .parent = &tc_ck.clk,
283 .recalc = &followparent_recalc,
284 /* Note: On 1510 the frequency follows TC_CK
285 *
286 * 16xx version is in MPU clocks.
287 */
288};
289
290static struct clk tipb_ck = {
291 /* No-idle controlled by "tc_ck" */
292 .name = "tipb_ck",
293 .ops = &clkops_null,
294 .parent = &tc_ck.clk,
295 .recalc = &followparent_recalc,
296};
297
298static struct clk l3_ocpi_ck = {
299 /* No-idle controlled by "tc_ck" */
300 .name = "l3_ocpi_ck",
301 .ops = &clkops_generic,
302 .parent = &tc_ck.clk,
303 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
304 .enable_bit = EN_OCPI_CK,
305 .recalc = &followparent_recalc,
306};
307
308static struct clk tc1_ck = {
309 .name = "tc1_ck",
310 .ops = &clkops_generic,
311 .parent = &tc_ck.clk,
312 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
313 .enable_bit = EN_TC1_CK,
314 .recalc = &followparent_recalc,
315};
316
317/*
318 * FIXME: This clock seems to be necessary but no-one has asked for its
319 * activation. [ pm.c (SRAM), CCP, Camera ]
320 */
321static struct clk tc2_ck = {
322 .name = "tc2_ck",
323 .ops = &clkops_generic,
324 .parent = &tc_ck.clk,
325 .flags = ENABLE_ON_INIT,
326 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
327 .enable_bit = EN_TC2_CK,
328 .recalc = &followparent_recalc,
329};
330
331static struct clk dma_ck = {
332 /* No-idle controlled by "tc_ck" */
333 .name = "dma_ck",
334 .ops = &clkops_null,
335 .parent = &tc_ck.clk,
336 .recalc = &followparent_recalc,
337};
338
339static struct clk dma_lcdfree_ck = {
340 .name = "dma_lcdfree_ck",
341 .ops = &clkops_null,
342 .parent = &tc_ck.clk,
343 .recalc = &followparent_recalc,
344};
345
346static struct arm_idlect1_clk api_ck = {
347 .clk = {
348 .name = "api_ck",
349 .ops = &clkops_generic,
350 .parent = &tc_ck.clk,
351 .flags = CLOCK_IDLE_CONTROL,
352 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
353 .enable_bit = EN_APICK,
354 .recalc = &followparent_recalc,
355 },
356 .idlect_shift = IDLAPI_ARM_SHIFT,
357};
358
359static struct arm_idlect1_clk lb_ck = {
360 .clk = {
361 .name = "lb_ck",
362 .ops = &clkops_generic,
363 .parent = &tc_ck.clk,
364 .flags = CLOCK_IDLE_CONTROL,
365 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
366 .enable_bit = EN_LBCK,
367 .recalc = &followparent_recalc,
368 },
369 .idlect_shift = IDLLB_ARM_SHIFT,
370};
371
372static struct clk rhea1_ck = {
373 .name = "rhea1_ck",
374 .ops = &clkops_null,
375 .parent = &tc_ck.clk,
376 .recalc = &followparent_recalc,
377};
378
379static struct clk rhea2_ck = {
380 .name = "rhea2_ck",
381 .ops = &clkops_null,
382 .parent = &tc_ck.clk,
383 .recalc = &followparent_recalc,
384};
385
386static struct clk lcd_ck_16xx = {
387 .name = "lcd_ck",
388 .ops = &clkops_generic,
389 .parent = &ck_dpll1,
390 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
391 .enable_bit = EN_LCDCK,
392 .rate_offset = CKCTL_LCDDIV_OFFSET,
393 .recalc = &omap1_ckctl_recalc,
394 .round_rate = omap1_clk_round_rate_ckctl_arm,
395 .set_rate = omap1_clk_set_rate_ckctl_arm,
396};
397
398static struct arm_idlect1_clk lcd_ck_1510 = {
399 .clk = {
400 .name = "lcd_ck",
401 .ops = &clkops_generic,
402 .parent = &ck_dpll1,
403 .flags = CLOCK_IDLE_CONTROL,
404 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
405 .enable_bit = EN_LCDCK,
406 .rate_offset = CKCTL_LCDDIV_OFFSET,
407 .recalc = &omap1_ckctl_recalc,
408 .round_rate = omap1_clk_round_rate_ckctl_arm,
409 .set_rate = omap1_clk_set_rate_ckctl_arm,
410 },
411 .idlect_shift = OMAP1510_IDLLCD_ARM_SHIFT,
412};
413
414/*
415 * XXX The enable_bit here is misused - it simply switches between 12MHz
416 * and 48MHz. Reimplement with clksel.
417 *
418 * XXX does this need SYSC register handling?
419 */
420static struct clk uart1_1510 = {
421 .name = "uart1_ck",
422 .ops = &clkops_null,
423 /* Direct from ULPD, no real parent */
424 .parent = &armper_ck.clk,
425 .rate = 12000000,
426 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
427 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
428 .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
429 .set_rate = &omap1_set_uart_rate,
430 .recalc = &omap1_uart_recalc,
431};
432
433/*
434 * XXX The enable_bit here is misused - it simply switches between 12MHz
435 * and 48MHz. Reimplement with clksel.
436 *
437 * XXX SYSC register handling does not belong in the clock framework
438 */
439static struct uart_clk uart1_16xx = {
440 .clk = {
441 .name = "uart1_ck",
442 .ops = &clkops_uart_16xx,
443 /* Direct from ULPD, no real parent */
444 .parent = &armper_ck.clk,
445 .rate = 48000000,
446 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
447 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
448 .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
449 },
450 .sysc_addr = 0xfffb0054,
451};
452
453/*
454 * XXX The enable_bit here is misused - it simply switches between 12MHz
455 * and 48MHz. Reimplement with clksel.
456 *
457 * XXX does this need SYSC register handling?
458 */
459static struct clk uart2_ck = {
460 .name = "uart2_ck",
461 .ops = &clkops_null,
462 /* Direct from ULPD, no real parent */
463 .parent = &armper_ck.clk,
464 .rate = 12000000,
465 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
466 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
467 .enable_bit = CONF_MOD_UART2_CLK_MODE_R,
468 .set_rate = &omap1_set_uart_rate,
469 .recalc = &omap1_uart_recalc,
470};
471
472/*
473 * XXX The enable_bit here is misused - it simply switches between 12MHz
474 * and 48MHz. Reimplement with clksel.
475 *
476 * XXX does this need SYSC register handling?
477 */
478static struct clk uart3_1510 = {
479 .name = "uart3_ck",
480 .ops = &clkops_null,
481 /* Direct from ULPD, no real parent */
482 .parent = &armper_ck.clk,
483 .rate = 12000000,
484 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
485 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
486 .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
487 .set_rate = &omap1_set_uart_rate,
488 .recalc = &omap1_uart_recalc,
489};
490
491/*
492 * XXX The enable_bit here is misused - it simply switches between 12MHz
493 * and 48MHz. Reimplement with clksel.
494 *
495 * XXX SYSC register handling does not belong in the clock framework
496 */
497static struct uart_clk uart3_16xx = {
498 .clk = {
499 .name = "uart3_ck",
500 .ops = &clkops_uart_16xx,
501 /* Direct from ULPD, no real parent */
502 .parent = &armper_ck.clk,
503 .rate = 48000000,
504 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
505 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
506 .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
507 },
508 .sysc_addr = 0xfffb9854,
509};
510
511static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
512 .name = "usb_clko",
513 .ops = &clkops_generic,
514 /* Direct from ULPD, no parent */
515 .rate = 6000000,
516 .flags = ENABLE_REG_32BIT,
517 .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
518 .enable_bit = USB_MCLK_EN_BIT,
519};
520
521static struct clk usb_hhc_ck1510 = {
522 .name = "usb_hhc_ck",
523 .ops = &clkops_generic,
524 /* Direct from ULPD, no parent */
525 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
526 .flags = ENABLE_REG_32BIT,
527 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
528 .enable_bit = USB_HOST_HHC_UHOST_EN,
529};
530
531static struct clk usb_hhc_ck16xx = {
532 .name = "usb_hhc_ck",
533 .ops = &clkops_generic,
534 /* Direct from ULPD, no parent */
535 .rate = 48000000,
536 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
537 .flags = ENABLE_REG_32BIT,
538 .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
539 .enable_bit = OTG_SYSCON_2_UHOST_EN_SHIFT
540};
541
542static struct clk usb_dc_ck = {
543 .name = "usb_dc_ck",
544 .ops = &clkops_generic,
545 /* Direct from ULPD, no parent */
546 .rate = 48000000,
547 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
548 .enable_bit = USB_REQ_EN_SHIFT,
549};
550
551static struct clk usb_dc_ck7xx = {
552 .name = "usb_dc_ck",
553 .ops = &clkops_generic,
554 /* Direct from ULPD, no parent */
555 .rate = 48000000,
556 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
557 .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT,
558};
559
560static struct clk uart1_7xx = {
561 .name = "uart1_ck",
562 .ops = &clkops_generic,
563 /* Direct from ULPD, no parent */
564 .rate = 12000000,
565 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
566 .enable_bit = 9,
567};
568
569static struct clk uart2_7xx = {
570 .name = "uart2_ck",
571 .ops = &clkops_generic,
572 /* Direct from ULPD, no parent */
573 .rate = 12000000,
574 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
575 .enable_bit = 11,
576};
577
578static struct clk mclk_1510 = {
579 .name = "mclk",
580 .ops = &clkops_generic,
581 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
582 .rate = 12000000,
583 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
584 .enable_bit = SOFT_COM_MCKO_REQ_SHIFT,
585};
586
587static struct clk mclk_16xx = {
588 .name = "mclk",
589 .ops = &clkops_generic,
590 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
591 .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
592 .enable_bit = COM_ULPD_PLL_CLK_REQ,
593 .set_rate = &omap1_set_ext_clk_rate,
594 .round_rate = &omap1_round_ext_clk_rate,
595 .init = &omap1_init_ext_clk,
596};
597
598static struct clk bclk_1510 = {
599 .name = "bclk",
600 .ops = &clkops_generic,
601 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
602 .rate = 12000000,
603};
604
605static struct clk bclk_16xx = {
606 .name = "bclk",
607 .ops = &clkops_generic,
608 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
609 .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
610 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
611 .set_rate = &omap1_set_ext_clk_rate,
612 .round_rate = &omap1_round_ext_clk_rate,
613 .init = &omap1_init_ext_clk,
614};
615
616static struct clk mmc1_ck = {
617 .name = "mmc1_ck",
618 .ops = &clkops_generic,
619 /* Functional clock is direct from ULPD, interface clock is ARMPER */
620 .parent = &armper_ck.clk,
621 .rate = 48000000,
622 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
623 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
624 .enable_bit = CONF_MOD_MMC_SD_CLK_REQ_R,
625};
626
627/*
628 * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as
629 * CONF_MOD_MCBSP3_AUXON ??
630 */
631static struct clk mmc2_ck = {
632 .name = "mmc2_ck",
633 .ops = &clkops_generic,
634 /* Functional clock is direct from ULPD, interface clock is ARMPER */
635 .parent = &armper_ck.clk,
636 .rate = 48000000,
637 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
638 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
639 .enable_bit = 20,
640};
641
642static struct clk mmc3_ck = {
643 .name = "mmc3_ck",
644 .ops = &clkops_generic,
645 /* Functional clock is direct from ULPD, interface clock is ARMPER */
646 .parent = &armper_ck.clk,
647 .rate = 48000000,
648 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
649 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
650 .enable_bit = SOFT_MMC_DPLL_REQ_SHIFT,
651};
652
653static struct clk virtual_ck_mpu = {
654 .name = "mpu",
655 .ops = &clkops_null,
656 .parent = &arm_ck, /* Is smarter alias for */
657 .recalc = &followparent_recalc,
658 .set_rate = &omap1_select_table_rate,
659 .round_rate = &omap1_round_to_table_rate,
660};
661
662/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
663remains active during MPU idle whenever this is enabled */
664static struct clk i2c_fck = {
665 .name = "i2c_fck",
666 .ops = &clkops_null,
667 .flags = CLOCK_NO_IDLE_PARENT,
668 .parent = &armxor_ck.clk,
669 .recalc = &followparent_recalc,
670};
671
672static struct clk i2c_ick = {
673 .name = "i2c_ick",
674 .ops = &clkops_null,
675 .flags = CLOCK_NO_IDLE_PARENT,
676 .parent = &armper_ck.clk,
677 .recalc = &followparent_recalc,
678};
679
680/*
681 * clkdev integration
682 */
683
684static struct omap_clk omap_clks[] = {
685 /* non-ULPD clocks */
686 CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX),
687 CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310 | CK_7XX),
688 /* CK_GEN1 clocks */
689 CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
690 CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX),
691 CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310),
692 CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
693 CLK("omap_gpio.0", "ick", &arm_gpio_ck, CK_1510 | CK_310),
694 CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
695 CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
696 CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
697 CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX),
698 CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310),
699 CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310),
700 CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX),
701 /* CK_GEN2 clocks */
702 CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310),
703 CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310),
704 CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310),
705 CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
706 CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310),
707 /* CK_GEN3 clocks */
708 CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
709 CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310),
710 CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX),
711 CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX),
712 CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX),
713 CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310),
714 CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
715 CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
716 CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310),
717 CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX),
718 CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX),
719 CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX),
720 CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310),
721 /* ULPD clocks */
722 CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310),
723 CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX),
724 CLK(NULL, "uart1_ck", &uart1_7xx, CK_7XX),
725 CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310),
726 CLK(NULL, "uart2_ck", &uart2_7xx, CK_7XX),
727 CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310),
728 CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX),
729 CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310),
730 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310),
731 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX),
732 CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX),
733 CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX),
734 CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310),
735 CLK(NULL, "mclk", &mclk_16xx, CK_16XX),
736 CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310),
737 CLK(NULL, "bclk", &bclk_16xx, CK_16XX),
738 CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310),
739 CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX),
740 CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
741 CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX),
742 CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX),
743 /* Virtual clocks */
744 CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
745 CLK("omap_i2c.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX),
746 CLK("omap_i2c.1", "ick", &i2c_ick, CK_16XX),
747 CLK("omap_i2c.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX),
748 CLK("omap1_spi100k.1", "fck", &dummy_ck, CK_7XX),
749 CLK("omap1_spi100k.1", "ick", &dummy_ck, CK_7XX),
750 CLK("omap1_spi100k.2", "fck", &dummy_ck, CK_7XX),
751 CLK("omap1_spi100k.2", "ick", &dummy_ck, CK_7XX),
752 CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
753 CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX),
754 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310),
755 CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX),
756 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310),
757 CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX),
758 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310),
759 CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
760 CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
761 CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
762};
763
764/*
765 * init
766 */
767
768static struct clk_functions omap1_clk_functions = {
769 .clk_enable = omap1_clk_enable,
770 .clk_disable = omap1_clk_disable,
771 .clk_round_rate = omap1_clk_round_rate,
772 .clk_set_rate = omap1_clk_set_rate,
773 .clk_disable_unused = omap1_clk_disable_unused,
774};
775
776static void __init omap1_show_rates(void)
777{
778 pr_notice("Clocking rate (xtal/DPLL1/MPU): "
779 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
780 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
781 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
782 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
783}
784
785u32 cpu_mask;
786
787int __init omap1_clk_init(void)
788{
789 struct omap_clk *c;
790 const struct omap_clock_config *info;
791 int crystal_type = 0; /* Default 12 MHz */
792 u32 reg;
793
794#ifdef CONFIG_DEBUG_LL
795 /*
796 * Resets some clocks that may be left on from bootloader,
797 * but leaves serial clocks on.
798 */
799 omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
800#endif
801
802 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
803 reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
804 omap_writew(reg, SOFT_REQ_REG);
805 if (!cpu_is_omap15xx())
806 omap_writew(0, SOFT_REQ_REG2);
807
808 clk_init(&omap1_clk_functions);
809
810 /* By default all idlect1 clocks are allowed to idle */
811 arm_idlect1_mask = ~0;
812
813 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
814 clk_preinit(c->lk.clk);
815
816 cpu_mask = 0;
817 if (cpu_is_omap1710())
818 cpu_mask |= CK_1710;
819 if (cpu_is_omap16xx())
820 cpu_mask |= CK_16XX;
821 if (cpu_is_omap1510())
822 cpu_mask |= CK_1510;
823 if (cpu_is_omap7xx())
824 cpu_mask |= CK_7XX;
825 if (cpu_is_omap310())
826 cpu_mask |= CK_310;
827
828 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
829 if (c->cpu & cpu_mask) {
830 clkdev_add(&c->lk);
831 clk_register(c->lk.clk);
832 }
833
834 /* Pointers to these clocks are needed by code in clock.c */
835 api_ck_p = clk_get(NULL, "api_ck");
836 ck_dpll1_p = clk_get(NULL, "ck_dpll1");
837 ck_ref_p = clk_get(NULL, "ck_ref");
838
839 info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
840 if (info != NULL) {
841 if (!cpu_is_omap15xx())
842 crystal_type = info->system_clock_type;
843 }
844
845 if (cpu_is_omap7xx())
846 ck_ref.rate = 13000000;
847 if (cpu_is_omap16xx() && crystal_type == 2)
848 ck_ref.rate = 19200000;
849
850 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
851 "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
852 omap_readw(ARM_CKCTL));
853
854 /* We want to be in syncronous scalable mode */
855 omap_writew(0x1000, ARM_SYSST);
856
857
858 /*
859 * Initially use the values set by bootloader. Determine PLL rate and
860 * recalculate dependent clocks as if kernel had changed PLL or
861 * divisors. See also omap1_clk_late_init() that can reprogram dpll1
862 * after the SRAM is initialized.
863 */
864 {
865 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
866
867 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
868 if (pll_ctl_val & 0x10) {
869 /* PLL enabled, apply multiplier and divisor */
870 if (pll_ctl_val & 0xf80)
871 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
872 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
873 } else {
874 /* PLL disabled, apply bypass divisor */
875 switch (pll_ctl_val & 0xc) {
876 case 0:
877 break;
878 case 0x4:
879 ck_dpll1.rate /= 2;
880 break;
881 default:
882 ck_dpll1.rate /= 4;
883 break;
884 }
885 }
886 }
887 propagate_rate(&ck_dpll1);
888 /* Cache rates for clocks connected to ck_ref (not dpll1) */
889 propagate_rate(&ck_ref);
890 omap1_show_rates();
891 if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
892 /* Select slicer output as OMAP input clock */
893 omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1,
894 OMAP7XX_PCC_UPLD_CTRL);
895 }
896
897 /* Amstrad Delta wants BCLK high when inactive */
898 if (machine_is_ams_delta())
899 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
900 (1 << SDW_MCLK_INV_BIT),
901 ULPD_CLOCK_CTRL);
902
903 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
904 /* (on 730, bit 13 must not be cleared) */
905 if (cpu_is_omap7xx())
906 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
907 else
908 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
909
910 /* Put DSP/MPUI into reset until needed */
911 omap_writew(0, ARM_RSTCT1);
912 omap_writew(1, ARM_RSTCT2);
913 omap_writew(0x400, ARM_IDLECT1);
914
915 /*
916 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
917 * of the ARM_IDLECT2 register must be set to zero. The power-on
918 * default value of this bit is one.
919 */
920 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
921
922 /*
923 * Only enable those clocks we will need, let the drivers
924 * enable other clocks as necessary
925 */
926 clk_enable(&armper_ck.clk);
927 clk_enable(&armxor_ck.clk);
928 clk_enable(&armtim_ck.clk); /* This should be done by timer code */
929
930 if (cpu_is_omap15xx())
931 clk_enable(&arm_gpio_ck);
932
933 return 0;
934}
935
936#define OMAP1_DPLL1_SANE_VALUE 60000000
937
938void __init omap1_clk_late_init(void)
939{
940 unsigned long rate = ck_dpll1.rate;
941
942 /* Find the highest supported frequency and enable it */
943 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
944 pr_err("System frequencies not set, using default. Check your config.\n");
945 /*
946 * Reprogramming the DPLL is tricky, it must be done from SRAM.
947 */
948 omap_sram_reprogram_clock(0x2290, 0x0005);
949 ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;
950 }
951 propagate_rate(&ck_dpll1);
952 omap1_show_rates();
953 loops_per_jiffy = cpufreq_scale(loops_per_jiffy, rate, ck_dpll1.rate);
954}