1/*
 2 *  linux/arch/arm/kernel/smp_scu.c
 3 *
 4 *  Copyright (C) 2002 ARM Ltd.
 5 *  All Rights Reserved
 6 *
 7 * This program is free software; you can redistribute it and/or modify
 8 * it under the terms of the GNU General Public License version 2 as
 9 * published by the Free Software Foundation.
10 */
11#include <linux/init.h>
12#include <linux/io.h>
13
14#include <asm/smp_plat.h>
15#include <asm/smp_scu.h>
16#include <asm/cacheflush.h>
17#include <asm/cputype.h>
18
19#define SCU_CTRL		0x00
20#define SCU_CONFIG		0x04
21#define SCU_CPU_STATUS		0x08
22#define SCU_INVALIDATE		0x0c
23#define SCU_FPGA_REVISION	0x10
24
25#ifdef CONFIG_SMP
26/*
27 * Get the number of CPU cores from the SCU configuration
28 */
29unsigned int __init scu_get_core_count(void __iomem *scu_base)
30{
31	unsigned int ncores = readl_relaxed(scu_base + SCU_CONFIG);
32	return (ncores & 0x03) + 1;
33}
34
35/*
36 * Enable the SCU
37 */
38void scu_enable(void __iomem *scu_base)
39{
40	u32 scu_ctrl;
41
42#ifdef CONFIG_ARM_ERRATA_764369
43	/* Cortex-A9 only */
44	if ((read_cpuid_id() & 0xff0ffff0) == 0x410fc090) {
45		scu_ctrl = readl_relaxed(scu_base + 0x30);
46		if (!(scu_ctrl & 1))
47			writel_relaxed(scu_ctrl | 0x1, scu_base + 0x30);
48	}
49#endif
50
51	scu_ctrl = readl_relaxed(scu_base + SCU_CTRL);
52	/* already enabled? */
53	if (scu_ctrl & 1)
54		return;
55
56	scu_ctrl |= 1;
57	writel_relaxed(scu_ctrl, scu_base + SCU_CTRL);
58
59	/*
60	 * Ensure that the data accessed by CPU0 before the SCU was
61	 * initialised is visible to the other CPUs.
62	 */
63	flush_cache_all();
64}
65#endif
66
67/*
68 * Set the executing CPUs power mode as defined.  This will be in
69 * preparation for it executing a WFI instruction.
70 *
71 * This function must be called with preemption disabled, and as it
72 * has the side effect of disabling coherency, caches must have been
73 * flushed.  Interrupts must also have been disabled.
74 */
75int scu_power_mode(void __iomem *scu_base, unsigned int mode)
76{
77	unsigned int val;
78	int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
79
80	if (mode > 3 || mode == 1 || cpu > 3)
81		return -EINVAL;
82
83	val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;
84	val |= mode;
85	writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu);
86
87	return 0;
88}

 1/*
 2 *  linux/arch/arm/kernel/smp_scu.c
 3 *
 4 *  Copyright (C) 2002 ARM Ltd.
 5 *  All Rights Reserved
 6 *
 7 * This program is free software; you can redistribute it and/or modify
 8 * it under the terms of the GNU General Public License version 2 as
 9 * published by the Free Software Foundation.
10 */
11#include <linux/init.h>
12#include <linux/io.h>
13
14#include <asm/smp_plat.h>
15#include <asm/smp_scu.h>
16#include <asm/cacheflush.h>
17#include <asm/cputype.h>
18
19#define SCU_CTRL		0x00
20#define SCU_CONFIG		0x04
21#define SCU_CPU_STATUS		0x08
22#define SCU_INVALIDATE		0x0c
23#define SCU_FPGA_REVISION	0x10
24
25#ifdef CONFIG_SMP
26/*
27 * Get the number of CPU cores from the SCU configuration
28 */
29unsigned int __init scu_get_core_count(void __iomem *scu_base)
30{
31	unsigned int ncores = __raw_readl(scu_base + SCU_CONFIG);
32	return (ncores & 0x03) + 1;
33}
34
35/*
36 * Enable the SCU
37 */
38void scu_enable(void __iomem *scu_base)
39{
40	u32 scu_ctrl;
41
42#ifdef CONFIG_ARM_ERRATA_764369
43	/* Cortex-A9 only */
44	if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {
45		scu_ctrl = __raw_readl(scu_base + 0x30);
46		if (!(scu_ctrl & 1))
47			__raw_writel(scu_ctrl | 0x1, scu_base + 0x30);
48	}
49#endif
50
51	scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
52	/* already enabled? */
53	if (scu_ctrl & 1)
54		return;
55
56	scu_ctrl |= 1;
57	__raw_writel(scu_ctrl, scu_base + SCU_CTRL);
58
59	/*
60	 * Ensure that the data accessed by CPU0 before the SCU was
61	 * initialised is visible to the other CPUs.
62	 */
63	flush_cache_all();
64}
65#endif
66
67/*
68 * Set the executing CPUs power mode as defined.  This will be in
69 * preparation for it executing a WFI instruction.
70 *
71 * This function must be called with preemption disabled, and as it
72 * has the side effect of disabling coherency, caches must have been
73 * flushed.  Interrupts must also have been disabled.
74 */
75int scu_power_mode(void __iomem *scu_base, unsigned int mode)
76{
77	unsigned int val;
78	int cpu = cpu_logical_map(smp_processor_id());
79
80	if (mode > 3 || mode == 1 || cpu > 3)
81		return -EINVAL;
82
83	val = __raw_readb(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;
84	val |= mode;
85	__raw_writeb(val, scu_base + SCU_CPU_STATUS + cpu);
86
87	return 0;
88}