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1#ifndef __KVM_X86_LAPIC_H
2#define __KVM_X86_LAPIC_H
3
4#include "iodev.h"
5
6#include <linux/kvm_host.h>
7
8#define KVM_APIC_INIT 0
9#define KVM_APIC_SIPI 1
10
11struct kvm_timer {
12 struct hrtimer timer;
13 s64 period; /* unit: ns */
14 u32 timer_mode_mask;
15 u64 tscdeadline;
16 atomic_t pending; /* accumulated triggered timers */
17};
18
19struct kvm_lapic {
20 unsigned long base_address;
21 struct kvm_io_device dev;
22 struct kvm_timer lapic_timer;
23 u32 divide_count;
24 struct kvm_vcpu *vcpu;
25 bool irr_pending;
26 /* Number of bits set in ISR. */
27 s16 isr_count;
28 /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
29 int highest_isr_cache;
30 /**
31 * APIC register page. The layout matches the register layout seen by
32 * the guest 1:1, because it is accessed by the vmx microcode.
33 * Note: Only one register, the TPR, is used by the microcode.
34 */
35 void *regs;
36 gpa_t vapic_addr;
37 struct gfn_to_hva_cache vapic_cache;
38 unsigned long pending_events;
39 unsigned int sipi_vector;
40};
41int kvm_create_lapic(struct kvm_vcpu *vcpu);
42void kvm_free_lapic(struct kvm_vcpu *vcpu);
43
44int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
45int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
46int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
47void kvm_apic_accept_events(struct kvm_vcpu *vcpu);
48void kvm_lapic_reset(struct kvm_vcpu *vcpu);
49u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
50void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
51void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
52void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
53u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
54void kvm_apic_set_version(struct kvm_vcpu *vcpu);
55
56void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr);
57void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir);
58int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest);
59int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda);
60int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
61 unsigned long *dest_map);
62int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
63
64bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
65 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map);
66
67u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
68int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
69void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
70 struct kvm_lapic_state *s);
71int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
72
73u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
74void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
75
76void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
77void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
78
79int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
80void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
81void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
82
83int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
84int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
85
86int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
87int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
88
89static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
90{
91 return vcpu->arch.hv_vapic & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE;
92}
93
94int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data);
95void kvm_lapic_init(void);
96
97static inline u32 kvm_apic_get_reg(struct kvm_lapic *apic, int reg_off)
98{
99 return *((u32 *) (apic->regs + reg_off));
100}
101
102extern struct static_key kvm_no_apic_vcpu;
103
104static inline bool kvm_vcpu_has_lapic(struct kvm_vcpu *vcpu)
105{
106 if (static_key_false(&kvm_no_apic_vcpu))
107 return vcpu->arch.apic;
108 return true;
109}
110
111extern struct static_key_deferred apic_hw_disabled;
112
113static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic)
114{
115 if (static_key_false(&apic_hw_disabled.key))
116 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
117 return MSR_IA32_APICBASE_ENABLE;
118}
119
120extern struct static_key_deferred apic_sw_disabled;
121
122static inline int kvm_apic_sw_enabled(struct kvm_lapic *apic)
123{
124 if (static_key_false(&apic_sw_disabled.key))
125 return kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
126 return APIC_SPIV_APIC_ENABLED;
127}
128
129static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
130{
131 return kvm_vcpu_has_lapic(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
132}
133
134static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
135{
136 return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
137}
138
139static inline int apic_x2apic_mode(struct kvm_lapic *apic)
140{
141 return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
142}
143
144static inline bool kvm_apic_vid_enabled(struct kvm *kvm)
145{
146 return kvm_x86_ops->vm_has_apicv(kvm);
147}
148
149static inline u16 apic_cluster_id(struct kvm_apic_map *map, u32 ldr)
150{
151 u16 cid;
152 ldr >>= 32 - map->ldr_bits;
153 cid = (ldr >> map->cid_shift) & map->cid_mask;
154
155 BUG_ON(cid >= ARRAY_SIZE(map->logical_map));
156
157 return cid;
158}
159
160static inline u16 apic_logical_id(struct kvm_apic_map *map, u32 ldr)
161{
162 ldr >>= (32 - map->ldr_bits);
163 return ldr & map->lid_mask;
164}
165
166static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu)
167{
168 return vcpu->arch.apic->pending_events;
169}
170
171bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);
172
173#endif
1#ifndef __KVM_X86_LAPIC_H
2#define __KVM_X86_LAPIC_H
3
4#include "iodev.h"
5#include "kvm_timer.h"
6
7#include <linux/kvm_host.h>
8
9struct kvm_lapic {
10 unsigned long base_address;
11 struct kvm_io_device dev;
12 struct kvm_timer lapic_timer;
13 u32 divide_count;
14 struct kvm_vcpu *vcpu;
15 bool irr_pending;
16 void *regs;
17 gpa_t vapic_addr;
18 struct page *vapic_page;
19};
20int kvm_create_lapic(struct kvm_vcpu *vcpu);
21void kvm_free_lapic(struct kvm_vcpu *vcpu);
22
23int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
24int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
25int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
26void kvm_lapic_reset(struct kvm_vcpu *vcpu);
27u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
28void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
29void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
30u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
31void kvm_apic_set_version(struct kvm_vcpu *vcpu);
32
33int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest);
34int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda);
35int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq);
36
37u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
38void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data);
39void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu);
40int kvm_lapic_enabled(struct kvm_vcpu *vcpu);
41bool kvm_apic_present(struct kvm_vcpu *vcpu);
42int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
43
44void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
45void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
46void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
47
48int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
49int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
50
51int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
52int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
53
54static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
55{
56 return vcpu->arch.hv_vapic & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE;
57}
58#endif