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1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23/*
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
29 *
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
41 *
42 * Cycle bit rules:
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
47 *
48 * Producer rules:
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
52 * cycle state).
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
56 *
57 * Consumer rules:
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
65 */
66
67#include <linux/scatterlist.h>
68#include <linux/slab.h>
69#include "xhci.h"
70
71static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
72 struct xhci_virt_device *virt_dev,
73 struct xhci_event_cmd *event);
74
75/*
76 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
77 * address of the TRB.
78 */
79dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
80 union xhci_trb *trb)
81{
82 unsigned long segment_offset;
83
84 if (!seg || !trb || trb < seg->trbs)
85 return 0;
86 /* offset in TRBs */
87 segment_offset = trb - seg->trbs;
88 if (segment_offset > TRBS_PER_SEGMENT)
89 return 0;
90 return seg->dma + (segment_offset * sizeof(*trb));
91}
92
93/* Does this link TRB point to the first segment in a ring,
94 * or was the previous TRB the last TRB on the last segment in the ERST?
95 */
96static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
97 struct xhci_segment *seg, union xhci_trb *trb)
98{
99 if (ring == xhci->event_ring)
100 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
101 (seg->next == xhci->event_ring->first_seg);
102 else
103 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
104}
105
106/* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
107 * segment? I.e. would the updated event TRB pointer step off the end of the
108 * event seg?
109 */
110static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
111 struct xhci_segment *seg, union xhci_trb *trb)
112{
113 if (ring == xhci->event_ring)
114 return trb == &seg->trbs[TRBS_PER_SEGMENT];
115 else
116 return TRB_TYPE_LINK_LE32(trb->link.control);
117}
118
119static int enqueue_is_link_trb(struct xhci_ring *ring)
120{
121 struct xhci_link_trb *link = &ring->enqueue->link;
122 return TRB_TYPE_LINK_LE32(link->control);
123}
124
125/* Updates trb to point to the next TRB in the ring, and updates seg if the next
126 * TRB is in a new segment. This does not skip over link TRBs, and it does not
127 * effect the ring dequeue or enqueue pointers.
128 */
129static void next_trb(struct xhci_hcd *xhci,
130 struct xhci_ring *ring,
131 struct xhci_segment **seg,
132 union xhci_trb **trb)
133{
134 if (last_trb(xhci, ring, *seg, *trb)) {
135 *seg = (*seg)->next;
136 *trb = ((*seg)->trbs);
137 } else {
138 (*trb)++;
139 }
140}
141
142/*
143 * See Cycle bit rules. SW is the consumer for the event ring only.
144 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
145 */
146static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
147{
148 union xhci_trb *next = ++(ring->dequeue);
149 unsigned long long addr;
150
151 ring->deq_updates++;
152 /* Update the dequeue pointer further if that was a link TRB or we're at
153 * the end of an event ring segment (which doesn't have link TRBS)
154 */
155 while (last_trb(xhci, ring, ring->deq_seg, next)) {
156 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
157 ring->cycle_state = (ring->cycle_state ? 0 : 1);
158 if (!in_interrupt())
159 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
160 ring,
161 (unsigned int) ring->cycle_state);
162 }
163 ring->deq_seg = ring->deq_seg->next;
164 ring->dequeue = ring->deq_seg->trbs;
165 next = ring->dequeue;
166 }
167 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
168}
169
170/*
171 * See Cycle bit rules. SW is the consumer for the event ring only.
172 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
173 *
174 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
175 * chain bit is set), then set the chain bit in all the following link TRBs.
176 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
177 * have their chain bit cleared (so that each Link TRB is a separate TD).
178 *
179 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
180 * set, but other sections talk about dealing with the chain bit set. This was
181 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
182 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
183 *
184 * @more_trbs_coming: Will you enqueue more TRBs before calling
185 * prepare_transfer()?
186 */
187static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
188 bool consumer, bool more_trbs_coming)
189{
190 u32 chain;
191 union xhci_trb *next;
192 unsigned long long addr;
193
194 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
195 next = ++(ring->enqueue);
196
197 ring->enq_updates++;
198 /* Update the dequeue pointer further if that was a link TRB or we're at
199 * the end of an event ring segment (which doesn't have link TRBS)
200 */
201 while (last_trb(xhci, ring, ring->enq_seg, next)) {
202 if (!consumer) {
203 if (ring != xhci->event_ring) {
204 /*
205 * If the caller doesn't plan on enqueueing more
206 * TDs before ringing the doorbell, then we
207 * don't want to give the link TRB to the
208 * hardware just yet. We'll give the link TRB
209 * back in prepare_ring() just before we enqueue
210 * the TD at the top of the ring.
211 */
212 if (!chain && !more_trbs_coming)
213 break;
214
215 /* If we're not dealing with 0.95 hardware,
216 * carry over the chain bit of the previous TRB
217 * (which may mean the chain bit is cleared).
218 */
219 if (!xhci_link_trb_quirk(xhci)) {
220 next->link.control &=
221 cpu_to_le32(~TRB_CHAIN);
222 next->link.control |=
223 cpu_to_le32(chain);
224 }
225 /* Give this link TRB to the hardware */
226 wmb();
227 next->link.control ^= cpu_to_le32(TRB_CYCLE);
228 }
229 /* Toggle the cycle bit after the last ring segment. */
230 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
231 ring->cycle_state = (ring->cycle_state ? 0 : 1);
232 if (!in_interrupt())
233 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
234 ring,
235 (unsigned int) ring->cycle_state);
236 }
237 }
238 ring->enq_seg = ring->enq_seg->next;
239 ring->enqueue = ring->enq_seg->trbs;
240 next = ring->enqueue;
241 }
242 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
243}
244
245/*
246 * Check to see if there's room to enqueue num_trbs on the ring. See rules
247 * above.
248 * FIXME: this would be simpler and faster if we just kept track of the number
249 * of free TRBs in a ring.
250 */
251static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
252 unsigned int num_trbs)
253{
254 int i;
255 union xhci_trb *enq = ring->enqueue;
256 struct xhci_segment *enq_seg = ring->enq_seg;
257 struct xhci_segment *cur_seg;
258 unsigned int left_on_ring;
259
260 /* If we are currently pointing to a link TRB, advance the
261 * enqueue pointer before checking for space */
262 while (last_trb(xhci, ring, enq_seg, enq)) {
263 enq_seg = enq_seg->next;
264 enq = enq_seg->trbs;
265 }
266
267 /* Check if ring is empty */
268 if (enq == ring->dequeue) {
269 /* Can't use link trbs */
270 left_on_ring = TRBS_PER_SEGMENT - 1;
271 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
272 cur_seg = cur_seg->next)
273 left_on_ring += TRBS_PER_SEGMENT - 1;
274
275 /* Always need one TRB free in the ring. */
276 left_on_ring -= 1;
277 if (num_trbs > left_on_ring) {
278 xhci_warn(xhci, "Not enough room on ring; "
279 "need %u TRBs, %u TRBs left\n",
280 num_trbs, left_on_ring);
281 return 0;
282 }
283 return 1;
284 }
285 /* Make sure there's an extra empty TRB available */
286 for (i = 0; i <= num_trbs; ++i) {
287 if (enq == ring->dequeue)
288 return 0;
289 enq++;
290 while (last_trb(xhci, ring, enq_seg, enq)) {
291 enq_seg = enq_seg->next;
292 enq = enq_seg->trbs;
293 }
294 }
295 return 1;
296}
297
298/* Ring the host controller doorbell after placing a command on the ring */
299void xhci_ring_cmd_db(struct xhci_hcd *xhci)
300{
301 xhci_dbg(xhci, "// Ding dong!\n");
302 xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
303 /* Flush PCI posted writes */
304 xhci_readl(xhci, &xhci->dba->doorbell[0]);
305}
306
307void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
308 unsigned int slot_id,
309 unsigned int ep_index,
310 unsigned int stream_id)
311{
312 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
313 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
314 unsigned int ep_state = ep->ep_state;
315
316 /* Don't ring the doorbell for this endpoint if there are pending
317 * cancellations because we don't want to interrupt processing.
318 * We don't want to restart any stream rings if there's a set dequeue
319 * pointer command pending because the device can choose to start any
320 * stream once the endpoint is on the HW schedule.
321 * FIXME - check all the stream rings for pending cancellations.
322 */
323 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
324 (ep_state & EP_HALTED))
325 return;
326 xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
327 /* The CPU has better things to do at this point than wait for a
328 * write-posting flush. It'll get there soon enough.
329 */
330}
331
332/* Ring the doorbell for any rings with pending URBs */
333static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
334 unsigned int slot_id,
335 unsigned int ep_index)
336{
337 unsigned int stream_id;
338 struct xhci_virt_ep *ep;
339
340 ep = &xhci->devs[slot_id]->eps[ep_index];
341
342 /* A ring has pending URBs if its TD list is not empty */
343 if (!(ep->ep_state & EP_HAS_STREAMS)) {
344 if (!(list_empty(&ep->ring->td_list)))
345 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
346 return;
347 }
348
349 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
350 stream_id++) {
351 struct xhci_stream_info *stream_info = ep->stream_info;
352 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
353 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
354 stream_id);
355 }
356}
357
358/*
359 * Find the segment that trb is in. Start searching in start_seg.
360 * If we must move past a segment that has a link TRB with a toggle cycle state
361 * bit set, then we will toggle the value pointed at by cycle_state.
362 */
363static struct xhci_segment *find_trb_seg(
364 struct xhci_segment *start_seg,
365 union xhci_trb *trb, int *cycle_state)
366{
367 struct xhci_segment *cur_seg = start_seg;
368 struct xhci_generic_trb *generic_trb;
369
370 while (cur_seg->trbs > trb ||
371 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
372 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
373 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
374 *cycle_state ^= 0x1;
375 cur_seg = cur_seg->next;
376 if (cur_seg == start_seg)
377 /* Looped over the entire list. Oops! */
378 return NULL;
379 }
380 return cur_seg;
381}
382
383
384static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
385 unsigned int slot_id, unsigned int ep_index,
386 unsigned int stream_id)
387{
388 struct xhci_virt_ep *ep;
389
390 ep = &xhci->devs[slot_id]->eps[ep_index];
391 /* Common case: no streams */
392 if (!(ep->ep_state & EP_HAS_STREAMS))
393 return ep->ring;
394
395 if (stream_id == 0) {
396 xhci_warn(xhci,
397 "WARN: Slot ID %u, ep index %u has streams, "
398 "but URB has no stream ID.\n",
399 slot_id, ep_index);
400 return NULL;
401 }
402
403 if (stream_id < ep->stream_info->num_streams)
404 return ep->stream_info->stream_rings[stream_id];
405
406 xhci_warn(xhci,
407 "WARN: Slot ID %u, ep index %u has "
408 "stream IDs 1 to %u allocated, "
409 "but stream ID %u is requested.\n",
410 slot_id, ep_index,
411 ep->stream_info->num_streams - 1,
412 stream_id);
413 return NULL;
414}
415
416/* Get the right ring for the given URB.
417 * If the endpoint supports streams, boundary check the URB's stream ID.
418 * If the endpoint doesn't support streams, return the singular endpoint ring.
419 */
420static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
421 struct urb *urb)
422{
423 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
424 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
425}
426
427/*
428 * Move the xHC's endpoint ring dequeue pointer past cur_td.
429 * Record the new state of the xHC's endpoint ring dequeue segment,
430 * dequeue pointer, and new consumer cycle state in state.
431 * Update our internal representation of the ring's dequeue pointer.
432 *
433 * We do this in three jumps:
434 * - First we update our new ring state to be the same as when the xHC stopped.
435 * - Then we traverse the ring to find the segment that contains
436 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
437 * any link TRBs with the toggle cycle bit set.
438 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
439 * if we've moved it past a link TRB with the toggle cycle bit set.
440 *
441 * Some of the uses of xhci_generic_trb are grotty, but if they're done
442 * with correct __le32 accesses they should work fine. Only users of this are
443 * in here.
444 */
445void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
446 unsigned int slot_id, unsigned int ep_index,
447 unsigned int stream_id, struct xhci_td *cur_td,
448 struct xhci_dequeue_state *state)
449{
450 struct xhci_virt_device *dev = xhci->devs[slot_id];
451 struct xhci_ring *ep_ring;
452 struct xhci_generic_trb *trb;
453 struct xhci_ep_ctx *ep_ctx;
454 dma_addr_t addr;
455
456 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
457 ep_index, stream_id);
458 if (!ep_ring) {
459 xhci_warn(xhci, "WARN can't find new dequeue state "
460 "for invalid stream ID %u.\n",
461 stream_id);
462 return;
463 }
464 state->new_cycle_state = 0;
465 xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
466 state->new_deq_seg = find_trb_seg(cur_td->start_seg,
467 dev->eps[ep_index].stopped_trb,
468 &state->new_cycle_state);
469 if (!state->new_deq_seg) {
470 WARN_ON(1);
471 return;
472 }
473
474 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
475 xhci_dbg(xhci, "Finding endpoint context\n");
476 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
477 state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
478
479 state->new_deq_ptr = cur_td->last_trb;
480 xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
481 state->new_deq_seg = find_trb_seg(state->new_deq_seg,
482 state->new_deq_ptr,
483 &state->new_cycle_state);
484 if (!state->new_deq_seg) {
485 WARN_ON(1);
486 return;
487 }
488
489 trb = &state->new_deq_ptr->generic;
490 if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
491 (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
492 state->new_cycle_state ^= 0x1;
493 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
494
495 /*
496 * If there is only one segment in a ring, find_trb_seg()'s while loop
497 * will not run, and it will return before it has a chance to see if it
498 * needs to toggle the cycle bit. It can't tell if the stalled transfer
499 * ended just before the link TRB on a one-segment ring, or if the TD
500 * wrapped around the top of the ring, because it doesn't have the TD in
501 * question. Look for the one-segment case where stalled TRB's address
502 * is greater than the new dequeue pointer address.
503 */
504 if (ep_ring->first_seg == ep_ring->first_seg->next &&
505 state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
506 state->new_cycle_state ^= 0x1;
507 xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
508
509 /* Don't update the ring cycle state for the producer (us). */
510 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
511 state->new_deq_seg);
512 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
513 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
514 (unsigned long long) addr);
515}
516
517/* flip_cycle means flip the cycle bit of all but the first and last TRB.
518 * (The last TRB actually points to the ring enqueue pointer, which is not part
519 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
520 */
521static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
522 struct xhci_td *cur_td, bool flip_cycle)
523{
524 struct xhci_segment *cur_seg;
525 union xhci_trb *cur_trb;
526
527 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
528 true;
529 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
530 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
531 /* Unchain any chained Link TRBs, but
532 * leave the pointers intact.
533 */
534 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
535 /* Flip the cycle bit (link TRBs can't be the first
536 * or last TRB).
537 */
538 if (flip_cycle)
539 cur_trb->generic.field[3] ^=
540 cpu_to_le32(TRB_CYCLE);
541 xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
542 xhci_dbg(xhci, "Address = %p (0x%llx dma); "
543 "in seg %p (0x%llx dma)\n",
544 cur_trb,
545 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
546 cur_seg,
547 (unsigned long long)cur_seg->dma);
548 } else {
549 cur_trb->generic.field[0] = 0;
550 cur_trb->generic.field[1] = 0;
551 cur_trb->generic.field[2] = 0;
552 /* Preserve only the cycle bit of this TRB */
553 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
554 /* Flip the cycle bit except on the first or last TRB */
555 if (flip_cycle && cur_trb != cur_td->first_trb &&
556 cur_trb != cur_td->last_trb)
557 cur_trb->generic.field[3] ^=
558 cpu_to_le32(TRB_CYCLE);
559 cur_trb->generic.field[3] |= cpu_to_le32(
560 TRB_TYPE(TRB_TR_NOOP));
561 xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
562 "in seg %p (0x%llx dma)\n",
563 cur_trb,
564 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
565 cur_seg,
566 (unsigned long long)cur_seg->dma);
567 }
568 if (cur_trb == cur_td->last_trb)
569 break;
570 }
571}
572
573static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
574 unsigned int ep_index, unsigned int stream_id,
575 struct xhci_segment *deq_seg,
576 union xhci_trb *deq_ptr, u32 cycle_state);
577
578void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
579 unsigned int slot_id, unsigned int ep_index,
580 unsigned int stream_id,
581 struct xhci_dequeue_state *deq_state)
582{
583 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
584
585 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
586 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
587 deq_state->new_deq_seg,
588 (unsigned long long)deq_state->new_deq_seg->dma,
589 deq_state->new_deq_ptr,
590 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
591 deq_state->new_cycle_state);
592 queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
593 deq_state->new_deq_seg,
594 deq_state->new_deq_ptr,
595 (u32) deq_state->new_cycle_state);
596 /* Stop the TD queueing code from ringing the doorbell until
597 * this command completes. The HC won't set the dequeue pointer
598 * if the ring is running, and ringing the doorbell starts the
599 * ring running.
600 */
601 ep->ep_state |= SET_DEQ_PENDING;
602}
603
604static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
605 struct xhci_virt_ep *ep)
606{
607 ep->ep_state &= ~EP_HALT_PENDING;
608 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
609 * timer is running on another CPU, we don't decrement stop_cmds_pending
610 * (since we didn't successfully stop the watchdog timer).
611 */
612 if (del_timer(&ep->stop_cmd_timer))
613 ep->stop_cmds_pending--;
614}
615
616/* Must be called with xhci->lock held in interrupt context */
617static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
618 struct xhci_td *cur_td, int status, char *adjective)
619{
620 struct usb_hcd *hcd;
621 struct urb *urb;
622 struct urb_priv *urb_priv;
623
624 urb = cur_td->urb;
625 urb_priv = urb->hcpriv;
626 urb_priv->td_cnt++;
627 hcd = bus_to_hcd(urb->dev->bus);
628
629 /* Only giveback urb when this is the last td in urb */
630 if (urb_priv->td_cnt == urb_priv->length) {
631 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
632 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
633 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
634 if (xhci->quirks & XHCI_AMD_PLL_FIX)
635 usb_amd_quirk_pll_enable();
636 }
637 }
638 usb_hcd_unlink_urb_from_ep(hcd, urb);
639
640 spin_unlock(&xhci->lock);
641 usb_hcd_giveback_urb(hcd, urb, status);
642 xhci_urb_free_priv(xhci, urb_priv);
643 spin_lock(&xhci->lock);
644 }
645}
646
647/*
648 * When we get a command completion for a Stop Endpoint Command, we need to
649 * unlink any cancelled TDs from the ring. There are two ways to do that:
650 *
651 * 1. If the HW was in the middle of processing the TD that needs to be
652 * cancelled, then we must move the ring's dequeue pointer past the last TRB
653 * in the TD with a Set Dequeue Pointer Command.
654 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
655 * bit cleared) so that the HW will skip over them.
656 */
657static void handle_stopped_endpoint(struct xhci_hcd *xhci,
658 union xhci_trb *trb, struct xhci_event_cmd *event)
659{
660 unsigned int slot_id;
661 unsigned int ep_index;
662 struct xhci_virt_device *virt_dev;
663 struct xhci_ring *ep_ring;
664 struct xhci_virt_ep *ep;
665 struct list_head *entry;
666 struct xhci_td *cur_td = NULL;
667 struct xhci_td *last_unlinked_td;
668
669 struct xhci_dequeue_state deq_state;
670
671 if (unlikely(TRB_TO_SUSPEND_PORT(
672 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
673 slot_id = TRB_TO_SLOT_ID(
674 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
675 virt_dev = xhci->devs[slot_id];
676 if (virt_dev)
677 handle_cmd_in_cmd_wait_list(xhci, virt_dev,
678 event);
679 else
680 xhci_warn(xhci, "Stop endpoint command "
681 "completion for disabled slot %u\n",
682 slot_id);
683 return;
684 }
685
686 memset(&deq_state, 0, sizeof(deq_state));
687 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
688 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
689 ep = &xhci->devs[slot_id]->eps[ep_index];
690
691 if (list_empty(&ep->cancelled_td_list)) {
692 xhci_stop_watchdog_timer_in_irq(xhci, ep);
693 ep->stopped_td = NULL;
694 ep->stopped_trb = NULL;
695 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
696 return;
697 }
698
699 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
700 * We have the xHCI lock, so nothing can modify this list until we drop
701 * it. We're also in the event handler, so we can't get re-interrupted
702 * if another Stop Endpoint command completes
703 */
704 list_for_each(entry, &ep->cancelled_td_list) {
705 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
706 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
707 cur_td->first_trb,
708 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
709 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
710 if (!ep_ring) {
711 /* This shouldn't happen unless a driver is mucking
712 * with the stream ID after submission. This will
713 * leave the TD on the hardware ring, and the hardware
714 * will try to execute it, and may access a buffer
715 * that has already been freed. In the best case, the
716 * hardware will execute it, and the event handler will
717 * ignore the completion event for that TD, since it was
718 * removed from the td_list for that endpoint. In
719 * short, don't muck with the stream ID after
720 * submission.
721 */
722 xhci_warn(xhci, "WARN Cancelled URB %p "
723 "has invalid stream ID %u.\n",
724 cur_td->urb,
725 cur_td->urb->stream_id);
726 goto remove_finished_td;
727 }
728 /*
729 * If we stopped on the TD we need to cancel, then we have to
730 * move the xHC endpoint ring dequeue pointer past this TD.
731 */
732 if (cur_td == ep->stopped_td)
733 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
734 cur_td->urb->stream_id,
735 cur_td, &deq_state);
736 else
737 td_to_noop(xhci, ep_ring, cur_td, false);
738remove_finished_td:
739 /*
740 * The event handler won't see a completion for this TD anymore,
741 * so remove it from the endpoint ring's TD list. Keep it in
742 * the cancelled TD list for URB completion later.
743 */
744 list_del_init(&cur_td->td_list);
745 }
746 last_unlinked_td = cur_td;
747 xhci_stop_watchdog_timer_in_irq(xhci, ep);
748
749 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
750 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
751 xhci_queue_new_dequeue_state(xhci,
752 slot_id, ep_index,
753 ep->stopped_td->urb->stream_id,
754 &deq_state);
755 xhci_ring_cmd_db(xhci);
756 } else {
757 /* Otherwise ring the doorbell(s) to restart queued transfers */
758 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
759 }
760 ep->stopped_td = NULL;
761 ep->stopped_trb = NULL;
762
763 /*
764 * Drop the lock and complete the URBs in the cancelled TD list.
765 * New TDs to be cancelled might be added to the end of the list before
766 * we can complete all the URBs for the TDs we already unlinked.
767 * So stop when we've completed the URB for the last TD we unlinked.
768 */
769 do {
770 cur_td = list_entry(ep->cancelled_td_list.next,
771 struct xhci_td, cancelled_td_list);
772 list_del_init(&cur_td->cancelled_td_list);
773
774 /* Clean up the cancelled URB */
775 /* Doesn't matter what we pass for status, since the core will
776 * just overwrite it (because the URB has been unlinked).
777 */
778 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
779
780 /* Stop processing the cancelled list if the watchdog timer is
781 * running.
782 */
783 if (xhci->xhc_state & XHCI_STATE_DYING)
784 return;
785 } while (cur_td != last_unlinked_td);
786
787 /* Return to the event handler with xhci->lock re-acquired */
788}
789
790/* Watchdog timer function for when a stop endpoint command fails to complete.
791 * In this case, we assume the host controller is broken or dying or dead. The
792 * host may still be completing some other events, so we have to be careful to
793 * let the event ring handler and the URB dequeueing/enqueueing functions know
794 * through xhci->state.
795 *
796 * The timer may also fire if the host takes a very long time to respond to the
797 * command, and the stop endpoint command completion handler cannot delete the
798 * timer before the timer function is called. Another endpoint cancellation may
799 * sneak in before the timer function can grab the lock, and that may queue
800 * another stop endpoint command and add the timer back. So we cannot use a
801 * simple flag to say whether there is a pending stop endpoint command for a
802 * particular endpoint.
803 *
804 * Instead we use a combination of that flag and a counter for the number of
805 * pending stop endpoint commands. If the timer is the tail end of the last
806 * stop endpoint command, and the endpoint's command is still pending, we assume
807 * the host is dying.
808 */
809void xhci_stop_endpoint_command_watchdog(unsigned long arg)
810{
811 struct xhci_hcd *xhci;
812 struct xhci_virt_ep *ep;
813 struct xhci_virt_ep *temp_ep;
814 struct xhci_ring *ring;
815 struct xhci_td *cur_td;
816 int ret, i, j;
817
818 ep = (struct xhci_virt_ep *) arg;
819 xhci = ep->xhci;
820
821 spin_lock(&xhci->lock);
822
823 ep->stop_cmds_pending--;
824 if (xhci->xhc_state & XHCI_STATE_DYING) {
825 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
826 "xHCI as DYING, exiting.\n");
827 spin_unlock(&xhci->lock);
828 return;
829 }
830 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
831 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
832 "exiting.\n");
833 spin_unlock(&xhci->lock);
834 return;
835 }
836
837 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
838 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
839 /* Oops, HC is dead or dying or at least not responding to the stop
840 * endpoint command.
841 */
842 xhci->xhc_state |= XHCI_STATE_DYING;
843 /* Disable interrupts from the host controller and start halting it */
844 xhci_quiesce(xhci);
845 spin_unlock(&xhci->lock);
846
847 ret = xhci_halt(xhci);
848
849 spin_lock(&xhci->lock);
850 if (ret < 0) {
851 /* This is bad; the host is not responding to commands and it's
852 * not allowing itself to be halted. At least interrupts are
853 * disabled. If we call usb_hc_died(), it will attempt to
854 * disconnect all device drivers under this host. Those
855 * disconnect() methods will wait for all URBs to be unlinked,
856 * so we must complete them.
857 */
858 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
859 xhci_warn(xhci, "Completing active URBs anyway.\n");
860 /* We could turn all TDs on the rings to no-ops. This won't
861 * help if the host has cached part of the ring, and is slow if
862 * we want to preserve the cycle bit. Skip it and hope the host
863 * doesn't touch the memory.
864 */
865 }
866 for (i = 0; i < MAX_HC_SLOTS; i++) {
867 if (!xhci->devs[i])
868 continue;
869 for (j = 0; j < 31; j++) {
870 temp_ep = &xhci->devs[i]->eps[j];
871 ring = temp_ep->ring;
872 if (!ring)
873 continue;
874 xhci_dbg(xhci, "Killing URBs for slot ID %u, "
875 "ep index %u\n", i, j);
876 while (!list_empty(&ring->td_list)) {
877 cur_td = list_first_entry(&ring->td_list,
878 struct xhci_td,
879 td_list);
880 list_del_init(&cur_td->td_list);
881 if (!list_empty(&cur_td->cancelled_td_list))
882 list_del_init(&cur_td->cancelled_td_list);
883 xhci_giveback_urb_in_irq(xhci, cur_td,
884 -ESHUTDOWN, "killed");
885 }
886 while (!list_empty(&temp_ep->cancelled_td_list)) {
887 cur_td = list_first_entry(
888 &temp_ep->cancelled_td_list,
889 struct xhci_td,
890 cancelled_td_list);
891 list_del_init(&cur_td->cancelled_td_list);
892 xhci_giveback_urb_in_irq(xhci, cur_td,
893 -ESHUTDOWN, "killed");
894 }
895 }
896 }
897 spin_unlock(&xhci->lock);
898 xhci_dbg(xhci, "Calling usb_hc_died()\n");
899 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
900 xhci_dbg(xhci, "xHCI host controller is dead.\n");
901}
902
903/*
904 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
905 * we need to clear the set deq pending flag in the endpoint ring state, so that
906 * the TD queueing code can ring the doorbell again. We also need to ring the
907 * endpoint doorbell to restart the ring, but only if there aren't more
908 * cancellations pending.
909 */
910static void handle_set_deq_completion(struct xhci_hcd *xhci,
911 struct xhci_event_cmd *event,
912 union xhci_trb *trb)
913{
914 unsigned int slot_id;
915 unsigned int ep_index;
916 unsigned int stream_id;
917 struct xhci_ring *ep_ring;
918 struct xhci_virt_device *dev;
919 struct xhci_ep_ctx *ep_ctx;
920 struct xhci_slot_ctx *slot_ctx;
921
922 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
923 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
924 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
925 dev = xhci->devs[slot_id];
926
927 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
928 if (!ep_ring) {
929 xhci_warn(xhci, "WARN Set TR deq ptr command for "
930 "freed stream ID %u\n",
931 stream_id);
932 /* XXX: Harmless??? */
933 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
934 return;
935 }
936
937 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
938 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
939
940 if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
941 unsigned int ep_state;
942 unsigned int slot_state;
943
944 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
945 case COMP_TRB_ERR:
946 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
947 "of stream ID configuration\n");
948 break;
949 case COMP_CTX_STATE:
950 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
951 "to incorrect slot or ep state.\n");
952 ep_state = le32_to_cpu(ep_ctx->ep_info);
953 ep_state &= EP_STATE_MASK;
954 slot_state = le32_to_cpu(slot_ctx->dev_state);
955 slot_state = GET_SLOT_STATE(slot_state);
956 xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
957 slot_state, ep_state);
958 break;
959 case COMP_EBADSLT:
960 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
961 "slot %u was not enabled.\n", slot_id);
962 break;
963 default:
964 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
965 "completion code of %u.\n",
966 GET_COMP_CODE(le32_to_cpu(event->status)));
967 break;
968 }
969 /* OK what do we do now? The endpoint state is hosed, and we
970 * should never get to this point if the synchronization between
971 * queueing, and endpoint state are correct. This might happen
972 * if the device gets disconnected after we've finished
973 * cancelling URBs, which might not be an error...
974 */
975 } else {
976 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
977 le64_to_cpu(ep_ctx->deq));
978 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
979 dev->eps[ep_index].queued_deq_ptr) ==
980 (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
981 /* Update the ring's dequeue segment and dequeue pointer
982 * to reflect the new position.
983 */
984 ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
985 ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
986 } else {
987 xhci_warn(xhci, "Mismatch between completed Set TR Deq "
988 "Ptr command & xHCI internal state.\n");
989 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
990 dev->eps[ep_index].queued_deq_seg,
991 dev->eps[ep_index].queued_deq_ptr);
992 }
993 }
994
995 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
996 dev->eps[ep_index].queued_deq_seg = NULL;
997 dev->eps[ep_index].queued_deq_ptr = NULL;
998 /* Restart any rings with pending URBs */
999 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1000}
1001
1002static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1003 struct xhci_event_cmd *event,
1004 union xhci_trb *trb)
1005{
1006 int slot_id;
1007 unsigned int ep_index;
1008
1009 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1010 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1011 /* This command will only fail if the endpoint wasn't halted,
1012 * but we don't care.
1013 */
1014 xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1015 GET_COMP_CODE(le32_to_cpu(event->status)));
1016
1017 /* HW with the reset endpoint quirk needs to have a configure endpoint
1018 * command complete before the endpoint can be used. Queue that here
1019 * because the HW can't handle two commands being queued in a row.
1020 */
1021 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1022 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1023 xhci_queue_configure_endpoint(xhci,
1024 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1025 false);
1026 xhci_ring_cmd_db(xhci);
1027 } else {
1028 /* Clear our internal halted state and restart the ring(s) */
1029 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1030 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1031 }
1032}
1033
1034/* Check to see if a command in the device's command queue matches this one.
1035 * Signal the completion or free the command, and return 1. Return 0 if the
1036 * completed command isn't at the head of the command list.
1037 */
1038static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1039 struct xhci_virt_device *virt_dev,
1040 struct xhci_event_cmd *event)
1041{
1042 struct xhci_command *command;
1043
1044 if (list_empty(&virt_dev->cmd_list))
1045 return 0;
1046
1047 command = list_entry(virt_dev->cmd_list.next,
1048 struct xhci_command, cmd_list);
1049 if (xhci->cmd_ring->dequeue != command->command_trb)
1050 return 0;
1051
1052 command->status = GET_COMP_CODE(le32_to_cpu(event->status));
1053 list_del(&command->cmd_list);
1054 if (command->completion)
1055 complete(command->completion);
1056 else
1057 xhci_free_command(xhci, command);
1058 return 1;
1059}
1060
1061static void handle_cmd_completion(struct xhci_hcd *xhci,
1062 struct xhci_event_cmd *event)
1063{
1064 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1065 u64 cmd_dma;
1066 dma_addr_t cmd_dequeue_dma;
1067 struct xhci_input_control_ctx *ctrl_ctx;
1068 struct xhci_virt_device *virt_dev;
1069 unsigned int ep_index;
1070 struct xhci_ring *ep_ring;
1071 unsigned int ep_state;
1072
1073 cmd_dma = le64_to_cpu(event->cmd_trb);
1074 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1075 xhci->cmd_ring->dequeue);
1076 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1077 if (cmd_dequeue_dma == 0) {
1078 xhci->error_bitmask |= 1 << 4;
1079 return;
1080 }
1081 /* Does the DMA address match our internal dequeue pointer address? */
1082 if (cmd_dma != (u64) cmd_dequeue_dma) {
1083 xhci->error_bitmask |= 1 << 5;
1084 return;
1085 }
1086 switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1087 & TRB_TYPE_BITMASK) {
1088 case TRB_TYPE(TRB_ENABLE_SLOT):
1089 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1090 xhci->slot_id = slot_id;
1091 else
1092 xhci->slot_id = 0;
1093 complete(&xhci->addr_dev);
1094 break;
1095 case TRB_TYPE(TRB_DISABLE_SLOT):
1096 if (xhci->devs[slot_id]) {
1097 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1098 /* Delete default control endpoint resources */
1099 xhci_free_device_endpoint_resources(xhci,
1100 xhci->devs[slot_id], true);
1101 xhci_free_virt_device(xhci, slot_id);
1102 }
1103 break;
1104 case TRB_TYPE(TRB_CONFIG_EP):
1105 virt_dev = xhci->devs[slot_id];
1106 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1107 break;
1108 /*
1109 * Configure endpoint commands can come from the USB core
1110 * configuration or alt setting changes, or because the HW
1111 * needed an extra configure endpoint command after a reset
1112 * endpoint command or streams were being configured.
1113 * If the command was for a halted endpoint, the xHCI driver
1114 * is not waiting on the configure endpoint command.
1115 */
1116 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1117 virt_dev->in_ctx);
1118 /* Input ctx add_flags are the endpoint index plus one */
1119 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1120 /* A usb_set_interface() call directly after clearing a halted
1121 * condition may race on this quirky hardware. Not worth
1122 * worrying about, since this is prototype hardware. Not sure
1123 * if this will work for streams, but streams support was
1124 * untested on this prototype.
1125 */
1126 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1127 ep_index != (unsigned int) -1 &&
1128 le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1129 le32_to_cpu(ctrl_ctx->drop_flags)) {
1130 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1131 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1132 if (!(ep_state & EP_HALTED))
1133 goto bandwidth_change;
1134 xhci_dbg(xhci, "Completed config ep cmd - "
1135 "last ep index = %d, state = %d\n",
1136 ep_index, ep_state);
1137 /* Clear internal halted state and restart ring(s) */
1138 xhci->devs[slot_id]->eps[ep_index].ep_state &=
1139 ~EP_HALTED;
1140 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1141 break;
1142 }
1143bandwidth_change:
1144 xhci_dbg(xhci, "Completed config ep cmd\n");
1145 xhci->devs[slot_id]->cmd_status =
1146 GET_COMP_CODE(le32_to_cpu(event->status));
1147 complete(&xhci->devs[slot_id]->cmd_completion);
1148 break;
1149 case TRB_TYPE(TRB_EVAL_CONTEXT):
1150 virt_dev = xhci->devs[slot_id];
1151 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1152 break;
1153 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1154 complete(&xhci->devs[slot_id]->cmd_completion);
1155 break;
1156 case TRB_TYPE(TRB_ADDR_DEV):
1157 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1158 complete(&xhci->addr_dev);
1159 break;
1160 case TRB_TYPE(TRB_STOP_RING):
1161 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1162 break;
1163 case TRB_TYPE(TRB_SET_DEQ):
1164 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1165 break;
1166 case TRB_TYPE(TRB_CMD_NOOP):
1167 break;
1168 case TRB_TYPE(TRB_RESET_EP):
1169 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1170 break;
1171 case TRB_TYPE(TRB_RESET_DEV):
1172 xhci_dbg(xhci, "Completed reset device command.\n");
1173 slot_id = TRB_TO_SLOT_ID(
1174 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1175 virt_dev = xhci->devs[slot_id];
1176 if (virt_dev)
1177 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1178 else
1179 xhci_warn(xhci, "Reset device command completion "
1180 "for disabled slot %u\n", slot_id);
1181 break;
1182 case TRB_TYPE(TRB_NEC_GET_FW):
1183 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1184 xhci->error_bitmask |= 1 << 6;
1185 break;
1186 }
1187 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1188 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1189 NEC_FW_MINOR(le32_to_cpu(event->status)));
1190 break;
1191 default:
1192 /* Skip over unknown commands on the event ring */
1193 xhci->error_bitmask |= 1 << 6;
1194 break;
1195 }
1196 inc_deq(xhci, xhci->cmd_ring, false);
1197}
1198
1199static void handle_vendor_event(struct xhci_hcd *xhci,
1200 union xhci_trb *event)
1201{
1202 u32 trb_type;
1203
1204 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1205 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1206 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1207 handle_cmd_completion(xhci, &event->event_cmd);
1208}
1209
1210/* @port_id: the one-based port ID from the hardware (indexed from array of all
1211 * port registers -- USB 3.0 and USB 2.0).
1212 *
1213 * Returns a zero-based port number, which is suitable for indexing into each of
1214 * the split roothubs' port arrays and bus state arrays.
1215 */
1216static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1217 struct xhci_hcd *xhci, u32 port_id)
1218{
1219 unsigned int i;
1220 unsigned int num_similar_speed_ports = 0;
1221
1222 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1223 * and usb2_ports are 0-based indexes. Count the number of similar
1224 * speed ports, up to 1 port before this port.
1225 */
1226 for (i = 0; i < (port_id - 1); i++) {
1227 u8 port_speed = xhci->port_array[i];
1228
1229 /*
1230 * Skip ports that don't have known speeds, or have duplicate
1231 * Extended Capabilities port speed entries.
1232 */
1233 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1234 continue;
1235
1236 /*
1237 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1238 * 1.1 ports are under the USB 2.0 hub. If the port speed
1239 * matches the device speed, it's a similar speed port.
1240 */
1241 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1242 num_similar_speed_ports++;
1243 }
1244 return num_similar_speed_ports;
1245}
1246
1247static void handle_port_status(struct xhci_hcd *xhci,
1248 union xhci_trb *event)
1249{
1250 struct usb_hcd *hcd;
1251 u32 port_id;
1252 u32 temp, temp1;
1253 int max_ports;
1254 int slot_id;
1255 unsigned int faked_port_index;
1256 u8 major_revision;
1257 struct xhci_bus_state *bus_state;
1258 __le32 __iomem **port_array;
1259 bool bogus_port_status = false;
1260
1261 /* Port status change events always have a successful completion code */
1262 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1263 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1264 xhci->error_bitmask |= 1 << 8;
1265 }
1266 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1267 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1268
1269 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1270 if ((port_id <= 0) || (port_id > max_ports)) {
1271 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1272 bogus_port_status = true;
1273 goto cleanup;
1274 }
1275
1276 /* Figure out which usb_hcd this port is attached to:
1277 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1278 */
1279 major_revision = xhci->port_array[port_id - 1];
1280 if (major_revision == 0) {
1281 xhci_warn(xhci, "Event for port %u not in "
1282 "Extended Capabilities, ignoring.\n",
1283 port_id);
1284 bogus_port_status = true;
1285 goto cleanup;
1286 }
1287 if (major_revision == DUPLICATE_ENTRY) {
1288 xhci_warn(xhci, "Event for port %u duplicated in"
1289 "Extended Capabilities, ignoring.\n",
1290 port_id);
1291 bogus_port_status = true;
1292 goto cleanup;
1293 }
1294
1295 /*
1296 * Hardware port IDs reported by a Port Status Change Event include USB
1297 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1298 * resume event, but we first need to translate the hardware port ID
1299 * into the index into the ports on the correct split roothub, and the
1300 * correct bus_state structure.
1301 */
1302 /* Find the right roothub. */
1303 hcd = xhci_to_hcd(xhci);
1304 if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1305 hcd = xhci->shared_hcd;
1306 bus_state = &xhci->bus_state[hcd_index(hcd)];
1307 if (hcd->speed == HCD_USB3)
1308 port_array = xhci->usb3_ports;
1309 else
1310 port_array = xhci->usb2_ports;
1311 /* Find the faked port hub number */
1312 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1313 port_id);
1314
1315 temp = xhci_readl(xhci, port_array[faked_port_index]);
1316 if (hcd->state == HC_STATE_SUSPENDED) {
1317 xhci_dbg(xhci, "resume root hub\n");
1318 usb_hcd_resume_root_hub(hcd);
1319 }
1320
1321 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1322 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1323
1324 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1325 if (!(temp1 & CMD_RUN)) {
1326 xhci_warn(xhci, "xHC is not running.\n");
1327 goto cleanup;
1328 }
1329
1330 if (DEV_SUPERSPEED(temp)) {
1331 xhci_dbg(xhci, "resume SS port %d\n", port_id);
1332 temp = xhci_port_state_to_neutral(temp);
1333 temp &= ~PORT_PLS_MASK;
1334 temp |= PORT_LINK_STROBE | XDEV_U0;
1335 xhci_writel(xhci, temp, port_array[faked_port_index]);
1336 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1337 faked_port_index);
1338 if (!slot_id) {
1339 xhci_dbg(xhci, "slot_id is zero\n");
1340 goto cleanup;
1341 }
1342 xhci_ring_device(xhci, slot_id);
1343 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1344 /* Clear PORT_PLC */
1345 temp = xhci_readl(xhci, port_array[faked_port_index]);
1346 temp = xhci_port_state_to_neutral(temp);
1347 temp |= PORT_PLC;
1348 xhci_writel(xhci, temp, port_array[faked_port_index]);
1349 } else {
1350 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1351 bus_state->resume_done[faked_port_index] = jiffies +
1352 msecs_to_jiffies(20);
1353 mod_timer(&hcd->rh_timer,
1354 bus_state->resume_done[faked_port_index]);
1355 /* Do the rest in GetPortStatus */
1356 }
1357 }
1358
1359cleanup:
1360 /* Update event ring dequeue pointer before dropping the lock */
1361 inc_deq(xhci, xhci->event_ring, true);
1362
1363 /* Don't make the USB core poll the roothub if we got a bad port status
1364 * change event. Besides, at that point we can't tell which roothub
1365 * (USB 2.0 or USB 3.0) to kick.
1366 */
1367 if (bogus_port_status)
1368 return;
1369
1370 spin_unlock(&xhci->lock);
1371 /* Pass this up to the core */
1372 usb_hcd_poll_rh_status(hcd);
1373 spin_lock(&xhci->lock);
1374}
1375
1376/*
1377 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1378 * at end_trb, which may be in another segment. If the suspect DMA address is a
1379 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1380 * returns 0.
1381 */
1382struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1383 union xhci_trb *start_trb,
1384 union xhci_trb *end_trb,
1385 dma_addr_t suspect_dma)
1386{
1387 dma_addr_t start_dma;
1388 dma_addr_t end_seg_dma;
1389 dma_addr_t end_trb_dma;
1390 struct xhci_segment *cur_seg;
1391
1392 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1393 cur_seg = start_seg;
1394
1395 do {
1396 if (start_dma == 0)
1397 return NULL;
1398 /* We may get an event for a Link TRB in the middle of a TD */
1399 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1400 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1401 /* If the end TRB isn't in this segment, this is set to 0 */
1402 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1403
1404 if (end_trb_dma > 0) {
1405 /* The end TRB is in this segment, so suspect should be here */
1406 if (start_dma <= end_trb_dma) {
1407 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1408 return cur_seg;
1409 } else {
1410 /* Case for one segment with
1411 * a TD wrapped around to the top
1412 */
1413 if ((suspect_dma >= start_dma &&
1414 suspect_dma <= end_seg_dma) ||
1415 (suspect_dma >= cur_seg->dma &&
1416 suspect_dma <= end_trb_dma))
1417 return cur_seg;
1418 }
1419 return NULL;
1420 } else {
1421 /* Might still be somewhere in this segment */
1422 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1423 return cur_seg;
1424 }
1425 cur_seg = cur_seg->next;
1426 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1427 } while (cur_seg != start_seg);
1428
1429 return NULL;
1430}
1431
1432static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1433 unsigned int slot_id, unsigned int ep_index,
1434 unsigned int stream_id,
1435 struct xhci_td *td, union xhci_trb *event_trb)
1436{
1437 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1438 ep->ep_state |= EP_HALTED;
1439 ep->stopped_td = td;
1440 ep->stopped_trb = event_trb;
1441 ep->stopped_stream = stream_id;
1442
1443 xhci_queue_reset_ep(xhci, slot_id, ep_index);
1444 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1445
1446 ep->stopped_td = NULL;
1447 ep->stopped_trb = NULL;
1448 ep->stopped_stream = 0;
1449
1450 xhci_ring_cmd_db(xhci);
1451}
1452
1453/* Check if an error has halted the endpoint ring. The class driver will
1454 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1455 * However, a babble and other errors also halt the endpoint ring, and the class
1456 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1457 * Ring Dequeue Pointer command manually.
1458 */
1459static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1460 struct xhci_ep_ctx *ep_ctx,
1461 unsigned int trb_comp_code)
1462{
1463 /* TRB completion codes that may require a manual halt cleanup */
1464 if (trb_comp_code == COMP_TX_ERR ||
1465 trb_comp_code == COMP_BABBLE ||
1466 trb_comp_code == COMP_SPLIT_ERR)
1467 /* The 0.96 spec says a babbling control endpoint
1468 * is not halted. The 0.96 spec says it is. Some HW
1469 * claims to be 0.95 compliant, but it halts the control
1470 * endpoint anyway. Check if a babble halted the
1471 * endpoint.
1472 */
1473 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1474 cpu_to_le32(EP_STATE_HALTED))
1475 return 1;
1476
1477 return 0;
1478}
1479
1480int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1481{
1482 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1483 /* Vendor defined "informational" completion code,
1484 * treat as not-an-error.
1485 */
1486 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1487 trb_comp_code);
1488 xhci_dbg(xhci, "Treating code as success.\n");
1489 return 1;
1490 }
1491 return 0;
1492}
1493
1494/*
1495 * Finish the td processing, remove the td from td list;
1496 * Return 1 if the urb can be given back.
1497 */
1498static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1499 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1500 struct xhci_virt_ep *ep, int *status, bool skip)
1501{
1502 struct xhci_virt_device *xdev;
1503 struct xhci_ring *ep_ring;
1504 unsigned int slot_id;
1505 int ep_index;
1506 struct urb *urb = NULL;
1507 struct xhci_ep_ctx *ep_ctx;
1508 int ret = 0;
1509 struct urb_priv *urb_priv;
1510 u32 trb_comp_code;
1511
1512 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1513 xdev = xhci->devs[slot_id];
1514 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1515 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1516 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1517 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1518
1519 if (skip)
1520 goto td_cleanup;
1521
1522 if (trb_comp_code == COMP_STOP_INVAL ||
1523 trb_comp_code == COMP_STOP) {
1524 /* The Endpoint Stop Command completion will take care of any
1525 * stopped TDs. A stopped TD may be restarted, so don't update
1526 * the ring dequeue pointer or take this TD off any lists yet.
1527 */
1528 ep->stopped_td = td;
1529 ep->stopped_trb = event_trb;
1530 return 0;
1531 } else {
1532 if (trb_comp_code == COMP_STALL) {
1533 /* The transfer is completed from the driver's
1534 * perspective, but we need to issue a set dequeue
1535 * command for this stalled endpoint to move the dequeue
1536 * pointer past the TD. We can't do that here because
1537 * the halt condition must be cleared first. Let the
1538 * USB class driver clear the stall later.
1539 */
1540 ep->stopped_td = td;
1541 ep->stopped_trb = event_trb;
1542 ep->stopped_stream = ep_ring->stream_id;
1543 } else if (xhci_requires_manual_halt_cleanup(xhci,
1544 ep_ctx, trb_comp_code)) {
1545 /* Other types of errors halt the endpoint, but the
1546 * class driver doesn't call usb_reset_endpoint() unless
1547 * the error is -EPIPE. Clear the halted status in the
1548 * xHCI hardware manually.
1549 */
1550 xhci_cleanup_halted_endpoint(xhci,
1551 slot_id, ep_index, ep_ring->stream_id,
1552 td, event_trb);
1553 } else {
1554 /* Update ring dequeue pointer */
1555 while (ep_ring->dequeue != td->last_trb)
1556 inc_deq(xhci, ep_ring, false);
1557 inc_deq(xhci, ep_ring, false);
1558 }
1559
1560td_cleanup:
1561 /* Clean up the endpoint's TD list */
1562 urb = td->urb;
1563 urb_priv = urb->hcpriv;
1564
1565 /* Do one last check of the actual transfer length.
1566 * If the host controller said we transferred more data than
1567 * the buffer length, urb->actual_length will be a very big
1568 * number (since it's unsigned). Play it safe and say we didn't
1569 * transfer anything.
1570 */
1571 if (urb->actual_length > urb->transfer_buffer_length) {
1572 xhci_warn(xhci, "URB transfer length is wrong, "
1573 "xHC issue? req. len = %u, "
1574 "act. len = %u\n",
1575 urb->transfer_buffer_length,
1576 urb->actual_length);
1577 urb->actual_length = 0;
1578 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1579 *status = -EREMOTEIO;
1580 else
1581 *status = 0;
1582 }
1583 list_del_init(&td->td_list);
1584 /* Was this TD slated to be cancelled but completed anyway? */
1585 if (!list_empty(&td->cancelled_td_list))
1586 list_del_init(&td->cancelled_td_list);
1587
1588 urb_priv->td_cnt++;
1589 /* Giveback the urb when all the tds are completed */
1590 if (urb_priv->td_cnt == urb_priv->length) {
1591 ret = 1;
1592 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1593 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1594 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1595 == 0) {
1596 if (xhci->quirks & XHCI_AMD_PLL_FIX)
1597 usb_amd_quirk_pll_enable();
1598 }
1599 }
1600 }
1601 }
1602
1603 return ret;
1604}
1605
1606/*
1607 * Process control tds, update urb status and actual_length.
1608 */
1609static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1610 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1611 struct xhci_virt_ep *ep, int *status)
1612{
1613 struct xhci_virt_device *xdev;
1614 struct xhci_ring *ep_ring;
1615 unsigned int slot_id;
1616 int ep_index;
1617 struct xhci_ep_ctx *ep_ctx;
1618 u32 trb_comp_code;
1619
1620 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1621 xdev = xhci->devs[slot_id];
1622 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1623 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1624 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1625 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1626
1627 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1628 switch (trb_comp_code) {
1629 case COMP_SUCCESS:
1630 if (event_trb == ep_ring->dequeue) {
1631 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1632 "without IOC set??\n");
1633 *status = -ESHUTDOWN;
1634 } else if (event_trb != td->last_trb) {
1635 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1636 "without IOC set??\n");
1637 *status = -ESHUTDOWN;
1638 } else {
1639 *status = 0;
1640 }
1641 break;
1642 case COMP_SHORT_TX:
1643 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1644 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1645 *status = -EREMOTEIO;
1646 else
1647 *status = 0;
1648 break;
1649 case COMP_STOP_INVAL:
1650 case COMP_STOP:
1651 return finish_td(xhci, td, event_trb, event, ep, status, false);
1652 default:
1653 if (!xhci_requires_manual_halt_cleanup(xhci,
1654 ep_ctx, trb_comp_code))
1655 break;
1656 xhci_dbg(xhci, "TRB error code %u, "
1657 "halted endpoint index = %u\n",
1658 trb_comp_code, ep_index);
1659 /* else fall through */
1660 case COMP_STALL:
1661 /* Did we transfer part of the data (middle) phase? */
1662 if (event_trb != ep_ring->dequeue &&
1663 event_trb != td->last_trb)
1664 td->urb->actual_length =
1665 td->urb->transfer_buffer_length
1666 - TRB_LEN(le32_to_cpu(event->transfer_len));
1667 else
1668 td->urb->actual_length = 0;
1669
1670 xhci_cleanup_halted_endpoint(xhci,
1671 slot_id, ep_index, 0, td, event_trb);
1672 return finish_td(xhci, td, event_trb, event, ep, status, true);
1673 }
1674 /*
1675 * Did we transfer any data, despite the errors that might have
1676 * happened? I.e. did we get past the setup stage?
1677 */
1678 if (event_trb != ep_ring->dequeue) {
1679 /* The event was for the status stage */
1680 if (event_trb == td->last_trb) {
1681 if (td->urb->actual_length != 0) {
1682 /* Don't overwrite a previously set error code
1683 */
1684 if ((*status == -EINPROGRESS || *status == 0) &&
1685 (td->urb->transfer_flags
1686 & URB_SHORT_NOT_OK))
1687 /* Did we already see a short data
1688 * stage? */
1689 *status = -EREMOTEIO;
1690 } else {
1691 td->urb->actual_length =
1692 td->urb->transfer_buffer_length;
1693 }
1694 } else {
1695 /* Maybe the event was for the data stage? */
1696 td->urb->actual_length =
1697 td->urb->transfer_buffer_length -
1698 TRB_LEN(le32_to_cpu(event->transfer_len));
1699 xhci_dbg(xhci, "Waiting for status "
1700 "stage event\n");
1701 return 0;
1702 }
1703 }
1704
1705 return finish_td(xhci, td, event_trb, event, ep, status, false);
1706}
1707
1708/*
1709 * Process isochronous tds, update urb packet status and actual_length.
1710 */
1711static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1712 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1713 struct xhci_virt_ep *ep, int *status)
1714{
1715 struct xhci_ring *ep_ring;
1716 struct urb_priv *urb_priv;
1717 int idx;
1718 int len = 0;
1719 union xhci_trb *cur_trb;
1720 struct xhci_segment *cur_seg;
1721 struct usb_iso_packet_descriptor *frame;
1722 u32 trb_comp_code;
1723 bool skip_td = false;
1724
1725 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1726 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1727 urb_priv = td->urb->hcpriv;
1728 idx = urb_priv->td_cnt;
1729 frame = &td->urb->iso_frame_desc[idx];
1730
1731 /* handle completion code */
1732 switch (trb_comp_code) {
1733 case COMP_SUCCESS:
1734 frame->status = 0;
1735 break;
1736 case COMP_SHORT_TX:
1737 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
1738 -EREMOTEIO : 0;
1739 break;
1740 case COMP_BW_OVER:
1741 frame->status = -ECOMM;
1742 skip_td = true;
1743 break;
1744 case COMP_BUFF_OVER:
1745 case COMP_BABBLE:
1746 frame->status = -EOVERFLOW;
1747 skip_td = true;
1748 break;
1749 case COMP_DEV_ERR:
1750 case COMP_STALL:
1751 frame->status = -EPROTO;
1752 skip_td = true;
1753 break;
1754 case COMP_STOP:
1755 case COMP_STOP_INVAL:
1756 break;
1757 default:
1758 frame->status = -1;
1759 break;
1760 }
1761
1762 if (trb_comp_code == COMP_SUCCESS || skip_td) {
1763 frame->actual_length = frame->length;
1764 td->urb->actual_length += frame->length;
1765 } else {
1766 for (cur_trb = ep_ring->dequeue,
1767 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
1768 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1769 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1770 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
1771 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1772 }
1773 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1774 TRB_LEN(le32_to_cpu(event->transfer_len));
1775
1776 if (trb_comp_code != COMP_STOP_INVAL) {
1777 frame->actual_length = len;
1778 td->urb->actual_length += len;
1779 }
1780 }
1781
1782 return finish_td(xhci, td, event_trb, event, ep, status, false);
1783}
1784
1785static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1786 struct xhci_transfer_event *event,
1787 struct xhci_virt_ep *ep, int *status)
1788{
1789 struct xhci_ring *ep_ring;
1790 struct urb_priv *urb_priv;
1791 struct usb_iso_packet_descriptor *frame;
1792 int idx;
1793
1794 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1795 urb_priv = td->urb->hcpriv;
1796 idx = urb_priv->td_cnt;
1797 frame = &td->urb->iso_frame_desc[idx];
1798
1799 /* The transfer is partly done. */
1800 frame->status = -EXDEV;
1801
1802 /* calc actual length */
1803 frame->actual_length = 0;
1804
1805 /* Update ring dequeue pointer */
1806 while (ep_ring->dequeue != td->last_trb)
1807 inc_deq(xhci, ep_ring, false);
1808 inc_deq(xhci, ep_ring, false);
1809
1810 return finish_td(xhci, td, NULL, event, ep, status, true);
1811}
1812
1813/*
1814 * Process bulk and interrupt tds, update urb status and actual_length.
1815 */
1816static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1817 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1818 struct xhci_virt_ep *ep, int *status)
1819{
1820 struct xhci_ring *ep_ring;
1821 union xhci_trb *cur_trb;
1822 struct xhci_segment *cur_seg;
1823 u32 trb_comp_code;
1824
1825 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1826 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1827
1828 switch (trb_comp_code) {
1829 case COMP_SUCCESS:
1830 /* Double check that the HW transferred everything. */
1831 if (event_trb != td->last_trb) {
1832 xhci_warn(xhci, "WARN Successful completion "
1833 "on short TX\n");
1834 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1835 *status = -EREMOTEIO;
1836 else
1837 *status = 0;
1838 } else {
1839 *status = 0;
1840 }
1841 break;
1842 case COMP_SHORT_TX:
1843 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1844 *status = -EREMOTEIO;
1845 else
1846 *status = 0;
1847 break;
1848 default:
1849 /* Others already handled above */
1850 break;
1851 }
1852 if (trb_comp_code == COMP_SHORT_TX)
1853 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
1854 "%d bytes untransferred\n",
1855 td->urb->ep->desc.bEndpointAddress,
1856 td->urb->transfer_buffer_length,
1857 TRB_LEN(le32_to_cpu(event->transfer_len)));
1858 /* Fast path - was this the last TRB in the TD for this URB? */
1859 if (event_trb == td->last_trb) {
1860 if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
1861 td->urb->actual_length =
1862 td->urb->transfer_buffer_length -
1863 TRB_LEN(le32_to_cpu(event->transfer_len));
1864 if (td->urb->transfer_buffer_length <
1865 td->urb->actual_length) {
1866 xhci_warn(xhci, "HC gave bad length "
1867 "of %d bytes left\n",
1868 TRB_LEN(le32_to_cpu(event->transfer_len)));
1869 td->urb->actual_length = 0;
1870 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1871 *status = -EREMOTEIO;
1872 else
1873 *status = 0;
1874 }
1875 /* Don't overwrite a previously set error code */
1876 if (*status == -EINPROGRESS) {
1877 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1878 *status = -EREMOTEIO;
1879 else
1880 *status = 0;
1881 }
1882 } else {
1883 td->urb->actual_length =
1884 td->urb->transfer_buffer_length;
1885 /* Ignore a short packet completion if the
1886 * untransferred length was zero.
1887 */
1888 if (*status == -EREMOTEIO)
1889 *status = 0;
1890 }
1891 } else {
1892 /* Slow path - walk the list, starting from the dequeue
1893 * pointer, to get the actual length transferred.
1894 */
1895 td->urb->actual_length = 0;
1896 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1897 cur_trb != event_trb;
1898 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1899 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1900 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
1901 td->urb->actual_length +=
1902 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1903 }
1904 /* If the ring didn't stop on a Link or No-op TRB, add
1905 * in the actual bytes transferred from the Normal TRB
1906 */
1907 if (trb_comp_code != COMP_STOP_INVAL)
1908 td->urb->actual_length +=
1909 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1910 TRB_LEN(le32_to_cpu(event->transfer_len));
1911 }
1912
1913 return finish_td(xhci, td, event_trb, event, ep, status, false);
1914}
1915
1916/*
1917 * If this function returns an error condition, it means it got a Transfer
1918 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1919 * At this point, the host controller is probably hosed and should be reset.
1920 */
1921static int handle_tx_event(struct xhci_hcd *xhci,
1922 struct xhci_transfer_event *event)
1923{
1924 struct xhci_virt_device *xdev;
1925 struct xhci_virt_ep *ep;
1926 struct xhci_ring *ep_ring;
1927 unsigned int slot_id;
1928 int ep_index;
1929 struct xhci_td *td = NULL;
1930 dma_addr_t event_dma;
1931 struct xhci_segment *event_seg;
1932 union xhci_trb *event_trb;
1933 struct urb *urb = NULL;
1934 int status = -EINPROGRESS;
1935 struct urb_priv *urb_priv;
1936 struct xhci_ep_ctx *ep_ctx;
1937 struct list_head *tmp;
1938 u32 trb_comp_code;
1939 int ret = 0;
1940 int td_num = 0;
1941
1942 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1943 xdev = xhci->devs[slot_id];
1944 if (!xdev) {
1945 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1946 return -ENODEV;
1947 }
1948
1949 /* Endpoint ID is 1 based, our index is zero based */
1950 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1951 ep = &xdev->eps[ep_index];
1952 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1953 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1954 if (!ep_ring ||
1955 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
1956 EP_STATE_DISABLED) {
1957 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
1958 "or incorrect stream ring\n");
1959 return -ENODEV;
1960 }
1961
1962 /* Count current td numbers if ep->skip is set */
1963 if (ep->skip) {
1964 list_for_each(tmp, &ep_ring->td_list)
1965 td_num++;
1966 }
1967
1968 event_dma = le64_to_cpu(event->buffer);
1969 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1970 /* Look for common error cases */
1971 switch (trb_comp_code) {
1972 /* Skip codes that require special handling depending on
1973 * transfer type
1974 */
1975 case COMP_SUCCESS:
1976 case COMP_SHORT_TX:
1977 break;
1978 case COMP_STOP:
1979 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1980 break;
1981 case COMP_STOP_INVAL:
1982 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1983 break;
1984 case COMP_STALL:
1985 xhci_warn(xhci, "WARN: Stalled endpoint\n");
1986 ep->ep_state |= EP_HALTED;
1987 status = -EPIPE;
1988 break;
1989 case COMP_TRB_ERR:
1990 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
1991 status = -EILSEQ;
1992 break;
1993 case COMP_SPLIT_ERR:
1994 case COMP_TX_ERR:
1995 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
1996 status = -EPROTO;
1997 break;
1998 case COMP_BABBLE:
1999 xhci_warn(xhci, "WARN: babble error on endpoint\n");
2000 status = -EOVERFLOW;
2001 break;
2002 case COMP_DB_ERR:
2003 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2004 status = -ENOSR;
2005 break;
2006 case COMP_BW_OVER:
2007 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2008 break;
2009 case COMP_BUFF_OVER:
2010 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2011 break;
2012 case COMP_UNDERRUN:
2013 /*
2014 * When the Isoch ring is empty, the xHC will generate
2015 * a Ring Overrun Event for IN Isoch endpoint or Ring
2016 * Underrun Event for OUT Isoch endpoint.
2017 */
2018 xhci_dbg(xhci, "underrun event on endpoint\n");
2019 if (!list_empty(&ep_ring->td_list))
2020 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2021 "still with TDs queued?\n",
2022 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2023 ep_index);
2024 goto cleanup;
2025 case COMP_OVERRUN:
2026 xhci_dbg(xhci, "overrun event on endpoint\n");
2027 if (!list_empty(&ep_ring->td_list))
2028 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2029 "still with TDs queued?\n",
2030 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2031 ep_index);
2032 goto cleanup;
2033 case COMP_DEV_ERR:
2034 xhci_warn(xhci, "WARN: detect an incompatible device");
2035 status = -EPROTO;
2036 break;
2037 case COMP_MISSED_INT:
2038 /*
2039 * When encounter missed service error, one or more isoc tds
2040 * may be missed by xHC.
2041 * Set skip flag of the ep_ring; Complete the missed tds as
2042 * short transfer when process the ep_ring next time.
2043 */
2044 ep->skip = true;
2045 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2046 goto cleanup;
2047 default:
2048 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2049 status = 0;
2050 break;
2051 }
2052 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2053 "busted\n");
2054 goto cleanup;
2055 }
2056
2057 do {
2058 /* This TRB should be in the TD at the head of this ring's
2059 * TD list.
2060 */
2061 if (list_empty(&ep_ring->td_list)) {
2062 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
2063 "with no TDs queued?\n",
2064 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2065 ep_index);
2066 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2067 (le32_to_cpu(event->flags) &
2068 TRB_TYPE_BITMASK)>>10);
2069 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2070 if (ep->skip) {
2071 ep->skip = false;
2072 xhci_dbg(xhci, "td_list is empty while skip "
2073 "flag set. Clear skip flag.\n");
2074 }
2075 ret = 0;
2076 goto cleanup;
2077 }
2078
2079 /* We've skipped all the TDs on the ep ring when ep->skip set */
2080 if (ep->skip && td_num == 0) {
2081 ep->skip = false;
2082 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2083 "Clear skip flag.\n");
2084 ret = 0;
2085 goto cleanup;
2086 }
2087
2088 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2089 if (ep->skip)
2090 td_num--;
2091
2092 /* Is this a TRB in the currently executing TD? */
2093 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2094 td->last_trb, event_dma);
2095
2096 /*
2097 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2098 * is not in the current TD pointed by ep_ring->dequeue because
2099 * that the hardware dequeue pointer still at the previous TRB
2100 * of the current TD. The previous TRB maybe a Link TD or the
2101 * last TRB of the previous TD. The command completion handle
2102 * will take care the rest.
2103 */
2104 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2105 ret = 0;
2106 goto cleanup;
2107 }
2108
2109 if (!event_seg) {
2110 if (!ep->skip ||
2111 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2112 /* Some host controllers give a spurious
2113 * successful event after a short transfer.
2114 * Ignore it.
2115 */
2116 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2117 ep_ring->last_td_was_short) {
2118 ep_ring->last_td_was_short = false;
2119 ret = 0;
2120 goto cleanup;
2121 }
2122 /* HC is busted, give up! */
2123 xhci_err(xhci,
2124 "ERROR Transfer event TRB DMA ptr not "
2125 "part of current TD\n");
2126 return -ESHUTDOWN;
2127 }
2128
2129 ret = skip_isoc_td(xhci, td, event, ep, &status);
2130 goto cleanup;
2131 }
2132 if (trb_comp_code == COMP_SHORT_TX)
2133 ep_ring->last_td_was_short = true;
2134 else
2135 ep_ring->last_td_was_short = false;
2136
2137 if (ep->skip) {
2138 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2139 ep->skip = false;
2140 }
2141
2142 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2143 sizeof(*event_trb)];
2144 /*
2145 * No-op TRB should not trigger interrupts.
2146 * If event_trb is a no-op TRB, it means the
2147 * corresponding TD has been cancelled. Just ignore
2148 * the TD.
2149 */
2150 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2151 xhci_dbg(xhci,
2152 "event_trb is a no-op TRB. Skip it\n");
2153 goto cleanup;
2154 }
2155
2156 /* Now update the urb's actual_length and give back to
2157 * the core
2158 */
2159 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2160 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2161 &status);
2162 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2163 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2164 &status);
2165 else
2166 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2167 ep, &status);
2168
2169cleanup:
2170 /*
2171 * Do not update event ring dequeue pointer if ep->skip is set.
2172 * Will roll back to continue process missed tds.
2173 */
2174 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2175 inc_deq(xhci, xhci->event_ring, true);
2176 }
2177
2178 if (ret) {
2179 urb = td->urb;
2180 urb_priv = urb->hcpriv;
2181 /* Leave the TD around for the reset endpoint function
2182 * to use(but only if it's not a control endpoint,
2183 * since we already queued the Set TR dequeue pointer
2184 * command for stalled control endpoints).
2185 */
2186 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2187 (trb_comp_code != COMP_STALL &&
2188 trb_comp_code != COMP_BABBLE))
2189 xhci_urb_free_priv(xhci, urb_priv);
2190
2191 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2192 if ((urb->actual_length != urb->transfer_buffer_length &&
2193 (urb->transfer_flags &
2194 URB_SHORT_NOT_OK)) ||
2195 status != 0)
2196 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2197 "expected = %x, status = %d\n",
2198 urb, urb->actual_length,
2199 urb->transfer_buffer_length,
2200 status);
2201 spin_unlock(&xhci->lock);
2202 /* EHCI, UHCI, and OHCI always unconditionally set the
2203 * urb->status of an isochronous endpoint to 0.
2204 */
2205 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2206 status = 0;
2207 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2208 spin_lock(&xhci->lock);
2209 }
2210
2211 /*
2212 * If ep->skip is set, it means there are missed tds on the
2213 * endpoint ring need to take care of.
2214 * Process them as short transfer until reach the td pointed by
2215 * the event.
2216 */
2217 } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2218
2219 return 0;
2220}
2221
2222/*
2223 * This function handles all OS-owned events on the event ring. It may drop
2224 * xhci->lock between event processing (e.g. to pass up port status changes).
2225 * Returns >0 for "possibly more events to process" (caller should call again),
2226 * otherwise 0 if done. In future, <0 returns should indicate error code.
2227 */
2228static int xhci_handle_event(struct xhci_hcd *xhci)
2229{
2230 union xhci_trb *event;
2231 int update_ptrs = 1;
2232 int ret;
2233
2234 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2235 xhci->error_bitmask |= 1 << 1;
2236 return 0;
2237 }
2238
2239 event = xhci->event_ring->dequeue;
2240 /* Does the HC or OS own the TRB? */
2241 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2242 xhci->event_ring->cycle_state) {
2243 xhci->error_bitmask |= 1 << 2;
2244 return 0;
2245 }
2246
2247 /*
2248 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2249 * speculative reads of the event's flags/data below.
2250 */
2251 rmb();
2252 /* FIXME: Handle more event types. */
2253 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2254 case TRB_TYPE(TRB_COMPLETION):
2255 handle_cmd_completion(xhci, &event->event_cmd);
2256 break;
2257 case TRB_TYPE(TRB_PORT_STATUS):
2258 handle_port_status(xhci, event);
2259 update_ptrs = 0;
2260 break;
2261 case TRB_TYPE(TRB_TRANSFER):
2262 ret = handle_tx_event(xhci, &event->trans_event);
2263 if (ret < 0)
2264 xhci->error_bitmask |= 1 << 9;
2265 else
2266 update_ptrs = 0;
2267 break;
2268 default:
2269 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2270 TRB_TYPE(48))
2271 handle_vendor_event(xhci, event);
2272 else
2273 xhci->error_bitmask |= 1 << 3;
2274 }
2275 /* Any of the above functions may drop and re-acquire the lock, so check
2276 * to make sure a watchdog timer didn't mark the host as non-responsive.
2277 */
2278 if (xhci->xhc_state & XHCI_STATE_DYING) {
2279 xhci_dbg(xhci, "xHCI host dying, returning from "
2280 "event handler.\n");
2281 return 0;
2282 }
2283
2284 if (update_ptrs)
2285 /* Update SW event ring dequeue pointer */
2286 inc_deq(xhci, xhci->event_ring, true);
2287
2288 /* Are there more items on the event ring? Caller will call us again to
2289 * check.
2290 */
2291 return 1;
2292}
2293
2294/*
2295 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2296 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2297 * indicators of an event TRB error, but we check the status *first* to be safe.
2298 */
2299irqreturn_t xhci_irq(struct usb_hcd *hcd)
2300{
2301 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2302 u32 status;
2303 union xhci_trb *trb;
2304 u64 temp_64;
2305 union xhci_trb *event_ring_deq;
2306 dma_addr_t deq;
2307
2308 spin_lock(&xhci->lock);
2309 trb = xhci->event_ring->dequeue;
2310 /* Check if the xHC generated the interrupt, or the irq is shared */
2311 status = xhci_readl(xhci, &xhci->op_regs->status);
2312 if (status == 0xffffffff)
2313 goto hw_died;
2314
2315 if (!(status & STS_EINT)) {
2316 spin_unlock(&xhci->lock);
2317 return IRQ_NONE;
2318 }
2319 if (status & STS_FATAL) {
2320 xhci_warn(xhci, "WARNING: Host System Error\n");
2321 xhci_halt(xhci);
2322hw_died:
2323 spin_unlock(&xhci->lock);
2324 return -ESHUTDOWN;
2325 }
2326
2327 /*
2328 * Clear the op reg interrupt status first,
2329 * so we can receive interrupts from other MSI-X interrupters.
2330 * Write 1 to clear the interrupt status.
2331 */
2332 status |= STS_EINT;
2333 xhci_writel(xhci, status, &xhci->op_regs->status);
2334 /* FIXME when MSI-X is supported and there are multiple vectors */
2335 /* Clear the MSI-X event interrupt status */
2336
2337 if (hcd->irq != -1) {
2338 u32 irq_pending;
2339 /* Acknowledge the PCI interrupt */
2340 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2341 irq_pending |= 0x3;
2342 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2343 }
2344
2345 if (xhci->xhc_state & XHCI_STATE_DYING) {
2346 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2347 "Shouldn't IRQs be disabled?\n");
2348 /* Clear the event handler busy flag (RW1C);
2349 * the event ring should be empty.
2350 */
2351 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2352 xhci_write_64(xhci, temp_64 | ERST_EHB,
2353 &xhci->ir_set->erst_dequeue);
2354 spin_unlock(&xhci->lock);
2355
2356 return IRQ_HANDLED;
2357 }
2358
2359 event_ring_deq = xhci->event_ring->dequeue;
2360 /* FIXME this should be a delayed service routine
2361 * that clears the EHB.
2362 */
2363 while (xhci_handle_event(xhci) > 0) {}
2364
2365 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2366 /* If necessary, update the HW's version of the event ring deq ptr. */
2367 if (event_ring_deq != xhci->event_ring->dequeue) {
2368 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2369 xhci->event_ring->dequeue);
2370 if (deq == 0)
2371 xhci_warn(xhci, "WARN something wrong with SW event "
2372 "ring dequeue ptr.\n");
2373 /* Update HC event ring dequeue pointer */
2374 temp_64 &= ERST_PTR_MASK;
2375 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2376 }
2377
2378 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2379 temp_64 |= ERST_EHB;
2380 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2381
2382 spin_unlock(&xhci->lock);
2383
2384 return IRQ_HANDLED;
2385}
2386
2387irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2388{
2389 irqreturn_t ret;
2390 struct xhci_hcd *xhci;
2391
2392 xhci = hcd_to_xhci(hcd);
2393 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2394 if (xhci->shared_hcd)
2395 set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags);
2396
2397 ret = xhci_irq(hcd);
2398
2399 return ret;
2400}
2401
2402/**** Endpoint Ring Operations ****/
2403
2404/*
2405 * Generic function for queueing a TRB on a ring.
2406 * The caller must have checked to make sure there's room on the ring.
2407 *
2408 * @more_trbs_coming: Will you enqueue more TRBs before calling
2409 * prepare_transfer()?
2410 */
2411static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2412 bool consumer, bool more_trbs_coming,
2413 u32 field1, u32 field2, u32 field3, u32 field4)
2414{
2415 struct xhci_generic_trb *trb;
2416
2417 trb = &ring->enqueue->generic;
2418 trb->field[0] = cpu_to_le32(field1);
2419 trb->field[1] = cpu_to_le32(field2);
2420 trb->field[2] = cpu_to_le32(field3);
2421 trb->field[3] = cpu_to_le32(field4);
2422 inc_enq(xhci, ring, consumer, more_trbs_coming);
2423}
2424
2425/*
2426 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2427 * FIXME allocate segments if the ring is full.
2428 */
2429static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2430 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2431{
2432 /* Make sure the endpoint has been added to xHC schedule */
2433 switch (ep_state) {
2434 case EP_STATE_DISABLED:
2435 /*
2436 * USB core changed config/interfaces without notifying us,
2437 * or hardware is reporting the wrong state.
2438 */
2439 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2440 return -ENOENT;
2441 case EP_STATE_ERROR:
2442 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2443 /* FIXME event handling code for error needs to clear it */
2444 /* XXX not sure if this should be -ENOENT or not */
2445 return -EINVAL;
2446 case EP_STATE_HALTED:
2447 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2448 case EP_STATE_STOPPED:
2449 case EP_STATE_RUNNING:
2450 break;
2451 default:
2452 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2453 /*
2454 * FIXME issue Configure Endpoint command to try to get the HC
2455 * back into a known state.
2456 */
2457 return -EINVAL;
2458 }
2459 if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2460 /* FIXME allocate more room */
2461 xhci_err(xhci, "ERROR no room on ep ring\n");
2462 return -ENOMEM;
2463 }
2464
2465 if (enqueue_is_link_trb(ep_ring)) {
2466 struct xhci_ring *ring = ep_ring;
2467 union xhci_trb *next;
2468
2469 next = ring->enqueue;
2470
2471 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2472 /* If we're not dealing with 0.95 hardware,
2473 * clear the chain bit.
2474 */
2475 if (!xhci_link_trb_quirk(xhci))
2476 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2477 else
2478 next->link.control |= cpu_to_le32(TRB_CHAIN);
2479
2480 wmb();
2481 next->link.control ^= cpu_to_le32(TRB_CYCLE);
2482
2483 /* Toggle the cycle bit after the last ring segment. */
2484 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2485 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2486 if (!in_interrupt()) {
2487 xhci_dbg(xhci, "queue_trb: Toggle cycle "
2488 "state for ring %p = %i\n",
2489 ring, (unsigned int)ring->cycle_state);
2490 }
2491 }
2492 ring->enq_seg = ring->enq_seg->next;
2493 ring->enqueue = ring->enq_seg->trbs;
2494 next = ring->enqueue;
2495 }
2496 }
2497
2498 return 0;
2499}
2500
2501static int prepare_transfer(struct xhci_hcd *xhci,
2502 struct xhci_virt_device *xdev,
2503 unsigned int ep_index,
2504 unsigned int stream_id,
2505 unsigned int num_trbs,
2506 struct urb *urb,
2507 unsigned int td_index,
2508 gfp_t mem_flags)
2509{
2510 int ret;
2511 struct urb_priv *urb_priv;
2512 struct xhci_td *td;
2513 struct xhci_ring *ep_ring;
2514 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2515
2516 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2517 if (!ep_ring) {
2518 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2519 stream_id);
2520 return -EINVAL;
2521 }
2522
2523 ret = prepare_ring(xhci, ep_ring,
2524 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2525 num_trbs, mem_flags);
2526 if (ret)
2527 return ret;
2528
2529 urb_priv = urb->hcpriv;
2530 td = urb_priv->td[td_index];
2531
2532 INIT_LIST_HEAD(&td->td_list);
2533 INIT_LIST_HEAD(&td->cancelled_td_list);
2534
2535 if (td_index == 0) {
2536 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2537 if (unlikely(ret))
2538 return ret;
2539 }
2540
2541 td->urb = urb;
2542 /* Add this TD to the tail of the endpoint ring's TD list */
2543 list_add_tail(&td->td_list, &ep_ring->td_list);
2544 td->start_seg = ep_ring->enq_seg;
2545 td->first_trb = ep_ring->enqueue;
2546
2547 urb_priv->td[td_index] = td;
2548
2549 return 0;
2550}
2551
2552static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2553{
2554 int num_sgs, num_trbs, running_total, temp, i;
2555 struct scatterlist *sg;
2556
2557 sg = NULL;
2558 num_sgs = urb->num_sgs;
2559 temp = urb->transfer_buffer_length;
2560
2561 xhci_dbg(xhci, "count sg list trbs: \n");
2562 num_trbs = 0;
2563 for_each_sg(urb->sg, sg, num_sgs, i) {
2564 unsigned int previous_total_trbs = num_trbs;
2565 unsigned int len = sg_dma_len(sg);
2566
2567 /* Scatter gather list entries may cross 64KB boundaries */
2568 running_total = TRB_MAX_BUFF_SIZE -
2569 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2570 running_total &= TRB_MAX_BUFF_SIZE - 1;
2571 if (running_total != 0)
2572 num_trbs++;
2573
2574 /* How many more 64KB chunks to transfer, how many more TRBs? */
2575 while (running_total < sg_dma_len(sg) && running_total < temp) {
2576 num_trbs++;
2577 running_total += TRB_MAX_BUFF_SIZE;
2578 }
2579 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2580 i, (unsigned long long)sg_dma_address(sg),
2581 len, len, num_trbs - previous_total_trbs);
2582
2583 len = min_t(int, len, temp);
2584 temp -= len;
2585 if (temp == 0)
2586 break;
2587 }
2588 xhci_dbg(xhci, "\n");
2589 if (!in_interrupt())
2590 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2591 "num_trbs = %d\n",
2592 urb->ep->desc.bEndpointAddress,
2593 urb->transfer_buffer_length,
2594 num_trbs);
2595 return num_trbs;
2596}
2597
2598static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2599{
2600 if (num_trbs != 0)
2601 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2602 "TRBs, %d left\n", __func__,
2603 urb->ep->desc.bEndpointAddress, num_trbs);
2604 if (running_total != urb->transfer_buffer_length)
2605 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2606 "queued %#x (%d), asked for %#x (%d)\n",
2607 __func__,
2608 urb->ep->desc.bEndpointAddress,
2609 running_total, running_total,
2610 urb->transfer_buffer_length,
2611 urb->transfer_buffer_length);
2612}
2613
2614static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2615 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2616 struct xhci_generic_trb *start_trb)
2617{
2618 /*
2619 * Pass all the TRBs to the hardware at once and make sure this write
2620 * isn't reordered.
2621 */
2622 wmb();
2623 if (start_cycle)
2624 start_trb->field[3] |= cpu_to_le32(start_cycle);
2625 else
2626 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2627 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2628}
2629
2630/*
2631 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2632 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2633 * (comprised of sg list entries) can take several service intervals to
2634 * transmit.
2635 */
2636int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2637 struct urb *urb, int slot_id, unsigned int ep_index)
2638{
2639 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2640 xhci->devs[slot_id]->out_ctx, ep_index);
2641 int xhci_interval;
2642 int ep_interval;
2643
2644 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2645 ep_interval = urb->interval;
2646 /* Convert to microframes */
2647 if (urb->dev->speed == USB_SPEED_LOW ||
2648 urb->dev->speed == USB_SPEED_FULL)
2649 ep_interval *= 8;
2650 /* FIXME change this to a warning and a suggestion to use the new API
2651 * to set the polling interval (once the API is added).
2652 */
2653 if (xhci_interval != ep_interval) {
2654 if (printk_ratelimit())
2655 dev_dbg(&urb->dev->dev, "Driver uses different interval"
2656 " (%d microframe%s) than xHCI "
2657 "(%d microframe%s)\n",
2658 ep_interval,
2659 ep_interval == 1 ? "" : "s",
2660 xhci_interval,
2661 xhci_interval == 1 ? "" : "s");
2662 urb->interval = xhci_interval;
2663 /* Convert back to frames for LS/FS devices */
2664 if (urb->dev->speed == USB_SPEED_LOW ||
2665 urb->dev->speed == USB_SPEED_FULL)
2666 urb->interval /= 8;
2667 }
2668 return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2669}
2670
2671/*
2672 * The TD size is the number of bytes remaining in the TD (including this TRB),
2673 * right shifted by 10.
2674 * It must fit in bits 21:17, so it can't be bigger than 31.
2675 */
2676static u32 xhci_td_remainder(unsigned int remainder)
2677{
2678 u32 max = (1 << (21 - 17 + 1)) - 1;
2679
2680 if ((remainder >> 10) >= max)
2681 return max << 17;
2682 else
2683 return (remainder >> 10) << 17;
2684}
2685
2686/*
2687 * For xHCI 1.0 host controllers, TD size is the number of packets remaining in
2688 * the TD (*not* including this TRB).
2689 *
2690 * Total TD packet count = total_packet_count =
2691 * roundup(TD size in bytes / wMaxPacketSize)
2692 *
2693 * Packets transferred up to and including this TRB = packets_transferred =
2694 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
2695 *
2696 * TD size = total_packet_count - packets_transferred
2697 *
2698 * It must fit in bits 21:17, so it can't be bigger than 31.
2699 */
2700
2701static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
2702 unsigned int total_packet_count, struct urb *urb)
2703{
2704 int packets_transferred;
2705
2706 /* One TRB with a zero-length data packet. */
2707 if (running_total == 0 && trb_buff_len == 0)
2708 return 0;
2709
2710 /* All the TRB queueing functions don't count the current TRB in
2711 * running_total.
2712 */
2713 packets_transferred = (running_total + trb_buff_len) /
2714 le16_to_cpu(urb->ep->desc.wMaxPacketSize);
2715
2716 return xhci_td_remainder(total_packet_count - packets_transferred);
2717}
2718
2719static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2720 struct urb *urb, int slot_id, unsigned int ep_index)
2721{
2722 struct xhci_ring *ep_ring;
2723 unsigned int num_trbs;
2724 struct urb_priv *urb_priv;
2725 struct xhci_td *td;
2726 struct scatterlist *sg;
2727 int num_sgs;
2728 int trb_buff_len, this_sg_len, running_total;
2729 unsigned int total_packet_count;
2730 bool first_trb;
2731 u64 addr;
2732 bool more_trbs_coming;
2733
2734 struct xhci_generic_trb *start_trb;
2735 int start_cycle;
2736
2737 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2738 if (!ep_ring)
2739 return -EINVAL;
2740
2741 num_trbs = count_sg_trbs_needed(xhci, urb);
2742 num_sgs = urb->num_sgs;
2743 total_packet_count = roundup(urb->transfer_buffer_length,
2744 le16_to_cpu(urb->ep->desc.wMaxPacketSize));
2745
2746 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
2747 ep_index, urb->stream_id,
2748 num_trbs, urb, 0, mem_flags);
2749 if (trb_buff_len < 0)
2750 return trb_buff_len;
2751
2752 urb_priv = urb->hcpriv;
2753 td = urb_priv->td[0];
2754
2755 /*
2756 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2757 * until we've finished creating all the other TRBs. The ring's cycle
2758 * state may change as we enqueue the other TRBs, so save it too.
2759 */
2760 start_trb = &ep_ring->enqueue->generic;
2761 start_cycle = ep_ring->cycle_state;
2762
2763 running_total = 0;
2764 /*
2765 * How much data is in the first TRB?
2766 *
2767 * There are three forces at work for TRB buffer pointers and lengths:
2768 * 1. We don't want to walk off the end of this sg-list entry buffer.
2769 * 2. The transfer length that the driver requested may be smaller than
2770 * the amount of memory allocated for this scatter-gather list.
2771 * 3. TRBs buffers can't cross 64KB boundaries.
2772 */
2773 sg = urb->sg;
2774 addr = (u64) sg_dma_address(sg);
2775 this_sg_len = sg_dma_len(sg);
2776 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
2777 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2778 if (trb_buff_len > urb->transfer_buffer_length)
2779 trb_buff_len = urb->transfer_buffer_length;
2780 xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
2781 trb_buff_len);
2782
2783 first_trb = true;
2784 /* Queue the first TRB, even if it's zero-length */
2785 do {
2786 u32 field = 0;
2787 u32 length_field = 0;
2788 u32 remainder = 0;
2789
2790 /* Don't change the cycle bit of the first TRB until later */
2791 if (first_trb) {
2792 first_trb = false;
2793 if (start_cycle == 0)
2794 field |= 0x1;
2795 } else
2796 field |= ep_ring->cycle_state;
2797
2798 /* Chain all the TRBs together; clear the chain bit in the last
2799 * TRB to indicate it's the last TRB in the chain.
2800 */
2801 if (num_trbs > 1) {
2802 field |= TRB_CHAIN;
2803 } else {
2804 /* FIXME - add check for ZERO_PACKET flag before this */
2805 td->last_trb = ep_ring->enqueue;
2806 field |= TRB_IOC;
2807 }
2808
2809 /* Only set interrupt on short packet for IN endpoints */
2810 if (usb_urb_dir_in(urb))
2811 field |= TRB_ISP;
2812
2813 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
2814 "64KB boundary at %#x, end dma = %#x\n",
2815 (unsigned int) addr, trb_buff_len, trb_buff_len,
2816 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2817 (unsigned int) addr + trb_buff_len);
2818 if (TRB_MAX_BUFF_SIZE -
2819 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
2820 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2821 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2822 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2823 (unsigned int) addr + trb_buff_len);
2824 }
2825
2826 /* Set the TRB length, TD size, and interrupter fields. */
2827 if (xhci->hci_version < 0x100) {
2828 remainder = xhci_td_remainder(
2829 urb->transfer_buffer_length -
2830 running_total);
2831 } else {
2832 remainder = xhci_v1_0_td_remainder(running_total,
2833 trb_buff_len, total_packet_count, urb);
2834 }
2835 length_field = TRB_LEN(trb_buff_len) |
2836 remainder |
2837 TRB_INTR_TARGET(0);
2838
2839 if (num_trbs > 1)
2840 more_trbs_coming = true;
2841 else
2842 more_trbs_coming = false;
2843 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2844 lower_32_bits(addr),
2845 upper_32_bits(addr),
2846 length_field,
2847 field | TRB_TYPE(TRB_NORMAL));
2848 --num_trbs;
2849 running_total += trb_buff_len;
2850
2851 /* Calculate length for next transfer --
2852 * Are we done queueing all the TRBs for this sg entry?
2853 */
2854 this_sg_len -= trb_buff_len;
2855 if (this_sg_len == 0) {
2856 --num_sgs;
2857 if (num_sgs == 0)
2858 break;
2859 sg = sg_next(sg);
2860 addr = (u64) sg_dma_address(sg);
2861 this_sg_len = sg_dma_len(sg);
2862 } else {
2863 addr += trb_buff_len;
2864 }
2865
2866 trb_buff_len = TRB_MAX_BUFF_SIZE -
2867 (addr & (TRB_MAX_BUFF_SIZE - 1));
2868 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2869 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2870 trb_buff_len =
2871 urb->transfer_buffer_length - running_total;
2872 } while (running_total < urb->transfer_buffer_length);
2873
2874 check_trb_math(urb, num_trbs, running_total);
2875 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2876 start_cycle, start_trb);
2877 return 0;
2878}
2879
2880/* This is very similar to what ehci-q.c qtd_fill() does */
2881int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2882 struct urb *urb, int slot_id, unsigned int ep_index)
2883{
2884 struct xhci_ring *ep_ring;
2885 struct urb_priv *urb_priv;
2886 struct xhci_td *td;
2887 int num_trbs;
2888 struct xhci_generic_trb *start_trb;
2889 bool first_trb;
2890 bool more_trbs_coming;
2891 int start_cycle;
2892 u32 field, length_field;
2893
2894 int running_total, trb_buff_len, ret;
2895 unsigned int total_packet_count;
2896 u64 addr;
2897
2898 if (urb->num_sgs)
2899 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2900
2901 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2902 if (!ep_ring)
2903 return -EINVAL;
2904
2905 num_trbs = 0;
2906 /* How much data is (potentially) left before the 64KB boundary? */
2907 running_total = TRB_MAX_BUFF_SIZE -
2908 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2909 running_total &= TRB_MAX_BUFF_SIZE - 1;
2910
2911 /* If there's some data on this 64KB chunk, or we have to send a
2912 * zero-length transfer, we need at least one TRB
2913 */
2914 if (running_total != 0 || urb->transfer_buffer_length == 0)
2915 num_trbs++;
2916 /* How many more 64KB chunks to transfer, how many more TRBs? */
2917 while (running_total < urb->transfer_buffer_length) {
2918 num_trbs++;
2919 running_total += TRB_MAX_BUFF_SIZE;
2920 }
2921 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2922
2923 if (!in_interrupt())
2924 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
2925 "addr = %#llx, num_trbs = %d\n",
2926 urb->ep->desc.bEndpointAddress,
2927 urb->transfer_buffer_length,
2928 urb->transfer_buffer_length,
2929 (unsigned long long)urb->transfer_dma,
2930 num_trbs);
2931
2932 ret = prepare_transfer(xhci, xhci->devs[slot_id],
2933 ep_index, urb->stream_id,
2934 num_trbs, urb, 0, mem_flags);
2935 if (ret < 0)
2936 return ret;
2937
2938 urb_priv = urb->hcpriv;
2939 td = urb_priv->td[0];
2940
2941 /*
2942 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2943 * until we've finished creating all the other TRBs. The ring's cycle
2944 * state may change as we enqueue the other TRBs, so save it too.
2945 */
2946 start_trb = &ep_ring->enqueue->generic;
2947 start_cycle = ep_ring->cycle_state;
2948
2949 running_total = 0;
2950 total_packet_count = roundup(urb->transfer_buffer_length,
2951 le16_to_cpu(urb->ep->desc.wMaxPacketSize));
2952 /* How much data is in the first TRB? */
2953 addr = (u64) urb->transfer_dma;
2954 trb_buff_len = TRB_MAX_BUFF_SIZE -
2955 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2956 if (trb_buff_len > urb->transfer_buffer_length)
2957 trb_buff_len = urb->transfer_buffer_length;
2958
2959 first_trb = true;
2960
2961 /* Queue the first TRB, even if it's zero-length */
2962 do {
2963 u32 remainder = 0;
2964 field = 0;
2965
2966 /* Don't change the cycle bit of the first TRB until later */
2967 if (first_trb) {
2968 first_trb = false;
2969 if (start_cycle == 0)
2970 field |= 0x1;
2971 } else
2972 field |= ep_ring->cycle_state;
2973
2974 /* Chain all the TRBs together; clear the chain bit in the last
2975 * TRB to indicate it's the last TRB in the chain.
2976 */
2977 if (num_trbs > 1) {
2978 field |= TRB_CHAIN;
2979 } else {
2980 /* FIXME - add check for ZERO_PACKET flag before this */
2981 td->last_trb = ep_ring->enqueue;
2982 field |= TRB_IOC;
2983 }
2984
2985 /* Only set interrupt on short packet for IN endpoints */
2986 if (usb_urb_dir_in(urb))
2987 field |= TRB_ISP;
2988
2989 /* Set the TRB length, TD size, and interrupter fields. */
2990 if (xhci->hci_version < 0x100) {
2991 remainder = xhci_td_remainder(
2992 urb->transfer_buffer_length -
2993 running_total);
2994 } else {
2995 remainder = xhci_v1_0_td_remainder(running_total,
2996 trb_buff_len, total_packet_count, urb);
2997 }
2998 length_field = TRB_LEN(trb_buff_len) |
2999 remainder |
3000 TRB_INTR_TARGET(0);
3001
3002 if (num_trbs > 1)
3003 more_trbs_coming = true;
3004 else
3005 more_trbs_coming = false;
3006 queue_trb(xhci, ep_ring, false, more_trbs_coming,
3007 lower_32_bits(addr),
3008 upper_32_bits(addr),
3009 length_field,
3010 field | TRB_TYPE(TRB_NORMAL));
3011 --num_trbs;
3012 running_total += trb_buff_len;
3013
3014 /* Calculate length for next transfer */
3015 addr += trb_buff_len;
3016 trb_buff_len = urb->transfer_buffer_length - running_total;
3017 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3018 trb_buff_len = TRB_MAX_BUFF_SIZE;
3019 } while (running_total < urb->transfer_buffer_length);
3020
3021 check_trb_math(urb, num_trbs, running_total);
3022 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3023 start_cycle, start_trb);
3024 return 0;
3025}
3026
3027/* Caller must have locked xhci->lock */
3028int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3029 struct urb *urb, int slot_id, unsigned int ep_index)
3030{
3031 struct xhci_ring *ep_ring;
3032 int num_trbs;
3033 int ret;
3034 struct usb_ctrlrequest *setup;
3035 struct xhci_generic_trb *start_trb;
3036 int start_cycle;
3037 u32 field, length_field;
3038 struct urb_priv *urb_priv;
3039 struct xhci_td *td;
3040
3041 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3042 if (!ep_ring)
3043 return -EINVAL;
3044
3045 /*
3046 * Need to copy setup packet into setup TRB, so we can't use the setup
3047 * DMA address.
3048 */
3049 if (!urb->setup_packet)
3050 return -EINVAL;
3051
3052 if (!in_interrupt())
3053 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
3054 slot_id, ep_index);
3055 /* 1 TRB for setup, 1 for status */
3056 num_trbs = 2;
3057 /*
3058 * Don't need to check if we need additional event data and normal TRBs,
3059 * since data in control transfers will never get bigger than 16MB
3060 * XXX: can we get a buffer that crosses 64KB boundaries?
3061 */
3062 if (urb->transfer_buffer_length > 0)
3063 num_trbs++;
3064 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3065 ep_index, urb->stream_id,
3066 num_trbs, urb, 0, mem_flags);
3067 if (ret < 0)
3068 return ret;
3069
3070 urb_priv = urb->hcpriv;
3071 td = urb_priv->td[0];
3072
3073 /*
3074 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3075 * until we've finished creating all the other TRBs. The ring's cycle
3076 * state may change as we enqueue the other TRBs, so save it too.
3077 */
3078 start_trb = &ep_ring->enqueue->generic;
3079 start_cycle = ep_ring->cycle_state;
3080
3081 /* Queue setup TRB - see section 6.4.1.2.1 */
3082 /* FIXME better way to translate setup_packet into two u32 fields? */
3083 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3084 field = 0;
3085 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3086 if (start_cycle == 0)
3087 field |= 0x1;
3088
3089 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3090 if (xhci->hci_version == 0x100) {
3091 if (urb->transfer_buffer_length > 0) {
3092 if (setup->bRequestType & USB_DIR_IN)
3093 field |= TRB_TX_TYPE(TRB_DATA_IN);
3094 else
3095 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3096 }
3097 }
3098
3099 queue_trb(xhci, ep_ring, false, true,
3100 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3101 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3102 TRB_LEN(8) | TRB_INTR_TARGET(0),
3103 /* Immediate data in pointer */
3104 field);
3105
3106 /* If there's data, queue data TRBs */
3107 /* Only set interrupt on short packet for IN endpoints */
3108 if (usb_urb_dir_in(urb))
3109 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3110 else
3111 field = TRB_TYPE(TRB_DATA);
3112
3113 length_field = TRB_LEN(urb->transfer_buffer_length) |
3114 xhci_td_remainder(urb->transfer_buffer_length) |
3115 TRB_INTR_TARGET(0);
3116 if (urb->transfer_buffer_length > 0) {
3117 if (setup->bRequestType & USB_DIR_IN)
3118 field |= TRB_DIR_IN;
3119 queue_trb(xhci, ep_ring, false, true,
3120 lower_32_bits(urb->transfer_dma),
3121 upper_32_bits(urb->transfer_dma),
3122 length_field,
3123 field | ep_ring->cycle_state);
3124 }
3125
3126 /* Save the DMA address of the last TRB in the TD */
3127 td->last_trb = ep_ring->enqueue;
3128
3129 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3130 /* If the device sent data, the status stage is an OUT transfer */
3131 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3132 field = 0;
3133 else
3134 field = TRB_DIR_IN;
3135 queue_trb(xhci, ep_ring, false, false,
3136 0,
3137 0,
3138 TRB_INTR_TARGET(0),
3139 /* Event on completion */
3140 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3141
3142 giveback_first_trb(xhci, slot_id, ep_index, 0,
3143 start_cycle, start_trb);
3144 return 0;
3145}
3146
3147static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3148 struct urb *urb, int i)
3149{
3150 int num_trbs = 0;
3151 u64 addr, td_len;
3152
3153 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3154 td_len = urb->iso_frame_desc[i].length;
3155
3156 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3157 TRB_MAX_BUFF_SIZE);
3158 if (num_trbs == 0)
3159 num_trbs++;
3160
3161 return num_trbs;
3162}
3163
3164/*
3165 * The transfer burst count field of the isochronous TRB defines the number of
3166 * bursts that are required to move all packets in this TD. Only SuperSpeed
3167 * devices can burst up to bMaxBurst number of packets per service interval.
3168 * This field is zero based, meaning a value of zero in the field means one
3169 * burst. Basically, for everything but SuperSpeed devices, this field will be
3170 * zero. Only xHCI 1.0 host controllers support this field.
3171 */
3172static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3173 struct usb_device *udev,
3174 struct urb *urb, unsigned int total_packet_count)
3175{
3176 unsigned int max_burst;
3177
3178 if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3179 return 0;
3180
3181 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3182 return roundup(total_packet_count, max_burst + 1) - 1;
3183}
3184
3185/*
3186 * Returns the number of packets in the last "burst" of packets. This field is
3187 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3188 * the last burst packet count is equal to the total number of packets in the
3189 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3190 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3191 * contain 1 to (bMaxBurst + 1) packets.
3192 */
3193static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3194 struct usb_device *udev,
3195 struct urb *urb, unsigned int total_packet_count)
3196{
3197 unsigned int max_burst;
3198 unsigned int residue;
3199
3200 if (xhci->hci_version < 0x100)
3201 return 0;
3202
3203 switch (udev->speed) {
3204 case USB_SPEED_SUPER:
3205 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3206 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3207 residue = total_packet_count % (max_burst + 1);
3208 /* If residue is zero, the last burst contains (max_burst + 1)
3209 * number of packets, but the TLBPC field is zero-based.
3210 */
3211 if (residue == 0)
3212 return max_burst;
3213 return residue - 1;
3214 default:
3215 if (total_packet_count == 0)
3216 return 0;
3217 return total_packet_count - 1;
3218 }
3219}
3220
3221/* This is for isoc transfer */
3222static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3223 struct urb *urb, int slot_id, unsigned int ep_index)
3224{
3225 struct xhci_ring *ep_ring;
3226 struct urb_priv *urb_priv;
3227 struct xhci_td *td;
3228 int num_tds, trbs_per_td;
3229 struct xhci_generic_trb *start_trb;
3230 bool first_trb;
3231 int start_cycle;
3232 u32 field, length_field;
3233 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3234 u64 start_addr, addr;
3235 int i, j;
3236 bool more_trbs_coming;
3237
3238 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3239
3240 num_tds = urb->number_of_packets;
3241 if (num_tds < 1) {
3242 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3243 return -EINVAL;
3244 }
3245
3246 if (!in_interrupt())
3247 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
3248 " addr = %#llx, num_tds = %d\n",
3249 urb->ep->desc.bEndpointAddress,
3250 urb->transfer_buffer_length,
3251 urb->transfer_buffer_length,
3252 (unsigned long long)urb->transfer_dma,
3253 num_tds);
3254
3255 start_addr = (u64) urb->transfer_dma;
3256 start_trb = &ep_ring->enqueue->generic;
3257 start_cycle = ep_ring->cycle_state;
3258
3259 urb_priv = urb->hcpriv;
3260 /* Queue the first TRB, even if it's zero-length */
3261 for (i = 0; i < num_tds; i++) {
3262 unsigned int total_packet_count;
3263 unsigned int burst_count;
3264 unsigned int residue;
3265
3266 first_trb = true;
3267 running_total = 0;
3268 addr = start_addr + urb->iso_frame_desc[i].offset;
3269 td_len = urb->iso_frame_desc[i].length;
3270 td_remain_len = td_len;
3271 total_packet_count = roundup(td_len,
3272 le16_to_cpu(urb->ep->desc.wMaxPacketSize));
3273 /* A zero-length transfer still involves at least one packet. */
3274 if (total_packet_count == 0)
3275 total_packet_count++;
3276 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3277 total_packet_count);
3278 residue = xhci_get_last_burst_packet_count(xhci,
3279 urb->dev, urb, total_packet_count);
3280
3281 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3282
3283 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3284 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3285 if (ret < 0) {
3286 if (i == 0)
3287 return ret;
3288 goto cleanup;
3289 }
3290
3291 td = urb_priv->td[i];
3292 for (j = 0; j < trbs_per_td; j++) {
3293 u32 remainder = 0;
3294 field = TRB_TBC(burst_count) | TRB_TLBPC(residue);
3295
3296 if (first_trb) {
3297 /* Queue the isoc TRB */
3298 field |= TRB_TYPE(TRB_ISOC);
3299 /* Assume URB_ISO_ASAP is set */
3300 field |= TRB_SIA;
3301 if (i == 0) {
3302 if (start_cycle == 0)
3303 field |= 0x1;
3304 } else
3305 field |= ep_ring->cycle_state;
3306 first_trb = false;
3307 } else {
3308 /* Queue other normal TRBs */
3309 field |= TRB_TYPE(TRB_NORMAL);
3310 field |= ep_ring->cycle_state;
3311 }
3312
3313 /* Only set interrupt on short packet for IN EPs */
3314 if (usb_urb_dir_in(urb))
3315 field |= TRB_ISP;
3316
3317 /* Chain all the TRBs together; clear the chain bit in
3318 * the last TRB to indicate it's the last TRB in the
3319 * chain.
3320 */
3321 if (j < trbs_per_td - 1) {
3322 field |= TRB_CHAIN;
3323 more_trbs_coming = true;
3324 } else {
3325 td->last_trb = ep_ring->enqueue;
3326 field |= TRB_IOC;
3327 if (xhci->hci_version == 0x100) {
3328 /* Set BEI bit except for the last td */
3329 if (i < num_tds - 1)
3330 field |= TRB_BEI;
3331 }
3332 more_trbs_coming = false;
3333 }
3334
3335 /* Calculate TRB length */
3336 trb_buff_len = TRB_MAX_BUFF_SIZE -
3337 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3338 if (trb_buff_len > td_remain_len)
3339 trb_buff_len = td_remain_len;
3340
3341 /* Set the TRB length, TD size, & interrupter fields. */
3342 if (xhci->hci_version < 0x100) {
3343 remainder = xhci_td_remainder(
3344 td_len - running_total);
3345 } else {
3346 remainder = xhci_v1_0_td_remainder(
3347 running_total, trb_buff_len,
3348 total_packet_count, urb);
3349 }
3350 length_field = TRB_LEN(trb_buff_len) |
3351 remainder |
3352 TRB_INTR_TARGET(0);
3353
3354 queue_trb(xhci, ep_ring, false, more_trbs_coming,
3355 lower_32_bits(addr),
3356 upper_32_bits(addr),
3357 length_field,
3358 field);
3359 running_total += trb_buff_len;
3360
3361 addr += trb_buff_len;
3362 td_remain_len -= trb_buff_len;
3363 }
3364
3365 /* Check TD length */
3366 if (running_total != td_len) {
3367 xhci_err(xhci, "ISOC TD length unmatch\n");
3368 return -EINVAL;
3369 }
3370 }
3371
3372 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3373 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3374 usb_amd_quirk_pll_disable();
3375 }
3376 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3377
3378 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3379 start_cycle, start_trb);
3380 return 0;
3381cleanup:
3382 /* Clean up a partially enqueued isoc transfer. */
3383
3384 for (i--; i >= 0; i--)
3385 list_del_init(&urb_priv->td[i]->td_list);
3386
3387 /* Use the first TD as a temporary variable to turn the TDs we've queued
3388 * into No-ops with a software-owned cycle bit. That way the hardware
3389 * won't accidentally start executing bogus TDs when we partially
3390 * overwrite them. td->first_trb and td->start_seg are already set.
3391 */
3392 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3393 /* Every TRB except the first & last will have its cycle bit flipped. */
3394 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3395
3396 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3397 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3398 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3399 ep_ring->cycle_state = start_cycle;
3400 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3401 return ret;
3402}
3403
3404/*
3405 * Check transfer ring to guarantee there is enough room for the urb.
3406 * Update ISO URB start_frame and interval.
3407 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3408 * update the urb->start_frame by now.
3409 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3410 */
3411int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3412 struct urb *urb, int slot_id, unsigned int ep_index)
3413{
3414 struct xhci_virt_device *xdev;
3415 struct xhci_ring *ep_ring;
3416 struct xhci_ep_ctx *ep_ctx;
3417 int start_frame;
3418 int xhci_interval;
3419 int ep_interval;
3420 int num_tds, num_trbs, i;
3421 int ret;
3422
3423 xdev = xhci->devs[slot_id];
3424 ep_ring = xdev->eps[ep_index].ring;
3425 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3426
3427 num_trbs = 0;
3428 num_tds = urb->number_of_packets;
3429 for (i = 0; i < num_tds; i++)
3430 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3431
3432 /* Check the ring to guarantee there is enough room for the whole urb.
3433 * Do not insert any td of the urb to the ring if the check failed.
3434 */
3435 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3436 num_trbs, mem_flags);
3437 if (ret)
3438 return ret;
3439
3440 start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3441 start_frame &= 0x3fff;
3442
3443 urb->start_frame = start_frame;
3444 if (urb->dev->speed == USB_SPEED_LOW ||
3445 urb->dev->speed == USB_SPEED_FULL)
3446 urb->start_frame >>= 3;
3447
3448 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3449 ep_interval = urb->interval;
3450 /* Convert to microframes */
3451 if (urb->dev->speed == USB_SPEED_LOW ||
3452 urb->dev->speed == USB_SPEED_FULL)
3453 ep_interval *= 8;
3454 /* FIXME change this to a warning and a suggestion to use the new API
3455 * to set the polling interval (once the API is added).
3456 */
3457 if (xhci_interval != ep_interval) {
3458 if (printk_ratelimit())
3459 dev_dbg(&urb->dev->dev, "Driver uses different interval"
3460 " (%d microframe%s) than xHCI "
3461 "(%d microframe%s)\n",
3462 ep_interval,
3463 ep_interval == 1 ? "" : "s",
3464 xhci_interval,
3465 xhci_interval == 1 ? "" : "s");
3466 urb->interval = xhci_interval;
3467 /* Convert back to frames for LS/FS devices */
3468 if (urb->dev->speed == USB_SPEED_LOW ||
3469 urb->dev->speed == USB_SPEED_FULL)
3470 urb->interval /= 8;
3471 }
3472 return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3473}
3474
3475/**** Command Ring Operations ****/
3476
3477/* Generic function for queueing a command TRB on the command ring.
3478 * Check to make sure there's room on the command ring for one command TRB.
3479 * Also check that there's room reserved for commands that must not fail.
3480 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3481 * then only check for the number of reserved spots.
3482 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3483 * because the command event handler may want to resubmit a failed command.
3484 */
3485static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3486 u32 field3, u32 field4, bool command_must_succeed)
3487{
3488 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3489 int ret;
3490
3491 if (!command_must_succeed)
3492 reserved_trbs++;
3493
3494 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3495 reserved_trbs, GFP_ATOMIC);
3496 if (ret < 0) {
3497 xhci_err(xhci, "ERR: No room for command on command ring\n");
3498 if (command_must_succeed)
3499 xhci_err(xhci, "ERR: Reserved TRB counting for "
3500 "unfailable commands failed.\n");
3501 return ret;
3502 }
3503 queue_trb(xhci, xhci->cmd_ring, false, false, field1, field2, field3,
3504 field4 | xhci->cmd_ring->cycle_state);
3505 return 0;
3506}
3507
3508/* Queue a slot enable or disable request on the command ring */
3509int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3510{
3511 return queue_command(xhci, 0, 0, 0,
3512 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3513}
3514
3515/* Queue an address device command TRB */
3516int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3517 u32 slot_id)
3518{
3519 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3520 upper_32_bits(in_ctx_ptr), 0,
3521 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3522 false);
3523}
3524
3525int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3526 u32 field1, u32 field2, u32 field3, u32 field4)
3527{
3528 return queue_command(xhci, field1, field2, field3, field4, false);
3529}
3530
3531/* Queue a reset device command TRB */
3532int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3533{
3534 return queue_command(xhci, 0, 0, 0,
3535 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3536 false);
3537}
3538
3539/* Queue a configure endpoint command TRB */
3540int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3541 u32 slot_id, bool command_must_succeed)
3542{
3543 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3544 upper_32_bits(in_ctx_ptr), 0,
3545 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3546 command_must_succeed);
3547}
3548
3549/* Queue an evaluate context command TRB */
3550int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3551 u32 slot_id)
3552{
3553 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3554 upper_32_bits(in_ctx_ptr), 0,
3555 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3556 false);
3557}
3558
3559/*
3560 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3561 * activity on an endpoint that is about to be suspended.
3562 */
3563int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3564 unsigned int ep_index, int suspend)
3565{
3566 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3567 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3568 u32 type = TRB_TYPE(TRB_STOP_RING);
3569 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3570
3571 return queue_command(xhci, 0, 0, 0,
3572 trb_slot_id | trb_ep_index | type | trb_suspend, false);
3573}
3574
3575/* Set Transfer Ring Dequeue Pointer command.
3576 * This should not be used for endpoints that have streams enabled.
3577 */
3578static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3579 unsigned int ep_index, unsigned int stream_id,
3580 struct xhci_segment *deq_seg,
3581 union xhci_trb *deq_ptr, u32 cycle_state)
3582{
3583 dma_addr_t addr;
3584 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3585 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3586 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3587 u32 type = TRB_TYPE(TRB_SET_DEQ);
3588 struct xhci_virt_ep *ep;
3589
3590 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3591 if (addr == 0) {
3592 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3593 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3594 deq_seg, deq_ptr);
3595 return 0;
3596 }
3597 ep = &xhci->devs[slot_id]->eps[ep_index];
3598 if ((ep->ep_state & SET_DEQ_PENDING)) {
3599 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3600 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3601 return 0;
3602 }
3603 ep->queued_deq_seg = deq_seg;
3604 ep->queued_deq_ptr = deq_ptr;
3605 return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3606 upper_32_bits(addr), trb_stream_id,
3607 trb_slot_id | trb_ep_index | type, false);
3608}
3609
3610int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3611 unsigned int ep_index)
3612{
3613 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3614 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3615 u32 type = TRB_TYPE(TRB_RESET_EP);
3616
3617 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3618 false);
3619}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * xHCI host controller driver
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11/*
12 * Ring initialization rules:
13 * 1. Each segment is initialized to zero, except for link TRBs.
14 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
15 * Consumer Cycle State (CCS), depending on ring function.
16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
17 *
18 * Ring behavior rules:
19 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
20 * least one free TRB in the ring. This is useful if you want to turn that
21 * into a link TRB and expand the ring.
22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
23 * link TRB, then load the pointer with the address in the link TRB. If the
24 * link TRB had its toggle bit set, you may need to update the ring cycle
25 * state (see cycle bit rules). You may have to do this multiple times
26 * until you reach a non-link TRB.
27 * 3. A ring is full if enqueue++ (for the definition of increment above)
28 * equals the dequeue pointer.
29 *
30 * Cycle bit rules:
31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
32 * in a link TRB, it must toggle the ring cycle state.
33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
34 * in a link TRB, it must toggle the ring cycle state.
35 *
36 * Producer rules:
37 * 1. Check if ring is full before you enqueue.
38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
39 * Update enqueue pointer between each write (which may update the ring
40 * cycle state).
41 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
42 * and endpoint rings. If HC is the producer for the event ring,
43 * and it generates an interrupt according to interrupt modulation rules.
44 *
45 * Consumer rules:
46 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
47 * the TRB is owned by the consumer.
48 * 2. Update dequeue pointer (which may update the ring cycle state) and
49 * continue processing TRBs until you reach a TRB which is not owned by you.
50 * 3. Notify the producer. SW is the consumer for the event ring, and it
51 * updates event ring dequeue pointer. HC is the consumer for the command and
52 * endpoint rings; it generates events on the event ring for these.
53 */
54
55#include <linux/scatterlist.h>
56#include <linux/slab.h>
57#include <linux/dma-mapping.h>
58#include "xhci.h"
59#include "xhci-trace.h"
60
61static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
62 u32 field1, u32 field2,
63 u32 field3, u32 field4, bool command_must_succeed);
64
65/*
66 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
67 * address of the TRB.
68 */
69dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
70 union xhci_trb *trb)
71{
72 unsigned long segment_offset;
73
74 if (!seg || !trb || trb < seg->trbs)
75 return 0;
76 /* offset in TRBs */
77 segment_offset = trb - seg->trbs;
78 if (segment_offset >= TRBS_PER_SEGMENT)
79 return 0;
80 return seg->dma + (segment_offset * sizeof(*trb));
81}
82
83static bool trb_is_noop(union xhci_trb *trb)
84{
85 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
86}
87
88static bool trb_is_link(union xhci_trb *trb)
89{
90 return TRB_TYPE_LINK_LE32(trb->link.control);
91}
92
93static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
94{
95 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
96}
97
98static bool last_trb_on_ring(struct xhci_ring *ring,
99 struct xhci_segment *seg, union xhci_trb *trb)
100{
101 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
102}
103
104static bool link_trb_toggles_cycle(union xhci_trb *trb)
105{
106 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
107}
108
109static bool last_td_in_urb(struct xhci_td *td)
110{
111 struct urb_priv *urb_priv = td->urb->hcpriv;
112
113 return urb_priv->num_tds_done == urb_priv->num_tds;
114}
115
116static bool unhandled_event_trb(struct xhci_ring *ring)
117{
118 return ((le32_to_cpu(ring->dequeue->event_cmd.flags) & TRB_CYCLE) ==
119 ring->cycle_state);
120}
121
122static void inc_td_cnt(struct urb *urb)
123{
124 struct urb_priv *urb_priv = urb->hcpriv;
125
126 urb_priv->num_tds_done++;
127}
128
129static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
130{
131 if (trb_is_link(trb)) {
132 /* unchain chained link TRBs */
133 trb->link.control &= cpu_to_le32(~TRB_CHAIN);
134 } else {
135 trb->generic.field[0] = 0;
136 trb->generic.field[1] = 0;
137 trb->generic.field[2] = 0;
138 /* Preserve only the cycle bit of this TRB */
139 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
140 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
141 }
142}
143
144/* Updates trb to point to the next TRB in the ring, and updates seg if the next
145 * TRB is in a new segment. This does not skip over link TRBs, and it does not
146 * effect the ring dequeue or enqueue pointers.
147 */
148static void next_trb(struct xhci_hcd *xhci,
149 struct xhci_ring *ring,
150 struct xhci_segment **seg,
151 union xhci_trb **trb)
152{
153 if (trb_is_link(*trb) || last_trb_on_seg(*seg, *trb)) {
154 *seg = (*seg)->next;
155 *trb = ((*seg)->trbs);
156 } else {
157 (*trb)++;
158 }
159}
160
161/*
162 * See Cycle bit rules. SW is the consumer for the event ring only.
163 */
164void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
165{
166 unsigned int link_trb_count = 0;
167
168 /* event ring doesn't have link trbs, check for last trb */
169 if (ring->type == TYPE_EVENT) {
170 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
171 ring->dequeue++;
172 goto out;
173 }
174 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
175 ring->cycle_state ^= 1;
176 ring->deq_seg = ring->deq_seg->next;
177 ring->dequeue = ring->deq_seg->trbs;
178 goto out;
179 }
180
181 /* All other rings have link trbs */
182 if (!trb_is_link(ring->dequeue)) {
183 if (last_trb_on_seg(ring->deq_seg, ring->dequeue))
184 xhci_warn(xhci, "Missing link TRB at end of segment\n");
185 else
186 ring->dequeue++;
187 }
188
189 while (trb_is_link(ring->dequeue)) {
190 ring->deq_seg = ring->deq_seg->next;
191 ring->dequeue = ring->deq_seg->trbs;
192
193 if (link_trb_count++ > ring->num_segs) {
194 xhci_warn(xhci, "Ring is an endless link TRB loop\n");
195 break;
196 }
197 }
198out:
199 trace_xhci_inc_deq(ring);
200
201 return;
202}
203
204/*
205 * See Cycle bit rules. SW is the consumer for the event ring only.
206 *
207 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
208 * chain bit is set), then set the chain bit in all the following link TRBs.
209 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
210 * have their chain bit cleared (so that each Link TRB is a separate TD).
211 *
212 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
213 * set, but other sections talk about dealing with the chain bit set. This was
214 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
215 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
216 *
217 * @more_trbs_coming: Will you enqueue more TRBs before calling
218 * prepare_transfer()?
219 */
220static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
221 bool more_trbs_coming)
222{
223 u32 chain;
224 union xhci_trb *next;
225 unsigned int link_trb_count = 0;
226
227 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
228
229 if (last_trb_on_seg(ring->enq_seg, ring->enqueue)) {
230 xhci_err(xhci, "Tried to move enqueue past ring segment\n");
231 return;
232 }
233
234 next = ++(ring->enqueue);
235
236 /* Update the dequeue pointer further if that was a link TRB */
237 while (trb_is_link(next)) {
238
239 /*
240 * If the caller doesn't plan on enqueueing more TDs before
241 * ringing the doorbell, then we don't want to give the link TRB
242 * to the hardware just yet. We'll give the link TRB back in
243 * prepare_ring() just before we enqueue the TD at the top of
244 * the ring.
245 */
246 if (!chain && !more_trbs_coming)
247 break;
248
249 /* If we're not dealing with 0.95 hardware or isoc rings on
250 * AMD 0.96 host, carry over the chain bit of the previous TRB
251 * (which may mean the chain bit is cleared).
252 */
253 if (!(ring->type == TYPE_ISOC &&
254 (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
255 !xhci_link_trb_quirk(xhci)) {
256 next->link.control &= cpu_to_le32(~TRB_CHAIN);
257 next->link.control |= cpu_to_le32(chain);
258 }
259 /* Give this link TRB to the hardware */
260 wmb();
261 next->link.control ^= cpu_to_le32(TRB_CYCLE);
262
263 /* Toggle the cycle bit after the last ring segment. */
264 if (link_trb_toggles_cycle(next))
265 ring->cycle_state ^= 1;
266
267 ring->enq_seg = ring->enq_seg->next;
268 ring->enqueue = ring->enq_seg->trbs;
269 next = ring->enqueue;
270
271 if (link_trb_count++ > ring->num_segs) {
272 xhci_warn(xhci, "%s: Ring link TRB loop\n", __func__);
273 break;
274 }
275 }
276
277 trace_xhci_inc_enq(ring);
278}
279
280/*
281 * Return number of free normal TRBs from enqueue to dequeue pointer on ring.
282 * Not counting an assumed link TRB at end of each TRBS_PER_SEGMENT sized segment.
283 * Only for transfer and command rings where driver is the producer, not for
284 * event rings.
285 */
286static unsigned int xhci_num_trbs_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
287{
288 struct xhci_segment *enq_seg = ring->enq_seg;
289 union xhci_trb *enq = ring->enqueue;
290 union xhci_trb *last_on_seg;
291 unsigned int free = 0;
292 int i = 0;
293
294 /* Ring might be empty even if enq != deq if enq is left on a link trb */
295 if (trb_is_link(enq)) {
296 enq_seg = enq_seg->next;
297 enq = enq_seg->trbs;
298 }
299
300 /* Empty ring, common case, don't walk the segments */
301 if (enq == ring->dequeue)
302 return ring->num_segs * (TRBS_PER_SEGMENT - 1);
303
304 do {
305 if (ring->deq_seg == enq_seg && ring->dequeue >= enq)
306 return free + (ring->dequeue - enq);
307 last_on_seg = &enq_seg->trbs[TRBS_PER_SEGMENT - 1];
308 free += last_on_seg - enq;
309 enq_seg = enq_seg->next;
310 enq = enq_seg->trbs;
311 } while (i++ <= ring->num_segs);
312
313 return free;
314}
315
316/*
317 * Check to see if there's room to enqueue num_trbs on the ring and make sure
318 * enqueue pointer will not advance into dequeue segment. See rules above.
319 * return number of new segments needed to ensure this.
320 */
321
322static unsigned int xhci_ring_expansion_needed(struct xhci_hcd *xhci, struct xhci_ring *ring,
323 unsigned int num_trbs)
324{
325 struct xhci_segment *seg;
326 int trbs_past_seg;
327 int enq_used;
328 int new_segs;
329
330 enq_used = ring->enqueue - ring->enq_seg->trbs;
331
332 /* how many trbs will be queued past the enqueue segment? */
333 trbs_past_seg = enq_used + num_trbs - (TRBS_PER_SEGMENT - 1);
334
335 /*
336 * Consider expanding the ring already if num_trbs fills the current
337 * segment (i.e. trbs_past_seg == 0), not only when num_trbs goes into
338 * the next segment. Avoids confusing full ring with special empty ring
339 * case below
340 */
341 if (trbs_past_seg < 0)
342 return 0;
343
344 /* Empty ring special case, enqueue stuck on link trb while dequeue advanced */
345 if (trb_is_link(ring->enqueue) && ring->enq_seg->next->trbs == ring->dequeue)
346 return 0;
347
348 new_segs = 1 + (trbs_past_seg / (TRBS_PER_SEGMENT - 1));
349 seg = ring->enq_seg;
350
351 while (new_segs > 0) {
352 seg = seg->next;
353 if (seg == ring->deq_seg) {
354 xhci_dbg(xhci, "Ring expansion by %d segments needed\n",
355 new_segs);
356 xhci_dbg(xhci, "Adding %d trbs moves enq %d trbs into deq seg\n",
357 num_trbs, trbs_past_seg % TRBS_PER_SEGMENT);
358 return new_segs;
359 }
360 new_segs--;
361 }
362
363 return 0;
364}
365
366/* Ring the host controller doorbell after placing a command on the ring */
367void xhci_ring_cmd_db(struct xhci_hcd *xhci)
368{
369 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
370 return;
371
372 xhci_dbg(xhci, "// Ding dong!\n");
373
374 trace_xhci_ring_host_doorbell(0, DB_VALUE_HOST);
375
376 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
377 /* Flush PCI posted writes */
378 readl(&xhci->dba->doorbell[0]);
379}
380
381static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci)
382{
383 return mod_delayed_work(system_wq, &xhci->cmd_timer,
384 msecs_to_jiffies(xhci->current_cmd->timeout_ms));
385}
386
387static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
388{
389 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
390 cmd_list);
391}
392
393/*
394 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
395 * If there are other commands waiting then restart the ring and kick the timer.
396 * This must be called with command ring stopped and xhci->lock held.
397 */
398static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
399 struct xhci_command *cur_cmd)
400{
401 struct xhci_command *i_cmd;
402
403 /* Turn all aborted commands in list to no-ops, then restart */
404 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
405
406 if (i_cmd->status != COMP_COMMAND_ABORTED)
407 continue;
408
409 i_cmd->status = COMP_COMMAND_RING_STOPPED;
410
411 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
412 i_cmd->command_trb);
413
414 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
415
416 /*
417 * caller waiting for completion is called when command
418 * completion event is received for these no-op commands
419 */
420 }
421
422 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
423
424 /* ring command ring doorbell to restart the command ring */
425 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
426 !(xhci->xhc_state & XHCI_STATE_DYING)) {
427 xhci->current_cmd = cur_cmd;
428 xhci_mod_cmd_timer(xhci);
429 xhci_ring_cmd_db(xhci);
430 }
431}
432
433/* Must be called with xhci->lock held, releases and aquires lock back */
434static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
435{
436 struct xhci_segment *new_seg = xhci->cmd_ring->deq_seg;
437 union xhci_trb *new_deq = xhci->cmd_ring->dequeue;
438 u64 crcr;
439 int ret;
440
441 xhci_dbg(xhci, "Abort command ring\n");
442
443 reinit_completion(&xhci->cmd_ring_stop_completion);
444
445 /*
446 * The control bits like command stop, abort are located in lower
447 * dword of the command ring control register.
448 * Some controllers require all 64 bits to be written to abort the ring.
449 * Make sure the upper dword is valid, pointing to the next command,
450 * avoiding corrupting the command ring pointer in case the command ring
451 * is stopped by the time the upper dword is written.
452 */
453 next_trb(xhci, NULL, &new_seg, &new_deq);
454 if (trb_is_link(new_deq))
455 next_trb(xhci, NULL, &new_seg, &new_deq);
456
457 crcr = xhci_trb_virt_to_dma(new_seg, new_deq);
458 xhci_write_64(xhci, crcr | CMD_RING_ABORT, &xhci->op_regs->cmd_ring);
459
460 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
461 * completion of the Command Abort operation. If CRR is not negated in 5
462 * seconds then driver handles it as if host died (-ENODEV).
463 * In the future we should distinguish between -ENODEV and -ETIMEDOUT
464 * and try to recover a -ETIMEDOUT with a host controller reset.
465 */
466 ret = xhci_handshake_check_state(xhci, &xhci->op_regs->cmd_ring,
467 CMD_RING_RUNNING, 0, 5 * 1000 * 1000,
468 XHCI_STATE_REMOVING);
469 if (ret < 0) {
470 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
471 xhci_halt(xhci);
472 xhci_hc_died(xhci);
473 return ret;
474 }
475 /*
476 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
477 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
478 * but the completion event in never sent. Wait 2 secs (arbitrary
479 * number) to handle those cases after negation of CMD_RING_RUNNING.
480 */
481 spin_unlock_irqrestore(&xhci->lock, flags);
482 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
483 msecs_to_jiffies(2000));
484 spin_lock_irqsave(&xhci->lock, flags);
485 if (!ret) {
486 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
487 xhci_cleanup_command_queue(xhci);
488 } else {
489 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
490 }
491 return 0;
492}
493
494void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
495 unsigned int slot_id,
496 unsigned int ep_index,
497 unsigned int stream_id)
498{
499 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
500 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
501 unsigned int ep_state = ep->ep_state;
502
503 /* Don't ring the doorbell for this endpoint if there are pending
504 * cancellations because we don't want to interrupt processing.
505 * We don't want to restart any stream rings if there's a set dequeue
506 * pointer command pending because the device can choose to start any
507 * stream once the endpoint is on the HW schedule.
508 */
509 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
510 (ep_state & EP_HALTED) || (ep_state & EP_CLEARING_TT))
511 return;
512
513 trace_xhci_ring_ep_doorbell(slot_id, DB_VALUE(ep_index, stream_id));
514
515 writel(DB_VALUE(ep_index, stream_id), db_addr);
516 /* flush the write */
517 readl(db_addr);
518}
519
520/* Ring the doorbell for any rings with pending URBs */
521static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
522 unsigned int slot_id,
523 unsigned int ep_index)
524{
525 unsigned int stream_id;
526 struct xhci_virt_ep *ep;
527
528 ep = &xhci->devs[slot_id]->eps[ep_index];
529
530 /* A ring has pending URBs if its TD list is not empty */
531 if (!(ep->ep_state & EP_HAS_STREAMS)) {
532 if (ep->ring && !(list_empty(&ep->ring->td_list)))
533 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
534 return;
535 }
536
537 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
538 stream_id++) {
539 struct xhci_stream_info *stream_info = ep->stream_info;
540 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
541 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
542 stream_id);
543 }
544}
545
546void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
547 unsigned int slot_id,
548 unsigned int ep_index)
549{
550 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
551}
552
553static struct xhci_virt_ep *xhci_get_virt_ep(struct xhci_hcd *xhci,
554 unsigned int slot_id,
555 unsigned int ep_index)
556{
557 if (slot_id == 0 || slot_id >= MAX_HC_SLOTS) {
558 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
559 return NULL;
560 }
561 if (ep_index >= EP_CTX_PER_DEV) {
562 xhci_warn(xhci, "Invalid endpoint index %u\n", ep_index);
563 return NULL;
564 }
565 if (!xhci->devs[slot_id]) {
566 xhci_warn(xhci, "No xhci virt device for slot_id %u\n", slot_id);
567 return NULL;
568 }
569
570 return &xhci->devs[slot_id]->eps[ep_index];
571}
572
573static struct xhci_ring *xhci_virt_ep_to_ring(struct xhci_hcd *xhci,
574 struct xhci_virt_ep *ep,
575 unsigned int stream_id)
576{
577 /* common case, no streams */
578 if (!(ep->ep_state & EP_HAS_STREAMS))
579 return ep->ring;
580
581 if (!ep->stream_info)
582 return NULL;
583
584 if (stream_id == 0 || stream_id >= ep->stream_info->num_streams) {
585 xhci_warn(xhci, "Invalid stream_id %u request for slot_id %u ep_index %u\n",
586 stream_id, ep->vdev->slot_id, ep->ep_index);
587 return NULL;
588 }
589
590 return ep->stream_info->stream_rings[stream_id];
591}
592
593/* Get the right ring for the given slot_id, ep_index and stream_id.
594 * If the endpoint supports streams, boundary check the URB's stream ID.
595 * If the endpoint doesn't support streams, return the singular endpoint ring.
596 */
597struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
598 unsigned int slot_id, unsigned int ep_index,
599 unsigned int stream_id)
600{
601 struct xhci_virt_ep *ep;
602
603 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
604 if (!ep)
605 return NULL;
606
607 return xhci_virt_ep_to_ring(xhci, ep, stream_id);
608}
609
610
611/*
612 * Get the hw dequeue pointer xHC stopped on, either directly from the
613 * endpoint context, or if streams are in use from the stream context.
614 * The returned hw_dequeue contains the lowest four bits with cycle state
615 * and possbile stream context type.
616 */
617static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
618 unsigned int ep_index, unsigned int stream_id)
619{
620 struct xhci_ep_ctx *ep_ctx;
621 struct xhci_stream_ctx *st_ctx;
622 struct xhci_virt_ep *ep;
623
624 ep = &vdev->eps[ep_index];
625
626 if (ep->ep_state & EP_HAS_STREAMS) {
627 st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
628 return le64_to_cpu(st_ctx->stream_ring);
629 }
630 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
631 return le64_to_cpu(ep_ctx->deq);
632}
633
634static int xhci_move_dequeue_past_td(struct xhci_hcd *xhci,
635 unsigned int slot_id, unsigned int ep_index,
636 unsigned int stream_id, struct xhci_td *td)
637{
638 struct xhci_virt_device *dev = xhci->devs[slot_id];
639 struct xhci_virt_ep *ep = &dev->eps[ep_index];
640 struct xhci_ring *ep_ring;
641 struct xhci_command *cmd;
642 struct xhci_segment *new_seg;
643 union xhci_trb *new_deq;
644 int new_cycle;
645 dma_addr_t addr;
646 u64 hw_dequeue;
647 bool cycle_found = false;
648 bool td_last_trb_found = false;
649 u32 trb_sct = 0;
650 int ret;
651
652 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
653 ep_index, stream_id);
654 if (!ep_ring) {
655 xhci_warn(xhci, "WARN can't find new dequeue, invalid stream ID %u\n",
656 stream_id);
657 return -ENODEV;
658 }
659 /*
660 * A cancelled TD can complete with a stall if HW cached the trb.
661 * In this case driver can't find td, but if the ring is empty we
662 * can move the dequeue pointer to the current enqueue position.
663 * We shouldn't hit this anymore as cached cancelled TRBs are given back
664 * after clearing the cache, but be on the safe side and keep it anyway
665 */
666 if (!td) {
667 if (list_empty(&ep_ring->td_list)) {
668 new_seg = ep_ring->enq_seg;
669 new_deq = ep_ring->enqueue;
670 new_cycle = ep_ring->cycle_state;
671 xhci_dbg(xhci, "ep ring empty, Set new dequeue = enqueue");
672 goto deq_found;
673 } else {
674 xhci_warn(xhci, "Can't find new dequeue state, missing td\n");
675 return -EINVAL;
676 }
677 }
678
679 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
680 new_seg = ep_ring->deq_seg;
681 new_deq = ep_ring->dequeue;
682 new_cycle = hw_dequeue & 0x1;
683
684 /*
685 * We want to find the pointer, segment and cycle state of the new trb
686 * (the one after current TD's last_trb). We know the cycle state at
687 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
688 * found.
689 */
690 do {
691 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
692 == (dma_addr_t)(hw_dequeue & ~0xf)) {
693 cycle_found = true;
694 if (td_last_trb_found)
695 break;
696 }
697 if (new_deq == td->last_trb)
698 td_last_trb_found = true;
699
700 if (cycle_found && trb_is_link(new_deq) &&
701 link_trb_toggles_cycle(new_deq))
702 new_cycle ^= 0x1;
703
704 next_trb(xhci, ep_ring, &new_seg, &new_deq);
705
706 /* Search wrapped around, bail out */
707 if (new_deq == ep->ring->dequeue) {
708 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
709 return -EINVAL;
710 }
711
712 } while (!cycle_found || !td_last_trb_found);
713
714deq_found:
715
716 /* Don't update the ring cycle state for the producer (us). */
717 addr = xhci_trb_virt_to_dma(new_seg, new_deq);
718 if (addr == 0) {
719 xhci_warn(xhci, "Can't find dma of new dequeue ptr\n");
720 xhci_warn(xhci, "deq seg = %p, deq ptr = %p\n", new_seg, new_deq);
721 return -EINVAL;
722 }
723
724 if ((ep->ep_state & SET_DEQ_PENDING)) {
725 xhci_warn(xhci, "Set TR Deq already pending, don't submit for 0x%pad\n",
726 &addr);
727 return -EBUSY;
728 }
729
730 /* This function gets called from contexts where it cannot sleep */
731 cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
732 if (!cmd) {
733 xhci_warn(xhci, "Can't alloc Set TR Deq cmd 0x%pad\n", &addr);
734 return -ENOMEM;
735 }
736
737 if (stream_id)
738 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
739 ret = queue_command(xhci, cmd,
740 lower_32_bits(addr) | trb_sct | new_cycle,
741 upper_32_bits(addr),
742 STREAM_ID_FOR_TRB(stream_id), SLOT_ID_FOR_TRB(slot_id) |
743 EP_ID_FOR_TRB(ep_index) | TRB_TYPE(TRB_SET_DEQ), false);
744 if (ret < 0) {
745 xhci_free_command(xhci, cmd);
746 return ret;
747 }
748 ep->queued_deq_seg = new_seg;
749 ep->queued_deq_ptr = new_deq;
750
751 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
752 "Set TR Deq ptr 0x%llx, cycle %u\n", addr, new_cycle);
753
754 /* Stop the TD queueing code from ringing the doorbell until
755 * this command completes. The HC won't set the dequeue pointer
756 * if the ring is running, and ringing the doorbell starts the
757 * ring running.
758 */
759 ep->ep_state |= SET_DEQ_PENDING;
760 xhci_ring_cmd_db(xhci);
761 return 0;
762}
763
764/* flip_cycle means flip the cycle bit of all but the first and last TRB.
765 * (The last TRB actually points to the ring enqueue pointer, which is not part
766 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
767 */
768static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
769 struct xhci_td *td, bool flip_cycle)
770{
771 struct xhci_segment *seg = td->start_seg;
772 union xhci_trb *trb = td->first_trb;
773
774 while (1) {
775 trb_to_noop(trb, TRB_TR_NOOP);
776
777 /* flip cycle if asked to */
778 if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
779 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
780
781 if (trb == td->last_trb)
782 break;
783
784 next_trb(xhci, ep_ring, &seg, &trb);
785 }
786}
787
788/*
789 * Must be called with xhci->lock held in interrupt context,
790 * releases and re-acquires xhci->lock
791 */
792static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
793 struct xhci_td *cur_td, int status)
794{
795 struct urb *urb = cur_td->urb;
796 struct urb_priv *urb_priv = urb->hcpriv;
797 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus);
798
799 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
800 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
801 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
802 if (xhci->quirks & XHCI_AMD_PLL_FIX)
803 usb_amd_quirk_pll_enable();
804 }
805 }
806 xhci_urb_free_priv(urb_priv);
807 usb_hcd_unlink_urb_from_ep(hcd, urb);
808 trace_xhci_urb_giveback(urb);
809 usb_hcd_giveback_urb(hcd, urb, status);
810}
811
812static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
813 struct xhci_ring *ring, struct xhci_td *td)
814{
815 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
816 struct xhci_segment *seg = td->bounce_seg;
817 struct urb *urb = td->urb;
818 size_t len;
819
820 if (!ring || !seg || !urb)
821 return;
822
823 if (usb_urb_dir_out(urb)) {
824 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
825 DMA_TO_DEVICE);
826 return;
827 }
828
829 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
830 DMA_FROM_DEVICE);
831 /* for in tranfers we need to copy the data from bounce to sg */
832 if (urb->num_sgs) {
833 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
834 seg->bounce_len, seg->bounce_offs);
835 if (len != seg->bounce_len)
836 xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
837 len, seg->bounce_len);
838 } else {
839 memcpy(urb->transfer_buffer + seg->bounce_offs, seg->bounce_buf,
840 seg->bounce_len);
841 }
842 seg->bounce_len = 0;
843 seg->bounce_offs = 0;
844}
845
846static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
847 struct xhci_ring *ep_ring, int status)
848{
849 struct urb *urb = NULL;
850
851 /* Clean up the endpoint's TD list */
852 urb = td->urb;
853
854 /* if a bounce buffer was used to align this td then unmap it */
855 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
856
857 /* Do one last check of the actual transfer length.
858 * If the host controller said we transferred more data than the buffer
859 * length, urb->actual_length will be a very big number (since it's
860 * unsigned). Play it safe and say we didn't transfer anything.
861 */
862 if (urb->actual_length > urb->transfer_buffer_length) {
863 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
864 urb->transfer_buffer_length, urb->actual_length);
865 urb->actual_length = 0;
866 status = 0;
867 }
868 /* TD might be removed from td_list if we are giving back a cancelled URB */
869 if (!list_empty(&td->td_list))
870 list_del_init(&td->td_list);
871 /* Giving back a cancelled URB, or if a slated TD completed anyway */
872 if (!list_empty(&td->cancelled_td_list))
873 list_del_init(&td->cancelled_td_list);
874
875 inc_td_cnt(urb);
876 /* Giveback the urb when all the tds are completed */
877 if (last_td_in_urb(td)) {
878 if ((urb->actual_length != urb->transfer_buffer_length &&
879 (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
880 (status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
881 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
882 urb, urb->actual_length,
883 urb->transfer_buffer_length, status);
884
885 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
886 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
887 status = 0;
888 xhci_giveback_urb_in_irq(xhci, td, status);
889 }
890
891 return 0;
892}
893
894
895/* Complete the cancelled URBs we unlinked from td_list. */
896static void xhci_giveback_invalidated_tds(struct xhci_virt_ep *ep)
897{
898 struct xhci_ring *ring;
899 struct xhci_td *td, *tmp_td;
900
901 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
902 cancelled_td_list) {
903
904 ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
905
906 if (td->cancel_status == TD_CLEARED) {
907 xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n",
908 __func__, td->urb);
909 xhci_td_cleanup(ep->xhci, td, ring, td->status);
910 } else {
911 xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n",
912 __func__, td->urb, td->cancel_status);
913 }
914 if (ep->xhci->xhc_state & XHCI_STATE_DYING)
915 return;
916 }
917}
918
919static int xhci_reset_halted_ep(struct xhci_hcd *xhci, unsigned int slot_id,
920 unsigned int ep_index, enum xhci_ep_reset_type reset_type)
921{
922 struct xhci_command *command;
923 int ret = 0;
924
925 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
926 if (!command) {
927 ret = -ENOMEM;
928 goto done;
929 }
930
931 xhci_dbg(xhci, "%s-reset ep %u, slot %u\n",
932 (reset_type == EP_HARD_RESET) ? "Hard" : "Soft",
933 ep_index, slot_id);
934
935 ret = xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
936done:
937 if (ret)
938 xhci_err(xhci, "ERROR queuing reset endpoint for slot %d ep_index %d, %d\n",
939 slot_id, ep_index, ret);
940 return ret;
941}
942
943static int xhci_handle_halted_endpoint(struct xhci_hcd *xhci,
944 struct xhci_virt_ep *ep,
945 struct xhci_td *td,
946 enum xhci_ep_reset_type reset_type)
947{
948 unsigned int slot_id = ep->vdev->slot_id;
949 int err;
950
951 /*
952 * Avoid resetting endpoint if link is inactive. Can cause host hang.
953 * Device will be reset soon to recover the link so don't do anything
954 */
955 if (ep->vdev->flags & VDEV_PORT_ERROR)
956 return -ENODEV;
957
958 /* add td to cancelled list and let reset ep handler take care of it */
959 if (reset_type == EP_HARD_RESET) {
960 ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
961 if (td && list_empty(&td->cancelled_td_list)) {
962 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
963 td->cancel_status = TD_HALTED;
964 }
965 }
966
967 if (ep->ep_state & EP_HALTED) {
968 xhci_dbg(xhci, "Reset ep command for ep_index %d already pending\n",
969 ep->ep_index);
970 return 0;
971 }
972
973 err = xhci_reset_halted_ep(xhci, slot_id, ep->ep_index, reset_type);
974 if (err)
975 return err;
976
977 ep->ep_state |= EP_HALTED;
978
979 xhci_ring_cmd_db(xhci);
980
981 return 0;
982}
983
984/*
985 * Fix up the ep ring first, so HW stops executing cancelled TDs.
986 * We have the xHCI lock, so nothing can modify this list until we drop it.
987 * We're also in the event handler, so we can't get re-interrupted if another
988 * Stop Endpoint command completes.
989 *
990 * only call this when ring is not in a running state
991 */
992
993static int xhci_invalidate_cancelled_tds(struct xhci_virt_ep *ep)
994{
995 struct xhci_hcd *xhci;
996 struct xhci_td *td = NULL;
997 struct xhci_td *tmp_td = NULL;
998 struct xhci_td *cached_td = NULL;
999 struct xhci_ring *ring;
1000 u64 hw_deq;
1001 unsigned int slot_id = ep->vdev->slot_id;
1002 int err;
1003
1004 xhci = ep->xhci;
1005
1006 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) {
1007 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1008 "Removing canceled TD starting at 0x%llx (dma) in stream %u URB %p",
1009 (unsigned long long)xhci_trb_virt_to_dma(
1010 td->start_seg, td->first_trb),
1011 td->urb->stream_id, td->urb);
1012 list_del_init(&td->td_list);
1013 ring = xhci_urb_to_transfer_ring(xhci, td->urb);
1014 if (!ring) {
1015 xhci_warn(xhci, "WARN Cancelled URB %p has invalid stream ID %u.\n",
1016 td->urb, td->urb->stream_id);
1017 continue;
1018 }
1019 /*
1020 * If a ring stopped on the TD we need to cancel then we have to
1021 * move the xHC endpoint ring dequeue pointer past this TD.
1022 * Rings halted due to STALL may show hw_deq is past the stalled
1023 * TD, but still require a set TR Deq command to flush xHC cache.
1024 */
1025 hw_deq = xhci_get_hw_deq(xhci, ep->vdev, ep->ep_index,
1026 td->urb->stream_id);
1027 hw_deq &= ~0xf;
1028
1029 if (td->cancel_status == TD_HALTED ||
1030 trb_in_td(xhci, td->start_seg, td->first_trb, td->last_trb, hw_deq, false)) {
1031 switch (td->cancel_status) {
1032 case TD_CLEARED: /* TD is already no-op */
1033 case TD_CLEARING_CACHE: /* set TR deq command already queued */
1034 break;
1035 case TD_DIRTY: /* TD is cached, clear it */
1036 case TD_HALTED:
1037 td->cancel_status = TD_CLEARING_CACHE;
1038 if (cached_td)
1039 /* FIXME stream case, several stopped rings */
1040 xhci_dbg(xhci,
1041 "Move dq past stream %u URB %p instead of stream %u URB %p\n",
1042 td->urb->stream_id, td->urb,
1043 cached_td->urb->stream_id, cached_td->urb);
1044 cached_td = td;
1045 break;
1046 }
1047 } else {
1048 td_to_noop(xhci, ring, td, false);
1049 td->cancel_status = TD_CLEARED;
1050 }
1051 }
1052
1053 /* If there's no need to move the dequeue pointer then we're done */
1054 if (!cached_td)
1055 return 0;
1056
1057 err = xhci_move_dequeue_past_td(xhci, slot_id, ep->ep_index,
1058 cached_td->urb->stream_id,
1059 cached_td);
1060 if (err) {
1061 /* Failed to move past cached td, just set cached TDs to no-op */
1062 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) {
1063 if (td->cancel_status != TD_CLEARING_CACHE)
1064 continue;
1065 xhci_dbg(xhci, "Failed to clear cancelled cached URB %p, mark clear anyway\n",
1066 td->urb);
1067 td_to_noop(xhci, ring, td, false);
1068 td->cancel_status = TD_CLEARED;
1069 }
1070 }
1071 return 0;
1072}
1073
1074/*
1075 * Returns the TD the endpoint ring halted on.
1076 * Only call for non-running rings without streams.
1077 */
1078static struct xhci_td *find_halted_td(struct xhci_virt_ep *ep)
1079{
1080 struct xhci_td *td;
1081 u64 hw_deq;
1082
1083 if (!list_empty(&ep->ring->td_list)) { /* Not streams compatible */
1084 hw_deq = xhci_get_hw_deq(ep->xhci, ep->vdev, ep->ep_index, 0);
1085 hw_deq &= ~0xf;
1086 td = list_first_entry(&ep->ring->td_list, struct xhci_td, td_list);
1087 if (trb_in_td(ep->xhci, td->start_seg, td->first_trb,
1088 td->last_trb, hw_deq, false))
1089 return td;
1090 }
1091 return NULL;
1092}
1093
1094/*
1095 * When we get a command completion for a Stop Endpoint Command, we need to
1096 * unlink any cancelled TDs from the ring. There are two ways to do that:
1097 *
1098 * 1. If the HW was in the middle of processing the TD that needs to be
1099 * cancelled, then we must move the ring's dequeue pointer past the last TRB
1100 * in the TD with a Set Dequeue Pointer Command.
1101 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
1102 * bit cleared) so that the HW will skip over them.
1103 */
1104static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
1105 union xhci_trb *trb, u32 comp_code)
1106{
1107 unsigned int ep_index;
1108 struct xhci_virt_ep *ep;
1109 struct xhci_ep_ctx *ep_ctx;
1110 struct xhci_td *td = NULL;
1111 enum xhci_ep_reset_type reset_type;
1112 struct xhci_command *command;
1113 int err;
1114
1115 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
1116 if (!xhci->devs[slot_id])
1117 xhci_warn(xhci, "Stop endpoint command completion for disabled slot %u\n",
1118 slot_id);
1119 return;
1120 }
1121
1122 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1123 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1124 if (!ep)
1125 return;
1126
1127 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1128
1129 trace_xhci_handle_cmd_stop_ep(ep_ctx);
1130
1131 if (comp_code == COMP_CONTEXT_STATE_ERROR) {
1132 /*
1133 * If stop endpoint command raced with a halting endpoint we need to
1134 * reset the host side endpoint first.
1135 * If the TD we halted on isn't cancelled the TD should be given back
1136 * with a proper error code, and the ring dequeue moved past the TD.
1137 * If streams case we can't find hw_deq, or the TD we halted on so do a
1138 * soft reset.
1139 *
1140 * Proper error code is unknown here, it would be -EPIPE if device side
1141 * of enadpoit halted (aka STALL), and -EPROTO if not (transaction error)
1142 * We use -EPROTO, if device is stalled it should return a stall error on
1143 * next transfer, which then will return -EPIPE, and device side stall is
1144 * noted and cleared by class driver.
1145 */
1146 switch (GET_EP_CTX_STATE(ep_ctx)) {
1147 case EP_STATE_HALTED:
1148 xhci_dbg(xhci, "Stop ep completion raced with stall, reset ep\n");
1149 if (ep->ep_state & EP_HAS_STREAMS) {
1150 reset_type = EP_SOFT_RESET;
1151 } else {
1152 reset_type = EP_HARD_RESET;
1153 td = find_halted_td(ep);
1154 if (td)
1155 td->status = -EPROTO;
1156 }
1157 /* reset ep, reset handler cleans up cancelled tds */
1158 err = xhci_handle_halted_endpoint(xhci, ep, td, reset_type);
1159 if (err)
1160 break;
1161 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1162 return;
1163 case EP_STATE_STOPPED:
1164 /*
1165 * NEC uPD720200 sometimes sets this state and fails with
1166 * Context Error while continuing to process TRBs.
1167 * Be conservative and trust EP_CTX_STATE on other chips.
1168 */
1169 if (!(xhci->quirks & XHCI_NEC_HOST))
1170 break;
1171 fallthrough;
1172 case EP_STATE_RUNNING:
1173 /* Race, HW handled stop ep cmd before ep was running */
1174 xhci_dbg(xhci, "Stop ep completion ctx error, ep is running\n");
1175
1176 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1177 if (!command) {
1178 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1179 return;
1180 }
1181 xhci_queue_stop_endpoint(xhci, command, slot_id, ep_index, 0);
1182 xhci_ring_cmd_db(xhci);
1183
1184 return;
1185 default:
1186 break;
1187 }
1188 }
1189
1190 /* will queue a set TR deq if stopped on a cancelled, uncleared TD */
1191 xhci_invalidate_cancelled_tds(ep);
1192 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1193
1194 /* Otherwise ring the doorbell(s) to restart queued transfers */
1195 xhci_giveback_invalidated_tds(ep);
1196 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1197}
1198
1199static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
1200{
1201 struct xhci_td *cur_td;
1202 struct xhci_td *tmp;
1203
1204 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
1205 list_del_init(&cur_td->td_list);
1206
1207 if (!list_empty(&cur_td->cancelled_td_list))
1208 list_del_init(&cur_td->cancelled_td_list);
1209
1210 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
1211
1212 inc_td_cnt(cur_td->urb);
1213 if (last_td_in_urb(cur_td))
1214 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1215 }
1216}
1217
1218static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
1219 int slot_id, int ep_index)
1220{
1221 struct xhci_td *cur_td;
1222 struct xhci_td *tmp;
1223 struct xhci_virt_ep *ep;
1224 struct xhci_ring *ring;
1225
1226 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1227 if (!ep)
1228 return;
1229
1230 if ((ep->ep_state & EP_HAS_STREAMS) ||
1231 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
1232 int stream_id;
1233
1234 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
1235 stream_id++) {
1236 ring = ep->stream_info->stream_rings[stream_id];
1237 if (!ring)
1238 continue;
1239
1240 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1241 "Killing URBs for slot ID %u, ep index %u, stream %u",
1242 slot_id, ep_index, stream_id);
1243 xhci_kill_ring_urbs(xhci, ring);
1244 }
1245 } else {
1246 ring = ep->ring;
1247 if (!ring)
1248 return;
1249 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1250 "Killing URBs for slot ID %u, ep index %u",
1251 slot_id, ep_index);
1252 xhci_kill_ring_urbs(xhci, ring);
1253 }
1254
1255 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
1256 cancelled_td_list) {
1257 list_del_init(&cur_td->cancelled_td_list);
1258 inc_td_cnt(cur_td->urb);
1259
1260 if (last_td_in_urb(cur_td))
1261 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1262 }
1263}
1264
1265/*
1266 * host controller died, register read returns 0xffffffff
1267 * Complete pending commands, mark them ABORTED.
1268 * URBs need to be given back as usb core might be waiting with device locks
1269 * held for the URBs to finish during device disconnect, blocking host remove.
1270 *
1271 * Call with xhci->lock held.
1272 * lock is relased and re-acquired while giving back urb.
1273 */
1274void xhci_hc_died(struct xhci_hcd *xhci)
1275{
1276 int i, j;
1277
1278 if (xhci->xhc_state & XHCI_STATE_DYING)
1279 return;
1280
1281 xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
1282 xhci->xhc_state |= XHCI_STATE_DYING;
1283
1284 xhci_cleanup_command_queue(xhci);
1285
1286 /* return any pending urbs, remove may be waiting for them */
1287 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
1288 if (!xhci->devs[i])
1289 continue;
1290 for (j = 0; j < 31; j++)
1291 xhci_kill_endpoint_urbs(xhci, i, j);
1292 }
1293
1294 /* inform usb core hc died if PCI remove isn't already handling it */
1295 if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
1296 usb_hc_died(xhci_to_hcd(xhci));
1297}
1298
1299static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1300 struct xhci_virt_device *dev,
1301 struct xhci_ring *ep_ring,
1302 unsigned int ep_index)
1303{
1304 union xhci_trb *dequeue_temp;
1305
1306 dequeue_temp = ep_ring->dequeue;
1307
1308 /* If we get two back-to-back stalls, and the first stalled transfer
1309 * ends just before a link TRB, the dequeue pointer will be left on
1310 * the link TRB by the code in the while loop. So we have to update
1311 * the dequeue pointer one segment further, or we'll jump off
1312 * the segment into la-la-land.
1313 */
1314 if (trb_is_link(ep_ring->dequeue)) {
1315 ep_ring->deq_seg = ep_ring->deq_seg->next;
1316 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1317 }
1318
1319 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1320 /* We have more usable TRBs */
1321 ep_ring->dequeue++;
1322 if (trb_is_link(ep_ring->dequeue)) {
1323 if (ep_ring->dequeue ==
1324 dev->eps[ep_index].queued_deq_ptr)
1325 break;
1326 ep_ring->deq_seg = ep_ring->deq_seg->next;
1327 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1328 }
1329 if (ep_ring->dequeue == dequeue_temp) {
1330 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1331 break;
1332 }
1333 }
1334}
1335
1336/*
1337 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1338 * we need to clear the set deq pending flag in the endpoint ring state, so that
1339 * the TD queueing code can ring the doorbell again. We also need to ring the
1340 * endpoint doorbell to restart the ring, but only if there aren't more
1341 * cancellations pending.
1342 */
1343static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1344 union xhci_trb *trb, u32 cmd_comp_code)
1345{
1346 unsigned int ep_index;
1347 unsigned int stream_id;
1348 struct xhci_ring *ep_ring;
1349 struct xhci_virt_ep *ep;
1350 struct xhci_ep_ctx *ep_ctx;
1351 struct xhci_slot_ctx *slot_ctx;
1352 struct xhci_td *td, *tmp_td;
1353
1354 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1355 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1356 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1357 if (!ep)
1358 return;
1359
1360 ep_ring = xhci_virt_ep_to_ring(xhci, ep, stream_id);
1361 if (!ep_ring) {
1362 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1363 stream_id);
1364 /* XXX: Harmless??? */
1365 goto cleanup;
1366 }
1367
1368 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1369 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
1370 trace_xhci_handle_cmd_set_deq(slot_ctx);
1371 trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1372
1373 if (cmd_comp_code != COMP_SUCCESS) {
1374 unsigned int ep_state;
1375 unsigned int slot_state;
1376
1377 switch (cmd_comp_code) {
1378 case COMP_TRB_ERROR:
1379 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1380 break;
1381 case COMP_CONTEXT_STATE_ERROR:
1382 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1383 ep_state = GET_EP_CTX_STATE(ep_ctx);
1384 slot_state = le32_to_cpu(slot_ctx->dev_state);
1385 slot_state = GET_SLOT_STATE(slot_state);
1386 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1387 "Slot state = %u, EP state = %u",
1388 slot_state, ep_state);
1389 break;
1390 case COMP_SLOT_NOT_ENABLED_ERROR:
1391 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1392 slot_id);
1393 break;
1394 default:
1395 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1396 cmd_comp_code);
1397 break;
1398 }
1399 /* OK what do we do now? The endpoint state is hosed, and we
1400 * should never get to this point if the synchronization between
1401 * queueing, and endpoint state are correct. This might happen
1402 * if the device gets disconnected after we've finished
1403 * cancelling URBs, which might not be an error...
1404 */
1405 } else {
1406 u64 deq;
1407 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1408 if (ep->ep_state & EP_HAS_STREAMS) {
1409 struct xhci_stream_ctx *ctx =
1410 &ep->stream_info->stream_ctx_array[stream_id];
1411 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1412 } else {
1413 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1414 }
1415 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1416 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1417 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1418 ep->queued_deq_ptr) == deq) {
1419 /* Update the ring's dequeue segment and dequeue pointer
1420 * to reflect the new position.
1421 */
1422 update_ring_for_set_deq_completion(xhci, ep->vdev,
1423 ep_ring, ep_index);
1424 } else {
1425 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1426 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1427 ep->queued_deq_seg, ep->queued_deq_ptr);
1428 }
1429 }
1430 /* HW cached TDs cleared from cache, give them back */
1431 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
1432 cancelled_td_list) {
1433 ep_ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
1434 if (td->cancel_status == TD_CLEARING_CACHE) {
1435 td->cancel_status = TD_CLEARED;
1436 xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n",
1437 __func__, td->urb);
1438 xhci_td_cleanup(ep->xhci, td, ep_ring, td->status);
1439 } else {
1440 xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n",
1441 __func__, td->urb, td->cancel_status);
1442 }
1443 }
1444cleanup:
1445 ep->ep_state &= ~SET_DEQ_PENDING;
1446 ep->queued_deq_seg = NULL;
1447 ep->queued_deq_ptr = NULL;
1448 /* Restart any rings with pending URBs */
1449 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1450}
1451
1452static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1453 union xhci_trb *trb, u32 cmd_comp_code)
1454{
1455 struct xhci_virt_ep *ep;
1456 struct xhci_ep_ctx *ep_ctx;
1457 unsigned int ep_index;
1458
1459 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1460 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1461 if (!ep)
1462 return;
1463
1464 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1465 trace_xhci_handle_cmd_reset_ep(ep_ctx);
1466
1467 /* This command will only fail if the endpoint wasn't halted,
1468 * but we don't care.
1469 */
1470 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1471 "Ignoring reset ep completion code of %u", cmd_comp_code);
1472
1473 /* Cleanup cancelled TDs as ep is stopped. May queue a Set TR Deq cmd */
1474 xhci_invalidate_cancelled_tds(ep);
1475
1476 /* Clear our internal halted state */
1477 ep->ep_state &= ~EP_HALTED;
1478
1479 xhci_giveback_invalidated_tds(ep);
1480
1481 /* if this was a soft reset, then restart */
1482 if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP)
1483 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1484}
1485
1486static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1487 struct xhci_command *command, u32 cmd_comp_code)
1488{
1489 if (cmd_comp_code == COMP_SUCCESS)
1490 command->slot_id = slot_id;
1491 else
1492 command->slot_id = 0;
1493}
1494
1495static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1496{
1497 struct xhci_virt_device *virt_dev;
1498 struct xhci_slot_ctx *slot_ctx;
1499
1500 virt_dev = xhci->devs[slot_id];
1501 if (!virt_dev)
1502 return;
1503
1504 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1505 trace_xhci_handle_cmd_disable_slot(slot_ctx);
1506
1507 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1508 /* Delete default control endpoint resources */
1509 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1510}
1511
1512static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1513 u32 cmd_comp_code)
1514{
1515 struct xhci_virt_device *virt_dev;
1516 struct xhci_input_control_ctx *ctrl_ctx;
1517 struct xhci_ep_ctx *ep_ctx;
1518 unsigned int ep_index;
1519 u32 add_flags;
1520
1521 /*
1522 * Configure endpoint commands can come from the USB core configuration
1523 * or alt setting changes, or when streams were being configured.
1524 */
1525
1526 virt_dev = xhci->devs[slot_id];
1527 if (!virt_dev)
1528 return;
1529 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1530 if (!ctrl_ctx) {
1531 xhci_warn(xhci, "Could not get input context, bad type.\n");
1532 return;
1533 }
1534
1535 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1536
1537 /* Input ctx add_flags are the endpoint index plus one */
1538 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1539
1540 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1541 trace_xhci_handle_cmd_config_ep(ep_ctx);
1542
1543 return;
1544}
1545
1546static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1547{
1548 struct xhci_virt_device *vdev;
1549 struct xhci_slot_ctx *slot_ctx;
1550
1551 vdev = xhci->devs[slot_id];
1552 if (!vdev)
1553 return;
1554 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1555 trace_xhci_handle_cmd_addr_dev(slot_ctx);
1556}
1557
1558static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id)
1559{
1560 struct xhci_virt_device *vdev;
1561 struct xhci_slot_ctx *slot_ctx;
1562
1563 vdev = xhci->devs[slot_id];
1564 if (!vdev) {
1565 xhci_warn(xhci, "Reset device command completion for disabled slot %u\n",
1566 slot_id);
1567 return;
1568 }
1569 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1570 trace_xhci_handle_cmd_reset_dev(slot_ctx);
1571
1572 xhci_dbg(xhci, "Completed reset device command.\n");
1573}
1574
1575static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1576 struct xhci_event_cmd *event)
1577{
1578 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1579 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1580 return;
1581 }
1582 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1583 "NEC firmware version %2x.%02x",
1584 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1585 NEC_FW_MINOR(le32_to_cpu(event->status)));
1586}
1587
1588static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1589{
1590 list_del(&cmd->cmd_list);
1591
1592 if (cmd->completion) {
1593 cmd->status = status;
1594 complete(cmd->completion);
1595 } else {
1596 kfree(cmd);
1597 }
1598}
1599
1600void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1601{
1602 struct xhci_command *cur_cmd, *tmp_cmd;
1603 xhci->current_cmd = NULL;
1604 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1605 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1606}
1607
1608void xhci_handle_command_timeout(struct work_struct *work)
1609{
1610 struct xhci_hcd *xhci;
1611 unsigned long flags;
1612 char str[XHCI_MSG_MAX];
1613 u64 hw_ring_state;
1614 u32 cmd_field3;
1615 u32 usbsts;
1616
1617 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1618
1619 spin_lock_irqsave(&xhci->lock, flags);
1620
1621 /*
1622 * If timeout work is pending, or current_cmd is NULL, it means we
1623 * raced with command completion. Command is handled so just return.
1624 */
1625 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1626 spin_unlock_irqrestore(&xhci->lock, flags);
1627 return;
1628 }
1629
1630 cmd_field3 = le32_to_cpu(xhci->current_cmd->command_trb->generic.field[3]);
1631 usbsts = readl(&xhci->op_regs->status);
1632 xhci_dbg(xhci, "Command timeout, USBSTS:%s\n", xhci_decode_usbsts(str, usbsts));
1633
1634 /* Bail out and tear down xhci if a stop endpoint command failed */
1635 if (TRB_FIELD_TO_TYPE(cmd_field3) == TRB_STOP_RING) {
1636 struct xhci_virt_ep *ep;
1637
1638 xhci_warn(xhci, "xHCI host not responding to stop endpoint command\n");
1639
1640 ep = xhci_get_virt_ep(xhci, TRB_TO_SLOT_ID(cmd_field3),
1641 TRB_TO_EP_INDEX(cmd_field3));
1642 if (ep)
1643 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1644
1645 xhci_halt(xhci);
1646 xhci_hc_died(xhci);
1647 goto time_out_completed;
1648 }
1649
1650 /* mark this command to be cancelled */
1651 xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1652
1653 /* Make sure command ring is running before aborting it */
1654 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1655 if (hw_ring_state == ~(u64)0) {
1656 xhci_hc_died(xhci);
1657 goto time_out_completed;
1658 }
1659
1660 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1661 (hw_ring_state & CMD_RING_RUNNING)) {
1662 /* Prevent new doorbell, and start command abort */
1663 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1664 xhci_dbg(xhci, "Command timeout\n");
1665 xhci_abort_cmd_ring(xhci, flags);
1666 goto time_out_completed;
1667 }
1668
1669 /* host removed. Bail out */
1670 if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1671 xhci_dbg(xhci, "host removed, ring start fail?\n");
1672 xhci_cleanup_command_queue(xhci);
1673
1674 goto time_out_completed;
1675 }
1676
1677 /* command timeout on stopped ring, ring can't be aborted */
1678 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1679 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1680
1681time_out_completed:
1682 spin_unlock_irqrestore(&xhci->lock, flags);
1683 return;
1684}
1685
1686static void handle_cmd_completion(struct xhci_hcd *xhci,
1687 struct xhci_event_cmd *event)
1688{
1689 unsigned int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1690 u64 cmd_dma;
1691 dma_addr_t cmd_dequeue_dma;
1692 u32 cmd_comp_code;
1693 union xhci_trb *cmd_trb;
1694 struct xhci_command *cmd;
1695 u32 cmd_type;
1696
1697 if (slot_id >= MAX_HC_SLOTS) {
1698 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
1699 return;
1700 }
1701
1702 cmd_dma = le64_to_cpu(event->cmd_trb);
1703 cmd_trb = xhci->cmd_ring->dequeue;
1704
1705 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1706
1707 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1708 cmd_trb);
1709 /*
1710 * Check whether the completion event is for our internal kept
1711 * command.
1712 */
1713 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1714 xhci_warn(xhci,
1715 "ERROR mismatched command completion event\n");
1716 return;
1717 }
1718
1719 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1720
1721 cancel_delayed_work(&xhci->cmd_timer);
1722
1723 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1724
1725 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1726 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1727 complete_all(&xhci->cmd_ring_stop_completion);
1728 return;
1729 }
1730
1731 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1732 xhci_err(xhci,
1733 "Command completion event does not match command\n");
1734 return;
1735 }
1736
1737 /*
1738 * Host aborted the command ring, check if the current command was
1739 * supposed to be aborted, otherwise continue normally.
1740 * The command ring is stopped now, but the xHC will issue a Command
1741 * Ring Stopped event which will cause us to restart it.
1742 */
1743 if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1744 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1745 if (cmd->status == COMP_COMMAND_ABORTED) {
1746 if (xhci->current_cmd == cmd)
1747 xhci->current_cmd = NULL;
1748 goto event_handled;
1749 }
1750 }
1751
1752 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1753 switch (cmd_type) {
1754 case TRB_ENABLE_SLOT:
1755 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1756 break;
1757 case TRB_DISABLE_SLOT:
1758 xhci_handle_cmd_disable_slot(xhci, slot_id);
1759 break;
1760 case TRB_CONFIG_EP:
1761 if (!cmd->completion)
1762 xhci_handle_cmd_config_ep(xhci, slot_id, cmd_comp_code);
1763 break;
1764 case TRB_EVAL_CONTEXT:
1765 break;
1766 case TRB_ADDR_DEV:
1767 xhci_handle_cmd_addr_dev(xhci, slot_id);
1768 break;
1769 case TRB_STOP_RING:
1770 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1771 le32_to_cpu(cmd_trb->generic.field[3])));
1772 if (!cmd->completion)
1773 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb,
1774 cmd_comp_code);
1775 break;
1776 case TRB_SET_DEQ:
1777 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1778 le32_to_cpu(cmd_trb->generic.field[3])));
1779 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1780 break;
1781 case TRB_CMD_NOOP:
1782 /* Is this an aborted command turned to NO-OP? */
1783 if (cmd->status == COMP_COMMAND_RING_STOPPED)
1784 cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1785 break;
1786 case TRB_RESET_EP:
1787 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1788 le32_to_cpu(cmd_trb->generic.field[3])));
1789 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1790 break;
1791 case TRB_RESET_DEV:
1792 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1793 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1794 */
1795 slot_id = TRB_TO_SLOT_ID(
1796 le32_to_cpu(cmd_trb->generic.field[3]));
1797 xhci_handle_cmd_reset_dev(xhci, slot_id);
1798 break;
1799 case TRB_NEC_GET_FW:
1800 xhci_handle_cmd_nec_get_fw(xhci, event);
1801 break;
1802 default:
1803 /* Skip over unknown commands on the event ring */
1804 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1805 break;
1806 }
1807
1808 /* restart timer if this wasn't the last command */
1809 if (!list_is_singular(&xhci->cmd_list)) {
1810 xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1811 struct xhci_command, cmd_list);
1812 xhci_mod_cmd_timer(xhci);
1813 } else if (xhci->current_cmd == cmd) {
1814 xhci->current_cmd = NULL;
1815 }
1816
1817event_handled:
1818 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1819
1820 inc_deq(xhci, xhci->cmd_ring);
1821}
1822
1823static void handle_vendor_event(struct xhci_hcd *xhci,
1824 union xhci_trb *event, u32 trb_type)
1825{
1826 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1827 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1828 handle_cmd_completion(xhci, &event->event_cmd);
1829}
1830
1831static void handle_device_notification(struct xhci_hcd *xhci,
1832 union xhci_trb *event)
1833{
1834 u32 slot_id;
1835 struct usb_device *udev;
1836
1837 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1838 if (!xhci->devs[slot_id]) {
1839 xhci_warn(xhci, "Device Notification event for "
1840 "unused slot %u\n", slot_id);
1841 return;
1842 }
1843
1844 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1845 slot_id);
1846 udev = xhci->devs[slot_id]->udev;
1847 if (udev && udev->parent)
1848 usb_wakeup_notification(udev->parent, udev->portnum);
1849}
1850
1851/*
1852 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1853 * Controller.
1854 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1855 * If a connection to a USB 1 device is followed by another connection
1856 * to a USB 2 device.
1857 *
1858 * Reset the PHY after the USB device is disconnected if device speed
1859 * is less than HCD_USB3.
1860 * Retry the reset sequence max of 4 times checking the PLL lock status.
1861 *
1862 */
1863static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1864{
1865 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1866 u32 pll_lock_check;
1867 u32 retry_count = 4;
1868
1869 do {
1870 /* Assert PHY reset */
1871 writel(0x6F, hcd->regs + 0x1048);
1872 udelay(10);
1873 /* De-assert the PHY reset */
1874 writel(0x7F, hcd->regs + 0x1048);
1875 udelay(200);
1876 pll_lock_check = readl(hcd->regs + 0x1070);
1877 } while (!(pll_lock_check & 0x1) && --retry_count);
1878}
1879
1880static void handle_port_status(struct xhci_hcd *xhci,
1881 struct xhci_interrupter *ir,
1882 union xhci_trb *event)
1883{
1884 struct usb_hcd *hcd;
1885 u32 port_id;
1886 u32 portsc, cmd_reg;
1887 int max_ports;
1888 unsigned int hcd_portnum;
1889 struct xhci_bus_state *bus_state;
1890 bool bogus_port_status = false;
1891 struct xhci_port *port;
1892
1893 /* Port status change events always have a successful completion code */
1894 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1895 xhci_warn(xhci,
1896 "WARN: xHC returned failed port status event\n");
1897
1898 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1899 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1900
1901 if ((port_id <= 0) || (port_id > max_ports)) {
1902 xhci_warn(xhci, "Port change event with invalid port ID %d\n",
1903 port_id);
1904 return;
1905 }
1906
1907 port = &xhci->hw_ports[port_id - 1];
1908 if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
1909 xhci_warn(xhci, "Port change event, no port for port ID %u\n",
1910 port_id);
1911 bogus_port_status = true;
1912 goto cleanup;
1913 }
1914
1915 /* We might get interrupts after shared_hcd is removed */
1916 if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) {
1917 xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n");
1918 bogus_port_status = true;
1919 goto cleanup;
1920 }
1921
1922 hcd = port->rhub->hcd;
1923 bus_state = &port->rhub->bus_state;
1924 hcd_portnum = port->hcd_portnum;
1925 portsc = readl(port->addr);
1926
1927 xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n",
1928 hcd->self.busnum, hcd_portnum + 1, port_id, portsc);
1929
1930 trace_xhci_handle_port_status(port, portsc);
1931
1932 if (hcd->state == HC_STATE_SUSPENDED) {
1933 xhci_dbg(xhci, "resume root hub\n");
1934 usb_hcd_resume_root_hub(hcd);
1935 }
1936
1937 if (hcd->speed >= HCD_USB3 &&
1938 (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) {
1939 if (port->slot_id && xhci->devs[port->slot_id])
1940 xhci->devs[port->slot_id]->flags |= VDEV_PORT_ERROR;
1941 }
1942
1943 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
1944 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1945
1946 cmd_reg = readl(&xhci->op_regs->command);
1947 if (!(cmd_reg & CMD_RUN)) {
1948 xhci_warn(xhci, "xHC is not running.\n");
1949 goto cleanup;
1950 }
1951
1952 if (DEV_SUPERSPEED_ANY(portsc)) {
1953 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1954 /* Set a flag to say the port signaled remote wakeup,
1955 * so we can tell the difference between the end of
1956 * device and host initiated resume.
1957 */
1958 bus_state->port_remote_wakeup |= 1 << hcd_portnum;
1959 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1960 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1961 xhci_set_link_state(xhci, port, XDEV_U0);
1962 /* Need to wait until the next link state change
1963 * indicates the device is actually in U0.
1964 */
1965 bogus_port_status = true;
1966 goto cleanup;
1967 } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
1968 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1969 port->resume_timestamp = jiffies +
1970 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1971 set_bit(hcd_portnum, &bus_state->resuming_ports);
1972 /* Do the rest in GetPortStatus after resume time delay.
1973 * Avoid polling roothub status before that so that a
1974 * usb device auto-resume latency around ~40ms.
1975 */
1976 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1977 mod_timer(&hcd->rh_timer,
1978 port->resume_timestamp);
1979 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1980 bogus_port_status = true;
1981 }
1982 }
1983
1984 if ((portsc & PORT_PLC) &&
1985 DEV_SUPERSPEED_ANY(portsc) &&
1986 ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
1987 (portsc & PORT_PLS_MASK) == XDEV_U1 ||
1988 (portsc & PORT_PLS_MASK) == XDEV_U2)) {
1989 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1990 complete(&port->u3exit_done);
1991 /* We've just brought the device into U0/1/2 through either the
1992 * Resume state after a device remote wakeup, or through the
1993 * U3Exit state after a host-initiated resume. If it's a device
1994 * initiated remote wake, don't pass up the link state change,
1995 * so the roothub behavior is consistent with external
1996 * USB 3.0 hub behavior.
1997 */
1998 if (port->slot_id && xhci->devs[port->slot_id])
1999 xhci_ring_device(xhci, port->slot_id);
2000 if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
2001 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
2002 usb_wakeup_notification(hcd->self.root_hub,
2003 hcd_portnum + 1);
2004 bogus_port_status = true;
2005 goto cleanup;
2006 }
2007 }
2008
2009 /*
2010 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
2011 * RExit to a disconnect state). If so, let the driver know it's
2012 * out of the RExit state.
2013 */
2014 if (hcd->speed < HCD_USB3 && port->rexit_active) {
2015 complete(&port->rexit_done);
2016 port->rexit_active = false;
2017 bogus_port_status = true;
2018 goto cleanup;
2019 }
2020
2021 if (hcd->speed < HCD_USB3) {
2022 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
2023 if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
2024 (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
2025 xhci_cavium_reset_phy_quirk(xhci);
2026 }
2027
2028cleanup:
2029
2030 /* Don't make the USB core poll the roothub if we got a bad port status
2031 * change event. Besides, at that point we can't tell which roothub
2032 * (USB 2.0 or USB 3.0) to kick.
2033 */
2034 if (bogus_port_status)
2035 return;
2036
2037 /*
2038 * xHCI port-status-change events occur when the "or" of all the
2039 * status-change bits in the portsc register changes from 0 to 1.
2040 * New status changes won't cause an event if any other change
2041 * bits are still set. When an event occurs, switch over to
2042 * polling to avoid losing status changes.
2043 */
2044 xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
2045 __func__, hcd->self.busnum);
2046 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
2047 spin_unlock(&xhci->lock);
2048 /* Pass this up to the core */
2049 usb_hcd_poll_rh_status(hcd);
2050 spin_lock(&xhci->lock);
2051}
2052
2053/*
2054 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
2055 * at end_trb, which may be in another segment. If the suspect DMA address is a
2056 * TRB in this TD, this function returns that TRB's segment. Otherwise it
2057 * returns 0.
2058 */
2059struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2060 struct xhci_segment *start_seg,
2061 union xhci_trb *start_trb,
2062 union xhci_trb *end_trb,
2063 dma_addr_t suspect_dma,
2064 bool debug)
2065{
2066 dma_addr_t start_dma;
2067 dma_addr_t end_seg_dma;
2068 dma_addr_t end_trb_dma;
2069 struct xhci_segment *cur_seg;
2070
2071 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
2072 cur_seg = start_seg;
2073
2074 do {
2075 if (start_dma == 0)
2076 return NULL;
2077 /* We may get an event for a Link TRB in the middle of a TD */
2078 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
2079 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
2080 /* If the end TRB isn't in this segment, this is set to 0 */
2081 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
2082
2083 if (debug)
2084 xhci_warn(xhci,
2085 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
2086 (unsigned long long)suspect_dma,
2087 (unsigned long long)start_dma,
2088 (unsigned long long)end_trb_dma,
2089 (unsigned long long)cur_seg->dma,
2090 (unsigned long long)end_seg_dma);
2091
2092 if (end_trb_dma > 0) {
2093 /* The end TRB is in this segment, so suspect should be here */
2094 if (start_dma <= end_trb_dma) {
2095 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
2096 return cur_seg;
2097 } else {
2098 /* Case for one segment with
2099 * a TD wrapped around to the top
2100 */
2101 if ((suspect_dma >= start_dma &&
2102 suspect_dma <= end_seg_dma) ||
2103 (suspect_dma >= cur_seg->dma &&
2104 suspect_dma <= end_trb_dma))
2105 return cur_seg;
2106 }
2107 return NULL;
2108 } else {
2109 /* Might still be somewhere in this segment */
2110 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
2111 return cur_seg;
2112 }
2113 cur_seg = cur_seg->next;
2114 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
2115 } while (cur_seg != start_seg);
2116
2117 return NULL;
2118}
2119
2120static void xhci_clear_hub_tt_buffer(struct xhci_hcd *xhci, struct xhci_td *td,
2121 struct xhci_virt_ep *ep)
2122{
2123 /*
2124 * As part of low/full-speed endpoint-halt processing
2125 * we must clear the TT buffer (USB 2.0 specification 11.17.5).
2126 */
2127 if (td->urb->dev->tt && !usb_pipeint(td->urb->pipe) &&
2128 (td->urb->dev->tt->hub != xhci_to_hcd(xhci)->self.root_hub) &&
2129 !(ep->ep_state & EP_CLEARING_TT)) {
2130 ep->ep_state |= EP_CLEARING_TT;
2131 td->urb->ep->hcpriv = td->urb->dev;
2132 if (usb_hub_clear_tt_buffer(td->urb))
2133 ep->ep_state &= ~EP_CLEARING_TT;
2134 }
2135}
2136
2137/* Check if an error has halted the endpoint ring. The class driver will
2138 * cleanup the halt for a non-default control endpoint if we indicate a stall.
2139 * However, a babble and other errors also halt the endpoint ring, and the class
2140 * driver won't clear the halt in that case, so we need to issue a Set Transfer
2141 * Ring Dequeue Pointer command manually.
2142 */
2143static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
2144 struct xhci_ep_ctx *ep_ctx,
2145 unsigned int trb_comp_code)
2146{
2147 /* TRB completion codes that may require a manual halt cleanup */
2148 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
2149 trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
2150 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
2151 /* The 0.95 spec says a babbling control endpoint
2152 * is not halted. The 0.96 spec says it is. Some HW
2153 * claims to be 0.95 compliant, but it halts the control
2154 * endpoint anyway. Check if a babble halted the
2155 * endpoint.
2156 */
2157 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
2158 return 1;
2159
2160 return 0;
2161}
2162
2163int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
2164{
2165 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
2166 /* Vendor defined "informational" completion code,
2167 * treat as not-an-error.
2168 */
2169 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
2170 trb_comp_code);
2171 xhci_dbg(xhci, "Treating code as success.\n");
2172 return 1;
2173 }
2174 return 0;
2175}
2176
2177static int finish_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2178 struct xhci_ring *ep_ring, struct xhci_td *td,
2179 u32 trb_comp_code)
2180{
2181 struct xhci_ep_ctx *ep_ctx;
2182
2183 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2184
2185 switch (trb_comp_code) {
2186 case COMP_STOPPED_LENGTH_INVALID:
2187 case COMP_STOPPED_SHORT_PACKET:
2188 case COMP_STOPPED:
2189 /*
2190 * The "Stop Endpoint" completion will take care of any
2191 * stopped TDs. A stopped TD may be restarted, so don't update
2192 * the ring dequeue pointer or take this TD off any lists yet.
2193 */
2194 return 0;
2195 case COMP_USB_TRANSACTION_ERROR:
2196 case COMP_BABBLE_DETECTED_ERROR:
2197 case COMP_SPLIT_TRANSACTION_ERROR:
2198 /*
2199 * If endpoint context state is not halted we might be
2200 * racing with a reset endpoint command issued by a unsuccessful
2201 * stop endpoint completion (context error). In that case the
2202 * td should be on the cancelled list, and EP_HALTED flag set.
2203 *
2204 * Or then it's not halted due to the 0.95 spec stating that a
2205 * babbling control endpoint should not halt. The 0.96 spec
2206 * again says it should. Some HW claims to be 0.95 compliant,
2207 * but it halts the control endpoint anyway.
2208 */
2209 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_HALTED) {
2210 /*
2211 * If EP_HALTED is set and TD is on the cancelled list
2212 * the TD and dequeue pointer will be handled by reset
2213 * ep command completion
2214 */
2215 if ((ep->ep_state & EP_HALTED) &&
2216 !list_empty(&td->cancelled_td_list)) {
2217 xhci_dbg(xhci, "Already resolving halted ep for 0x%llx\n",
2218 (unsigned long long)xhci_trb_virt_to_dma(
2219 td->start_seg, td->first_trb));
2220 return 0;
2221 }
2222 /* endpoint not halted, don't reset it */
2223 break;
2224 }
2225 /* Almost same procedure as for STALL_ERROR below */
2226 xhci_clear_hub_tt_buffer(xhci, td, ep);
2227 xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET);
2228 return 0;
2229 case COMP_STALL_ERROR:
2230 /*
2231 * xhci internal endpoint state will go to a "halt" state for
2232 * any stall, including default control pipe protocol stall.
2233 * To clear the host side halt we need to issue a reset endpoint
2234 * command, followed by a set dequeue command to move past the
2235 * TD.
2236 * Class drivers clear the device side halt from a functional
2237 * stall later. Hub TT buffer should only be cleared for FS/LS
2238 * devices behind HS hubs for functional stalls.
2239 */
2240 if (ep->ep_index != 0)
2241 xhci_clear_hub_tt_buffer(xhci, td, ep);
2242
2243 xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET);
2244
2245 return 0; /* xhci_handle_halted_endpoint marked td cancelled */
2246 default:
2247 break;
2248 }
2249
2250 /* Update ring dequeue pointer */
2251 ep_ring->dequeue = td->last_trb;
2252 ep_ring->deq_seg = td->last_trb_seg;
2253 inc_deq(xhci, ep_ring);
2254
2255 return xhci_td_cleanup(xhci, td, ep_ring, td->status);
2256}
2257
2258/* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
2259static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
2260 union xhci_trb *stop_trb)
2261{
2262 u32 sum;
2263 union xhci_trb *trb = ring->dequeue;
2264 struct xhci_segment *seg = ring->deq_seg;
2265
2266 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
2267 if (!trb_is_noop(trb) && !trb_is_link(trb))
2268 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
2269 }
2270 return sum;
2271}
2272
2273/*
2274 * Process control tds, update urb status and actual_length.
2275 */
2276static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2277 struct xhci_ring *ep_ring, struct xhci_td *td,
2278 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2279{
2280 struct xhci_ep_ctx *ep_ctx;
2281 u32 trb_comp_code;
2282 u32 remaining, requested;
2283 u32 trb_type;
2284
2285 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
2286 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2287 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2288 requested = td->urb->transfer_buffer_length;
2289 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2290
2291 switch (trb_comp_code) {
2292 case COMP_SUCCESS:
2293 if (trb_type != TRB_STATUS) {
2294 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
2295 (trb_type == TRB_DATA) ? "data" : "setup");
2296 td->status = -ESHUTDOWN;
2297 break;
2298 }
2299 td->status = 0;
2300 break;
2301 case COMP_SHORT_PACKET:
2302 td->status = 0;
2303 break;
2304 case COMP_STOPPED_SHORT_PACKET:
2305 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2306 td->urb->actual_length = remaining;
2307 else
2308 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2309 goto finish_td;
2310 case COMP_STOPPED:
2311 switch (trb_type) {
2312 case TRB_SETUP:
2313 td->urb->actual_length = 0;
2314 goto finish_td;
2315 case TRB_DATA:
2316 case TRB_NORMAL:
2317 td->urb->actual_length = requested - remaining;
2318 goto finish_td;
2319 case TRB_STATUS:
2320 td->urb->actual_length = requested;
2321 goto finish_td;
2322 default:
2323 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2324 trb_type);
2325 goto finish_td;
2326 }
2327 case COMP_STOPPED_LENGTH_INVALID:
2328 goto finish_td;
2329 default:
2330 if (!xhci_requires_manual_halt_cleanup(xhci,
2331 ep_ctx, trb_comp_code))
2332 break;
2333 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2334 trb_comp_code, ep->ep_index);
2335 fallthrough;
2336 case COMP_STALL_ERROR:
2337 /* Did we transfer part of the data (middle) phase? */
2338 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2339 td->urb->actual_length = requested - remaining;
2340 else if (!td->urb_length_set)
2341 td->urb->actual_length = 0;
2342 goto finish_td;
2343 }
2344
2345 /* stopped at setup stage, no data transferred */
2346 if (trb_type == TRB_SETUP)
2347 goto finish_td;
2348
2349 /*
2350 * if on data stage then update the actual_length of the URB and flag it
2351 * as set, so it won't be overwritten in the event for the last TRB.
2352 */
2353 if (trb_type == TRB_DATA ||
2354 trb_type == TRB_NORMAL) {
2355 td->urb_length_set = true;
2356 td->urb->actual_length = requested - remaining;
2357 xhci_dbg(xhci, "Waiting for status stage event\n");
2358 return 0;
2359 }
2360
2361 /* at status stage */
2362 if (!td->urb_length_set)
2363 td->urb->actual_length = requested;
2364
2365finish_td:
2366 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2367}
2368
2369/*
2370 * Process isochronous tds, update urb packet status and actual_length.
2371 */
2372static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2373 struct xhci_ring *ep_ring, struct xhci_td *td,
2374 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2375{
2376 struct urb_priv *urb_priv;
2377 int idx;
2378 struct usb_iso_packet_descriptor *frame;
2379 u32 trb_comp_code;
2380 bool sum_trbs_for_length = false;
2381 u32 remaining, requested, ep_trb_len;
2382 int short_framestatus;
2383
2384 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2385 urb_priv = td->urb->hcpriv;
2386 idx = urb_priv->num_tds_done;
2387 frame = &td->urb->iso_frame_desc[idx];
2388 requested = frame->length;
2389 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2390 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2391 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2392 -EREMOTEIO : 0;
2393
2394 /* handle completion code */
2395 switch (trb_comp_code) {
2396 case COMP_SUCCESS:
2397 /* Don't overwrite status if TD had an error, see xHCI 4.9.1 */
2398 if (td->error_mid_td)
2399 break;
2400 if (remaining) {
2401 frame->status = short_framestatus;
2402 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2403 sum_trbs_for_length = true;
2404 break;
2405 }
2406 frame->status = 0;
2407 break;
2408 case COMP_SHORT_PACKET:
2409 frame->status = short_framestatus;
2410 sum_trbs_for_length = true;
2411 break;
2412 case COMP_BANDWIDTH_OVERRUN_ERROR:
2413 frame->status = -ECOMM;
2414 break;
2415 case COMP_BABBLE_DETECTED_ERROR:
2416 sum_trbs_for_length = true;
2417 fallthrough;
2418 case COMP_ISOCH_BUFFER_OVERRUN:
2419 frame->status = -EOVERFLOW;
2420 if (ep_trb != td->last_trb)
2421 td->error_mid_td = true;
2422 break;
2423 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2424 case COMP_STALL_ERROR:
2425 frame->status = -EPROTO;
2426 break;
2427 case COMP_USB_TRANSACTION_ERROR:
2428 frame->status = -EPROTO;
2429 sum_trbs_for_length = true;
2430 if (ep_trb != td->last_trb)
2431 td->error_mid_td = true;
2432 break;
2433 case COMP_STOPPED:
2434 sum_trbs_for_length = true;
2435 break;
2436 case COMP_STOPPED_SHORT_PACKET:
2437 /* field normally containing residue now contains tranferred */
2438 frame->status = short_framestatus;
2439 requested = remaining;
2440 break;
2441 case COMP_STOPPED_LENGTH_INVALID:
2442 requested = 0;
2443 remaining = 0;
2444 break;
2445 default:
2446 sum_trbs_for_length = true;
2447 frame->status = -1;
2448 break;
2449 }
2450
2451 if (td->urb_length_set)
2452 goto finish_td;
2453
2454 if (sum_trbs_for_length)
2455 frame->actual_length = sum_trb_lengths(xhci, ep->ring, ep_trb) +
2456 ep_trb_len - remaining;
2457 else
2458 frame->actual_length = requested;
2459
2460 td->urb->actual_length += frame->actual_length;
2461
2462finish_td:
2463 /* Don't give back TD yet if we encountered an error mid TD */
2464 if (td->error_mid_td && ep_trb != td->last_trb) {
2465 xhci_dbg(xhci, "Error mid isoc TD, wait for final completion event\n");
2466 td->urb_length_set = true;
2467 return 0;
2468 }
2469
2470 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2471}
2472
2473static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2474 struct xhci_virt_ep *ep, int status)
2475{
2476 struct urb_priv *urb_priv;
2477 struct usb_iso_packet_descriptor *frame;
2478 int idx;
2479
2480 urb_priv = td->urb->hcpriv;
2481 idx = urb_priv->num_tds_done;
2482 frame = &td->urb->iso_frame_desc[idx];
2483
2484 /* The transfer is partly done. */
2485 frame->status = -EXDEV;
2486
2487 /* calc actual length */
2488 frame->actual_length = 0;
2489
2490 /* Update ring dequeue pointer */
2491 ep->ring->dequeue = td->last_trb;
2492 ep->ring->deq_seg = td->last_trb_seg;
2493 inc_deq(xhci, ep->ring);
2494
2495 return xhci_td_cleanup(xhci, td, ep->ring, status);
2496}
2497
2498/*
2499 * Process bulk and interrupt tds, update urb status and actual_length.
2500 */
2501static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2502 struct xhci_ring *ep_ring, struct xhci_td *td,
2503 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2504{
2505 struct xhci_slot_ctx *slot_ctx;
2506 u32 trb_comp_code;
2507 u32 remaining, requested, ep_trb_len;
2508
2509 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
2510 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2511 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2512 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2513 requested = td->urb->transfer_buffer_length;
2514
2515 switch (trb_comp_code) {
2516 case COMP_SUCCESS:
2517 ep->err_count = 0;
2518 /* handle success with untransferred data as short packet */
2519 if (ep_trb != td->last_trb || remaining) {
2520 xhci_warn(xhci, "WARN Successful completion on short TX\n");
2521 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2522 td->urb->ep->desc.bEndpointAddress,
2523 requested, remaining);
2524 }
2525 td->status = 0;
2526 break;
2527 case COMP_SHORT_PACKET:
2528 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2529 td->urb->ep->desc.bEndpointAddress,
2530 requested, remaining);
2531 td->status = 0;
2532 break;
2533 case COMP_STOPPED_SHORT_PACKET:
2534 td->urb->actual_length = remaining;
2535 goto finish_td;
2536 case COMP_STOPPED_LENGTH_INVALID:
2537 /* stopped on ep trb with invalid length, exclude it */
2538 ep_trb_len = 0;
2539 remaining = 0;
2540 break;
2541 case COMP_USB_TRANSACTION_ERROR:
2542 if (xhci->quirks & XHCI_NO_SOFT_RETRY ||
2543 (ep->err_count++ > MAX_SOFT_RETRY) ||
2544 le32_to_cpu(slot_ctx->tt_info) & TT_SLOT)
2545 break;
2546
2547 td->status = 0;
2548
2549 xhci_handle_halted_endpoint(xhci, ep, td, EP_SOFT_RESET);
2550 return 0;
2551 default:
2552 /* do nothing */
2553 break;
2554 }
2555
2556 if (ep_trb == td->last_trb)
2557 td->urb->actual_length = requested - remaining;
2558 else
2559 td->urb->actual_length =
2560 sum_trb_lengths(xhci, ep_ring, ep_trb) +
2561 ep_trb_len - remaining;
2562finish_td:
2563 if (remaining > requested) {
2564 xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2565 remaining);
2566 td->urb->actual_length = 0;
2567 }
2568
2569 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2570}
2571
2572/*
2573 * If this function returns an error condition, it means it got a Transfer
2574 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2575 * At this point, the host controller is probably hosed and should be reset.
2576 */
2577static int handle_tx_event(struct xhci_hcd *xhci,
2578 struct xhci_interrupter *ir,
2579 struct xhci_transfer_event *event)
2580{
2581 struct xhci_virt_ep *ep;
2582 struct xhci_ring *ep_ring;
2583 unsigned int slot_id;
2584 int ep_index;
2585 struct xhci_td *td = NULL;
2586 dma_addr_t ep_trb_dma;
2587 struct xhci_segment *ep_seg;
2588 union xhci_trb *ep_trb;
2589 int status = -EINPROGRESS;
2590 struct xhci_ep_ctx *ep_ctx;
2591 u32 trb_comp_code;
2592 int td_num = 0;
2593 bool handling_skipped_tds = false;
2594
2595 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2596 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2597 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2598 ep_trb_dma = le64_to_cpu(event->buffer);
2599
2600 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
2601 if (!ep) {
2602 xhci_err(xhci, "ERROR Invalid Transfer event\n");
2603 goto err_out;
2604 }
2605
2606 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2607 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
2608
2609 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2610 xhci_err(xhci,
2611 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2612 slot_id, ep_index);
2613 goto err_out;
2614 }
2615
2616 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2617 if (!ep_ring) {
2618 switch (trb_comp_code) {
2619 case COMP_STALL_ERROR:
2620 case COMP_USB_TRANSACTION_ERROR:
2621 case COMP_INVALID_STREAM_TYPE_ERROR:
2622 case COMP_INVALID_STREAM_ID_ERROR:
2623 xhci_dbg(xhci, "Stream transaction error ep %u no id\n",
2624 ep_index);
2625 if (ep->err_count++ > MAX_SOFT_RETRY)
2626 xhci_handle_halted_endpoint(xhci, ep, NULL,
2627 EP_HARD_RESET);
2628 else
2629 xhci_handle_halted_endpoint(xhci, ep, NULL,
2630 EP_SOFT_RESET);
2631 goto cleanup;
2632 case COMP_RING_UNDERRUN:
2633 case COMP_RING_OVERRUN:
2634 case COMP_STOPPED_LENGTH_INVALID:
2635 goto cleanup;
2636 default:
2637 xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2638 slot_id, ep_index);
2639 goto err_out;
2640 }
2641 }
2642
2643 /* Count current td numbers if ep->skip is set */
2644 if (ep->skip)
2645 td_num += list_count_nodes(&ep_ring->td_list);
2646
2647 /* Look for common error cases */
2648 switch (trb_comp_code) {
2649 /* Skip codes that require special handling depending on
2650 * transfer type
2651 */
2652 case COMP_SUCCESS:
2653 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2654 break;
2655 if (xhci->quirks & XHCI_TRUST_TX_LENGTH ||
2656 ep_ring->last_td_was_short)
2657 trb_comp_code = COMP_SHORT_PACKET;
2658 else
2659 xhci_warn_ratelimited(xhci,
2660 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2661 slot_id, ep_index);
2662 break;
2663 case COMP_SHORT_PACKET:
2664 break;
2665 /* Completion codes for endpoint stopped state */
2666 case COMP_STOPPED:
2667 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2668 slot_id, ep_index);
2669 break;
2670 case COMP_STOPPED_LENGTH_INVALID:
2671 xhci_dbg(xhci,
2672 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2673 slot_id, ep_index);
2674 break;
2675 case COMP_STOPPED_SHORT_PACKET:
2676 xhci_dbg(xhci,
2677 "Stopped with short packet transfer detected for slot %u ep %u\n",
2678 slot_id, ep_index);
2679 break;
2680 /* Completion codes for endpoint halted state */
2681 case COMP_STALL_ERROR:
2682 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2683 ep_index);
2684 status = -EPIPE;
2685 break;
2686 case COMP_SPLIT_TRANSACTION_ERROR:
2687 xhci_dbg(xhci, "Split transaction error for slot %u ep %u\n",
2688 slot_id, ep_index);
2689 status = -EPROTO;
2690 break;
2691 case COMP_USB_TRANSACTION_ERROR:
2692 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2693 slot_id, ep_index);
2694 status = -EPROTO;
2695 break;
2696 case COMP_BABBLE_DETECTED_ERROR:
2697 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2698 slot_id, ep_index);
2699 status = -EOVERFLOW;
2700 break;
2701 /* Completion codes for endpoint error state */
2702 case COMP_TRB_ERROR:
2703 xhci_warn(xhci,
2704 "WARN: TRB error for slot %u ep %u on endpoint\n",
2705 slot_id, ep_index);
2706 status = -EILSEQ;
2707 break;
2708 /* completion codes not indicating endpoint state change */
2709 case COMP_DATA_BUFFER_ERROR:
2710 xhci_warn(xhci,
2711 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2712 slot_id, ep_index);
2713 status = -ENOSR;
2714 break;
2715 case COMP_BANDWIDTH_OVERRUN_ERROR:
2716 xhci_warn(xhci,
2717 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2718 slot_id, ep_index);
2719 break;
2720 case COMP_ISOCH_BUFFER_OVERRUN:
2721 xhci_warn(xhci,
2722 "WARN: buffer overrun event for slot %u ep %u on endpoint",
2723 slot_id, ep_index);
2724 break;
2725 case COMP_RING_UNDERRUN:
2726 /*
2727 * When the Isoch ring is empty, the xHC will generate
2728 * a Ring Overrun Event for IN Isoch endpoint or Ring
2729 * Underrun Event for OUT Isoch endpoint.
2730 */
2731 xhci_dbg(xhci, "underrun event on endpoint\n");
2732 if (!list_empty(&ep_ring->td_list))
2733 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2734 "still with TDs queued?\n",
2735 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2736 ep_index);
2737 goto cleanup;
2738 case COMP_RING_OVERRUN:
2739 xhci_dbg(xhci, "overrun event on endpoint\n");
2740 if (!list_empty(&ep_ring->td_list))
2741 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2742 "still with TDs queued?\n",
2743 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2744 ep_index);
2745 goto cleanup;
2746 case COMP_MISSED_SERVICE_ERROR:
2747 /*
2748 * When encounter missed service error, one or more isoc tds
2749 * may be missed by xHC.
2750 * Set skip flag of the ep_ring; Complete the missed tds as
2751 * short transfer when process the ep_ring next time.
2752 */
2753 ep->skip = true;
2754 xhci_dbg(xhci,
2755 "Miss service interval error for slot %u ep %u, set skip flag\n",
2756 slot_id, ep_index);
2757 goto cleanup;
2758 case COMP_NO_PING_RESPONSE_ERROR:
2759 ep->skip = true;
2760 xhci_dbg(xhci,
2761 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2762 slot_id, ep_index);
2763 goto cleanup;
2764
2765 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2766 /* needs disable slot command to recover */
2767 xhci_warn(xhci,
2768 "WARN: detect an incompatible device for slot %u ep %u",
2769 slot_id, ep_index);
2770 status = -EPROTO;
2771 break;
2772 default:
2773 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2774 status = 0;
2775 break;
2776 }
2777 xhci_warn(xhci,
2778 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2779 trb_comp_code, slot_id, ep_index);
2780 goto cleanup;
2781 }
2782
2783 do {
2784 /* This TRB should be in the TD at the head of this ring's
2785 * TD list.
2786 */
2787 if (list_empty(&ep_ring->td_list)) {
2788 /*
2789 * Don't print wanings if it's due to a stopped endpoint
2790 * generating an extra completion event if the device
2791 * was suspended. Or, a event for the last TRB of a
2792 * short TD we already got a short event for.
2793 * The short TD is already removed from the TD list.
2794 */
2795
2796 if (!(trb_comp_code == COMP_STOPPED ||
2797 trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2798 ep_ring->last_td_was_short)) {
2799 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2800 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2801 ep_index);
2802 }
2803 if (ep->skip) {
2804 ep->skip = false;
2805 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2806 slot_id, ep_index);
2807 }
2808 if (trb_comp_code == COMP_STALL_ERROR ||
2809 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2810 trb_comp_code)) {
2811 xhci_handle_halted_endpoint(xhci, ep, NULL,
2812 EP_HARD_RESET);
2813 }
2814 goto cleanup;
2815 }
2816
2817 /* We've skipped all the TDs on the ep ring when ep->skip set */
2818 if (ep->skip && td_num == 0) {
2819 ep->skip = false;
2820 xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2821 slot_id, ep_index);
2822 goto cleanup;
2823 }
2824
2825 td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2826 td_list);
2827 if (ep->skip)
2828 td_num--;
2829
2830 /* Is this a TRB in the currently executing TD? */
2831 ep_seg = trb_in_td(xhci, td->start_seg, td->first_trb,
2832 td->last_trb, ep_trb_dma, false);
2833
2834 /*
2835 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2836 * is not in the current TD pointed by ep_ring->dequeue because
2837 * that the hardware dequeue pointer still at the previous TRB
2838 * of the current TD. The previous TRB maybe a Link TD or the
2839 * last TRB of the previous TD. The command completion handle
2840 * will take care the rest.
2841 */
2842 if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2843 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2844 goto cleanup;
2845 }
2846
2847 if (!ep_seg) {
2848
2849 if (ep->skip && usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2850 skip_isoc_td(xhci, td, ep, status);
2851 goto cleanup;
2852 }
2853
2854 /*
2855 * Some hosts give a spurious success event after a short
2856 * transfer. Ignore it.
2857 */
2858 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2859 ep_ring->last_td_was_short) {
2860 ep_ring->last_td_was_short = false;
2861 goto cleanup;
2862 }
2863
2864 /*
2865 * xhci 4.10.2 states isoc endpoints should continue
2866 * processing the next TD if there was an error mid TD.
2867 * So host like NEC don't generate an event for the last
2868 * isoc TRB even if the IOC flag is set.
2869 * xhci 4.9.1 states that if there are errors in mult-TRB
2870 * TDs xHC should generate an error for that TRB, and if xHC
2871 * proceeds to the next TD it should genete an event for
2872 * any TRB with IOC flag on the way. Other host follow this.
2873 * So this event might be for the next TD.
2874 */
2875 if (td->error_mid_td &&
2876 !list_is_last(&td->td_list, &ep_ring->td_list)) {
2877 struct xhci_td *td_next = list_next_entry(td, td_list);
2878
2879 ep_seg = trb_in_td(xhci, td_next->start_seg, td_next->first_trb,
2880 td_next->last_trb, ep_trb_dma, false);
2881 if (ep_seg) {
2882 /* give back previous TD, start handling new */
2883 xhci_dbg(xhci, "Missing TD completion event after mid TD error\n");
2884 ep_ring->dequeue = td->last_trb;
2885 ep_ring->deq_seg = td->last_trb_seg;
2886 inc_deq(xhci, ep_ring);
2887 xhci_td_cleanup(xhci, td, ep_ring, td->status);
2888 td = td_next;
2889 }
2890 }
2891
2892 if (!ep_seg) {
2893 /* HC is busted, give up! */
2894 xhci_err(xhci,
2895 "ERROR Transfer event TRB DMA ptr not "
2896 "part of current TD ep_index %d "
2897 "comp_code %u\n", ep_index,
2898 trb_comp_code);
2899 trb_in_td(xhci, td->start_seg, td->first_trb,
2900 td->last_trb, ep_trb_dma, true);
2901 return -ESHUTDOWN;
2902 }
2903 }
2904 if (trb_comp_code == COMP_SHORT_PACKET)
2905 ep_ring->last_td_was_short = true;
2906 else
2907 ep_ring->last_td_was_short = false;
2908
2909 if (ep->skip) {
2910 xhci_dbg(xhci,
2911 "Found td. Clear skip flag for slot %u ep %u.\n",
2912 slot_id, ep_index);
2913 ep->skip = false;
2914 }
2915
2916 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2917 sizeof(*ep_trb)];
2918
2919 trace_xhci_handle_transfer(ep_ring,
2920 (struct xhci_generic_trb *) ep_trb);
2921
2922 /*
2923 * No-op TRB could trigger interrupts in a case where
2924 * a URB was killed and a STALL_ERROR happens right
2925 * after the endpoint ring stopped. Reset the halted
2926 * endpoint. Otherwise, the endpoint remains stalled
2927 * indefinitely.
2928 */
2929
2930 if (trb_is_noop(ep_trb)) {
2931 if (trb_comp_code == COMP_STALL_ERROR ||
2932 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2933 trb_comp_code))
2934 xhci_handle_halted_endpoint(xhci, ep, td,
2935 EP_HARD_RESET);
2936 goto cleanup;
2937 }
2938
2939 td->status = status;
2940
2941 /* update the urb's actual_length and give back to the core */
2942 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2943 process_ctrl_td(xhci, ep, ep_ring, td, ep_trb, event);
2944 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2945 process_isoc_td(xhci, ep, ep_ring, td, ep_trb, event);
2946 else
2947 process_bulk_intr_td(xhci, ep, ep_ring, td, ep_trb, event);
2948cleanup:
2949 handling_skipped_tds = ep->skip &&
2950 trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2951 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2952
2953 /*
2954 * If ep->skip is set, it means there are missed tds on the
2955 * endpoint ring need to take care of.
2956 * Process them as short transfer until reach the td pointed by
2957 * the event.
2958 */
2959 } while (handling_skipped_tds);
2960
2961 return 0;
2962
2963err_out:
2964 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2965 (unsigned long long) xhci_trb_virt_to_dma(
2966 ir->event_ring->deq_seg,
2967 ir->event_ring->dequeue),
2968 lower_32_bits(le64_to_cpu(event->buffer)),
2969 upper_32_bits(le64_to_cpu(event->buffer)),
2970 le32_to_cpu(event->transfer_len),
2971 le32_to_cpu(event->flags));
2972 return -ENODEV;
2973}
2974
2975/*
2976 * This function handles one OS-owned event on the event ring. It may drop
2977 * xhci->lock between event processing (e.g. to pass up port status changes).
2978 */
2979static int xhci_handle_event_trb(struct xhci_hcd *xhci, struct xhci_interrupter *ir,
2980 union xhci_trb *event)
2981{
2982 u32 trb_type;
2983
2984 trace_xhci_handle_event(ir->event_ring, &event->generic);
2985
2986 /*
2987 * Barrier between reading the TRB_CYCLE (valid) flag before, and any
2988 * speculative reads of the event's flags/data below.
2989 */
2990 rmb();
2991 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
2992 /* FIXME: Handle more event types. */
2993
2994 switch (trb_type) {
2995 case TRB_COMPLETION:
2996 handle_cmd_completion(xhci, &event->event_cmd);
2997 break;
2998 case TRB_PORT_STATUS:
2999 handle_port_status(xhci, ir, event);
3000 break;
3001 case TRB_TRANSFER:
3002 handle_tx_event(xhci, ir, &event->trans_event);
3003 break;
3004 case TRB_DEV_NOTE:
3005 handle_device_notification(xhci, event);
3006 break;
3007 default:
3008 if (trb_type >= TRB_VENDOR_DEFINED_LOW)
3009 handle_vendor_event(xhci, event, trb_type);
3010 else
3011 xhci_warn(xhci, "ERROR unknown event type %d\n", trb_type);
3012 }
3013 /* Any of the above functions may drop and re-acquire the lock, so check
3014 * to make sure a watchdog timer didn't mark the host as non-responsive.
3015 */
3016 if (xhci->xhc_state & XHCI_STATE_DYING) {
3017 xhci_dbg(xhci, "xHCI host dying, returning from event handler.\n");
3018 return -ENODEV;
3019 }
3020
3021 return 0;
3022}
3023
3024/*
3025 * Update Event Ring Dequeue Pointer:
3026 * - When all events have finished
3027 * - To avoid "Event Ring Full Error" condition
3028 */
3029static void xhci_update_erst_dequeue(struct xhci_hcd *xhci,
3030 struct xhci_interrupter *ir,
3031 bool clear_ehb)
3032{
3033 u64 temp_64;
3034 dma_addr_t deq;
3035
3036 temp_64 = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
3037 deq = xhci_trb_virt_to_dma(ir->event_ring->deq_seg,
3038 ir->event_ring->dequeue);
3039 if (deq == 0)
3040 xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n");
3041 /*
3042 * Per 4.9.4, Software writes to the ERDP register shall always advance
3043 * the Event Ring Dequeue Pointer value.
3044 */
3045 if ((temp_64 & ERST_PTR_MASK) == (deq & ERST_PTR_MASK) && !clear_ehb)
3046 return;
3047
3048 /* Update HC event ring dequeue pointer */
3049 temp_64 = ir->event_ring->deq_seg->num & ERST_DESI_MASK;
3050 temp_64 |= deq & ERST_PTR_MASK;
3051
3052 /* Clear the event handler busy flag (RW1C) */
3053 if (clear_ehb)
3054 temp_64 |= ERST_EHB;
3055 xhci_write_64(xhci, temp_64, &ir->ir_set->erst_dequeue);
3056}
3057
3058/* Clear the interrupt pending bit for a specific interrupter. */
3059static void xhci_clear_interrupt_pending(struct xhci_hcd *xhci,
3060 struct xhci_interrupter *ir)
3061{
3062 if (!ir->ip_autoclear) {
3063 u32 irq_pending;
3064
3065 irq_pending = readl(&ir->ir_set->irq_pending);
3066 irq_pending |= IMAN_IP;
3067 writel(irq_pending, &ir->ir_set->irq_pending);
3068 }
3069}
3070
3071/*
3072 * Handle all OS-owned events on an interrupter event ring. It may drop
3073 * and reaquire xhci->lock between event processing.
3074 */
3075static int xhci_handle_events(struct xhci_hcd *xhci, struct xhci_interrupter *ir)
3076{
3077 int event_loop = 0;
3078 int err;
3079 u64 temp;
3080
3081 xhci_clear_interrupt_pending(xhci, ir);
3082
3083 /* Event ring hasn't been allocated yet. */
3084 if (!ir->event_ring || !ir->event_ring->dequeue) {
3085 xhci_err(xhci, "ERROR interrupter event ring not ready\n");
3086 return -ENOMEM;
3087 }
3088
3089 if (xhci->xhc_state & XHCI_STATE_DYING ||
3090 xhci->xhc_state & XHCI_STATE_HALTED) {
3091 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. Shouldn't IRQs be disabled?\n");
3092
3093 /* Clear the event handler busy flag (RW1C) */
3094 temp = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
3095 xhci_write_64(xhci, temp | ERST_EHB, &ir->ir_set->erst_dequeue);
3096 return -ENODEV;
3097 }
3098
3099 /* Process all OS owned event TRBs on this event ring */
3100 while (unhandled_event_trb(ir->event_ring)) {
3101 err = xhci_handle_event_trb(xhci, ir, ir->event_ring->dequeue);
3102
3103 /*
3104 * If half a segment of events have been handled in one go then
3105 * update ERDP, and force isoc trbs to interrupt more often
3106 */
3107 if (event_loop++ > TRBS_PER_SEGMENT / 2) {
3108 xhci_update_erst_dequeue(xhci, ir, false);
3109
3110 if (ir->isoc_bei_interval > AVOID_BEI_INTERVAL_MIN)
3111 ir->isoc_bei_interval = ir->isoc_bei_interval / 2;
3112
3113 event_loop = 0;
3114 }
3115
3116 /* Update SW event ring dequeue pointer */
3117 inc_deq(xhci, ir->event_ring);
3118
3119 if (err)
3120 break;
3121 }
3122
3123 xhci_update_erst_dequeue(xhci, ir, true);
3124
3125 return 0;
3126}
3127
3128/*
3129 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
3130 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
3131 * indicators of an event TRB error, but we check the status *first* to be safe.
3132 */
3133irqreturn_t xhci_irq(struct usb_hcd *hcd)
3134{
3135 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3136 irqreturn_t ret = IRQ_HANDLED;
3137 u32 status;
3138
3139 spin_lock(&xhci->lock);
3140 /* Check if the xHC generated the interrupt, or the irq is shared */
3141 status = readl(&xhci->op_regs->status);
3142 if (status == ~(u32)0) {
3143 xhci_hc_died(xhci);
3144 goto out;
3145 }
3146
3147 if (!(status & STS_EINT)) {
3148 ret = IRQ_NONE;
3149 goto out;
3150 }
3151
3152 if (status & STS_HCE) {
3153 xhci_warn(xhci, "WARNING: Host Controller Error\n");
3154 goto out;
3155 }
3156
3157 if (status & STS_FATAL) {
3158 xhci_warn(xhci, "WARNING: Host System Error\n");
3159 xhci_halt(xhci);
3160 goto out;
3161 }
3162
3163 /*
3164 * Clear the op reg interrupt status first,
3165 * so we can receive interrupts from other MSI-X interrupters.
3166 * Write 1 to clear the interrupt status.
3167 */
3168 status |= STS_EINT;
3169 writel(status, &xhci->op_regs->status);
3170
3171 /* This is the handler of the primary interrupter */
3172 xhci_handle_events(xhci, xhci->interrupters[0]);
3173out:
3174 spin_unlock(&xhci->lock);
3175
3176 return ret;
3177}
3178
3179irqreturn_t xhci_msi_irq(int irq, void *hcd)
3180{
3181 return xhci_irq(hcd);
3182}
3183EXPORT_SYMBOL_GPL(xhci_msi_irq);
3184
3185/**** Endpoint Ring Operations ****/
3186
3187/*
3188 * Generic function for queueing a TRB on a ring.
3189 * The caller must have checked to make sure there's room on the ring.
3190 *
3191 * @more_trbs_coming: Will you enqueue more TRBs before calling
3192 * prepare_transfer()?
3193 */
3194static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
3195 bool more_trbs_coming,
3196 u32 field1, u32 field2, u32 field3, u32 field4)
3197{
3198 struct xhci_generic_trb *trb;
3199
3200 trb = &ring->enqueue->generic;
3201 trb->field[0] = cpu_to_le32(field1);
3202 trb->field[1] = cpu_to_le32(field2);
3203 trb->field[2] = cpu_to_le32(field3);
3204 /* make sure TRB is fully written before giving it to the controller */
3205 wmb();
3206 trb->field[3] = cpu_to_le32(field4);
3207
3208 trace_xhci_queue_trb(ring, trb);
3209
3210 inc_enq(xhci, ring, more_trbs_coming);
3211}
3212
3213/*
3214 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
3215 * expand ring if it start to be full.
3216 */
3217static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
3218 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
3219{
3220 unsigned int link_trb_count = 0;
3221 unsigned int new_segs = 0;
3222
3223 /* Make sure the endpoint has been added to xHC schedule */
3224 switch (ep_state) {
3225 case EP_STATE_DISABLED:
3226 /*
3227 * USB core changed config/interfaces without notifying us,
3228 * or hardware is reporting the wrong state.
3229 */
3230 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
3231 return -ENOENT;
3232 case EP_STATE_ERROR:
3233 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
3234 /* FIXME event handling code for error needs to clear it */
3235 /* XXX not sure if this should be -ENOENT or not */
3236 return -EINVAL;
3237 case EP_STATE_HALTED:
3238 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
3239 break;
3240 case EP_STATE_STOPPED:
3241 case EP_STATE_RUNNING:
3242 break;
3243 default:
3244 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
3245 /*
3246 * FIXME issue Configure Endpoint command to try to get the HC
3247 * back into a known state.
3248 */
3249 return -EINVAL;
3250 }
3251
3252 if (ep_ring != xhci->cmd_ring) {
3253 new_segs = xhci_ring_expansion_needed(xhci, ep_ring, num_trbs);
3254 } else if (xhci_num_trbs_free(xhci, ep_ring) <= num_trbs) {
3255 xhci_err(xhci, "Do not support expand command ring\n");
3256 return -ENOMEM;
3257 }
3258
3259 if (new_segs) {
3260 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
3261 "ERROR no room on ep ring, try ring expansion");
3262 if (xhci_ring_expansion(xhci, ep_ring, new_segs, mem_flags)) {
3263 xhci_err(xhci, "Ring expansion failed\n");
3264 return -ENOMEM;
3265 }
3266 }
3267
3268 while (trb_is_link(ep_ring->enqueue)) {
3269 /* If we're not dealing with 0.95 hardware or isoc rings
3270 * on AMD 0.96 host, clear the chain bit.
3271 */
3272 if (!xhci_link_trb_quirk(xhci) &&
3273 !(ep_ring->type == TYPE_ISOC &&
3274 (xhci->quirks & XHCI_AMD_0x96_HOST)))
3275 ep_ring->enqueue->link.control &=
3276 cpu_to_le32(~TRB_CHAIN);
3277 else
3278 ep_ring->enqueue->link.control |=
3279 cpu_to_le32(TRB_CHAIN);
3280
3281 wmb();
3282 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
3283
3284 /* Toggle the cycle bit after the last ring segment. */
3285 if (link_trb_toggles_cycle(ep_ring->enqueue))
3286 ep_ring->cycle_state ^= 1;
3287
3288 ep_ring->enq_seg = ep_ring->enq_seg->next;
3289 ep_ring->enqueue = ep_ring->enq_seg->trbs;
3290
3291 /* prevent infinite loop if all first trbs are link trbs */
3292 if (link_trb_count++ > ep_ring->num_segs) {
3293 xhci_warn(xhci, "Ring is an endless link TRB loop\n");
3294 return -EINVAL;
3295 }
3296 }
3297
3298 if (last_trb_on_seg(ep_ring->enq_seg, ep_ring->enqueue)) {
3299 xhci_warn(xhci, "Missing link TRB at end of ring segment\n");
3300 return -EINVAL;
3301 }
3302
3303 return 0;
3304}
3305
3306static int prepare_transfer(struct xhci_hcd *xhci,
3307 struct xhci_virt_device *xdev,
3308 unsigned int ep_index,
3309 unsigned int stream_id,
3310 unsigned int num_trbs,
3311 struct urb *urb,
3312 unsigned int td_index,
3313 gfp_t mem_flags)
3314{
3315 int ret;
3316 struct urb_priv *urb_priv;
3317 struct xhci_td *td;
3318 struct xhci_ring *ep_ring;
3319 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3320
3321 ep_ring = xhci_triad_to_transfer_ring(xhci, xdev->slot_id, ep_index,
3322 stream_id);
3323 if (!ep_ring) {
3324 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3325 stream_id);
3326 return -EINVAL;
3327 }
3328
3329 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3330 num_trbs, mem_flags);
3331 if (ret)
3332 return ret;
3333
3334 urb_priv = urb->hcpriv;
3335 td = &urb_priv->td[td_index];
3336
3337 INIT_LIST_HEAD(&td->td_list);
3338 INIT_LIST_HEAD(&td->cancelled_td_list);
3339
3340 if (td_index == 0) {
3341 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3342 if (unlikely(ret))
3343 return ret;
3344 }
3345
3346 td->urb = urb;
3347 /* Add this TD to the tail of the endpoint ring's TD list */
3348 list_add_tail(&td->td_list, &ep_ring->td_list);
3349 td->start_seg = ep_ring->enq_seg;
3350 td->first_trb = ep_ring->enqueue;
3351
3352 return 0;
3353}
3354
3355unsigned int count_trbs(u64 addr, u64 len)
3356{
3357 unsigned int num_trbs;
3358
3359 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3360 TRB_MAX_BUFF_SIZE);
3361 if (num_trbs == 0)
3362 num_trbs++;
3363
3364 return num_trbs;
3365}
3366
3367static inline unsigned int count_trbs_needed(struct urb *urb)
3368{
3369 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
3370}
3371
3372static unsigned int count_sg_trbs_needed(struct urb *urb)
3373{
3374 struct scatterlist *sg;
3375 unsigned int i, len, full_len, num_trbs = 0;
3376
3377 full_len = urb->transfer_buffer_length;
3378
3379 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
3380 len = sg_dma_len(sg);
3381 num_trbs += count_trbs(sg_dma_address(sg), len);
3382 len = min_t(unsigned int, len, full_len);
3383 full_len -= len;
3384 if (full_len == 0)
3385 break;
3386 }
3387
3388 return num_trbs;
3389}
3390
3391static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3392{
3393 u64 addr, len;
3394
3395 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3396 len = urb->iso_frame_desc[i].length;
3397
3398 return count_trbs(addr, len);
3399}
3400
3401static void check_trb_math(struct urb *urb, int running_total)
3402{
3403 if (unlikely(running_total != urb->transfer_buffer_length))
3404 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3405 "queued %#x (%d), asked for %#x (%d)\n",
3406 __func__,
3407 urb->ep->desc.bEndpointAddress,
3408 running_total, running_total,
3409 urb->transfer_buffer_length,
3410 urb->transfer_buffer_length);
3411}
3412
3413static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3414 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3415 struct xhci_generic_trb *start_trb)
3416{
3417 /*
3418 * Pass all the TRBs to the hardware at once and make sure this write
3419 * isn't reordered.
3420 */
3421 wmb();
3422 if (start_cycle)
3423 start_trb->field[3] |= cpu_to_le32(start_cycle);
3424 else
3425 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3426 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3427}
3428
3429static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3430 struct xhci_ep_ctx *ep_ctx)
3431{
3432 int xhci_interval;
3433 int ep_interval;
3434
3435 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3436 ep_interval = urb->interval;
3437
3438 /* Convert to microframes */
3439 if (urb->dev->speed == USB_SPEED_LOW ||
3440 urb->dev->speed == USB_SPEED_FULL)
3441 ep_interval *= 8;
3442
3443 /* FIXME change this to a warning and a suggestion to use the new API
3444 * to set the polling interval (once the API is added).
3445 */
3446 if (xhci_interval != ep_interval) {
3447 dev_dbg_ratelimited(&urb->dev->dev,
3448 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3449 ep_interval, ep_interval == 1 ? "" : "s",
3450 xhci_interval, xhci_interval == 1 ? "" : "s");
3451 urb->interval = xhci_interval;
3452 /* Convert back to frames for LS/FS devices */
3453 if (urb->dev->speed == USB_SPEED_LOW ||
3454 urb->dev->speed == USB_SPEED_FULL)
3455 urb->interval /= 8;
3456 }
3457}
3458
3459/*
3460 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3461 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3462 * (comprised of sg list entries) can take several service intervals to
3463 * transmit.
3464 */
3465int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3466 struct urb *urb, int slot_id, unsigned int ep_index)
3467{
3468 struct xhci_ep_ctx *ep_ctx;
3469
3470 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3471 check_interval(xhci, urb, ep_ctx);
3472
3473 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3474}
3475
3476/*
3477 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3478 * packets remaining in the TD (*not* including this TRB).
3479 *
3480 * Total TD packet count = total_packet_count =
3481 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3482 *
3483 * Packets transferred up to and including this TRB = packets_transferred =
3484 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3485 *
3486 * TD size = total_packet_count - packets_transferred
3487 *
3488 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3489 * including this TRB, right shifted by 10
3490 *
3491 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3492 * This is taken care of in the TRB_TD_SIZE() macro
3493 *
3494 * The last TRB in a TD must have the TD size set to zero.
3495 */
3496static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3497 int trb_buff_len, unsigned int td_total_len,
3498 struct urb *urb, bool more_trbs_coming)
3499{
3500 u32 maxp, total_packet_count;
3501
3502 /* MTK xHCI 0.96 contains some features from 1.0 */
3503 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3504 return ((td_total_len - transferred) >> 10);
3505
3506 /* One TRB with a zero-length data packet. */
3507 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3508 trb_buff_len == td_total_len)
3509 return 0;
3510
3511 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3512 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3513 trb_buff_len = 0;
3514
3515 maxp = usb_endpoint_maxp(&urb->ep->desc);
3516 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3517
3518 /* Queueing functions don't count the current TRB into transferred */
3519 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3520}
3521
3522
3523static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3524 u32 *trb_buff_len, struct xhci_segment *seg)
3525{
3526 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
3527 unsigned int unalign;
3528 unsigned int max_pkt;
3529 u32 new_buff_len;
3530 size_t len;
3531
3532 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3533 unalign = (enqd_len + *trb_buff_len) % max_pkt;
3534
3535 /* we got lucky, last normal TRB data on segment is packet aligned */
3536 if (unalign == 0)
3537 return 0;
3538
3539 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3540 unalign, *trb_buff_len);
3541
3542 /* is the last nornal TRB alignable by splitting it */
3543 if (*trb_buff_len > unalign) {
3544 *trb_buff_len -= unalign;
3545 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3546 return 0;
3547 }
3548
3549 /*
3550 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3551 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3552 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3553 */
3554 new_buff_len = max_pkt - (enqd_len % max_pkt);
3555
3556 if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3557 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3558
3559 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3560 if (usb_urb_dir_out(urb)) {
3561 if (urb->num_sgs) {
3562 len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3563 seg->bounce_buf, new_buff_len, enqd_len);
3564 if (len != new_buff_len)
3565 xhci_warn(xhci, "WARN Wrong bounce buffer write length: %zu != %d\n",
3566 len, new_buff_len);
3567 } else {
3568 memcpy(seg->bounce_buf, urb->transfer_buffer + enqd_len, new_buff_len);
3569 }
3570
3571 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3572 max_pkt, DMA_TO_DEVICE);
3573 } else {
3574 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3575 max_pkt, DMA_FROM_DEVICE);
3576 }
3577
3578 if (dma_mapping_error(dev, seg->bounce_dma)) {
3579 /* try without aligning. Some host controllers survive */
3580 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3581 return 0;
3582 }
3583 *trb_buff_len = new_buff_len;
3584 seg->bounce_len = new_buff_len;
3585 seg->bounce_offs = enqd_len;
3586
3587 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3588
3589 return 1;
3590}
3591
3592/* This is very similar to what ehci-q.c qtd_fill() does */
3593int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3594 struct urb *urb, int slot_id, unsigned int ep_index)
3595{
3596 struct xhci_ring *ring;
3597 struct urb_priv *urb_priv;
3598 struct xhci_td *td;
3599 struct xhci_generic_trb *start_trb;
3600 struct scatterlist *sg = NULL;
3601 bool more_trbs_coming = true;
3602 bool need_zero_pkt = false;
3603 bool first_trb = true;
3604 unsigned int num_trbs;
3605 unsigned int start_cycle, num_sgs = 0;
3606 unsigned int enqd_len, block_len, trb_buff_len, full_len;
3607 int sent_len, ret;
3608 u32 field, length_field, remainder;
3609 u64 addr, send_addr;
3610
3611 ring = xhci_urb_to_transfer_ring(xhci, urb);
3612 if (!ring)
3613 return -EINVAL;
3614
3615 full_len = urb->transfer_buffer_length;
3616 /* If we have scatter/gather list, we use it. */
3617 if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) {
3618 num_sgs = urb->num_mapped_sgs;
3619 sg = urb->sg;
3620 addr = (u64) sg_dma_address(sg);
3621 block_len = sg_dma_len(sg);
3622 num_trbs = count_sg_trbs_needed(urb);
3623 } else {
3624 num_trbs = count_trbs_needed(urb);
3625 addr = (u64) urb->transfer_dma;
3626 block_len = full_len;
3627 }
3628 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3629 ep_index, urb->stream_id,
3630 num_trbs, urb, 0, mem_flags);
3631 if (unlikely(ret < 0))
3632 return ret;
3633
3634 urb_priv = urb->hcpriv;
3635
3636 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3637 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3638 need_zero_pkt = true;
3639
3640 td = &urb_priv->td[0];
3641
3642 /*
3643 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3644 * until we've finished creating all the other TRBs. The ring's cycle
3645 * state may change as we enqueue the other TRBs, so save it too.
3646 */
3647 start_trb = &ring->enqueue->generic;
3648 start_cycle = ring->cycle_state;
3649 send_addr = addr;
3650
3651 /* Queue the TRBs, even if they are zero-length */
3652 for (enqd_len = 0; first_trb || enqd_len < full_len;
3653 enqd_len += trb_buff_len) {
3654 field = TRB_TYPE(TRB_NORMAL);
3655
3656 /* TRB buffer should not cross 64KB boundaries */
3657 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3658 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3659
3660 if (enqd_len + trb_buff_len > full_len)
3661 trb_buff_len = full_len - enqd_len;
3662
3663 /* Don't change the cycle bit of the first TRB until later */
3664 if (first_trb) {
3665 first_trb = false;
3666 if (start_cycle == 0)
3667 field |= TRB_CYCLE;
3668 } else
3669 field |= ring->cycle_state;
3670
3671 /* Chain all the TRBs together; clear the chain bit in the last
3672 * TRB to indicate it's the last TRB in the chain.
3673 */
3674 if (enqd_len + trb_buff_len < full_len) {
3675 field |= TRB_CHAIN;
3676 if (trb_is_link(ring->enqueue + 1)) {
3677 if (xhci_align_td(xhci, urb, enqd_len,
3678 &trb_buff_len,
3679 ring->enq_seg)) {
3680 send_addr = ring->enq_seg->bounce_dma;
3681 /* assuming TD won't span 2 segs */
3682 td->bounce_seg = ring->enq_seg;
3683 }
3684 }
3685 }
3686 if (enqd_len + trb_buff_len >= full_len) {
3687 field &= ~TRB_CHAIN;
3688 field |= TRB_IOC;
3689 more_trbs_coming = false;
3690 td->last_trb = ring->enqueue;
3691 td->last_trb_seg = ring->enq_seg;
3692 if (xhci_urb_suitable_for_idt(urb)) {
3693 memcpy(&send_addr, urb->transfer_buffer,
3694 trb_buff_len);
3695 le64_to_cpus(&send_addr);
3696 field |= TRB_IDT;
3697 }
3698 }
3699
3700 /* Only set interrupt on short packet for IN endpoints */
3701 if (usb_urb_dir_in(urb))
3702 field |= TRB_ISP;
3703
3704 /* Set the TRB length, TD size, and interrupter fields. */
3705 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3706 full_len, urb, more_trbs_coming);
3707
3708 length_field = TRB_LEN(trb_buff_len) |
3709 TRB_TD_SIZE(remainder) |
3710 TRB_INTR_TARGET(0);
3711
3712 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3713 lower_32_bits(send_addr),
3714 upper_32_bits(send_addr),
3715 length_field,
3716 field);
3717 td->num_trbs++;
3718 addr += trb_buff_len;
3719 sent_len = trb_buff_len;
3720
3721 while (sg && sent_len >= block_len) {
3722 /* New sg entry */
3723 --num_sgs;
3724 sent_len -= block_len;
3725 sg = sg_next(sg);
3726 if (num_sgs != 0 && sg) {
3727 block_len = sg_dma_len(sg);
3728 addr = (u64) sg_dma_address(sg);
3729 addr += sent_len;
3730 }
3731 }
3732 block_len -= sent_len;
3733 send_addr = addr;
3734 }
3735
3736 if (need_zero_pkt) {
3737 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3738 ep_index, urb->stream_id,
3739 1, urb, 1, mem_flags);
3740 urb_priv->td[1].last_trb = ring->enqueue;
3741 urb_priv->td[1].last_trb_seg = ring->enq_seg;
3742 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3743 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3744 urb_priv->td[1].num_trbs++;
3745 }
3746
3747 check_trb_math(urb, enqd_len);
3748 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3749 start_cycle, start_trb);
3750 return 0;
3751}
3752
3753/* Caller must have locked xhci->lock */
3754int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3755 struct urb *urb, int slot_id, unsigned int ep_index)
3756{
3757 struct xhci_ring *ep_ring;
3758 int num_trbs;
3759 int ret;
3760 struct usb_ctrlrequest *setup;
3761 struct xhci_generic_trb *start_trb;
3762 int start_cycle;
3763 u32 field;
3764 struct urb_priv *urb_priv;
3765 struct xhci_td *td;
3766
3767 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3768 if (!ep_ring)
3769 return -EINVAL;
3770
3771 /*
3772 * Need to copy setup packet into setup TRB, so we can't use the setup
3773 * DMA address.
3774 */
3775 if (!urb->setup_packet)
3776 return -EINVAL;
3777
3778 /* 1 TRB for setup, 1 for status */
3779 num_trbs = 2;
3780 /*
3781 * Don't need to check if we need additional event data and normal TRBs,
3782 * since data in control transfers will never get bigger than 16MB
3783 * XXX: can we get a buffer that crosses 64KB boundaries?
3784 */
3785 if (urb->transfer_buffer_length > 0)
3786 num_trbs++;
3787 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3788 ep_index, urb->stream_id,
3789 num_trbs, urb, 0, mem_flags);
3790 if (ret < 0)
3791 return ret;
3792
3793 urb_priv = urb->hcpriv;
3794 td = &urb_priv->td[0];
3795 td->num_trbs = num_trbs;
3796
3797 /*
3798 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3799 * until we've finished creating all the other TRBs. The ring's cycle
3800 * state may change as we enqueue the other TRBs, so save it too.
3801 */
3802 start_trb = &ep_ring->enqueue->generic;
3803 start_cycle = ep_ring->cycle_state;
3804
3805 /* Queue setup TRB - see section 6.4.1.2.1 */
3806 /* FIXME better way to translate setup_packet into two u32 fields? */
3807 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3808 field = 0;
3809 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3810 if (start_cycle == 0)
3811 field |= 0x1;
3812
3813 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3814 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3815 if (urb->transfer_buffer_length > 0) {
3816 if (setup->bRequestType & USB_DIR_IN)
3817 field |= TRB_TX_TYPE(TRB_DATA_IN);
3818 else
3819 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3820 }
3821 }
3822
3823 queue_trb(xhci, ep_ring, true,
3824 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3825 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3826 TRB_LEN(8) | TRB_INTR_TARGET(0),
3827 /* Immediate data in pointer */
3828 field);
3829
3830 /* If there's data, queue data TRBs */
3831 /* Only set interrupt on short packet for IN endpoints */
3832 if (usb_urb_dir_in(urb))
3833 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3834 else
3835 field = TRB_TYPE(TRB_DATA);
3836
3837 if (urb->transfer_buffer_length > 0) {
3838 u32 length_field, remainder;
3839 u64 addr;
3840
3841 if (xhci_urb_suitable_for_idt(urb)) {
3842 memcpy(&addr, urb->transfer_buffer,
3843 urb->transfer_buffer_length);
3844 le64_to_cpus(&addr);
3845 field |= TRB_IDT;
3846 } else {
3847 addr = (u64) urb->transfer_dma;
3848 }
3849
3850 remainder = xhci_td_remainder(xhci, 0,
3851 urb->transfer_buffer_length,
3852 urb->transfer_buffer_length,
3853 urb, 1);
3854 length_field = TRB_LEN(urb->transfer_buffer_length) |
3855 TRB_TD_SIZE(remainder) |
3856 TRB_INTR_TARGET(0);
3857 if (setup->bRequestType & USB_DIR_IN)
3858 field |= TRB_DIR_IN;
3859 queue_trb(xhci, ep_ring, true,
3860 lower_32_bits(addr),
3861 upper_32_bits(addr),
3862 length_field,
3863 field | ep_ring->cycle_state);
3864 }
3865
3866 /* Save the DMA address of the last TRB in the TD */
3867 td->last_trb = ep_ring->enqueue;
3868 td->last_trb_seg = ep_ring->enq_seg;
3869
3870 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3871 /* If the device sent data, the status stage is an OUT transfer */
3872 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3873 field = 0;
3874 else
3875 field = TRB_DIR_IN;
3876 queue_trb(xhci, ep_ring, false,
3877 0,
3878 0,
3879 TRB_INTR_TARGET(0),
3880 /* Event on completion */
3881 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3882
3883 giveback_first_trb(xhci, slot_id, ep_index, 0,
3884 start_cycle, start_trb);
3885 return 0;
3886}
3887
3888/*
3889 * The transfer burst count field of the isochronous TRB defines the number of
3890 * bursts that are required to move all packets in this TD. Only SuperSpeed
3891 * devices can burst up to bMaxBurst number of packets per service interval.
3892 * This field is zero based, meaning a value of zero in the field means one
3893 * burst. Basically, for everything but SuperSpeed devices, this field will be
3894 * zero. Only xHCI 1.0 host controllers support this field.
3895 */
3896static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3897 struct urb *urb, unsigned int total_packet_count)
3898{
3899 unsigned int max_burst;
3900
3901 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3902 return 0;
3903
3904 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3905 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3906}
3907
3908/*
3909 * Returns the number of packets in the last "burst" of packets. This field is
3910 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3911 * the last burst packet count is equal to the total number of packets in the
3912 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3913 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3914 * contain 1 to (bMaxBurst + 1) packets.
3915 */
3916static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3917 struct urb *urb, unsigned int total_packet_count)
3918{
3919 unsigned int max_burst;
3920 unsigned int residue;
3921
3922 if (xhci->hci_version < 0x100)
3923 return 0;
3924
3925 if (urb->dev->speed >= USB_SPEED_SUPER) {
3926 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3927 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3928 residue = total_packet_count % (max_burst + 1);
3929 /* If residue is zero, the last burst contains (max_burst + 1)
3930 * number of packets, but the TLBPC field is zero-based.
3931 */
3932 if (residue == 0)
3933 return max_burst;
3934 return residue - 1;
3935 }
3936 if (total_packet_count == 0)
3937 return 0;
3938 return total_packet_count - 1;
3939}
3940
3941/*
3942 * Calculates Frame ID field of the isochronous TRB identifies the
3943 * target frame that the Interval associated with this Isochronous
3944 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3945 *
3946 * Returns actual frame id on success, negative value on error.
3947 */
3948static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3949 struct urb *urb, int index)
3950{
3951 int start_frame, ist, ret = 0;
3952 int start_frame_id, end_frame_id, current_frame_id;
3953
3954 if (urb->dev->speed == USB_SPEED_LOW ||
3955 urb->dev->speed == USB_SPEED_FULL)
3956 start_frame = urb->start_frame + index * urb->interval;
3957 else
3958 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3959
3960 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3961 *
3962 * If bit [3] of IST is cleared to '0', software can add a TRB no
3963 * later than IST[2:0] Microframes before that TRB is scheduled to
3964 * be executed.
3965 * If bit [3] of IST is set to '1', software can add a TRB no later
3966 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3967 */
3968 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3969 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3970 ist <<= 3;
3971
3972 /* Software shall not schedule an Isoch TD with a Frame ID value that
3973 * is less than the Start Frame ID or greater than the End Frame ID,
3974 * where:
3975 *
3976 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3977 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3978 *
3979 * Both the End Frame ID and Start Frame ID values are calculated
3980 * in microframes. When software determines the valid Frame ID value;
3981 * The End Frame ID value should be rounded down to the nearest Frame
3982 * boundary, and the Start Frame ID value should be rounded up to the
3983 * nearest Frame boundary.
3984 */
3985 current_frame_id = readl(&xhci->run_regs->microframe_index);
3986 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3987 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3988
3989 start_frame &= 0x7ff;
3990 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3991 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3992
3993 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3994 __func__, index, readl(&xhci->run_regs->microframe_index),
3995 start_frame_id, end_frame_id, start_frame);
3996
3997 if (start_frame_id < end_frame_id) {
3998 if (start_frame > end_frame_id ||
3999 start_frame < start_frame_id)
4000 ret = -EINVAL;
4001 } else if (start_frame_id > end_frame_id) {
4002 if ((start_frame > end_frame_id &&
4003 start_frame < start_frame_id))
4004 ret = -EINVAL;
4005 } else {
4006 ret = -EINVAL;
4007 }
4008
4009 if (index == 0) {
4010 if (ret == -EINVAL || start_frame == start_frame_id) {
4011 start_frame = start_frame_id + 1;
4012 if (urb->dev->speed == USB_SPEED_LOW ||
4013 urb->dev->speed == USB_SPEED_FULL)
4014 urb->start_frame = start_frame;
4015 else
4016 urb->start_frame = start_frame << 3;
4017 ret = 0;
4018 }
4019 }
4020
4021 if (ret) {
4022 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
4023 start_frame, current_frame_id, index,
4024 start_frame_id, end_frame_id);
4025 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
4026 return ret;
4027 }
4028
4029 return start_frame;
4030}
4031
4032/* Check if we should generate event interrupt for a TD in an isoc URB */
4033static bool trb_block_event_intr(struct xhci_hcd *xhci, int num_tds, int i,
4034 struct xhci_interrupter *ir)
4035{
4036 if (xhci->hci_version < 0x100)
4037 return false;
4038 /* always generate an event interrupt for the last TD */
4039 if (i == num_tds - 1)
4040 return false;
4041 /*
4042 * If AVOID_BEI is set the host handles full event rings poorly,
4043 * generate an event at least every 8th TD to clear the event ring
4044 */
4045 if (i && ir->isoc_bei_interval && xhci->quirks & XHCI_AVOID_BEI)
4046 return !!(i % ir->isoc_bei_interval);
4047
4048 return true;
4049}
4050
4051/* This is for isoc transfer */
4052static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
4053 struct urb *urb, int slot_id, unsigned int ep_index)
4054{
4055 struct xhci_interrupter *ir;
4056 struct xhci_ring *ep_ring;
4057 struct urb_priv *urb_priv;
4058 struct xhci_td *td;
4059 int num_tds, trbs_per_td;
4060 struct xhci_generic_trb *start_trb;
4061 bool first_trb;
4062 int start_cycle;
4063 u32 field, length_field;
4064 int running_total, trb_buff_len, td_len, td_remain_len, ret;
4065 u64 start_addr, addr;
4066 int i, j;
4067 bool more_trbs_coming;
4068 struct xhci_virt_ep *xep;
4069 int frame_id;
4070
4071 xep = &xhci->devs[slot_id]->eps[ep_index];
4072 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
4073 ir = xhci->interrupters[0];
4074
4075 num_tds = urb->number_of_packets;
4076 if (num_tds < 1) {
4077 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
4078 return -EINVAL;
4079 }
4080 start_addr = (u64) urb->transfer_dma;
4081 start_trb = &ep_ring->enqueue->generic;
4082 start_cycle = ep_ring->cycle_state;
4083
4084 urb_priv = urb->hcpriv;
4085 /* Queue the TRBs for each TD, even if they are zero-length */
4086 for (i = 0; i < num_tds; i++) {
4087 unsigned int total_pkt_count, max_pkt;
4088 unsigned int burst_count, last_burst_pkt_count;
4089 u32 sia_frame_id;
4090
4091 first_trb = true;
4092 running_total = 0;
4093 addr = start_addr + urb->iso_frame_desc[i].offset;
4094 td_len = urb->iso_frame_desc[i].length;
4095 td_remain_len = td_len;
4096 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
4097 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
4098
4099 /* A zero-length transfer still involves at least one packet. */
4100 if (total_pkt_count == 0)
4101 total_pkt_count++;
4102 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
4103 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
4104 urb, total_pkt_count);
4105
4106 trbs_per_td = count_isoc_trbs_needed(urb, i);
4107
4108 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
4109 urb->stream_id, trbs_per_td, urb, i, mem_flags);
4110 if (ret < 0) {
4111 if (i == 0)
4112 return ret;
4113 goto cleanup;
4114 }
4115 td = &urb_priv->td[i];
4116 td->num_trbs = trbs_per_td;
4117 /* use SIA as default, if frame id is used overwrite it */
4118 sia_frame_id = TRB_SIA;
4119 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
4120 HCC_CFC(xhci->hcc_params)) {
4121 frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
4122 if (frame_id >= 0)
4123 sia_frame_id = TRB_FRAME_ID(frame_id);
4124 }
4125 /*
4126 * Set isoc specific data for the first TRB in a TD.
4127 * Prevent HW from getting the TRBs by keeping the cycle state
4128 * inverted in the first TDs isoc TRB.
4129 */
4130 field = TRB_TYPE(TRB_ISOC) |
4131 TRB_TLBPC(last_burst_pkt_count) |
4132 sia_frame_id |
4133 (i ? ep_ring->cycle_state : !start_cycle);
4134
4135 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
4136 if (!xep->use_extended_tbc)
4137 field |= TRB_TBC(burst_count);
4138
4139 /* fill the rest of the TRB fields, and remaining normal TRBs */
4140 for (j = 0; j < trbs_per_td; j++) {
4141 u32 remainder = 0;
4142
4143 /* only first TRB is isoc, overwrite otherwise */
4144 if (!first_trb)
4145 field = TRB_TYPE(TRB_NORMAL) |
4146 ep_ring->cycle_state;
4147
4148 /* Only set interrupt on short packet for IN EPs */
4149 if (usb_urb_dir_in(urb))
4150 field |= TRB_ISP;
4151
4152 /* Set the chain bit for all except the last TRB */
4153 if (j < trbs_per_td - 1) {
4154 more_trbs_coming = true;
4155 field |= TRB_CHAIN;
4156 } else {
4157 more_trbs_coming = false;
4158 td->last_trb = ep_ring->enqueue;
4159 td->last_trb_seg = ep_ring->enq_seg;
4160 field |= TRB_IOC;
4161 if (trb_block_event_intr(xhci, num_tds, i, ir))
4162 field |= TRB_BEI;
4163 }
4164 /* Calculate TRB length */
4165 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
4166 if (trb_buff_len > td_remain_len)
4167 trb_buff_len = td_remain_len;
4168
4169 /* Set the TRB length, TD size, & interrupter fields. */
4170 remainder = xhci_td_remainder(xhci, running_total,
4171 trb_buff_len, td_len,
4172 urb, more_trbs_coming);
4173
4174 length_field = TRB_LEN(trb_buff_len) |
4175 TRB_INTR_TARGET(0);
4176
4177 /* xhci 1.1 with ETE uses TD Size field for TBC */
4178 if (first_trb && xep->use_extended_tbc)
4179 length_field |= TRB_TD_SIZE_TBC(burst_count);
4180 else
4181 length_field |= TRB_TD_SIZE(remainder);
4182 first_trb = false;
4183
4184 queue_trb(xhci, ep_ring, more_trbs_coming,
4185 lower_32_bits(addr),
4186 upper_32_bits(addr),
4187 length_field,
4188 field);
4189 running_total += trb_buff_len;
4190
4191 addr += trb_buff_len;
4192 td_remain_len -= trb_buff_len;
4193 }
4194
4195 /* Check TD length */
4196 if (running_total != td_len) {
4197 xhci_err(xhci, "ISOC TD length unmatch\n");
4198 ret = -EINVAL;
4199 goto cleanup;
4200 }
4201 }
4202
4203 /* store the next frame id */
4204 if (HCC_CFC(xhci->hcc_params))
4205 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
4206
4207 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
4208 if (xhci->quirks & XHCI_AMD_PLL_FIX)
4209 usb_amd_quirk_pll_disable();
4210 }
4211 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
4212
4213 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
4214 start_cycle, start_trb);
4215 return 0;
4216cleanup:
4217 /* Clean up a partially enqueued isoc transfer. */
4218
4219 for (i--; i >= 0; i--)
4220 list_del_init(&urb_priv->td[i].td_list);
4221
4222 /* Use the first TD as a temporary variable to turn the TDs we've queued
4223 * into No-ops with a software-owned cycle bit. That way the hardware
4224 * won't accidentally start executing bogus TDs when we partially
4225 * overwrite them. td->first_trb and td->start_seg are already set.
4226 */
4227 urb_priv->td[0].last_trb = ep_ring->enqueue;
4228 /* Every TRB except the first & last will have its cycle bit flipped. */
4229 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
4230
4231 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
4232 ep_ring->enqueue = urb_priv->td[0].first_trb;
4233 ep_ring->enq_seg = urb_priv->td[0].start_seg;
4234 ep_ring->cycle_state = start_cycle;
4235 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
4236 return ret;
4237}
4238
4239/*
4240 * Check transfer ring to guarantee there is enough room for the urb.
4241 * Update ISO URB start_frame and interval.
4242 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
4243 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
4244 * Contiguous Frame ID is not supported by HC.
4245 */
4246int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
4247 struct urb *urb, int slot_id, unsigned int ep_index)
4248{
4249 struct xhci_virt_device *xdev;
4250 struct xhci_ring *ep_ring;
4251 struct xhci_ep_ctx *ep_ctx;
4252 int start_frame;
4253 int num_tds, num_trbs, i;
4254 int ret;
4255 struct xhci_virt_ep *xep;
4256 int ist;
4257
4258 xdev = xhci->devs[slot_id];
4259 xep = &xhci->devs[slot_id]->eps[ep_index];
4260 ep_ring = xdev->eps[ep_index].ring;
4261 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
4262
4263 num_trbs = 0;
4264 num_tds = urb->number_of_packets;
4265 for (i = 0; i < num_tds; i++)
4266 num_trbs += count_isoc_trbs_needed(urb, i);
4267
4268 /* Check the ring to guarantee there is enough room for the whole urb.
4269 * Do not insert any td of the urb to the ring if the check failed.
4270 */
4271 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
4272 num_trbs, mem_flags);
4273 if (ret)
4274 return ret;
4275
4276 /*
4277 * Check interval value. This should be done before we start to
4278 * calculate the start frame value.
4279 */
4280 check_interval(xhci, urb, ep_ctx);
4281
4282 /* Calculate the start frame and put it in urb->start_frame. */
4283 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
4284 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
4285 urb->start_frame = xep->next_frame_id;
4286 goto skip_start_over;
4287 }
4288 }
4289
4290 start_frame = readl(&xhci->run_regs->microframe_index);
4291 start_frame &= 0x3fff;
4292 /*
4293 * Round up to the next frame and consider the time before trb really
4294 * gets scheduled by hardare.
4295 */
4296 ist = HCS_IST(xhci->hcs_params2) & 0x7;
4297 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
4298 ist <<= 3;
4299 start_frame += ist + XHCI_CFC_DELAY;
4300 start_frame = roundup(start_frame, 8);
4301
4302 /*
4303 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
4304 * is greate than 8 microframes.
4305 */
4306 if (urb->dev->speed == USB_SPEED_LOW ||
4307 urb->dev->speed == USB_SPEED_FULL) {
4308 start_frame = roundup(start_frame, urb->interval << 3);
4309 urb->start_frame = start_frame >> 3;
4310 } else {
4311 start_frame = roundup(start_frame, urb->interval);
4312 urb->start_frame = start_frame;
4313 }
4314
4315skip_start_over:
4316
4317 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
4318}
4319
4320/**** Command Ring Operations ****/
4321
4322/* Generic function for queueing a command TRB on the command ring.
4323 * Check to make sure there's room on the command ring for one command TRB.
4324 * Also check that there's room reserved for commands that must not fail.
4325 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4326 * then only check for the number of reserved spots.
4327 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4328 * because the command event handler may want to resubmit a failed command.
4329 */
4330static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4331 u32 field1, u32 field2,
4332 u32 field3, u32 field4, bool command_must_succeed)
4333{
4334 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4335 int ret;
4336
4337 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
4338 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4339 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
4340 return -ESHUTDOWN;
4341 }
4342
4343 if (!command_must_succeed)
4344 reserved_trbs++;
4345
4346 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4347 reserved_trbs, GFP_ATOMIC);
4348 if (ret < 0) {
4349 xhci_err(xhci, "ERR: No room for command on command ring\n");
4350 if (command_must_succeed)
4351 xhci_err(xhci, "ERR: Reserved TRB counting for "
4352 "unfailable commands failed.\n");
4353 return ret;
4354 }
4355
4356 cmd->command_trb = xhci->cmd_ring->enqueue;
4357
4358 /* if there are no other commands queued we start the timeout timer */
4359 if (list_empty(&xhci->cmd_list)) {
4360 xhci->current_cmd = cmd;
4361 xhci_mod_cmd_timer(xhci);
4362 }
4363
4364 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
4365
4366 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4367 field4 | xhci->cmd_ring->cycle_state);
4368 return 0;
4369}
4370
4371/* Queue a slot enable or disable request on the command ring */
4372int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
4373 u32 trb_type, u32 slot_id)
4374{
4375 return queue_command(xhci, cmd, 0, 0, 0,
4376 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4377}
4378
4379/* Queue an address device command TRB */
4380int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4381 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4382{
4383 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4384 upper_32_bits(in_ctx_ptr), 0,
4385 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4386 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4387}
4388
4389int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4390 u32 field1, u32 field2, u32 field3, u32 field4)
4391{
4392 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4393}
4394
4395/* Queue a reset device command TRB */
4396int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4397 u32 slot_id)
4398{
4399 return queue_command(xhci, cmd, 0, 0, 0,
4400 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4401 false);
4402}
4403
4404/* Queue a configure endpoint command TRB */
4405int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4406 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4407 u32 slot_id, bool command_must_succeed)
4408{
4409 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4410 upper_32_bits(in_ctx_ptr), 0,
4411 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4412 command_must_succeed);
4413}
4414
4415/* Queue an evaluate context command TRB */
4416int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4417 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4418{
4419 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4420 upper_32_bits(in_ctx_ptr), 0,
4421 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4422 command_must_succeed);
4423}
4424
4425/*
4426 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4427 * activity on an endpoint that is about to be suspended.
4428 */
4429int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4430 int slot_id, unsigned int ep_index, int suspend)
4431{
4432 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4433 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4434 u32 type = TRB_TYPE(TRB_STOP_RING);
4435 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4436
4437 return queue_command(xhci, cmd, 0, 0, 0,
4438 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4439}
4440
4441int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4442 int slot_id, unsigned int ep_index,
4443 enum xhci_ep_reset_type reset_type)
4444{
4445 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4446 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4447 u32 type = TRB_TYPE(TRB_RESET_EP);
4448
4449 if (reset_type == EP_SOFT_RESET)
4450 type |= TRB_TSP;
4451
4452 return queue_command(xhci, cmd, 0, 0, 0,
4453 trb_slot_id | trb_ep_index | type, false);
4454}