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1/*
2 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
3 *
4 * Copyright (C) 2005 James Chapman (ds1337 core)
5 * Copyright (C) 2006 David Brownell
6 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/slab.h>
16#include <linux/i2c.h>
17#include <linux/string.h>
18#include <linux/rtc.h>
19#include <linux/bcd.h>
20
21
22
23/* We can't determine type by probing, but if we expect pre-Linux code
24 * to have set the chip up as a clock (turning on the oscillator and
25 * setting the date and time), Linux can ignore the non-clock features.
26 * That's a natural job for a factory or repair bench.
27 */
28enum ds_type {
29 ds_1307,
30 ds_1337,
31 ds_1338,
32 ds_1339,
33 ds_1340,
34 ds_1388,
35 ds_3231,
36 m41t00,
37 rx_8025,
38 // rs5c372 too? different address...
39};
40
41
42/* RTC registers don't differ much, except for the century flag */
43#define DS1307_REG_SECS 0x00 /* 00-59 */
44# define DS1307_BIT_CH 0x80
45# define DS1340_BIT_nEOSC 0x80
46#define DS1307_REG_MIN 0x01 /* 00-59 */
47#define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
48# define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
49# define DS1307_BIT_PM 0x20 /* in REG_HOUR */
50# define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
51# define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
52#define DS1307_REG_WDAY 0x03 /* 01-07 */
53#define DS1307_REG_MDAY 0x04 /* 01-31 */
54#define DS1307_REG_MONTH 0x05 /* 01-12 */
55# define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
56#define DS1307_REG_YEAR 0x06 /* 00-99 */
57
58/* Other registers (control, status, alarms, trickle charge, NVRAM, etc)
59 * start at 7, and they differ a LOT. Only control and status matter for
60 * basic RTC date and time functionality; be careful using them.
61 */
62#define DS1307_REG_CONTROL 0x07 /* or ds1338 */
63# define DS1307_BIT_OUT 0x80
64# define DS1338_BIT_OSF 0x20
65# define DS1307_BIT_SQWE 0x10
66# define DS1307_BIT_RS1 0x02
67# define DS1307_BIT_RS0 0x01
68#define DS1337_REG_CONTROL 0x0e
69# define DS1337_BIT_nEOSC 0x80
70# define DS1339_BIT_BBSQI 0x20
71# define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
72# define DS1337_BIT_RS2 0x10
73# define DS1337_BIT_RS1 0x08
74# define DS1337_BIT_INTCN 0x04
75# define DS1337_BIT_A2IE 0x02
76# define DS1337_BIT_A1IE 0x01
77#define DS1340_REG_CONTROL 0x07
78# define DS1340_BIT_OUT 0x80
79# define DS1340_BIT_FT 0x40
80# define DS1340_BIT_CALIB_SIGN 0x20
81# define DS1340_M_CALIBRATION 0x1f
82#define DS1340_REG_FLAG 0x09
83# define DS1340_BIT_OSF 0x80
84#define DS1337_REG_STATUS 0x0f
85# define DS1337_BIT_OSF 0x80
86# define DS1337_BIT_A2I 0x02
87# define DS1337_BIT_A1I 0x01
88#define DS1339_REG_ALARM1_SECS 0x07
89#define DS1339_REG_TRICKLE 0x10
90
91#define RX8025_REG_CTRL1 0x0e
92# define RX8025_BIT_2412 0x20
93#define RX8025_REG_CTRL2 0x0f
94# define RX8025_BIT_PON 0x10
95# define RX8025_BIT_VDET 0x40
96# define RX8025_BIT_XST 0x20
97
98
99struct ds1307 {
100 u8 offset; /* register's offset */
101 u8 regs[11];
102 enum ds_type type;
103 unsigned long flags;
104#define HAS_NVRAM 0 /* bit 0 == sysfs file active */
105#define HAS_ALARM 1 /* bit 1 == irq claimed */
106 struct i2c_client *client;
107 struct rtc_device *rtc;
108 struct work_struct work;
109 s32 (*read_block_data)(const struct i2c_client *client, u8 command,
110 u8 length, u8 *values);
111 s32 (*write_block_data)(const struct i2c_client *client, u8 command,
112 u8 length, const u8 *values);
113};
114
115struct chip_desc {
116 unsigned nvram56:1;
117 unsigned alarm:1;
118};
119
120static const struct chip_desc chips[] = {
121[ds_1307] = {
122 .nvram56 = 1,
123},
124[ds_1337] = {
125 .alarm = 1,
126},
127[ds_1338] = {
128 .nvram56 = 1,
129},
130[ds_1339] = {
131 .alarm = 1,
132},
133[ds_1340] = {
134},
135[ds_3231] = {
136 .alarm = 1,
137},
138[m41t00] = {
139},
140[rx_8025] = {
141}, };
142
143static const struct i2c_device_id ds1307_id[] = {
144 { "ds1307", ds_1307 },
145 { "ds1337", ds_1337 },
146 { "ds1338", ds_1338 },
147 { "ds1339", ds_1339 },
148 { "ds1388", ds_1388 },
149 { "ds1340", ds_1340 },
150 { "ds3231", ds_3231 },
151 { "m41t00", m41t00 },
152 { "pt7c4338", ds_1307 },
153 { "rx8025", rx_8025 },
154 { }
155};
156MODULE_DEVICE_TABLE(i2c, ds1307_id);
157
158/*----------------------------------------------------------------------*/
159
160#define BLOCK_DATA_MAX_TRIES 10
161
162static s32 ds1307_read_block_data_once(const struct i2c_client *client,
163 u8 command, u8 length, u8 *values)
164{
165 s32 i, data;
166
167 for (i = 0; i < length; i++) {
168 data = i2c_smbus_read_byte_data(client, command + i);
169 if (data < 0)
170 return data;
171 values[i] = data;
172 }
173 return i;
174}
175
176static s32 ds1307_read_block_data(const struct i2c_client *client, u8 command,
177 u8 length, u8 *values)
178{
179 u8 oldvalues[I2C_SMBUS_BLOCK_MAX];
180 s32 ret;
181 int tries = 0;
182
183 dev_dbg(&client->dev, "ds1307_read_block_data (length=%d)\n", length);
184 ret = ds1307_read_block_data_once(client, command, length, values);
185 if (ret < 0)
186 return ret;
187 do {
188 if (++tries > BLOCK_DATA_MAX_TRIES) {
189 dev_err(&client->dev,
190 "ds1307_read_block_data failed\n");
191 return -EIO;
192 }
193 memcpy(oldvalues, values, length);
194 ret = ds1307_read_block_data_once(client, command, length,
195 values);
196 if (ret < 0)
197 return ret;
198 } while (memcmp(oldvalues, values, length));
199 return length;
200}
201
202static s32 ds1307_write_block_data(const struct i2c_client *client, u8 command,
203 u8 length, const u8 *values)
204{
205 u8 currvalues[I2C_SMBUS_BLOCK_MAX];
206 int tries = 0;
207
208 dev_dbg(&client->dev, "ds1307_write_block_data (length=%d)\n", length);
209 do {
210 s32 i, ret;
211
212 if (++tries > BLOCK_DATA_MAX_TRIES) {
213 dev_err(&client->dev,
214 "ds1307_write_block_data failed\n");
215 return -EIO;
216 }
217 for (i = 0; i < length; i++) {
218 ret = i2c_smbus_write_byte_data(client, command + i,
219 values[i]);
220 if (ret < 0)
221 return ret;
222 }
223 ret = ds1307_read_block_data_once(client, command, length,
224 currvalues);
225 if (ret < 0)
226 return ret;
227 } while (memcmp(currvalues, values, length));
228 return length;
229}
230
231/*----------------------------------------------------------------------*/
232
233/*
234 * The IRQ logic includes a "real" handler running in IRQ context just
235 * long enough to schedule this workqueue entry. We need a task context
236 * to talk to the RTC, since I2C I/O calls require that; and disable the
237 * IRQ until we clear its status on the chip, so that this handler can
238 * work with any type of triggering (not just falling edge).
239 *
240 * The ds1337 and ds1339 both have two alarms, but we only use the first
241 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
242 * signal; ds1339 chips have only one alarm signal.
243 */
244static void ds1307_work(struct work_struct *work)
245{
246 struct ds1307 *ds1307;
247 struct i2c_client *client;
248 struct mutex *lock;
249 int stat, control;
250
251 ds1307 = container_of(work, struct ds1307, work);
252 client = ds1307->client;
253 lock = &ds1307->rtc->ops_lock;
254
255 mutex_lock(lock);
256 stat = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS);
257 if (stat < 0)
258 goto out;
259
260 if (stat & DS1337_BIT_A1I) {
261 stat &= ~DS1337_BIT_A1I;
262 i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, stat);
263
264 control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
265 if (control < 0)
266 goto out;
267
268 control &= ~DS1337_BIT_A1IE;
269 i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control);
270
271 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
272 }
273
274out:
275 if (test_bit(HAS_ALARM, &ds1307->flags))
276 enable_irq(client->irq);
277 mutex_unlock(lock);
278}
279
280static irqreturn_t ds1307_irq(int irq, void *dev_id)
281{
282 struct i2c_client *client = dev_id;
283 struct ds1307 *ds1307 = i2c_get_clientdata(client);
284
285 disable_irq_nosync(irq);
286 schedule_work(&ds1307->work);
287 return IRQ_HANDLED;
288}
289
290/*----------------------------------------------------------------------*/
291
292static int ds1307_get_time(struct device *dev, struct rtc_time *t)
293{
294 struct ds1307 *ds1307 = dev_get_drvdata(dev);
295 int tmp;
296
297 /* read the RTC date and time registers all at once */
298 tmp = ds1307->read_block_data(ds1307->client,
299 ds1307->offset, 7, ds1307->regs);
300 if (tmp != 7) {
301 dev_err(dev, "%s error %d\n", "read", tmp);
302 return -EIO;
303 }
304
305 dev_dbg(dev, "%s: %02x %02x %02x %02x %02x %02x %02x\n",
306 "read",
307 ds1307->regs[0], ds1307->regs[1],
308 ds1307->regs[2], ds1307->regs[3],
309 ds1307->regs[4], ds1307->regs[5],
310 ds1307->regs[6]);
311
312 t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f);
313 t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f);
314 tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f;
315 t->tm_hour = bcd2bin(tmp);
316 t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1;
317 t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f);
318 tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f;
319 t->tm_mon = bcd2bin(tmp) - 1;
320
321 /* assume 20YY not 19YY, and ignore DS1337_BIT_CENTURY */
322 t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100;
323
324 dev_dbg(dev, "%s secs=%d, mins=%d, "
325 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
326 "read", t->tm_sec, t->tm_min,
327 t->tm_hour, t->tm_mday,
328 t->tm_mon, t->tm_year, t->tm_wday);
329
330 /* initial clock setting can be undefined */
331 return rtc_valid_tm(t);
332}
333
334static int ds1307_set_time(struct device *dev, struct rtc_time *t)
335{
336 struct ds1307 *ds1307 = dev_get_drvdata(dev);
337 int result;
338 int tmp;
339 u8 *buf = ds1307->regs;
340
341 dev_dbg(dev, "%s secs=%d, mins=%d, "
342 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
343 "write", t->tm_sec, t->tm_min,
344 t->tm_hour, t->tm_mday,
345 t->tm_mon, t->tm_year, t->tm_wday);
346
347 buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
348 buf[DS1307_REG_MIN] = bin2bcd(t->tm_min);
349 buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
350 buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
351 buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
352 buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
353
354 /* assume 20YY not 19YY */
355 tmp = t->tm_year - 100;
356 buf[DS1307_REG_YEAR] = bin2bcd(tmp);
357
358 switch (ds1307->type) {
359 case ds_1337:
360 case ds_1339:
361 case ds_3231:
362 buf[DS1307_REG_MONTH] |= DS1337_BIT_CENTURY;
363 break;
364 case ds_1340:
365 buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY_EN
366 | DS1340_BIT_CENTURY;
367 break;
368 default:
369 break;
370 }
371
372 dev_dbg(dev, "%s: %02x %02x %02x %02x %02x %02x %02x\n",
373 "write", buf[0], buf[1], buf[2], buf[3],
374 buf[4], buf[5], buf[6]);
375
376 result = ds1307->write_block_data(ds1307->client,
377 ds1307->offset, 7, buf);
378 if (result < 0) {
379 dev_err(dev, "%s error %d\n", "write", result);
380 return result;
381 }
382 return 0;
383}
384
385static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
386{
387 struct i2c_client *client = to_i2c_client(dev);
388 struct ds1307 *ds1307 = i2c_get_clientdata(client);
389 int ret;
390
391 if (!test_bit(HAS_ALARM, &ds1307->flags))
392 return -EINVAL;
393
394 /* read all ALARM1, ALARM2, and status registers at once */
395 ret = ds1307->read_block_data(client,
396 DS1339_REG_ALARM1_SECS, 9, ds1307->regs);
397 if (ret != 9) {
398 dev_err(dev, "%s error %d\n", "alarm read", ret);
399 return -EIO;
400 }
401
402 dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
403 "alarm read",
404 ds1307->regs[0], ds1307->regs[1],
405 ds1307->regs[2], ds1307->regs[3],
406 ds1307->regs[4], ds1307->regs[5],
407 ds1307->regs[6], ds1307->regs[7],
408 ds1307->regs[8]);
409
410 /* report alarm time (ALARM1); assume 24 hour and day-of-month modes,
411 * and that all four fields are checked matches
412 */
413 t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f);
414 t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f);
415 t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f);
416 t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f);
417 t->time.tm_mon = -1;
418 t->time.tm_year = -1;
419 t->time.tm_wday = -1;
420 t->time.tm_yday = -1;
421 t->time.tm_isdst = -1;
422
423 /* ... and status */
424 t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE);
425 t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I);
426
427 dev_dbg(dev, "%s secs=%d, mins=%d, "
428 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
429 "alarm read", t->time.tm_sec, t->time.tm_min,
430 t->time.tm_hour, t->time.tm_mday,
431 t->enabled, t->pending);
432
433 return 0;
434}
435
436static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
437{
438 struct i2c_client *client = to_i2c_client(dev);
439 struct ds1307 *ds1307 = i2c_get_clientdata(client);
440 unsigned char *buf = ds1307->regs;
441 u8 control, status;
442 int ret;
443
444 if (!test_bit(HAS_ALARM, &ds1307->flags))
445 return -EINVAL;
446
447 dev_dbg(dev, "%s secs=%d, mins=%d, "
448 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
449 "alarm set", t->time.tm_sec, t->time.tm_min,
450 t->time.tm_hour, t->time.tm_mday,
451 t->enabled, t->pending);
452
453 /* read current status of both alarms and the chip */
454 ret = ds1307->read_block_data(client,
455 DS1339_REG_ALARM1_SECS, 9, buf);
456 if (ret != 9) {
457 dev_err(dev, "%s error %d\n", "alarm write", ret);
458 return -EIO;
459 }
460 control = ds1307->regs[7];
461 status = ds1307->regs[8];
462
463 dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
464 "alarm set (old status)",
465 ds1307->regs[0], ds1307->regs[1],
466 ds1307->regs[2], ds1307->regs[3],
467 ds1307->regs[4], ds1307->regs[5],
468 ds1307->regs[6], control, status);
469
470 /* set ALARM1, using 24 hour and day-of-month modes */
471 buf[0] = bin2bcd(t->time.tm_sec);
472 buf[1] = bin2bcd(t->time.tm_min);
473 buf[2] = bin2bcd(t->time.tm_hour);
474 buf[3] = bin2bcd(t->time.tm_mday);
475
476 /* set ALARM2 to non-garbage */
477 buf[4] = 0;
478 buf[5] = 0;
479 buf[6] = 0;
480
481 /* optionally enable ALARM1 */
482 buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
483 if (t->enabled) {
484 dev_dbg(dev, "alarm IRQ armed\n");
485 buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
486 }
487 buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
488
489 ret = ds1307->write_block_data(client,
490 DS1339_REG_ALARM1_SECS, 9, buf);
491 if (ret < 0) {
492 dev_err(dev, "can't set alarm time\n");
493 return ret;
494 }
495
496 return 0;
497}
498
499static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
500{
501 struct i2c_client *client = to_i2c_client(dev);
502 struct ds1307 *ds1307 = i2c_get_clientdata(client);
503 int ret;
504
505 if (!test_bit(HAS_ALARM, &ds1307->flags))
506 return -ENOTTY;
507
508 ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
509 if (ret < 0)
510 return ret;
511
512 if (enabled)
513 ret |= DS1337_BIT_A1IE;
514 else
515 ret &= ~DS1337_BIT_A1IE;
516
517 ret = i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, ret);
518 if (ret < 0)
519 return ret;
520
521 return 0;
522}
523
524static const struct rtc_class_ops ds13xx_rtc_ops = {
525 .read_time = ds1307_get_time,
526 .set_time = ds1307_set_time,
527 .read_alarm = ds1337_read_alarm,
528 .set_alarm = ds1337_set_alarm,
529 .alarm_irq_enable = ds1307_alarm_irq_enable,
530};
531
532/*----------------------------------------------------------------------*/
533
534#define NVRAM_SIZE 56
535
536static ssize_t
537ds1307_nvram_read(struct file *filp, struct kobject *kobj,
538 struct bin_attribute *attr,
539 char *buf, loff_t off, size_t count)
540{
541 struct i2c_client *client;
542 struct ds1307 *ds1307;
543 int result;
544
545 client = kobj_to_i2c_client(kobj);
546 ds1307 = i2c_get_clientdata(client);
547
548 if (unlikely(off >= NVRAM_SIZE))
549 return 0;
550 if ((off + count) > NVRAM_SIZE)
551 count = NVRAM_SIZE - off;
552 if (unlikely(!count))
553 return count;
554
555 result = ds1307->read_block_data(client, 8 + off, count, buf);
556 if (result < 0)
557 dev_err(&client->dev, "%s error %d\n", "nvram read", result);
558 return result;
559}
560
561static ssize_t
562ds1307_nvram_write(struct file *filp, struct kobject *kobj,
563 struct bin_attribute *attr,
564 char *buf, loff_t off, size_t count)
565{
566 struct i2c_client *client;
567 struct ds1307 *ds1307;
568 int result;
569
570 client = kobj_to_i2c_client(kobj);
571 ds1307 = i2c_get_clientdata(client);
572
573 if (unlikely(off >= NVRAM_SIZE))
574 return -EFBIG;
575 if ((off + count) > NVRAM_SIZE)
576 count = NVRAM_SIZE - off;
577 if (unlikely(!count))
578 return count;
579
580 result = ds1307->write_block_data(client, 8 + off, count, buf);
581 if (result < 0) {
582 dev_err(&client->dev, "%s error %d\n", "nvram write", result);
583 return result;
584 }
585 return count;
586}
587
588static struct bin_attribute nvram = {
589 .attr = {
590 .name = "nvram",
591 .mode = S_IRUGO | S_IWUSR,
592 },
593
594 .read = ds1307_nvram_read,
595 .write = ds1307_nvram_write,
596 .size = NVRAM_SIZE,
597};
598
599/*----------------------------------------------------------------------*/
600
601static struct i2c_driver ds1307_driver;
602
603static int __devinit ds1307_probe(struct i2c_client *client,
604 const struct i2c_device_id *id)
605{
606 struct ds1307 *ds1307;
607 int err = -ENODEV;
608 int tmp;
609 const struct chip_desc *chip = &chips[id->driver_data];
610 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
611 int want_irq = false;
612 unsigned char *buf;
613 static const int bbsqi_bitpos[] = {
614 [ds_1337] = 0,
615 [ds_1339] = DS1339_BIT_BBSQI,
616 [ds_3231] = DS3231_BIT_BBSQW,
617 };
618
619 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)
620 && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK))
621 return -EIO;
622
623 if (!(ds1307 = kzalloc(sizeof(struct ds1307), GFP_KERNEL)))
624 return -ENOMEM;
625
626 i2c_set_clientdata(client, ds1307);
627
628 ds1307->client = client;
629 ds1307->type = id->driver_data;
630 ds1307->offset = 0;
631
632 buf = ds1307->regs;
633 if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) {
634 ds1307->read_block_data = i2c_smbus_read_i2c_block_data;
635 ds1307->write_block_data = i2c_smbus_write_i2c_block_data;
636 } else {
637 ds1307->read_block_data = ds1307_read_block_data;
638 ds1307->write_block_data = ds1307_write_block_data;
639 }
640
641 switch (ds1307->type) {
642 case ds_1337:
643 case ds_1339:
644 case ds_3231:
645 /* has IRQ? */
646 if (ds1307->client->irq > 0 && chip->alarm) {
647 INIT_WORK(&ds1307->work, ds1307_work);
648 want_irq = true;
649 }
650 /* get registers that the "rtc" read below won't read... */
651 tmp = ds1307->read_block_data(ds1307->client,
652 DS1337_REG_CONTROL, 2, buf);
653 if (tmp != 2) {
654 pr_debug("read error %d\n", tmp);
655 err = -EIO;
656 goto exit_free;
657 }
658
659 /* oscillator off? turn it on, so clock can tick. */
660 if (ds1307->regs[0] & DS1337_BIT_nEOSC)
661 ds1307->regs[0] &= ~DS1337_BIT_nEOSC;
662
663 /* Using IRQ? Disable the square wave and both alarms.
664 * For some variants, be sure alarms can trigger when we're
665 * running on Vbackup (BBSQI/BBSQW)
666 */
667 if (want_irq) {
668 ds1307->regs[0] |= DS1337_BIT_INTCN
669 | bbsqi_bitpos[ds1307->type];
670 ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
671 }
672
673 i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL,
674 ds1307->regs[0]);
675
676 /* oscillator fault? clear flag, and warn */
677 if (ds1307->regs[1] & DS1337_BIT_OSF) {
678 i2c_smbus_write_byte_data(client, DS1337_REG_STATUS,
679 ds1307->regs[1] & ~DS1337_BIT_OSF);
680 dev_warn(&client->dev, "SET TIME!\n");
681 }
682 break;
683
684 case rx_8025:
685 tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
686 RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
687 if (tmp != 2) {
688 pr_debug("read error %d\n", tmp);
689 err = -EIO;
690 goto exit_free;
691 }
692
693 /* oscillator off? turn it on, so clock can tick. */
694 if (!(ds1307->regs[1] & RX8025_BIT_XST)) {
695 ds1307->regs[1] |= RX8025_BIT_XST;
696 i2c_smbus_write_byte_data(client,
697 RX8025_REG_CTRL2 << 4 | 0x08,
698 ds1307->regs[1]);
699 dev_warn(&client->dev,
700 "oscillator stop detected - SET TIME!\n");
701 }
702
703 if (ds1307->regs[1] & RX8025_BIT_PON) {
704 ds1307->regs[1] &= ~RX8025_BIT_PON;
705 i2c_smbus_write_byte_data(client,
706 RX8025_REG_CTRL2 << 4 | 0x08,
707 ds1307->regs[1]);
708 dev_warn(&client->dev, "power-on detected\n");
709 }
710
711 if (ds1307->regs[1] & RX8025_BIT_VDET) {
712 ds1307->regs[1] &= ~RX8025_BIT_VDET;
713 i2c_smbus_write_byte_data(client,
714 RX8025_REG_CTRL2 << 4 | 0x08,
715 ds1307->regs[1]);
716 dev_warn(&client->dev, "voltage drop detected\n");
717 }
718
719 /* make sure we are running in 24hour mode */
720 if (!(ds1307->regs[0] & RX8025_BIT_2412)) {
721 u8 hour;
722
723 /* switch to 24 hour mode */
724 i2c_smbus_write_byte_data(client,
725 RX8025_REG_CTRL1 << 4 | 0x08,
726 ds1307->regs[0] |
727 RX8025_BIT_2412);
728
729 tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
730 RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
731 if (tmp != 2) {
732 pr_debug("read error %d\n", tmp);
733 err = -EIO;
734 goto exit_free;
735 }
736
737 /* correct hour */
738 hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]);
739 if (hour == 12)
740 hour = 0;
741 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
742 hour += 12;
743
744 i2c_smbus_write_byte_data(client,
745 DS1307_REG_HOUR << 4 | 0x08,
746 hour);
747 }
748 break;
749 case ds_1388:
750 ds1307->offset = 1; /* Seconds starts at 1 */
751 break;
752 default:
753 break;
754 }
755
756read_rtc:
757 /* read RTC registers */
758 tmp = ds1307->read_block_data(ds1307->client, ds1307->offset, 8, buf);
759 if (tmp != 8) {
760 pr_debug("read error %d\n", tmp);
761 err = -EIO;
762 goto exit_free;
763 }
764
765 /* minimal sanity checking; some chips (like DS1340) don't
766 * specify the extra bits as must-be-zero, but there are
767 * still a few values that are clearly out-of-range.
768 */
769 tmp = ds1307->regs[DS1307_REG_SECS];
770 switch (ds1307->type) {
771 case ds_1307:
772 case m41t00:
773 /* clock halted? turn it on, so clock can tick. */
774 if (tmp & DS1307_BIT_CH) {
775 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
776 dev_warn(&client->dev, "SET TIME!\n");
777 goto read_rtc;
778 }
779 break;
780 case ds_1338:
781 /* clock halted? turn it on, so clock can tick. */
782 if (tmp & DS1307_BIT_CH)
783 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
784
785 /* oscillator fault? clear flag, and warn */
786 if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
787 i2c_smbus_write_byte_data(client, DS1307_REG_CONTROL,
788 ds1307->regs[DS1307_REG_CONTROL]
789 & ~DS1338_BIT_OSF);
790 dev_warn(&client->dev, "SET TIME!\n");
791 goto read_rtc;
792 }
793 break;
794 case ds_1340:
795 /* clock halted? turn it on, so clock can tick. */
796 if (tmp & DS1340_BIT_nEOSC)
797 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
798
799 tmp = i2c_smbus_read_byte_data(client, DS1340_REG_FLAG);
800 if (tmp < 0) {
801 pr_debug("read error %d\n", tmp);
802 err = -EIO;
803 goto exit_free;
804 }
805
806 /* oscillator fault? clear flag, and warn */
807 if (tmp & DS1340_BIT_OSF) {
808 i2c_smbus_write_byte_data(client, DS1340_REG_FLAG, 0);
809 dev_warn(&client->dev, "SET TIME!\n");
810 }
811 break;
812 case rx_8025:
813 case ds_1337:
814 case ds_1339:
815 case ds_1388:
816 case ds_3231:
817 break;
818 }
819
820 tmp = ds1307->regs[DS1307_REG_HOUR];
821 switch (ds1307->type) {
822 case ds_1340:
823 case m41t00:
824 /* NOTE: ignores century bits; fix before deploying
825 * systems that will run through year 2100.
826 */
827 break;
828 case rx_8025:
829 break;
830 default:
831 if (!(tmp & DS1307_BIT_12HR))
832 break;
833
834 /* Be sure we're in 24 hour mode. Multi-master systems
835 * take note...
836 */
837 tmp = bcd2bin(tmp & 0x1f);
838 if (tmp == 12)
839 tmp = 0;
840 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
841 tmp += 12;
842 i2c_smbus_write_byte_data(client,
843 ds1307->offset + DS1307_REG_HOUR,
844 bin2bcd(tmp));
845 }
846
847 ds1307->rtc = rtc_device_register(client->name, &client->dev,
848 &ds13xx_rtc_ops, THIS_MODULE);
849 if (IS_ERR(ds1307->rtc)) {
850 err = PTR_ERR(ds1307->rtc);
851 dev_err(&client->dev,
852 "unable to register the class device\n");
853 goto exit_free;
854 }
855
856 if (want_irq) {
857 err = request_irq(client->irq, ds1307_irq, IRQF_SHARED,
858 ds1307->rtc->name, client);
859 if (err) {
860 dev_err(&client->dev,
861 "unable to request IRQ!\n");
862 goto exit_irq;
863 }
864
865 device_set_wakeup_capable(&client->dev, 1);
866 set_bit(HAS_ALARM, &ds1307->flags);
867 dev_dbg(&client->dev, "got IRQ %d\n", client->irq);
868 }
869
870 if (chip->nvram56) {
871 err = sysfs_create_bin_file(&client->dev.kobj, &nvram);
872 if (err == 0) {
873 set_bit(HAS_NVRAM, &ds1307->flags);
874 dev_info(&client->dev, "56 bytes nvram\n");
875 }
876 }
877
878 return 0;
879
880exit_irq:
881 rtc_device_unregister(ds1307->rtc);
882exit_free:
883 kfree(ds1307);
884 return err;
885}
886
887static int __devexit ds1307_remove(struct i2c_client *client)
888{
889 struct ds1307 *ds1307 = i2c_get_clientdata(client);
890
891 if (test_and_clear_bit(HAS_ALARM, &ds1307->flags)) {
892 free_irq(client->irq, client);
893 cancel_work_sync(&ds1307->work);
894 }
895
896 if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags))
897 sysfs_remove_bin_file(&client->dev.kobj, &nvram);
898
899 rtc_device_unregister(ds1307->rtc);
900 kfree(ds1307);
901 return 0;
902}
903
904static struct i2c_driver ds1307_driver = {
905 .driver = {
906 .name = "rtc-ds1307",
907 .owner = THIS_MODULE,
908 },
909 .probe = ds1307_probe,
910 .remove = __devexit_p(ds1307_remove),
911 .id_table = ds1307_id,
912};
913
914static int __init ds1307_init(void)
915{
916 return i2c_add_driver(&ds1307_driver);
917}
918module_init(ds1307_init);
919
920static void __exit ds1307_exit(void)
921{
922 i2c_del_driver(&ds1307_driver);
923}
924module_exit(ds1307_exit);
925
926MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
927MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
4 *
5 * Copyright (C) 2005 James Chapman (ds1337 core)
6 * Copyright (C) 2006 David Brownell
7 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
8 * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
9 */
10
11#include <linux/bcd.h>
12#include <linux/i2c.h>
13#include <linux/init.h>
14#include <linux/kstrtox.h>
15#include <linux/mod_devicetable.h>
16#include <linux/module.h>
17#include <linux/property.h>
18#include <linux/rtc/ds1307.h>
19#include <linux/rtc.h>
20#include <linux/slab.h>
21#include <linux/string.h>
22#include <linux/hwmon.h>
23#include <linux/hwmon-sysfs.h>
24#include <linux/clk-provider.h>
25#include <linux/regmap.h>
26#include <linux/watchdog.h>
27
28/*
29 * We can't determine type by probing, but if we expect pre-Linux code
30 * to have set the chip up as a clock (turning on the oscillator and
31 * setting the date and time), Linux can ignore the non-clock features.
32 * That's a natural job for a factory or repair bench.
33 */
34enum ds_type {
35 unknown_ds_type, /* always first and 0 */
36 ds_1307,
37 ds_1308,
38 ds_1337,
39 ds_1338,
40 ds_1339,
41 ds_1340,
42 ds_1341,
43 ds_1388,
44 ds_3231,
45 m41t0,
46 m41t00,
47 m41t11,
48 mcp794xx,
49 rx_8025,
50 rx_8130,
51 last_ds_type /* always last */
52 /* rs5c372 too? different address... */
53};
54
55/* RTC registers don't differ much, except for the century flag */
56#define DS1307_REG_SECS 0x00 /* 00-59 */
57# define DS1307_BIT_CH 0x80
58# define DS1340_BIT_nEOSC 0x80
59# define MCP794XX_BIT_ST 0x80
60#define DS1307_REG_MIN 0x01 /* 00-59 */
61# define M41T0_BIT_OF 0x80
62#define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
63# define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
64# define DS1307_BIT_PM 0x20 /* in REG_HOUR */
65# define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
66# define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
67#define DS1307_REG_WDAY 0x03 /* 01-07 */
68# define MCP794XX_BIT_VBATEN 0x08
69#define DS1307_REG_MDAY 0x04 /* 01-31 */
70#define DS1307_REG_MONTH 0x05 /* 01-12 */
71# define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
72#define DS1307_REG_YEAR 0x06 /* 00-99 */
73
74/*
75 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
76 * start at 7, and they differ a LOT. Only control and status matter for
77 * basic RTC date and time functionality; be careful using them.
78 */
79#define DS1307_REG_CONTROL 0x07 /* or ds1338 */
80# define DS1307_BIT_OUT 0x80
81# define DS1338_BIT_OSF 0x20
82# define DS1307_BIT_SQWE 0x10
83# define DS1307_BIT_RS1 0x02
84# define DS1307_BIT_RS0 0x01
85#define DS1337_REG_CONTROL 0x0e
86# define DS1337_BIT_nEOSC 0x80
87# define DS1339_BIT_BBSQI 0x20
88# define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
89# define DS1337_BIT_RS2 0x10
90# define DS1337_BIT_RS1 0x08
91# define DS1337_BIT_INTCN 0x04
92# define DS1337_BIT_A2IE 0x02
93# define DS1337_BIT_A1IE 0x01
94#define DS1340_REG_CONTROL 0x07
95# define DS1340_BIT_OUT 0x80
96# define DS1340_BIT_FT 0x40
97# define DS1340_BIT_CALIB_SIGN 0x20
98# define DS1340_M_CALIBRATION 0x1f
99#define DS1340_REG_FLAG 0x09
100# define DS1340_BIT_OSF 0x80
101#define DS1337_REG_STATUS 0x0f
102# define DS1337_BIT_OSF 0x80
103# define DS3231_BIT_EN32KHZ 0x08
104# define DS1337_BIT_A2I 0x02
105# define DS1337_BIT_A1I 0x01
106#define DS1339_REG_ALARM1_SECS 0x07
107
108#define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
109
110#define RX8025_REG_CTRL1 0x0e
111# define RX8025_BIT_2412 0x20
112#define RX8025_REG_CTRL2 0x0f
113# define RX8025_BIT_PON 0x10
114# define RX8025_BIT_VDET 0x40
115# define RX8025_BIT_XST 0x20
116
117#define RX8130_REG_ALARM_MIN 0x17
118#define RX8130_REG_ALARM_HOUR 0x18
119#define RX8130_REG_ALARM_WEEK_OR_DAY 0x19
120#define RX8130_REG_EXTENSION 0x1c
121#define RX8130_REG_EXTENSION_WADA BIT(3)
122#define RX8130_REG_FLAG 0x1d
123#define RX8130_REG_FLAG_VLF BIT(1)
124#define RX8130_REG_FLAG_AF BIT(3)
125#define RX8130_REG_CONTROL0 0x1e
126#define RX8130_REG_CONTROL0_AIE BIT(3)
127#define RX8130_REG_CONTROL1 0x1f
128#define RX8130_REG_CONTROL1_INIEN BIT(4)
129#define RX8130_REG_CONTROL1_CHGEN BIT(5)
130
131#define MCP794XX_REG_CONTROL 0x07
132# define MCP794XX_BIT_ALM0_EN 0x10
133# define MCP794XX_BIT_ALM1_EN 0x20
134#define MCP794XX_REG_ALARM0_BASE 0x0a
135#define MCP794XX_REG_ALARM0_CTRL 0x0d
136#define MCP794XX_REG_ALARM1_BASE 0x11
137#define MCP794XX_REG_ALARM1_CTRL 0x14
138# define MCP794XX_BIT_ALMX_IF BIT(3)
139# define MCP794XX_BIT_ALMX_C0 BIT(4)
140# define MCP794XX_BIT_ALMX_C1 BIT(5)
141# define MCP794XX_BIT_ALMX_C2 BIT(6)
142# define MCP794XX_BIT_ALMX_POL BIT(7)
143# define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
144 MCP794XX_BIT_ALMX_C1 | \
145 MCP794XX_BIT_ALMX_C2)
146
147#define M41TXX_REG_CONTROL 0x07
148# define M41TXX_BIT_OUT BIT(7)
149# define M41TXX_BIT_FT BIT(6)
150# define M41TXX_BIT_CALIB_SIGN BIT(5)
151# define M41TXX_M_CALIBRATION GENMASK(4, 0)
152
153#define DS1388_REG_WDOG_HUN_SECS 0x08
154#define DS1388_REG_WDOG_SECS 0x09
155#define DS1388_REG_FLAG 0x0b
156# define DS1388_BIT_WF BIT(6)
157# define DS1388_BIT_OSF BIT(7)
158#define DS1388_REG_CONTROL 0x0c
159# define DS1388_BIT_RST BIT(0)
160# define DS1388_BIT_WDE BIT(1)
161# define DS1388_BIT_nEOSC BIT(7)
162
163/* negative offset step is -2.034ppm */
164#define M41TXX_NEG_OFFSET_STEP_PPB 2034
165/* positive offset step is +4.068ppm */
166#define M41TXX_POS_OFFSET_STEP_PPB 4068
167/* Min and max values supported with 'offset' interface by M41TXX */
168#define M41TXX_MIN_OFFSET ((-31) * M41TXX_NEG_OFFSET_STEP_PPB)
169#define M41TXX_MAX_OFFSET ((31) * M41TXX_POS_OFFSET_STEP_PPB)
170
171struct ds1307 {
172 enum ds_type type;
173 struct device *dev;
174 struct regmap *regmap;
175 const char *name;
176 struct rtc_device *rtc;
177#ifdef CONFIG_COMMON_CLK
178 struct clk_hw clks[2];
179#endif
180};
181
182struct chip_desc {
183 unsigned alarm:1;
184 u16 nvram_offset;
185 u16 nvram_size;
186 u8 offset; /* register's offset */
187 u8 century_reg;
188 u8 century_enable_bit;
189 u8 century_bit;
190 u8 bbsqi_bit;
191 irq_handler_t irq_handler;
192 const struct rtc_class_ops *rtc_ops;
193 u16 trickle_charger_reg;
194 u8 (*do_trickle_setup)(struct ds1307 *, u32,
195 bool);
196 /* Does the RTC require trickle-resistor-ohms to select the value of
197 * the resistor between Vcc and Vbackup?
198 */
199 bool requires_trickle_resistor;
200 /* Some RTC's batteries and supercaps were charged by default, others
201 * allow charging but were not configured previously to do so.
202 * Remember this behavior to stay backwards compatible.
203 */
204 bool charge_default;
205};
206
207static const struct chip_desc chips[last_ds_type];
208
209static int ds1307_get_time(struct device *dev, struct rtc_time *t)
210{
211 struct ds1307 *ds1307 = dev_get_drvdata(dev);
212 int tmp, ret;
213 const struct chip_desc *chip = &chips[ds1307->type];
214 u8 regs[7];
215
216 if (ds1307->type == rx_8130) {
217 unsigned int regflag;
218 ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, ®flag);
219 if (ret) {
220 dev_err(dev, "%s error %d\n", "read", ret);
221 return ret;
222 }
223
224 if (regflag & RX8130_REG_FLAG_VLF) {
225 dev_warn_once(dev, "oscillator failed, set time!\n");
226 return -EINVAL;
227 }
228 }
229
230 /* read the RTC date and time registers all at once */
231 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
232 sizeof(regs));
233 if (ret) {
234 dev_err(dev, "%s error %d\n", "read", ret);
235 return ret;
236 }
237
238 dev_dbg(dev, "%s: %7ph\n", "read", regs);
239
240 /* if oscillator fail bit is set, no data can be trusted */
241 if (ds1307->type == m41t0 &&
242 regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
243 dev_warn_once(dev, "oscillator failed, set time!\n");
244 return -EINVAL;
245 }
246
247 tmp = regs[DS1307_REG_SECS];
248 switch (ds1307->type) {
249 case ds_1307:
250 case m41t0:
251 case m41t00:
252 case m41t11:
253 if (tmp & DS1307_BIT_CH)
254 return -EINVAL;
255 break;
256 case ds_1308:
257 case ds_1338:
258 if (tmp & DS1307_BIT_CH)
259 return -EINVAL;
260
261 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp);
262 if (ret)
263 return ret;
264 if (tmp & DS1338_BIT_OSF)
265 return -EINVAL;
266 break;
267 case ds_1340:
268 if (tmp & DS1340_BIT_nEOSC)
269 return -EINVAL;
270
271 ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
272 if (ret)
273 return ret;
274 if (tmp & DS1340_BIT_OSF)
275 return -EINVAL;
276 break;
277 case ds_1388:
278 ret = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &tmp);
279 if (ret)
280 return ret;
281 if (tmp & DS1388_BIT_OSF)
282 return -EINVAL;
283 break;
284 case mcp794xx:
285 if (!(tmp & MCP794XX_BIT_ST))
286 return -EINVAL;
287
288 break;
289 default:
290 break;
291 }
292
293 t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
294 t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
295 tmp = regs[DS1307_REG_HOUR] & 0x3f;
296 t->tm_hour = bcd2bin(tmp);
297 /* rx8130 is bit position, not BCD */
298 if (ds1307->type == rx_8130)
299 t->tm_wday = fls(regs[DS1307_REG_WDAY] & 0x7f);
300 else
301 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
302 t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
303 tmp = regs[DS1307_REG_MONTH] & 0x1f;
304 t->tm_mon = bcd2bin(tmp) - 1;
305 t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
306
307 if (regs[chip->century_reg] & chip->century_bit &&
308 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
309 t->tm_year += 100;
310
311 dev_dbg(dev, "%s secs=%d, mins=%d, "
312 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
313 "read", t->tm_sec, t->tm_min,
314 t->tm_hour, t->tm_mday,
315 t->tm_mon, t->tm_year, t->tm_wday);
316
317 return 0;
318}
319
320static int ds1307_set_time(struct device *dev, struct rtc_time *t)
321{
322 struct ds1307 *ds1307 = dev_get_drvdata(dev);
323 const struct chip_desc *chip = &chips[ds1307->type];
324 int result;
325 int tmp;
326 u8 regs[7];
327
328 dev_dbg(dev, "%s secs=%d, mins=%d, "
329 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
330 "write", t->tm_sec, t->tm_min,
331 t->tm_hour, t->tm_mday,
332 t->tm_mon, t->tm_year, t->tm_wday);
333
334 if (t->tm_year < 100)
335 return -EINVAL;
336
337#ifdef CONFIG_RTC_DRV_DS1307_CENTURY
338 if (t->tm_year > (chip->century_bit ? 299 : 199))
339 return -EINVAL;
340#else
341 if (t->tm_year > 199)
342 return -EINVAL;
343#endif
344
345 regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
346 regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
347 regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
348 /* rx8130 is bit position, not BCD */
349 if (ds1307->type == rx_8130)
350 regs[DS1307_REG_WDAY] = 1 << t->tm_wday;
351 else
352 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
353 regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
354 regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
355
356 /* assume 20YY not 19YY */
357 tmp = t->tm_year - 100;
358 regs[DS1307_REG_YEAR] = bin2bcd(tmp);
359
360 if (chip->century_enable_bit)
361 regs[chip->century_reg] |= chip->century_enable_bit;
362 if (t->tm_year > 199 && chip->century_bit)
363 regs[chip->century_reg] |= chip->century_bit;
364
365 switch (ds1307->type) {
366 case ds_1308:
367 case ds_1338:
368 regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL,
369 DS1338_BIT_OSF, 0);
370 break;
371 case ds_1340:
372 regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG,
373 DS1340_BIT_OSF, 0);
374 break;
375 case ds_1388:
376 regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
377 DS1388_BIT_OSF, 0);
378 break;
379 case mcp794xx:
380 /*
381 * these bits were cleared when preparing the date/time
382 * values and need to be set again before writing the
383 * regsfer out to the device.
384 */
385 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
386 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
387 break;
388 default:
389 break;
390 }
391
392 dev_dbg(dev, "%s: %7ph\n", "write", regs);
393
394 result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
395 sizeof(regs));
396 if (result) {
397 dev_err(dev, "%s error %d\n", "write", result);
398 return result;
399 }
400
401 if (ds1307->type == rx_8130) {
402 /* clear Voltage Loss Flag as data is available now */
403 result = regmap_write(ds1307->regmap, RX8130_REG_FLAG,
404 ~(u8)RX8130_REG_FLAG_VLF);
405 if (result) {
406 dev_err(dev, "%s error %d\n", "write", result);
407 return result;
408 }
409 }
410
411 return 0;
412}
413
414static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
415{
416 struct ds1307 *ds1307 = dev_get_drvdata(dev);
417 int ret;
418 u8 regs[9];
419
420 /* read all ALARM1, ALARM2, and status registers at once */
421 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
422 regs, sizeof(regs));
423 if (ret) {
424 dev_err(dev, "%s error %d\n", "alarm read", ret);
425 return ret;
426 }
427
428 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
429 ®s[0], ®s[4], ®s[7]);
430
431 /*
432 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
433 * and that all four fields are checked matches
434 */
435 t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
436 t->time.tm_min = bcd2bin(regs[1] & 0x7f);
437 t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
438 t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
439
440 /* ... and status */
441 t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
442 t->pending = !!(regs[8] & DS1337_BIT_A1I);
443
444 dev_dbg(dev, "%s secs=%d, mins=%d, "
445 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
446 "alarm read", t->time.tm_sec, t->time.tm_min,
447 t->time.tm_hour, t->time.tm_mday,
448 t->enabled, t->pending);
449
450 return 0;
451}
452
453static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
454{
455 struct ds1307 *ds1307 = dev_get_drvdata(dev);
456 unsigned char regs[9];
457 u8 control, status;
458 int ret;
459
460 dev_dbg(dev, "%s secs=%d, mins=%d, "
461 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
462 "alarm set", t->time.tm_sec, t->time.tm_min,
463 t->time.tm_hour, t->time.tm_mday,
464 t->enabled, t->pending);
465
466 /* read current status of both alarms and the chip */
467 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
468 sizeof(regs));
469 if (ret) {
470 dev_err(dev, "%s error %d\n", "alarm write", ret);
471 return ret;
472 }
473 control = regs[7];
474 status = regs[8];
475
476 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
477 ®s[0], ®s[4], control, status);
478
479 /* set ALARM1, using 24 hour and day-of-month modes */
480 regs[0] = bin2bcd(t->time.tm_sec);
481 regs[1] = bin2bcd(t->time.tm_min);
482 regs[2] = bin2bcd(t->time.tm_hour);
483 regs[3] = bin2bcd(t->time.tm_mday);
484
485 /* set ALARM2 to non-garbage */
486 regs[4] = 0;
487 regs[5] = 0;
488 regs[6] = 0;
489
490 /* disable alarms */
491 regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
492 regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
493
494 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
495 sizeof(regs));
496 if (ret) {
497 dev_err(dev, "can't set alarm time\n");
498 return ret;
499 }
500
501 /* optionally enable ALARM1 */
502 if (t->enabled) {
503 dev_dbg(dev, "alarm IRQ armed\n");
504 regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
505 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
506 }
507
508 return 0;
509}
510
511static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
512{
513 struct ds1307 *ds1307 = dev_get_drvdata(dev);
514
515 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
516 DS1337_BIT_A1IE,
517 enabled ? DS1337_BIT_A1IE : 0);
518}
519
520static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode)
521{
522 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
523 DS1307_TRICKLE_CHARGER_NO_DIODE;
524
525 setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
526
527 switch (ohms) {
528 case 250:
529 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
530 break;
531 case 2000:
532 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
533 break;
534 case 4000:
535 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
536 break;
537 default:
538 dev_warn(ds1307->dev,
539 "Unsupported ohm value %u in dt\n", ohms);
540 return 0;
541 }
542 return setup;
543}
544
545static u8 do_trickle_setup_rx8130(struct ds1307 *ds1307, u32 ohms, bool diode)
546{
547 /* make sure that the backup battery is enabled */
548 u8 setup = RX8130_REG_CONTROL1_INIEN;
549 if (diode)
550 setup |= RX8130_REG_CONTROL1_CHGEN;
551
552 return setup;
553}
554
555static irqreturn_t rx8130_irq(int irq, void *dev_id)
556{
557 struct ds1307 *ds1307 = dev_id;
558 u8 ctl[3];
559 int ret;
560
561 rtc_lock(ds1307->rtc);
562
563 /* Read control registers. */
564 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
565 sizeof(ctl));
566 if (ret < 0)
567 goto out;
568 if (!(ctl[1] & RX8130_REG_FLAG_AF))
569 goto out;
570 ctl[1] &= ~RX8130_REG_FLAG_AF;
571 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
572
573 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
574 sizeof(ctl));
575 if (ret < 0)
576 goto out;
577
578 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
579
580out:
581 rtc_unlock(ds1307->rtc);
582
583 return IRQ_HANDLED;
584}
585
586static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
587{
588 struct ds1307 *ds1307 = dev_get_drvdata(dev);
589 u8 ald[3], ctl[3];
590 int ret;
591
592 /* Read alarm registers. */
593 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
594 sizeof(ald));
595 if (ret < 0)
596 return ret;
597
598 /* Read control registers. */
599 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
600 sizeof(ctl));
601 if (ret < 0)
602 return ret;
603
604 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
605 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
606
607 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
608 t->time.tm_sec = -1;
609 t->time.tm_min = bcd2bin(ald[0] & 0x7f);
610 t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
611 t->time.tm_wday = -1;
612 t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
613 t->time.tm_mon = -1;
614 t->time.tm_year = -1;
615 t->time.tm_yday = -1;
616 t->time.tm_isdst = -1;
617
618 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
619 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
620 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
621
622 return 0;
623}
624
625static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
626{
627 struct ds1307 *ds1307 = dev_get_drvdata(dev);
628 u8 ald[3], ctl[3];
629 int ret;
630
631 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
632 "enabled=%d pending=%d\n", __func__,
633 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
634 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
635 t->enabled, t->pending);
636
637 /* Read control registers. */
638 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
639 sizeof(ctl));
640 if (ret < 0)
641 return ret;
642
643 ctl[0] &= RX8130_REG_EXTENSION_WADA;
644 ctl[1] &= ~RX8130_REG_FLAG_AF;
645 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
646
647 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
648 sizeof(ctl));
649 if (ret < 0)
650 return ret;
651
652 /* Hardware alarm precision is 1 minute! */
653 ald[0] = bin2bcd(t->time.tm_min);
654 ald[1] = bin2bcd(t->time.tm_hour);
655 ald[2] = bin2bcd(t->time.tm_mday);
656
657 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
658 sizeof(ald));
659 if (ret < 0)
660 return ret;
661
662 if (!t->enabled)
663 return 0;
664
665 ctl[2] |= RX8130_REG_CONTROL0_AIE;
666
667 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]);
668}
669
670static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
671{
672 struct ds1307 *ds1307 = dev_get_drvdata(dev);
673 int ret, reg;
674
675 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, ®);
676 if (ret < 0)
677 return ret;
678
679 if (enabled)
680 reg |= RX8130_REG_CONTROL0_AIE;
681 else
682 reg &= ~RX8130_REG_CONTROL0_AIE;
683
684 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
685}
686
687static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
688{
689 struct ds1307 *ds1307 = dev_id;
690 struct mutex *lock = &ds1307->rtc->ops_lock;
691 int reg, ret;
692
693 mutex_lock(lock);
694
695 /* Check and clear alarm 0 interrupt flag. */
696 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, ®);
697 if (ret)
698 goto out;
699 if (!(reg & MCP794XX_BIT_ALMX_IF))
700 goto out;
701 reg &= ~MCP794XX_BIT_ALMX_IF;
702 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
703 if (ret)
704 goto out;
705
706 /* Disable alarm 0. */
707 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
708 MCP794XX_BIT_ALM0_EN, 0);
709 if (ret)
710 goto out;
711
712 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
713
714out:
715 mutex_unlock(lock);
716
717 return IRQ_HANDLED;
718}
719
720static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
721{
722 struct ds1307 *ds1307 = dev_get_drvdata(dev);
723 u8 regs[10];
724 int ret;
725
726 /* Read control and alarm 0 registers. */
727 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
728 sizeof(regs));
729 if (ret)
730 return ret;
731
732 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
733
734 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
735 t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
736 t->time.tm_min = bcd2bin(regs[4] & 0x7f);
737 t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
738 t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
739 t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
740 t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
741 t->time.tm_year = -1;
742 t->time.tm_yday = -1;
743 t->time.tm_isdst = -1;
744
745 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
746 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
747 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
748 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
749 !!(regs[6] & MCP794XX_BIT_ALMX_POL),
750 !!(regs[6] & MCP794XX_BIT_ALMX_IF),
751 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
752
753 return 0;
754}
755
756/*
757 * We may have a random RTC weekday, therefore calculate alarm weekday based
758 * on current weekday we read from the RTC timekeeping regs
759 */
760static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm)
761{
762 struct rtc_time tm_now;
763 int days_now, days_alarm, ret;
764
765 ret = ds1307_get_time(dev, &tm_now);
766 if (ret)
767 return ret;
768
769 days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
770 days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
771
772 return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
773}
774
775static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
776{
777 struct ds1307 *ds1307 = dev_get_drvdata(dev);
778 unsigned char regs[10];
779 int wday, ret;
780
781 wday = mcp794xx_alm_weekday(dev, &t->time);
782 if (wday < 0)
783 return wday;
784
785 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
786 "enabled=%d pending=%d\n", __func__,
787 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
788 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
789 t->enabled, t->pending);
790
791 /* Read control and alarm 0 registers. */
792 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
793 sizeof(regs));
794 if (ret)
795 return ret;
796
797 /* Set alarm 0, using 24-hour and day-of-month modes. */
798 regs[3] = bin2bcd(t->time.tm_sec);
799 regs[4] = bin2bcd(t->time.tm_min);
800 regs[5] = bin2bcd(t->time.tm_hour);
801 regs[6] = wday;
802 regs[7] = bin2bcd(t->time.tm_mday);
803 regs[8] = bin2bcd(t->time.tm_mon + 1);
804
805 /* Clear the alarm 0 interrupt flag. */
806 regs[6] &= ~MCP794XX_BIT_ALMX_IF;
807 /* Set alarm match: second, minute, hour, day, date, month. */
808 regs[6] |= MCP794XX_MSK_ALMX_MATCH;
809 /* Disable interrupt. We will not enable until completely programmed */
810 regs[0] &= ~MCP794XX_BIT_ALM0_EN;
811
812 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
813 sizeof(regs));
814 if (ret)
815 return ret;
816
817 if (!t->enabled)
818 return 0;
819 regs[0] |= MCP794XX_BIT_ALM0_EN;
820 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
821}
822
823static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
824{
825 struct ds1307 *ds1307 = dev_get_drvdata(dev);
826
827 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
828 MCP794XX_BIT_ALM0_EN,
829 enabled ? MCP794XX_BIT_ALM0_EN : 0);
830}
831
832static int m41txx_rtc_read_offset(struct device *dev, long *offset)
833{
834 struct ds1307 *ds1307 = dev_get_drvdata(dev);
835 unsigned int ctrl_reg;
836 u8 val;
837
838 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
839
840 val = ctrl_reg & M41TXX_M_CALIBRATION;
841
842 /* check if positive */
843 if (ctrl_reg & M41TXX_BIT_CALIB_SIGN)
844 *offset = (val * M41TXX_POS_OFFSET_STEP_PPB);
845 else
846 *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB);
847
848 return 0;
849}
850
851static int m41txx_rtc_set_offset(struct device *dev, long offset)
852{
853 struct ds1307 *ds1307 = dev_get_drvdata(dev);
854 unsigned int ctrl_reg;
855
856 if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET))
857 return -ERANGE;
858
859 if (offset >= 0) {
860 ctrl_reg = DIV_ROUND_CLOSEST(offset,
861 M41TXX_POS_OFFSET_STEP_PPB);
862 ctrl_reg |= M41TXX_BIT_CALIB_SIGN;
863 } else {
864 ctrl_reg = DIV_ROUND_CLOSEST(abs(offset),
865 M41TXX_NEG_OFFSET_STEP_PPB);
866 }
867
868 return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL,
869 M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN,
870 ctrl_reg);
871}
872
873#ifdef CONFIG_WATCHDOG_CORE
874static int ds1388_wdt_start(struct watchdog_device *wdt_dev)
875{
876 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
877 u8 regs[2];
878 int ret;
879
880 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
881 DS1388_BIT_WF, 0);
882 if (ret)
883 return ret;
884
885 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
886 DS1388_BIT_WDE | DS1388_BIT_RST, 0);
887 if (ret)
888 return ret;
889
890 /*
891 * watchdog timeouts are measured in seconds. So ignore hundredths of
892 * seconds field.
893 */
894 regs[0] = 0;
895 regs[1] = bin2bcd(wdt_dev->timeout);
896
897 ret = regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
898 sizeof(regs));
899 if (ret)
900 return ret;
901
902 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
903 DS1388_BIT_WDE | DS1388_BIT_RST,
904 DS1388_BIT_WDE | DS1388_BIT_RST);
905}
906
907static int ds1388_wdt_stop(struct watchdog_device *wdt_dev)
908{
909 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
910
911 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
912 DS1388_BIT_WDE | DS1388_BIT_RST, 0);
913}
914
915static int ds1388_wdt_ping(struct watchdog_device *wdt_dev)
916{
917 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
918 u8 regs[2];
919
920 return regmap_bulk_read(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
921 sizeof(regs));
922}
923
924static int ds1388_wdt_set_timeout(struct watchdog_device *wdt_dev,
925 unsigned int val)
926{
927 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
928 u8 regs[2];
929
930 wdt_dev->timeout = val;
931 regs[0] = 0;
932 regs[1] = bin2bcd(wdt_dev->timeout);
933
934 return regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
935 sizeof(regs));
936}
937#endif
938
939static const struct rtc_class_ops rx8130_rtc_ops = {
940 .read_time = ds1307_get_time,
941 .set_time = ds1307_set_time,
942 .read_alarm = rx8130_read_alarm,
943 .set_alarm = rx8130_set_alarm,
944 .alarm_irq_enable = rx8130_alarm_irq_enable,
945};
946
947static const struct rtc_class_ops mcp794xx_rtc_ops = {
948 .read_time = ds1307_get_time,
949 .set_time = ds1307_set_time,
950 .read_alarm = mcp794xx_read_alarm,
951 .set_alarm = mcp794xx_set_alarm,
952 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
953};
954
955static const struct rtc_class_ops m41txx_rtc_ops = {
956 .read_time = ds1307_get_time,
957 .set_time = ds1307_set_time,
958 .read_alarm = ds1337_read_alarm,
959 .set_alarm = ds1337_set_alarm,
960 .alarm_irq_enable = ds1307_alarm_irq_enable,
961 .read_offset = m41txx_rtc_read_offset,
962 .set_offset = m41txx_rtc_set_offset,
963};
964
965static const struct chip_desc chips[last_ds_type] = {
966 [ds_1307] = {
967 .nvram_offset = 8,
968 .nvram_size = 56,
969 },
970 [ds_1308] = {
971 .nvram_offset = 8,
972 .nvram_size = 56,
973 },
974 [ds_1337] = {
975 .alarm = 1,
976 .century_reg = DS1307_REG_MONTH,
977 .century_bit = DS1337_BIT_CENTURY,
978 },
979 [ds_1338] = {
980 .nvram_offset = 8,
981 .nvram_size = 56,
982 },
983 [ds_1339] = {
984 .alarm = 1,
985 .century_reg = DS1307_REG_MONTH,
986 .century_bit = DS1337_BIT_CENTURY,
987 .bbsqi_bit = DS1339_BIT_BBSQI,
988 .trickle_charger_reg = 0x10,
989 .do_trickle_setup = &do_trickle_setup_ds1339,
990 .requires_trickle_resistor = true,
991 .charge_default = true,
992 },
993 [ds_1340] = {
994 .century_reg = DS1307_REG_HOUR,
995 .century_enable_bit = DS1340_BIT_CENTURY_EN,
996 .century_bit = DS1340_BIT_CENTURY,
997 .do_trickle_setup = &do_trickle_setup_ds1339,
998 .trickle_charger_reg = 0x08,
999 .requires_trickle_resistor = true,
1000 .charge_default = true,
1001 },
1002 [ds_1341] = {
1003 .century_reg = DS1307_REG_MONTH,
1004 .century_bit = DS1337_BIT_CENTURY,
1005 },
1006 [ds_1388] = {
1007 .offset = 1,
1008 .trickle_charger_reg = 0x0a,
1009 },
1010 [ds_3231] = {
1011 .alarm = 1,
1012 .century_reg = DS1307_REG_MONTH,
1013 .century_bit = DS1337_BIT_CENTURY,
1014 .bbsqi_bit = DS3231_BIT_BBSQW,
1015 },
1016 [rx_8130] = {
1017 .alarm = 1,
1018 /* this is battery backed SRAM */
1019 .nvram_offset = 0x20,
1020 .nvram_size = 4, /* 32bit (4 word x 8 bit) */
1021 .offset = 0x10,
1022 .irq_handler = rx8130_irq,
1023 .rtc_ops = &rx8130_rtc_ops,
1024 .trickle_charger_reg = RX8130_REG_CONTROL1,
1025 .do_trickle_setup = &do_trickle_setup_rx8130,
1026 },
1027 [m41t0] = {
1028 .rtc_ops = &m41txx_rtc_ops,
1029 },
1030 [m41t00] = {
1031 .rtc_ops = &m41txx_rtc_ops,
1032 },
1033 [m41t11] = {
1034 /* this is battery backed SRAM */
1035 .nvram_offset = 8,
1036 .nvram_size = 56,
1037 .rtc_ops = &m41txx_rtc_ops,
1038 },
1039 [mcp794xx] = {
1040 .alarm = 1,
1041 /* this is battery backed SRAM */
1042 .nvram_offset = 0x20,
1043 .nvram_size = 0x40,
1044 .irq_handler = mcp794xx_irq,
1045 .rtc_ops = &mcp794xx_rtc_ops,
1046 },
1047};
1048
1049static const struct i2c_device_id ds1307_id[] = {
1050 { "ds1307", ds_1307 },
1051 { "ds1308", ds_1308 },
1052 { "ds1337", ds_1337 },
1053 { "ds1338", ds_1338 },
1054 { "ds1339", ds_1339 },
1055 { "ds1388", ds_1388 },
1056 { "ds1340", ds_1340 },
1057 { "ds1341", ds_1341 },
1058 { "ds3231", ds_3231 },
1059 { "m41t0", m41t0 },
1060 { "m41t00", m41t00 },
1061 { "m41t11", m41t11 },
1062 { "mcp7940x", mcp794xx },
1063 { "mcp7941x", mcp794xx },
1064 { "pt7c4338", ds_1307 },
1065 { "rx8025", rx_8025 },
1066 { "isl12057", ds_1337 },
1067 { "rx8130", rx_8130 },
1068 { }
1069};
1070MODULE_DEVICE_TABLE(i2c, ds1307_id);
1071
1072static const struct of_device_id ds1307_of_match[] = {
1073 {
1074 .compatible = "dallas,ds1307",
1075 .data = (void *)ds_1307
1076 },
1077 {
1078 .compatible = "dallas,ds1308",
1079 .data = (void *)ds_1308
1080 },
1081 {
1082 .compatible = "dallas,ds1337",
1083 .data = (void *)ds_1337
1084 },
1085 {
1086 .compatible = "dallas,ds1338",
1087 .data = (void *)ds_1338
1088 },
1089 {
1090 .compatible = "dallas,ds1339",
1091 .data = (void *)ds_1339
1092 },
1093 {
1094 .compatible = "dallas,ds1388",
1095 .data = (void *)ds_1388
1096 },
1097 {
1098 .compatible = "dallas,ds1340",
1099 .data = (void *)ds_1340
1100 },
1101 {
1102 .compatible = "dallas,ds1341",
1103 .data = (void *)ds_1341
1104 },
1105 {
1106 .compatible = "maxim,ds3231",
1107 .data = (void *)ds_3231
1108 },
1109 {
1110 .compatible = "st,m41t0",
1111 .data = (void *)m41t0
1112 },
1113 {
1114 .compatible = "st,m41t00",
1115 .data = (void *)m41t00
1116 },
1117 {
1118 .compatible = "st,m41t11",
1119 .data = (void *)m41t11
1120 },
1121 {
1122 .compatible = "microchip,mcp7940x",
1123 .data = (void *)mcp794xx
1124 },
1125 {
1126 .compatible = "microchip,mcp7941x",
1127 .data = (void *)mcp794xx
1128 },
1129 {
1130 .compatible = "pericom,pt7c4338",
1131 .data = (void *)ds_1307
1132 },
1133 {
1134 .compatible = "epson,rx8025",
1135 .data = (void *)rx_8025
1136 },
1137 {
1138 .compatible = "isil,isl12057",
1139 .data = (void *)ds_1337
1140 },
1141 {
1142 .compatible = "epson,rx8130",
1143 .data = (void *)rx_8130
1144 },
1145 { }
1146};
1147MODULE_DEVICE_TABLE(of, ds1307_of_match);
1148
1149/*
1150 * The ds1337 and ds1339 both have two alarms, but we only use the first
1151 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
1152 * signal; ds1339 chips have only one alarm signal.
1153 */
1154static irqreturn_t ds1307_irq(int irq, void *dev_id)
1155{
1156 struct ds1307 *ds1307 = dev_id;
1157 struct mutex *lock = &ds1307->rtc->ops_lock;
1158 int stat, ret;
1159
1160 mutex_lock(lock);
1161 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
1162 if (ret)
1163 goto out;
1164
1165 if (stat & DS1337_BIT_A1I) {
1166 stat &= ~DS1337_BIT_A1I;
1167 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
1168
1169 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1170 DS1337_BIT_A1IE, 0);
1171 if (ret)
1172 goto out;
1173
1174 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
1175 }
1176
1177out:
1178 mutex_unlock(lock);
1179
1180 return IRQ_HANDLED;
1181}
1182
1183/*----------------------------------------------------------------------*/
1184
1185static const struct rtc_class_ops ds13xx_rtc_ops = {
1186 .read_time = ds1307_get_time,
1187 .set_time = ds1307_set_time,
1188 .read_alarm = ds1337_read_alarm,
1189 .set_alarm = ds1337_set_alarm,
1190 .alarm_irq_enable = ds1307_alarm_irq_enable,
1191};
1192
1193static ssize_t frequency_test_store(struct device *dev,
1194 struct device_attribute *attr,
1195 const char *buf, size_t count)
1196{
1197 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1198 bool freq_test_en;
1199 int ret;
1200
1201 ret = kstrtobool(buf, &freq_test_en);
1202 if (ret) {
1203 dev_err(dev, "Failed to store RTC Frequency Test attribute\n");
1204 return ret;
1205 }
1206
1207 regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT,
1208 freq_test_en ? M41TXX_BIT_FT : 0);
1209
1210 return count;
1211}
1212
1213static ssize_t frequency_test_show(struct device *dev,
1214 struct device_attribute *attr,
1215 char *buf)
1216{
1217 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1218 unsigned int ctrl_reg;
1219
1220 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
1221
1222 return sysfs_emit(buf, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" : "off\n");
1223}
1224
1225static DEVICE_ATTR_RW(frequency_test);
1226
1227static struct attribute *rtc_freq_test_attrs[] = {
1228 &dev_attr_frequency_test.attr,
1229 NULL,
1230};
1231
1232static const struct attribute_group rtc_freq_test_attr_group = {
1233 .attrs = rtc_freq_test_attrs,
1234};
1235
1236static int ds1307_add_frequency_test(struct ds1307 *ds1307)
1237{
1238 int err;
1239
1240 switch (ds1307->type) {
1241 case m41t0:
1242 case m41t00:
1243 case m41t11:
1244 err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group);
1245 if (err)
1246 return err;
1247 break;
1248 default:
1249 break;
1250 }
1251
1252 return 0;
1253}
1254
1255/*----------------------------------------------------------------------*/
1256
1257static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
1258 size_t bytes)
1259{
1260 struct ds1307 *ds1307 = priv;
1261 const struct chip_desc *chip = &chips[ds1307->type];
1262
1263 return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
1264 val, bytes);
1265}
1266
1267static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
1268 size_t bytes)
1269{
1270 struct ds1307 *ds1307 = priv;
1271 const struct chip_desc *chip = &chips[ds1307->type];
1272
1273 return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
1274 val, bytes);
1275}
1276
1277/*----------------------------------------------------------------------*/
1278
1279static u8 ds1307_trickle_init(struct ds1307 *ds1307,
1280 const struct chip_desc *chip)
1281{
1282 u32 ohms, chargeable;
1283 bool diode = chip->charge_default;
1284
1285 if (!chip->do_trickle_setup)
1286 return 0;
1287
1288 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
1289 &ohms) && chip->requires_trickle_resistor)
1290 return 0;
1291
1292 /* aux-voltage-chargeable takes precedence over the deprecated
1293 * trickle-diode-disable
1294 */
1295 if (!device_property_read_u32(ds1307->dev, "aux-voltage-chargeable",
1296 &chargeable)) {
1297 switch (chargeable) {
1298 case 0:
1299 diode = false;
1300 break;
1301 case 1:
1302 diode = true;
1303 break;
1304 default:
1305 dev_warn(ds1307->dev,
1306 "unsupported aux-voltage-chargeable value\n");
1307 break;
1308 }
1309 } else if (device_property_read_bool(ds1307->dev,
1310 "trickle-diode-disable")) {
1311 diode = false;
1312 }
1313
1314 return chip->do_trickle_setup(ds1307, ohms, diode);
1315}
1316
1317/*----------------------------------------------------------------------*/
1318
1319#if IS_REACHABLE(CONFIG_HWMON)
1320
1321/*
1322 * Temperature sensor support for ds3231 devices.
1323 */
1324
1325#define DS3231_REG_TEMPERATURE 0x11
1326
1327/*
1328 * A user-initiated temperature conversion is not started by this function,
1329 * so the temperature is updated once every 64 seconds.
1330 */
1331static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
1332{
1333 struct ds1307 *ds1307 = dev_get_drvdata(dev);
1334 u8 temp_buf[2];
1335 s16 temp;
1336 int ret;
1337
1338 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
1339 temp_buf, sizeof(temp_buf));
1340 if (ret)
1341 return ret;
1342 /*
1343 * Temperature is represented as a 10-bit code with a resolution of
1344 * 0.25 degree celsius and encoded in two's complement format.
1345 */
1346 temp = (temp_buf[0] << 8) | temp_buf[1];
1347 temp >>= 6;
1348 *mC = temp * 250;
1349
1350 return 0;
1351}
1352
1353static ssize_t ds3231_hwmon_show_temp(struct device *dev,
1354 struct device_attribute *attr, char *buf)
1355{
1356 int ret;
1357 s32 temp;
1358
1359 ret = ds3231_hwmon_read_temp(dev, &temp);
1360 if (ret)
1361 return ret;
1362
1363 return sprintf(buf, "%d\n", temp);
1364}
1365static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
1366 NULL, 0);
1367
1368static struct attribute *ds3231_hwmon_attrs[] = {
1369 &sensor_dev_attr_temp1_input.dev_attr.attr,
1370 NULL,
1371};
1372ATTRIBUTE_GROUPS(ds3231_hwmon);
1373
1374static void ds1307_hwmon_register(struct ds1307 *ds1307)
1375{
1376 struct device *dev;
1377
1378 if (ds1307->type != ds_3231)
1379 return;
1380
1381 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
1382 ds1307,
1383 ds3231_hwmon_groups);
1384 if (IS_ERR(dev)) {
1385 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1386 PTR_ERR(dev));
1387 }
1388}
1389
1390#else
1391
1392static void ds1307_hwmon_register(struct ds1307 *ds1307)
1393{
1394}
1395
1396#endif /* CONFIG_RTC_DRV_DS1307_HWMON */
1397
1398/*----------------------------------------------------------------------*/
1399
1400/*
1401 * Square-wave output support for DS3231
1402 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1403 */
1404#ifdef CONFIG_COMMON_CLK
1405
1406enum {
1407 DS3231_CLK_SQW = 0,
1408 DS3231_CLK_32KHZ,
1409};
1410
1411#define clk_sqw_to_ds1307(clk) \
1412 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1413#define clk_32khz_to_ds1307(clk) \
1414 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1415
1416static int ds3231_clk_sqw_rates[] = {
1417 1,
1418 1024,
1419 4096,
1420 8192,
1421};
1422
1423static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1424{
1425 struct mutex *lock = &ds1307->rtc->ops_lock;
1426 int ret;
1427
1428 mutex_lock(lock);
1429 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1430 mask, value);
1431 mutex_unlock(lock);
1432
1433 return ret;
1434}
1435
1436static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1437 unsigned long parent_rate)
1438{
1439 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1440 int control, ret;
1441 int rate_sel = 0;
1442
1443 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1444 if (ret)
1445 return ret;
1446 if (control & DS1337_BIT_RS1)
1447 rate_sel += 1;
1448 if (control & DS1337_BIT_RS2)
1449 rate_sel += 2;
1450
1451 return ds3231_clk_sqw_rates[rate_sel];
1452}
1453
1454static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
1455 unsigned long *prate)
1456{
1457 int i;
1458
1459 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1460 if (ds3231_clk_sqw_rates[i] <= rate)
1461 return ds3231_clk_sqw_rates[i];
1462 }
1463
1464 return 0;
1465}
1466
1467static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1468 unsigned long parent_rate)
1469{
1470 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1471 int control = 0;
1472 int rate_sel;
1473
1474 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1475 rate_sel++) {
1476 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1477 break;
1478 }
1479
1480 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1481 return -EINVAL;
1482
1483 if (rate_sel & 1)
1484 control |= DS1337_BIT_RS1;
1485 if (rate_sel & 2)
1486 control |= DS1337_BIT_RS2;
1487
1488 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1489 control);
1490}
1491
1492static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1493{
1494 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1495
1496 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1497}
1498
1499static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1500{
1501 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1502
1503 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1504}
1505
1506static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1507{
1508 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1509 int control, ret;
1510
1511 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1512 if (ret)
1513 return ret;
1514
1515 return !(control & DS1337_BIT_INTCN);
1516}
1517
1518static const struct clk_ops ds3231_clk_sqw_ops = {
1519 .prepare = ds3231_clk_sqw_prepare,
1520 .unprepare = ds3231_clk_sqw_unprepare,
1521 .is_prepared = ds3231_clk_sqw_is_prepared,
1522 .recalc_rate = ds3231_clk_sqw_recalc_rate,
1523 .round_rate = ds3231_clk_sqw_round_rate,
1524 .set_rate = ds3231_clk_sqw_set_rate,
1525};
1526
1527static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
1528 unsigned long parent_rate)
1529{
1530 return 32768;
1531}
1532
1533static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1534{
1535 struct mutex *lock = &ds1307->rtc->ops_lock;
1536 int ret;
1537
1538 mutex_lock(lock);
1539 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1540 DS3231_BIT_EN32KHZ,
1541 enable ? DS3231_BIT_EN32KHZ : 0);
1542 mutex_unlock(lock);
1543
1544 return ret;
1545}
1546
1547static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1548{
1549 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1550
1551 return ds3231_clk_32khz_control(ds1307, true);
1552}
1553
1554static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1555{
1556 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1557
1558 ds3231_clk_32khz_control(ds1307, false);
1559}
1560
1561static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1562{
1563 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1564 int status, ret;
1565
1566 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1567 if (ret)
1568 return ret;
1569
1570 return !!(status & DS3231_BIT_EN32KHZ);
1571}
1572
1573static const struct clk_ops ds3231_clk_32khz_ops = {
1574 .prepare = ds3231_clk_32khz_prepare,
1575 .unprepare = ds3231_clk_32khz_unprepare,
1576 .is_prepared = ds3231_clk_32khz_is_prepared,
1577 .recalc_rate = ds3231_clk_32khz_recalc_rate,
1578};
1579
1580static const char *ds3231_clks_names[] = {
1581 [DS3231_CLK_SQW] = "ds3231_clk_sqw",
1582 [DS3231_CLK_32KHZ] = "ds3231_clk_32khz",
1583};
1584
1585static struct clk_init_data ds3231_clks_init[] = {
1586 [DS3231_CLK_SQW] = {
1587 .ops = &ds3231_clk_sqw_ops,
1588 },
1589 [DS3231_CLK_32KHZ] = {
1590 .ops = &ds3231_clk_32khz_ops,
1591 },
1592};
1593
1594static int ds3231_clks_register(struct ds1307 *ds1307)
1595{
1596 struct device_node *node = ds1307->dev->of_node;
1597 struct clk_onecell_data *onecell;
1598 int i;
1599
1600 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
1601 if (!onecell)
1602 return -ENOMEM;
1603
1604 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
1605 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1606 sizeof(onecell->clks[0]), GFP_KERNEL);
1607 if (!onecell->clks)
1608 return -ENOMEM;
1609
1610 /* optional override of the clockname */
1611 device_property_read_string_array(ds1307->dev, "clock-output-names",
1612 ds3231_clks_names,
1613 ARRAY_SIZE(ds3231_clks_names));
1614
1615 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1616 struct clk_init_data init = ds3231_clks_init[i];
1617
1618 /*
1619 * Interrupt signal due to alarm conditions and square-wave
1620 * output share same pin, so don't initialize both.
1621 */
1622 if (i == DS3231_CLK_SQW && test_bit(RTC_FEATURE_ALARM, ds1307->rtc->features))
1623 continue;
1624
1625 init.name = ds3231_clks_names[i];
1626 ds1307->clks[i].init = &init;
1627
1628 onecell->clks[i] = devm_clk_register(ds1307->dev,
1629 &ds1307->clks[i]);
1630 if (IS_ERR(onecell->clks[i]))
1631 return PTR_ERR(onecell->clks[i]);
1632 }
1633
1634 if (node)
1635 of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1636
1637 return 0;
1638}
1639
1640static void ds1307_clks_register(struct ds1307 *ds1307)
1641{
1642 int ret;
1643
1644 if (ds1307->type != ds_3231)
1645 return;
1646
1647 ret = ds3231_clks_register(ds1307);
1648 if (ret) {
1649 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1650 ret);
1651 }
1652}
1653
1654#else
1655
1656static void ds1307_clks_register(struct ds1307 *ds1307)
1657{
1658}
1659
1660#endif /* CONFIG_COMMON_CLK */
1661
1662#ifdef CONFIG_WATCHDOG_CORE
1663static const struct watchdog_info ds1388_wdt_info = {
1664 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
1665 .identity = "DS1388 watchdog",
1666};
1667
1668static const struct watchdog_ops ds1388_wdt_ops = {
1669 .owner = THIS_MODULE,
1670 .start = ds1388_wdt_start,
1671 .stop = ds1388_wdt_stop,
1672 .ping = ds1388_wdt_ping,
1673 .set_timeout = ds1388_wdt_set_timeout,
1674
1675};
1676
1677static void ds1307_wdt_register(struct ds1307 *ds1307)
1678{
1679 struct watchdog_device *wdt;
1680 int err;
1681 int val;
1682
1683 if (ds1307->type != ds_1388)
1684 return;
1685
1686 wdt = devm_kzalloc(ds1307->dev, sizeof(*wdt), GFP_KERNEL);
1687 if (!wdt)
1688 return;
1689
1690 err = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &val);
1691 if (!err && val & DS1388_BIT_WF)
1692 wdt->bootstatus = WDIOF_CARDRESET;
1693
1694 wdt->info = &ds1388_wdt_info;
1695 wdt->ops = &ds1388_wdt_ops;
1696 wdt->timeout = 99;
1697 wdt->max_timeout = 99;
1698 wdt->min_timeout = 1;
1699
1700 watchdog_init_timeout(wdt, 0, ds1307->dev);
1701 watchdog_set_drvdata(wdt, ds1307);
1702 devm_watchdog_register_device(ds1307->dev, wdt);
1703}
1704#else
1705static void ds1307_wdt_register(struct ds1307 *ds1307)
1706{
1707}
1708#endif /* CONFIG_WATCHDOG_CORE */
1709
1710static const struct regmap_config regmap_config = {
1711 .reg_bits = 8,
1712 .val_bits = 8,
1713};
1714
1715static int ds1307_probe(struct i2c_client *client)
1716{
1717 const struct i2c_device_id *id = i2c_client_get_device_id(client);
1718 struct ds1307 *ds1307;
1719 const void *match;
1720 int err = -ENODEV;
1721 int tmp;
1722 const struct chip_desc *chip;
1723 bool want_irq;
1724 bool ds1307_can_wakeup_device = false;
1725 unsigned char regs[8];
1726 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
1727 u8 trickle_charger_setup = 0;
1728
1729 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
1730 if (!ds1307)
1731 return -ENOMEM;
1732
1733 dev_set_drvdata(&client->dev, ds1307);
1734 ds1307->dev = &client->dev;
1735 ds1307->name = client->name;
1736
1737 ds1307->regmap = devm_regmap_init_i2c(client, ®map_config);
1738 if (IS_ERR(ds1307->regmap)) {
1739 dev_err(ds1307->dev, "regmap allocation failed\n");
1740 return PTR_ERR(ds1307->regmap);
1741 }
1742
1743 i2c_set_clientdata(client, ds1307);
1744
1745 match = device_get_match_data(&client->dev);
1746 if (match) {
1747 ds1307->type = (uintptr_t)match;
1748 chip = &chips[ds1307->type];
1749 } else if (id) {
1750 chip = &chips[id->driver_data];
1751 ds1307->type = id->driver_data;
1752 } else {
1753 return -ENODEV;
1754 }
1755
1756 want_irq = client->irq > 0 && chip->alarm;
1757
1758 if (!pdata)
1759 trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
1760 else if (pdata->trickle_charger_setup)
1761 trickle_charger_setup = pdata->trickle_charger_setup;
1762
1763 if (trickle_charger_setup && chip->trickle_charger_reg) {
1764 dev_dbg(ds1307->dev,
1765 "writing trickle charger info 0x%x to 0x%x\n",
1766 trickle_charger_setup, chip->trickle_charger_reg);
1767 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
1768 trickle_charger_setup);
1769 }
1770
1771/*
1772 * For devices with no IRQ directly connected to the SoC, the RTC chip
1773 * can be forced as a wakeup source by stating that explicitly in
1774 * the device's .dts file using the "wakeup-source" boolean property.
1775 * If the "wakeup-source" property is set, don't request an IRQ.
1776 * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1777 * if supported by the RTC.
1778 */
1779 if (chip->alarm && device_property_read_bool(&client->dev, "wakeup-source"))
1780 ds1307_can_wakeup_device = true;
1781
1782 switch (ds1307->type) {
1783 case ds_1337:
1784 case ds_1339:
1785 case ds_1341:
1786 case ds_3231:
1787 /* get registers that the "rtc" read below won't read... */
1788 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
1789 regs, 2);
1790 if (err) {
1791 dev_dbg(ds1307->dev, "read error %d\n", err);
1792 goto exit;
1793 }
1794
1795 /* oscillator off? turn it on, so clock can tick. */
1796 if (regs[0] & DS1337_BIT_nEOSC)
1797 regs[0] &= ~DS1337_BIT_nEOSC;
1798
1799 /*
1800 * Using IRQ or defined as wakeup-source?
1801 * Disable the square wave and both alarms.
1802 * For some variants, be sure alarms can trigger when we're
1803 * running on Vbackup (BBSQI/BBSQW)
1804 */
1805 if (want_irq || ds1307_can_wakeup_device) {
1806 regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
1807 regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
1808 }
1809
1810 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
1811 regs[0]);
1812
1813 /* oscillator fault? clear flag, and warn */
1814 if (regs[1] & DS1337_BIT_OSF) {
1815 regmap_write(ds1307->regmap, DS1337_REG_STATUS,
1816 regs[1] & ~DS1337_BIT_OSF);
1817 dev_warn(ds1307->dev, "SET TIME!\n");
1818 }
1819 break;
1820
1821 case rx_8025:
1822 err = regmap_bulk_read(ds1307->regmap,
1823 RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
1824 if (err) {
1825 dev_dbg(ds1307->dev, "read error %d\n", err);
1826 goto exit;
1827 }
1828
1829 /* oscillator off? turn it on, so clock can tick. */
1830 if (!(regs[1] & RX8025_BIT_XST)) {
1831 regs[1] |= RX8025_BIT_XST;
1832 regmap_write(ds1307->regmap,
1833 RX8025_REG_CTRL2 << 4 | 0x08,
1834 regs[1]);
1835 dev_warn(ds1307->dev,
1836 "oscillator stop detected - SET TIME!\n");
1837 }
1838
1839 if (regs[1] & RX8025_BIT_PON) {
1840 regs[1] &= ~RX8025_BIT_PON;
1841 regmap_write(ds1307->regmap,
1842 RX8025_REG_CTRL2 << 4 | 0x08,
1843 regs[1]);
1844 dev_warn(ds1307->dev, "power-on detected\n");
1845 }
1846
1847 if (regs[1] & RX8025_BIT_VDET) {
1848 regs[1] &= ~RX8025_BIT_VDET;
1849 regmap_write(ds1307->regmap,
1850 RX8025_REG_CTRL2 << 4 | 0x08,
1851 regs[1]);
1852 dev_warn(ds1307->dev, "voltage drop detected\n");
1853 }
1854
1855 /* make sure we are running in 24hour mode */
1856 if (!(regs[0] & RX8025_BIT_2412)) {
1857 u8 hour;
1858
1859 /* switch to 24 hour mode */
1860 regmap_write(ds1307->regmap,
1861 RX8025_REG_CTRL1 << 4 | 0x08,
1862 regs[0] | RX8025_BIT_2412);
1863
1864 err = regmap_bulk_read(ds1307->regmap,
1865 RX8025_REG_CTRL1 << 4 | 0x08,
1866 regs, 2);
1867 if (err) {
1868 dev_dbg(ds1307->dev, "read error %d\n", err);
1869 goto exit;
1870 }
1871
1872 /* correct hour */
1873 hour = bcd2bin(regs[DS1307_REG_HOUR]);
1874 if (hour == 12)
1875 hour = 0;
1876 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1877 hour += 12;
1878
1879 regmap_write(ds1307->regmap,
1880 DS1307_REG_HOUR << 4 | 0x08, hour);
1881 }
1882 break;
1883 case ds_1388:
1884 err = regmap_read(ds1307->regmap, DS1388_REG_CONTROL, &tmp);
1885 if (err) {
1886 dev_dbg(ds1307->dev, "read error %d\n", err);
1887 goto exit;
1888 }
1889
1890 /* oscillator off? turn it on, so clock can tick. */
1891 if (tmp & DS1388_BIT_nEOSC) {
1892 tmp &= ~DS1388_BIT_nEOSC;
1893 regmap_write(ds1307->regmap, DS1388_REG_CONTROL, tmp);
1894 }
1895 break;
1896 default:
1897 break;
1898 }
1899
1900 /* read RTC registers */
1901 err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
1902 sizeof(regs));
1903 if (err) {
1904 dev_dbg(ds1307->dev, "read error %d\n", err);
1905 goto exit;
1906 }
1907
1908 if (ds1307->type == mcp794xx &&
1909 !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1910 regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1911 regs[DS1307_REG_WDAY] |
1912 MCP794XX_BIT_VBATEN);
1913 }
1914
1915 tmp = regs[DS1307_REG_HOUR];
1916 switch (ds1307->type) {
1917 case ds_1340:
1918 case m41t0:
1919 case m41t00:
1920 case m41t11:
1921 /*
1922 * NOTE: ignores century bits; fix before deploying
1923 * systems that will run through year 2100.
1924 */
1925 break;
1926 case rx_8025:
1927 break;
1928 default:
1929 if (!(tmp & DS1307_BIT_12HR))
1930 break;
1931
1932 /*
1933 * Be sure we're in 24 hour mode. Multi-master systems
1934 * take note...
1935 */
1936 tmp = bcd2bin(tmp & 0x1f);
1937 if (tmp == 12)
1938 tmp = 0;
1939 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1940 tmp += 12;
1941 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
1942 bin2bcd(tmp));
1943 }
1944
1945 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
1946 if (IS_ERR(ds1307->rtc))
1947 return PTR_ERR(ds1307->rtc);
1948
1949 if (want_irq || ds1307_can_wakeup_device)
1950 device_set_wakeup_capable(ds1307->dev, true);
1951 else
1952 clear_bit(RTC_FEATURE_ALARM, ds1307->rtc->features);
1953
1954 if (ds1307_can_wakeup_device && !want_irq) {
1955 dev_info(ds1307->dev,
1956 "'wakeup-source' is set, request for an IRQ is disabled!\n");
1957 /* We cannot support UIE mode if we do not have an IRQ line */
1958 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, ds1307->rtc->features);
1959 }
1960
1961 if (want_irq) {
1962 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
1963 chip->irq_handler ?: ds1307_irq,
1964 IRQF_SHARED | IRQF_ONESHOT,
1965 ds1307->name, ds1307);
1966 if (err) {
1967 client->irq = 0;
1968 device_set_wakeup_capable(ds1307->dev, false);
1969 clear_bit(RTC_FEATURE_ALARM, ds1307->rtc->features);
1970 dev_err(ds1307->dev, "unable to request IRQ!\n");
1971 } else {
1972 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
1973 }
1974 }
1975
1976 ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
1977 err = ds1307_add_frequency_test(ds1307);
1978 if (err)
1979 return err;
1980
1981 err = devm_rtc_register_device(ds1307->rtc);
1982 if (err)
1983 return err;
1984
1985 if (chip->nvram_size) {
1986 struct nvmem_config nvmem_cfg = {
1987 .name = "ds1307_nvram",
1988 .word_size = 1,
1989 .stride = 1,
1990 .size = chip->nvram_size,
1991 .reg_read = ds1307_nvram_read,
1992 .reg_write = ds1307_nvram_write,
1993 .priv = ds1307,
1994 };
1995
1996 devm_rtc_nvmem_register(ds1307->rtc, &nvmem_cfg);
1997 }
1998
1999 ds1307_hwmon_register(ds1307);
2000 ds1307_clks_register(ds1307);
2001 ds1307_wdt_register(ds1307);
2002
2003 return 0;
2004
2005exit:
2006 return err;
2007}
2008
2009static struct i2c_driver ds1307_driver = {
2010 .driver = {
2011 .name = "rtc-ds1307",
2012 .of_match_table = ds1307_of_match,
2013 },
2014 .probe = ds1307_probe,
2015 .id_table = ds1307_id,
2016};
2017
2018module_i2c_driver(ds1307_driver);
2019
2020MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
2021MODULE_LICENSE("GPL");