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1/*
2 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
3 *
4 * Copyright (C) 2005 James Chapman (ds1337 core)
5 * Copyright (C) 2006 David Brownell
6 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/slab.h>
16#include <linux/i2c.h>
17#include <linux/string.h>
18#include <linux/rtc.h>
19#include <linux/bcd.h>
20
21
22
23/* We can't determine type by probing, but if we expect pre-Linux code
24 * to have set the chip up as a clock (turning on the oscillator and
25 * setting the date and time), Linux can ignore the non-clock features.
26 * That's a natural job for a factory or repair bench.
27 */
28enum ds_type {
29 ds_1307,
30 ds_1337,
31 ds_1338,
32 ds_1339,
33 ds_1340,
34 ds_1388,
35 ds_3231,
36 m41t00,
37 rx_8025,
38 // rs5c372 too? different address...
39};
40
41
42/* RTC registers don't differ much, except for the century flag */
43#define DS1307_REG_SECS 0x00 /* 00-59 */
44# define DS1307_BIT_CH 0x80
45# define DS1340_BIT_nEOSC 0x80
46#define DS1307_REG_MIN 0x01 /* 00-59 */
47#define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
48# define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
49# define DS1307_BIT_PM 0x20 /* in REG_HOUR */
50# define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
51# define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
52#define DS1307_REG_WDAY 0x03 /* 01-07 */
53#define DS1307_REG_MDAY 0x04 /* 01-31 */
54#define DS1307_REG_MONTH 0x05 /* 01-12 */
55# define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
56#define DS1307_REG_YEAR 0x06 /* 00-99 */
57
58/* Other registers (control, status, alarms, trickle charge, NVRAM, etc)
59 * start at 7, and they differ a LOT. Only control and status matter for
60 * basic RTC date and time functionality; be careful using them.
61 */
62#define DS1307_REG_CONTROL 0x07 /* or ds1338 */
63# define DS1307_BIT_OUT 0x80
64# define DS1338_BIT_OSF 0x20
65# define DS1307_BIT_SQWE 0x10
66# define DS1307_BIT_RS1 0x02
67# define DS1307_BIT_RS0 0x01
68#define DS1337_REG_CONTROL 0x0e
69# define DS1337_BIT_nEOSC 0x80
70# define DS1339_BIT_BBSQI 0x20
71# define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
72# define DS1337_BIT_RS2 0x10
73# define DS1337_BIT_RS1 0x08
74# define DS1337_BIT_INTCN 0x04
75# define DS1337_BIT_A2IE 0x02
76# define DS1337_BIT_A1IE 0x01
77#define DS1340_REG_CONTROL 0x07
78# define DS1340_BIT_OUT 0x80
79# define DS1340_BIT_FT 0x40
80# define DS1340_BIT_CALIB_SIGN 0x20
81# define DS1340_M_CALIBRATION 0x1f
82#define DS1340_REG_FLAG 0x09
83# define DS1340_BIT_OSF 0x80
84#define DS1337_REG_STATUS 0x0f
85# define DS1337_BIT_OSF 0x80
86# define DS1337_BIT_A2I 0x02
87# define DS1337_BIT_A1I 0x01
88#define DS1339_REG_ALARM1_SECS 0x07
89#define DS1339_REG_TRICKLE 0x10
90
91#define RX8025_REG_CTRL1 0x0e
92# define RX8025_BIT_2412 0x20
93#define RX8025_REG_CTRL2 0x0f
94# define RX8025_BIT_PON 0x10
95# define RX8025_BIT_VDET 0x40
96# define RX8025_BIT_XST 0x20
97
98
99struct ds1307 {
100 u8 offset; /* register's offset */
101 u8 regs[11];
102 enum ds_type type;
103 unsigned long flags;
104#define HAS_NVRAM 0 /* bit 0 == sysfs file active */
105#define HAS_ALARM 1 /* bit 1 == irq claimed */
106 struct i2c_client *client;
107 struct rtc_device *rtc;
108 struct work_struct work;
109 s32 (*read_block_data)(const struct i2c_client *client, u8 command,
110 u8 length, u8 *values);
111 s32 (*write_block_data)(const struct i2c_client *client, u8 command,
112 u8 length, const u8 *values);
113};
114
115struct chip_desc {
116 unsigned nvram56:1;
117 unsigned alarm:1;
118};
119
120static const struct chip_desc chips[] = {
121[ds_1307] = {
122 .nvram56 = 1,
123},
124[ds_1337] = {
125 .alarm = 1,
126},
127[ds_1338] = {
128 .nvram56 = 1,
129},
130[ds_1339] = {
131 .alarm = 1,
132},
133[ds_1340] = {
134},
135[ds_3231] = {
136 .alarm = 1,
137},
138[m41t00] = {
139},
140[rx_8025] = {
141}, };
142
143static const struct i2c_device_id ds1307_id[] = {
144 { "ds1307", ds_1307 },
145 { "ds1337", ds_1337 },
146 { "ds1338", ds_1338 },
147 { "ds1339", ds_1339 },
148 { "ds1388", ds_1388 },
149 { "ds1340", ds_1340 },
150 { "ds3231", ds_3231 },
151 { "m41t00", m41t00 },
152 { "pt7c4338", ds_1307 },
153 { "rx8025", rx_8025 },
154 { }
155};
156MODULE_DEVICE_TABLE(i2c, ds1307_id);
157
158/*----------------------------------------------------------------------*/
159
160#define BLOCK_DATA_MAX_TRIES 10
161
162static s32 ds1307_read_block_data_once(const struct i2c_client *client,
163 u8 command, u8 length, u8 *values)
164{
165 s32 i, data;
166
167 for (i = 0; i < length; i++) {
168 data = i2c_smbus_read_byte_data(client, command + i);
169 if (data < 0)
170 return data;
171 values[i] = data;
172 }
173 return i;
174}
175
176static s32 ds1307_read_block_data(const struct i2c_client *client, u8 command,
177 u8 length, u8 *values)
178{
179 u8 oldvalues[I2C_SMBUS_BLOCK_MAX];
180 s32 ret;
181 int tries = 0;
182
183 dev_dbg(&client->dev, "ds1307_read_block_data (length=%d)\n", length);
184 ret = ds1307_read_block_data_once(client, command, length, values);
185 if (ret < 0)
186 return ret;
187 do {
188 if (++tries > BLOCK_DATA_MAX_TRIES) {
189 dev_err(&client->dev,
190 "ds1307_read_block_data failed\n");
191 return -EIO;
192 }
193 memcpy(oldvalues, values, length);
194 ret = ds1307_read_block_data_once(client, command, length,
195 values);
196 if (ret < 0)
197 return ret;
198 } while (memcmp(oldvalues, values, length));
199 return length;
200}
201
202static s32 ds1307_write_block_data(const struct i2c_client *client, u8 command,
203 u8 length, const u8 *values)
204{
205 u8 currvalues[I2C_SMBUS_BLOCK_MAX];
206 int tries = 0;
207
208 dev_dbg(&client->dev, "ds1307_write_block_data (length=%d)\n", length);
209 do {
210 s32 i, ret;
211
212 if (++tries > BLOCK_DATA_MAX_TRIES) {
213 dev_err(&client->dev,
214 "ds1307_write_block_data failed\n");
215 return -EIO;
216 }
217 for (i = 0; i < length; i++) {
218 ret = i2c_smbus_write_byte_data(client, command + i,
219 values[i]);
220 if (ret < 0)
221 return ret;
222 }
223 ret = ds1307_read_block_data_once(client, command, length,
224 currvalues);
225 if (ret < 0)
226 return ret;
227 } while (memcmp(currvalues, values, length));
228 return length;
229}
230
231/*----------------------------------------------------------------------*/
232
233/*
234 * The IRQ logic includes a "real" handler running in IRQ context just
235 * long enough to schedule this workqueue entry. We need a task context
236 * to talk to the RTC, since I2C I/O calls require that; and disable the
237 * IRQ until we clear its status on the chip, so that this handler can
238 * work with any type of triggering (not just falling edge).
239 *
240 * The ds1337 and ds1339 both have two alarms, but we only use the first
241 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
242 * signal; ds1339 chips have only one alarm signal.
243 */
244static void ds1307_work(struct work_struct *work)
245{
246 struct ds1307 *ds1307;
247 struct i2c_client *client;
248 struct mutex *lock;
249 int stat, control;
250
251 ds1307 = container_of(work, struct ds1307, work);
252 client = ds1307->client;
253 lock = &ds1307->rtc->ops_lock;
254
255 mutex_lock(lock);
256 stat = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS);
257 if (stat < 0)
258 goto out;
259
260 if (stat & DS1337_BIT_A1I) {
261 stat &= ~DS1337_BIT_A1I;
262 i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, stat);
263
264 control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
265 if (control < 0)
266 goto out;
267
268 control &= ~DS1337_BIT_A1IE;
269 i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control);
270
271 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
272 }
273
274out:
275 if (test_bit(HAS_ALARM, &ds1307->flags))
276 enable_irq(client->irq);
277 mutex_unlock(lock);
278}
279
280static irqreturn_t ds1307_irq(int irq, void *dev_id)
281{
282 struct i2c_client *client = dev_id;
283 struct ds1307 *ds1307 = i2c_get_clientdata(client);
284
285 disable_irq_nosync(irq);
286 schedule_work(&ds1307->work);
287 return IRQ_HANDLED;
288}
289
290/*----------------------------------------------------------------------*/
291
292static int ds1307_get_time(struct device *dev, struct rtc_time *t)
293{
294 struct ds1307 *ds1307 = dev_get_drvdata(dev);
295 int tmp;
296
297 /* read the RTC date and time registers all at once */
298 tmp = ds1307->read_block_data(ds1307->client,
299 ds1307->offset, 7, ds1307->regs);
300 if (tmp != 7) {
301 dev_err(dev, "%s error %d\n", "read", tmp);
302 return -EIO;
303 }
304
305 dev_dbg(dev, "%s: %02x %02x %02x %02x %02x %02x %02x\n",
306 "read",
307 ds1307->regs[0], ds1307->regs[1],
308 ds1307->regs[2], ds1307->regs[3],
309 ds1307->regs[4], ds1307->regs[5],
310 ds1307->regs[6]);
311
312 t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f);
313 t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f);
314 tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f;
315 t->tm_hour = bcd2bin(tmp);
316 t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1;
317 t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f);
318 tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f;
319 t->tm_mon = bcd2bin(tmp) - 1;
320
321 /* assume 20YY not 19YY, and ignore DS1337_BIT_CENTURY */
322 t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100;
323
324 dev_dbg(dev, "%s secs=%d, mins=%d, "
325 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
326 "read", t->tm_sec, t->tm_min,
327 t->tm_hour, t->tm_mday,
328 t->tm_mon, t->tm_year, t->tm_wday);
329
330 /* initial clock setting can be undefined */
331 return rtc_valid_tm(t);
332}
333
334static int ds1307_set_time(struct device *dev, struct rtc_time *t)
335{
336 struct ds1307 *ds1307 = dev_get_drvdata(dev);
337 int result;
338 int tmp;
339 u8 *buf = ds1307->regs;
340
341 dev_dbg(dev, "%s secs=%d, mins=%d, "
342 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
343 "write", t->tm_sec, t->tm_min,
344 t->tm_hour, t->tm_mday,
345 t->tm_mon, t->tm_year, t->tm_wday);
346
347 buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
348 buf[DS1307_REG_MIN] = bin2bcd(t->tm_min);
349 buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
350 buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
351 buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
352 buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
353
354 /* assume 20YY not 19YY */
355 tmp = t->tm_year - 100;
356 buf[DS1307_REG_YEAR] = bin2bcd(tmp);
357
358 switch (ds1307->type) {
359 case ds_1337:
360 case ds_1339:
361 case ds_3231:
362 buf[DS1307_REG_MONTH] |= DS1337_BIT_CENTURY;
363 break;
364 case ds_1340:
365 buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY_EN
366 | DS1340_BIT_CENTURY;
367 break;
368 default:
369 break;
370 }
371
372 dev_dbg(dev, "%s: %02x %02x %02x %02x %02x %02x %02x\n",
373 "write", buf[0], buf[1], buf[2], buf[3],
374 buf[4], buf[5], buf[6]);
375
376 result = ds1307->write_block_data(ds1307->client,
377 ds1307->offset, 7, buf);
378 if (result < 0) {
379 dev_err(dev, "%s error %d\n", "write", result);
380 return result;
381 }
382 return 0;
383}
384
385static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
386{
387 struct i2c_client *client = to_i2c_client(dev);
388 struct ds1307 *ds1307 = i2c_get_clientdata(client);
389 int ret;
390
391 if (!test_bit(HAS_ALARM, &ds1307->flags))
392 return -EINVAL;
393
394 /* read all ALARM1, ALARM2, and status registers at once */
395 ret = ds1307->read_block_data(client,
396 DS1339_REG_ALARM1_SECS, 9, ds1307->regs);
397 if (ret != 9) {
398 dev_err(dev, "%s error %d\n", "alarm read", ret);
399 return -EIO;
400 }
401
402 dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
403 "alarm read",
404 ds1307->regs[0], ds1307->regs[1],
405 ds1307->regs[2], ds1307->regs[3],
406 ds1307->regs[4], ds1307->regs[5],
407 ds1307->regs[6], ds1307->regs[7],
408 ds1307->regs[8]);
409
410 /* report alarm time (ALARM1); assume 24 hour and day-of-month modes,
411 * and that all four fields are checked matches
412 */
413 t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f);
414 t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f);
415 t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f);
416 t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f);
417 t->time.tm_mon = -1;
418 t->time.tm_year = -1;
419 t->time.tm_wday = -1;
420 t->time.tm_yday = -1;
421 t->time.tm_isdst = -1;
422
423 /* ... and status */
424 t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE);
425 t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I);
426
427 dev_dbg(dev, "%s secs=%d, mins=%d, "
428 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
429 "alarm read", t->time.tm_sec, t->time.tm_min,
430 t->time.tm_hour, t->time.tm_mday,
431 t->enabled, t->pending);
432
433 return 0;
434}
435
436static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
437{
438 struct i2c_client *client = to_i2c_client(dev);
439 struct ds1307 *ds1307 = i2c_get_clientdata(client);
440 unsigned char *buf = ds1307->regs;
441 u8 control, status;
442 int ret;
443
444 if (!test_bit(HAS_ALARM, &ds1307->flags))
445 return -EINVAL;
446
447 dev_dbg(dev, "%s secs=%d, mins=%d, "
448 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
449 "alarm set", t->time.tm_sec, t->time.tm_min,
450 t->time.tm_hour, t->time.tm_mday,
451 t->enabled, t->pending);
452
453 /* read current status of both alarms and the chip */
454 ret = ds1307->read_block_data(client,
455 DS1339_REG_ALARM1_SECS, 9, buf);
456 if (ret != 9) {
457 dev_err(dev, "%s error %d\n", "alarm write", ret);
458 return -EIO;
459 }
460 control = ds1307->regs[7];
461 status = ds1307->regs[8];
462
463 dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
464 "alarm set (old status)",
465 ds1307->regs[0], ds1307->regs[1],
466 ds1307->regs[2], ds1307->regs[3],
467 ds1307->regs[4], ds1307->regs[5],
468 ds1307->regs[6], control, status);
469
470 /* set ALARM1, using 24 hour and day-of-month modes */
471 buf[0] = bin2bcd(t->time.tm_sec);
472 buf[1] = bin2bcd(t->time.tm_min);
473 buf[2] = bin2bcd(t->time.tm_hour);
474 buf[3] = bin2bcd(t->time.tm_mday);
475
476 /* set ALARM2 to non-garbage */
477 buf[4] = 0;
478 buf[5] = 0;
479 buf[6] = 0;
480
481 /* optionally enable ALARM1 */
482 buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
483 if (t->enabled) {
484 dev_dbg(dev, "alarm IRQ armed\n");
485 buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
486 }
487 buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
488
489 ret = ds1307->write_block_data(client,
490 DS1339_REG_ALARM1_SECS, 9, buf);
491 if (ret < 0) {
492 dev_err(dev, "can't set alarm time\n");
493 return ret;
494 }
495
496 return 0;
497}
498
499static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
500{
501 struct i2c_client *client = to_i2c_client(dev);
502 struct ds1307 *ds1307 = i2c_get_clientdata(client);
503 int ret;
504
505 if (!test_bit(HAS_ALARM, &ds1307->flags))
506 return -ENOTTY;
507
508 ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
509 if (ret < 0)
510 return ret;
511
512 if (enabled)
513 ret |= DS1337_BIT_A1IE;
514 else
515 ret &= ~DS1337_BIT_A1IE;
516
517 ret = i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, ret);
518 if (ret < 0)
519 return ret;
520
521 return 0;
522}
523
524static const struct rtc_class_ops ds13xx_rtc_ops = {
525 .read_time = ds1307_get_time,
526 .set_time = ds1307_set_time,
527 .read_alarm = ds1337_read_alarm,
528 .set_alarm = ds1337_set_alarm,
529 .alarm_irq_enable = ds1307_alarm_irq_enable,
530};
531
532/*----------------------------------------------------------------------*/
533
534#define NVRAM_SIZE 56
535
536static ssize_t
537ds1307_nvram_read(struct file *filp, struct kobject *kobj,
538 struct bin_attribute *attr,
539 char *buf, loff_t off, size_t count)
540{
541 struct i2c_client *client;
542 struct ds1307 *ds1307;
543 int result;
544
545 client = kobj_to_i2c_client(kobj);
546 ds1307 = i2c_get_clientdata(client);
547
548 if (unlikely(off >= NVRAM_SIZE))
549 return 0;
550 if ((off + count) > NVRAM_SIZE)
551 count = NVRAM_SIZE - off;
552 if (unlikely(!count))
553 return count;
554
555 result = ds1307->read_block_data(client, 8 + off, count, buf);
556 if (result < 0)
557 dev_err(&client->dev, "%s error %d\n", "nvram read", result);
558 return result;
559}
560
561static ssize_t
562ds1307_nvram_write(struct file *filp, struct kobject *kobj,
563 struct bin_attribute *attr,
564 char *buf, loff_t off, size_t count)
565{
566 struct i2c_client *client;
567 struct ds1307 *ds1307;
568 int result;
569
570 client = kobj_to_i2c_client(kobj);
571 ds1307 = i2c_get_clientdata(client);
572
573 if (unlikely(off >= NVRAM_SIZE))
574 return -EFBIG;
575 if ((off + count) > NVRAM_SIZE)
576 count = NVRAM_SIZE - off;
577 if (unlikely(!count))
578 return count;
579
580 result = ds1307->write_block_data(client, 8 + off, count, buf);
581 if (result < 0) {
582 dev_err(&client->dev, "%s error %d\n", "nvram write", result);
583 return result;
584 }
585 return count;
586}
587
588static struct bin_attribute nvram = {
589 .attr = {
590 .name = "nvram",
591 .mode = S_IRUGO | S_IWUSR,
592 },
593
594 .read = ds1307_nvram_read,
595 .write = ds1307_nvram_write,
596 .size = NVRAM_SIZE,
597};
598
599/*----------------------------------------------------------------------*/
600
601static struct i2c_driver ds1307_driver;
602
603static int __devinit ds1307_probe(struct i2c_client *client,
604 const struct i2c_device_id *id)
605{
606 struct ds1307 *ds1307;
607 int err = -ENODEV;
608 int tmp;
609 const struct chip_desc *chip = &chips[id->driver_data];
610 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
611 int want_irq = false;
612 unsigned char *buf;
613 static const int bbsqi_bitpos[] = {
614 [ds_1337] = 0,
615 [ds_1339] = DS1339_BIT_BBSQI,
616 [ds_3231] = DS3231_BIT_BBSQW,
617 };
618
619 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)
620 && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK))
621 return -EIO;
622
623 if (!(ds1307 = kzalloc(sizeof(struct ds1307), GFP_KERNEL)))
624 return -ENOMEM;
625
626 i2c_set_clientdata(client, ds1307);
627
628 ds1307->client = client;
629 ds1307->type = id->driver_data;
630 ds1307->offset = 0;
631
632 buf = ds1307->regs;
633 if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) {
634 ds1307->read_block_data = i2c_smbus_read_i2c_block_data;
635 ds1307->write_block_data = i2c_smbus_write_i2c_block_data;
636 } else {
637 ds1307->read_block_data = ds1307_read_block_data;
638 ds1307->write_block_data = ds1307_write_block_data;
639 }
640
641 switch (ds1307->type) {
642 case ds_1337:
643 case ds_1339:
644 case ds_3231:
645 /* has IRQ? */
646 if (ds1307->client->irq > 0 && chip->alarm) {
647 INIT_WORK(&ds1307->work, ds1307_work);
648 want_irq = true;
649 }
650 /* get registers that the "rtc" read below won't read... */
651 tmp = ds1307->read_block_data(ds1307->client,
652 DS1337_REG_CONTROL, 2, buf);
653 if (tmp != 2) {
654 pr_debug("read error %d\n", tmp);
655 err = -EIO;
656 goto exit_free;
657 }
658
659 /* oscillator off? turn it on, so clock can tick. */
660 if (ds1307->regs[0] & DS1337_BIT_nEOSC)
661 ds1307->regs[0] &= ~DS1337_BIT_nEOSC;
662
663 /* Using IRQ? Disable the square wave and both alarms.
664 * For some variants, be sure alarms can trigger when we're
665 * running on Vbackup (BBSQI/BBSQW)
666 */
667 if (want_irq) {
668 ds1307->regs[0] |= DS1337_BIT_INTCN
669 | bbsqi_bitpos[ds1307->type];
670 ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
671 }
672
673 i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL,
674 ds1307->regs[0]);
675
676 /* oscillator fault? clear flag, and warn */
677 if (ds1307->regs[1] & DS1337_BIT_OSF) {
678 i2c_smbus_write_byte_data(client, DS1337_REG_STATUS,
679 ds1307->regs[1] & ~DS1337_BIT_OSF);
680 dev_warn(&client->dev, "SET TIME!\n");
681 }
682 break;
683
684 case rx_8025:
685 tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
686 RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
687 if (tmp != 2) {
688 pr_debug("read error %d\n", tmp);
689 err = -EIO;
690 goto exit_free;
691 }
692
693 /* oscillator off? turn it on, so clock can tick. */
694 if (!(ds1307->regs[1] & RX8025_BIT_XST)) {
695 ds1307->regs[1] |= RX8025_BIT_XST;
696 i2c_smbus_write_byte_data(client,
697 RX8025_REG_CTRL2 << 4 | 0x08,
698 ds1307->regs[1]);
699 dev_warn(&client->dev,
700 "oscillator stop detected - SET TIME!\n");
701 }
702
703 if (ds1307->regs[1] & RX8025_BIT_PON) {
704 ds1307->regs[1] &= ~RX8025_BIT_PON;
705 i2c_smbus_write_byte_data(client,
706 RX8025_REG_CTRL2 << 4 | 0x08,
707 ds1307->regs[1]);
708 dev_warn(&client->dev, "power-on detected\n");
709 }
710
711 if (ds1307->regs[1] & RX8025_BIT_VDET) {
712 ds1307->regs[1] &= ~RX8025_BIT_VDET;
713 i2c_smbus_write_byte_data(client,
714 RX8025_REG_CTRL2 << 4 | 0x08,
715 ds1307->regs[1]);
716 dev_warn(&client->dev, "voltage drop detected\n");
717 }
718
719 /* make sure we are running in 24hour mode */
720 if (!(ds1307->regs[0] & RX8025_BIT_2412)) {
721 u8 hour;
722
723 /* switch to 24 hour mode */
724 i2c_smbus_write_byte_data(client,
725 RX8025_REG_CTRL1 << 4 | 0x08,
726 ds1307->regs[0] |
727 RX8025_BIT_2412);
728
729 tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
730 RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
731 if (tmp != 2) {
732 pr_debug("read error %d\n", tmp);
733 err = -EIO;
734 goto exit_free;
735 }
736
737 /* correct hour */
738 hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]);
739 if (hour == 12)
740 hour = 0;
741 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
742 hour += 12;
743
744 i2c_smbus_write_byte_data(client,
745 DS1307_REG_HOUR << 4 | 0x08,
746 hour);
747 }
748 break;
749 case ds_1388:
750 ds1307->offset = 1; /* Seconds starts at 1 */
751 break;
752 default:
753 break;
754 }
755
756read_rtc:
757 /* read RTC registers */
758 tmp = ds1307->read_block_data(ds1307->client, ds1307->offset, 8, buf);
759 if (tmp != 8) {
760 pr_debug("read error %d\n", tmp);
761 err = -EIO;
762 goto exit_free;
763 }
764
765 /* minimal sanity checking; some chips (like DS1340) don't
766 * specify the extra bits as must-be-zero, but there are
767 * still a few values that are clearly out-of-range.
768 */
769 tmp = ds1307->regs[DS1307_REG_SECS];
770 switch (ds1307->type) {
771 case ds_1307:
772 case m41t00:
773 /* clock halted? turn it on, so clock can tick. */
774 if (tmp & DS1307_BIT_CH) {
775 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
776 dev_warn(&client->dev, "SET TIME!\n");
777 goto read_rtc;
778 }
779 break;
780 case ds_1338:
781 /* clock halted? turn it on, so clock can tick. */
782 if (tmp & DS1307_BIT_CH)
783 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
784
785 /* oscillator fault? clear flag, and warn */
786 if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
787 i2c_smbus_write_byte_data(client, DS1307_REG_CONTROL,
788 ds1307->regs[DS1307_REG_CONTROL]
789 & ~DS1338_BIT_OSF);
790 dev_warn(&client->dev, "SET TIME!\n");
791 goto read_rtc;
792 }
793 break;
794 case ds_1340:
795 /* clock halted? turn it on, so clock can tick. */
796 if (tmp & DS1340_BIT_nEOSC)
797 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
798
799 tmp = i2c_smbus_read_byte_data(client, DS1340_REG_FLAG);
800 if (tmp < 0) {
801 pr_debug("read error %d\n", tmp);
802 err = -EIO;
803 goto exit_free;
804 }
805
806 /* oscillator fault? clear flag, and warn */
807 if (tmp & DS1340_BIT_OSF) {
808 i2c_smbus_write_byte_data(client, DS1340_REG_FLAG, 0);
809 dev_warn(&client->dev, "SET TIME!\n");
810 }
811 break;
812 case rx_8025:
813 case ds_1337:
814 case ds_1339:
815 case ds_1388:
816 case ds_3231:
817 break;
818 }
819
820 tmp = ds1307->regs[DS1307_REG_HOUR];
821 switch (ds1307->type) {
822 case ds_1340:
823 case m41t00:
824 /* NOTE: ignores century bits; fix before deploying
825 * systems that will run through year 2100.
826 */
827 break;
828 case rx_8025:
829 break;
830 default:
831 if (!(tmp & DS1307_BIT_12HR))
832 break;
833
834 /* Be sure we're in 24 hour mode. Multi-master systems
835 * take note...
836 */
837 tmp = bcd2bin(tmp & 0x1f);
838 if (tmp == 12)
839 tmp = 0;
840 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
841 tmp += 12;
842 i2c_smbus_write_byte_data(client,
843 ds1307->offset + DS1307_REG_HOUR,
844 bin2bcd(tmp));
845 }
846
847 ds1307->rtc = rtc_device_register(client->name, &client->dev,
848 &ds13xx_rtc_ops, THIS_MODULE);
849 if (IS_ERR(ds1307->rtc)) {
850 err = PTR_ERR(ds1307->rtc);
851 dev_err(&client->dev,
852 "unable to register the class device\n");
853 goto exit_free;
854 }
855
856 if (want_irq) {
857 err = request_irq(client->irq, ds1307_irq, IRQF_SHARED,
858 ds1307->rtc->name, client);
859 if (err) {
860 dev_err(&client->dev,
861 "unable to request IRQ!\n");
862 goto exit_irq;
863 }
864
865 device_set_wakeup_capable(&client->dev, 1);
866 set_bit(HAS_ALARM, &ds1307->flags);
867 dev_dbg(&client->dev, "got IRQ %d\n", client->irq);
868 }
869
870 if (chip->nvram56) {
871 err = sysfs_create_bin_file(&client->dev.kobj, &nvram);
872 if (err == 0) {
873 set_bit(HAS_NVRAM, &ds1307->flags);
874 dev_info(&client->dev, "56 bytes nvram\n");
875 }
876 }
877
878 return 0;
879
880exit_irq:
881 rtc_device_unregister(ds1307->rtc);
882exit_free:
883 kfree(ds1307);
884 return err;
885}
886
887static int __devexit ds1307_remove(struct i2c_client *client)
888{
889 struct ds1307 *ds1307 = i2c_get_clientdata(client);
890
891 if (test_and_clear_bit(HAS_ALARM, &ds1307->flags)) {
892 free_irq(client->irq, client);
893 cancel_work_sync(&ds1307->work);
894 }
895
896 if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags))
897 sysfs_remove_bin_file(&client->dev.kobj, &nvram);
898
899 rtc_device_unregister(ds1307->rtc);
900 kfree(ds1307);
901 return 0;
902}
903
904static struct i2c_driver ds1307_driver = {
905 .driver = {
906 .name = "rtc-ds1307",
907 .owner = THIS_MODULE,
908 },
909 .probe = ds1307_probe,
910 .remove = __devexit_p(ds1307_remove),
911 .id_table = ds1307_id,
912};
913
914static int __init ds1307_init(void)
915{
916 return i2c_add_driver(&ds1307_driver);
917}
918module_init(ds1307_init);
919
920static void __exit ds1307_exit(void)
921{
922 i2c_del_driver(&ds1307_driver);
923}
924module_exit(ds1307_exit);
925
926MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
927MODULE_LICENSE("GPL");
1/*
2 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
3 *
4 * Copyright (C) 2005 James Chapman (ds1337 core)
5 * Copyright (C) 2006 David Brownell
6 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
7 * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/acpi.h>
15#include <linux/bcd.h>
16#include <linux/i2c.h>
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/of_device.h>
20#include <linux/rtc/ds1307.h>
21#include <linux/rtc.h>
22#include <linux/slab.h>
23#include <linux/string.h>
24#include <linux/hwmon.h>
25#include <linux/hwmon-sysfs.h>
26#include <linux/clk-provider.h>
27#include <linux/regmap.h>
28
29/*
30 * We can't determine type by probing, but if we expect pre-Linux code
31 * to have set the chip up as a clock (turning on the oscillator and
32 * setting the date and time), Linux can ignore the non-clock features.
33 * That's a natural job for a factory or repair bench.
34 */
35enum ds_type {
36 ds_1307,
37 ds_1308,
38 ds_1337,
39 ds_1338,
40 ds_1339,
41 ds_1340,
42 ds_1341,
43 ds_1388,
44 ds_3231,
45 m41t0,
46 m41t00,
47 mcp794xx,
48 rx_8025,
49 rx_8130,
50 last_ds_type /* always last */
51 /* rs5c372 too? different address... */
52};
53
54/* RTC registers don't differ much, except for the century flag */
55#define DS1307_REG_SECS 0x00 /* 00-59 */
56# define DS1307_BIT_CH 0x80
57# define DS1340_BIT_nEOSC 0x80
58# define MCP794XX_BIT_ST 0x80
59#define DS1307_REG_MIN 0x01 /* 00-59 */
60# define M41T0_BIT_OF 0x80
61#define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
62# define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
63# define DS1307_BIT_PM 0x20 /* in REG_HOUR */
64# define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
65# define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
66#define DS1307_REG_WDAY 0x03 /* 01-07 */
67# define MCP794XX_BIT_VBATEN 0x08
68#define DS1307_REG_MDAY 0x04 /* 01-31 */
69#define DS1307_REG_MONTH 0x05 /* 01-12 */
70# define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
71#define DS1307_REG_YEAR 0x06 /* 00-99 */
72
73/*
74 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
75 * start at 7, and they differ a LOT. Only control and status matter for
76 * basic RTC date and time functionality; be careful using them.
77 */
78#define DS1307_REG_CONTROL 0x07 /* or ds1338 */
79# define DS1307_BIT_OUT 0x80
80# define DS1338_BIT_OSF 0x20
81# define DS1307_BIT_SQWE 0x10
82# define DS1307_BIT_RS1 0x02
83# define DS1307_BIT_RS0 0x01
84#define DS1337_REG_CONTROL 0x0e
85# define DS1337_BIT_nEOSC 0x80
86# define DS1339_BIT_BBSQI 0x20
87# define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
88# define DS1337_BIT_RS2 0x10
89# define DS1337_BIT_RS1 0x08
90# define DS1337_BIT_INTCN 0x04
91# define DS1337_BIT_A2IE 0x02
92# define DS1337_BIT_A1IE 0x01
93#define DS1340_REG_CONTROL 0x07
94# define DS1340_BIT_OUT 0x80
95# define DS1340_BIT_FT 0x40
96# define DS1340_BIT_CALIB_SIGN 0x20
97# define DS1340_M_CALIBRATION 0x1f
98#define DS1340_REG_FLAG 0x09
99# define DS1340_BIT_OSF 0x80
100#define DS1337_REG_STATUS 0x0f
101# define DS1337_BIT_OSF 0x80
102# define DS3231_BIT_EN32KHZ 0x08
103# define DS1337_BIT_A2I 0x02
104# define DS1337_BIT_A1I 0x01
105#define DS1339_REG_ALARM1_SECS 0x07
106
107#define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
108
109#define RX8025_REG_CTRL1 0x0e
110# define RX8025_BIT_2412 0x20
111#define RX8025_REG_CTRL2 0x0f
112# define RX8025_BIT_PON 0x10
113# define RX8025_BIT_VDET 0x40
114# define RX8025_BIT_XST 0x20
115
116struct ds1307 {
117 enum ds_type type;
118 unsigned long flags;
119#define HAS_NVRAM 0 /* bit 0 == sysfs file active */
120#define HAS_ALARM 1 /* bit 1 == irq claimed */
121 struct device *dev;
122 struct regmap *regmap;
123 const char *name;
124 struct rtc_device *rtc;
125#ifdef CONFIG_COMMON_CLK
126 struct clk_hw clks[2];
127#endif
128};
129
130struct chip_desc {
131 unsigned alarm:1;
132 u16 nvram_offset;
133 u16 nvram_size;
134 u8 offset; /* register's offset */
135 u8 century_reg;
136 u8 century_enable_bit;
137 u8 century_bit;
138 u8 bbsqi_bit;
139 irq_handler_t irq_handler;
140 const struct rtc_class_ops *rtc_ops;
141 u16 trickle_charger_reg;
142 u8 (*do_trickle_setup)(struct ds1307 *, u32,
143 bool);
144};
145
146static int ds1307_get_time(struct device *dev, struct rtc_time *t);
147static int ds1307_set_time(struct device *dev, struct rtc_time *t);
148static u8 do_trickle_setup_ds1339(struct ds1307 *, u32 ohms, bool diode);
149static irqreturn_t rx8130_irq(int irq, void *dev_id);
150static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t);
151static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t);
152static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled);
153static irqreturn_t mcp794xx_irq(int irq, void *dev_id);
154static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t);
155static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t);
156static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled);
157
158static const struct rtc_class_ops rx8130_rtc_ops = {
159 .read_time = ds1307_get_time,
160 .set_time = ds1307_set_time,
161 .read_alarm = rx8130_read_alarm,
162 .set_alarm = rx8130_set_alarm,
163 .alarm_irq_enable = rx8130_alarm_irq_enable,
164};
165
166static const struct rtc_class_ops mcp794xx_rtc_ops = {
167 .read_time = ds1307_get_time,
168 .set_time = ds1307_set_time,
169 .read_alarm = mcp794xx_read_alarm,
170 .set_alarm = mcp794xx_set_alarm,
171 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
172};
173
174static const struct chip_desc chips[last_ds_type] = {
175 [ds_1307] = {
176 .nvram_offset = 8,
177 .nvram_size = 56,
178 },
179 [ds_1308] = {
180 .nvram_offset = 8,
181 .nvram_size = 56,
182 },
183 [ds_1337] = {
184 .alarm = 1,
185 .century_reg = DS1307_REG_MONTH,
186 .century_bit = DS1337_BIT_CENTURY,
187 },
188 [ds_1338] = {
189 .nvram_offset = 8,
190 .nvram_size = 56,
191 },
192 [ds_1339] = {
193 .alarm = 1,
194 .century_reg = DS1307_REG_MONTH,
195 .century_bit = DS1337_BIT_CENTURY,
196 .bbsqi_bit = DS1339_BIT_BBSQI,
197 .trickle_charger_reg = 0x10,
198 .do_trickle_setup = &do_trickle_setup_ds1339,
199 },
200 [ds_1340] = {
201 .century_reg = DS1307_REG_HOUR,
202 .century_enable_bit = DS1340_BIT_CENTURY_EN,
203 .century_bit = DS1340_BIT_CENTURY,
204 .trickle_charger_reg = 0x08,
205 },
206 [ds_1341] = {
207 .century_reg = DS1307_REG_MONTH,
208 .century_bit = DS1337_BIT_CENTURY,
209 },
210 [ds_1388] = {
211 .offset = 1,
212 .trickle_charger_reg = 0x0a,
213 },
214 [ds_3231] = {
215 .alarm = 1,
216 .century_reg = DS1307_REG_MONTH,
217 .century_bit = DS1337_BIT_CENTURY,
218 .bbsqi_bit = DS3231_BIT_BBSQW,
219 },
220 [rx_8130] = {
221 .alarm = 1,
222 /* this is battery backed SRAM */
223 .nvram_offset = 0x20,
224 .nvram_size = 4, /* 32bit (4 word x 8 bit) */
225 .offset = 0x10,
226 .irq_handler = rx8130_irq,
227 .rtc_ops = &rx8130_rtc_ops,
228 },
229 [mcp794xx] = {
230 .alarm = 1,
231 /* this is battery backed SRAM */
232 .nvram_offset = 0x20,
233 .nvram_size = 0x40,
234 .irq_handler = mcp794xx_irq,
235 .rtc_ops = &mcp794xx_rtc_ops,
236 },
237};
238
239static const struct i2c_device_id ds1307_id[] = {
240 { "ds1307", ds_1307 },
241 { "ds1308", ds_1308 },
242 { "ds1337", ds_1337 },
243 { "ds1338", ds_1338 },
244 { "ds1339", ds_1339 },
245 { "ds1388", ds_1388 },
246 { "ds1340", ds_1340 },
247 { "ds1341", ds_1341 },
248 { "ds3231", ds_3231 },
249 { "m41t0", m41t0 },
250 { "m41t00", m41t00 },
251 { "mcp7940x", mcp794xx },
252 { "mcp7941x", mcp794xx },
253 { "pt7c4338", ds_1307 },
254 { "rx8025", rx_8025 },
255 { "isl12057", ds_1337 },
256 { "rx8130", rx_8130 },
257 { }
258};
259MODULE_DEVICE_TABLE(i2c, ds1307_id);
260
261#ifdef CONFIG_OF
262static const struct of_device_id ds1307_of_match[] = {
263 {
264 .compatible = "dallas,ds1307",
265 .data = (void *)ds_1307
266 },
267 {
268 .compatible = "dallas,ds1308",
269 .data = (void *)ds_1308
270 },
271 {
272 .compatible = "dallas,ds1337",
273 .data = (void *)ds_1337
274 },
275 {
276 .compatible = "dallas,ds1338",
277 .data = (void *)ds_1338
278 },
279 {
280 .compatible = "dallas,ds1339",
281 .data = (void *)ds_1339
282 },
283 {
284 .compatible = "dallas,ds1388",
285 .data = (void *)ds_1388
286 },
287 {
288 .compatible = "dallas,ds1340",
289 .data = (void *)ds_1340
290 },
291 {
292 .compatible = "dallas,ds1341",
293 .data = (void *)ds_1341
294 },
295 {
296 .compatible = "maxim,ds3231",
297 .data = (void *)ds_3231
298 },
299 {
300 .compatible = "st,m41t0",
301 .data = (void *)m41t00
302 },
303 {
304 .compatible = "st,m41t00",
305 .data = (void *)m41t00
306 },
307 {
308 .compatible = "microchip,mcp7940x",
309 .data = (void *)mcp794xx
310 },
311 {
312 .compatible = "microchip,mcp7941x",
313 .data = (void *)mcp794xx
314 },
315 {
316 .compatible = "pericom,pt7c4338",
317 .data = (void *)ds_1307
318 },
319 {
320 .compatible = "epson,rx8025",
321 .data = (void *)rx_8025
322 },
323 {
324 .compatible = "isil,isl12057",
325 .data = (void *)ds_1337
326 },
327 {
328 .compatible = "epson,rx8130",
329 .data = (void *)rx_8130
330 },
331 { }
332};
333MODULE_DEVICE_TABLE(of, ds1307_of_match);
334#endif
335
336#ifdef CONFIG_ACPI
337static const struct acpi_device_id ds1307_acpi_ids[] = {
338 { .id = "DS1307", .driver_data = ds_1307 },
339 { .id = "DS1308", .driver_data = ds_1308 },
340 { .id = "DS1337", .driver_data = ds_1337 },
341 { .id = "DS1338", .driver_data = ds_1338 },
342 { .id = "DS1339", .driver_data = ds_1339 },
343 { .id = "DS1388", .driver_data = ds_1388 },
344 { .id = "DS1340", .driver_data = ds_1340 },
345 { .id = "DS1341", .driver_data = ds_1341 },
346 { .id = "DS3231", .driver_data = ds_3231 },
347 { .id = "M41T0", .driver_data = m41t0 },
348 { .id = "M41T00", .driver_data = m41t00 },
349 { .id = "MCP7940X", .driver_data = mcp794xx },
350 { .id = "MCP7941X", .driver_data = mcp794xx },
351 { .id = "PT7C4338", .driver_data = ds_1307 },
352 { .id = "RX8025", .driver_data = rx_8025 },
353 { .id = "ISL12057", .driver_data = ds_1337 },
354 { .id = "RX8130", .driver_data = rx_8130 },
355 { }
356};
357MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids);
358#endif
359
360/*
361 * The ds1337 and ds1339 both have two alarms, but we only use the first
362 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
363 * signal; ds1339 chips have only one alarm signal.
364 */
365static irqreturn_t ds1307_irq(int irq, void *dev_id)
366{
367 struct ds1307 *ds1307 = dev_id;
368 struct mutex *lock = &ds1307->rtc->ops_lock;
369 int stat, ret;
370
371 mutex_lock(lock);
372 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
373 if (ret)
374 goto out;
375
376 if (stat & DS1337_BIT_A1I) {
377 stat &= ~DS1337_BIT_A1I;
378 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
379
380 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
381 DS1337_BIT_A1IE, 0);
382 if (ret)
383 goto out;
384
385 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
386 }
387
388out:
389 mutex_unlock(lock);
390
391 return IRQ_HANDLED;
392}
393
394/*----------------------------------------------------------------------*/
395
396static int ds1307_get_time(struct device *dev, struct rtc_time *t)
397{
398 struct ds1307 *ds1307 = dev_get_drvdata(dev);
399 int tmp, ret;
400 const struct chip_desc *chip = &chips[ds1307->type];
401 u8 regs[7];
402
403 /* read the RTC date and time registers all at once */
404 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
405 sizeof(regs));
406 if (ret) {
407 dev_err(dev, "%s error %d\n", "read", ret);
408 return ret;
409 }
410
411 dev_dbg(dev, "%s: %7ph\n", "read", regs);
412
413 /* if oscillator fail bit is set, no data can be trusted */
414 if (ds1307->type == m41t0 &&
415 regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
416 dev_warn_once(dev, "oscillator failed, set time!\n");
417 return -EINVAL;
418 }
419
420 t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
421 t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
422 tmp = regs[DS1307_REG_HOUR] & 0x3f;
423 t->tm_hour = bcd2bin(tmp);
424 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
425 t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
426 tmp = regs[DS1307_REG_MONTH] & 0x1f;
427 t->tm_mon = bcd2bin(tmp) - 1;
428 t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
429
430 if (regs[chip->century_reg] & chip->century_bit &&
431 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
432 t->tm_year += 100;
433
434 dev_dbg(dev, "%s secs=%d, mins=%d, "
435 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
436 "read", t->tm_sec, t->tm_min,
437 t->tm_hour, t->tm_mday,
438 t->tm_mon, t->tm_year, t->tm_wday);
439
440 return 0;
441}
442
443static int ds1307_set_time(struct device *dev, struct rtc_time *t)
444{
445 struct ds1307 *ds1307 = dev_get_drvdata(dev);
446 const struct chip_desc *chip = &chips[ds1307->type];
447 int result;
448 int tmp;
449 u8 regs[7];
450
451 dev_dbg(dev, "%s secs=%d, mins=%d, "
452 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
453 "write", t->tm_sec, t->tm_min,
454 t->tm_hour, t->tm_mday,
455 t->tm_mon, t->tm_year, t->tm_wday);
456
457 if (t->tm_year < 100)
458 return -EINVAL;
459
460#ifdef CONFIG_RTC_DRV_DS1307_CENTURY
461 if (t->tm_year > (chip->century_bit ? 299 : 199))
462 return -EINVAL;
463#else
464 if (t->tm_year > 199)
465 return -EINVAL;
466#endif
467
468 regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
469 regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
470 regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
471 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
472 regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
473 regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
474
475 /* assume 20YY not 19YY */
476 tmp = t->tm_year - 100;
477 regs[DS1307_REG_YEAR] = bin2bcd(tmp);
478
479 if (chip->century_enable_bit)
480 regs[chip->century_reg] |= chip->century_enable_bit;
481 if (t->tm_year > 199 && chip->century_bit)
482 regs[chip->century_reg] |= chip->century_bit;
483
484 if (ds1307->type == mcp794xx) {
485 /*
486 * these bits were cleared when preparing the date/time
487 * values and need to be set again before writing the
488 * regsfer out to the device.
489 */
490 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
491 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
492 }
493
494 dev_dbg(dev, "%s: %7ph\n", "write", regs);
495
496 result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
497 sizeof(regs));
498 if (result) {
499 dev_err(dev, "%s error %d\n", "write", result);
500 return result;
501 }
502 return 0;
503}
504
505static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
506{
507 struct ds1307 *ds1307 = dev_get_drvdata(dev);
508 int ret;
509 u8 regs[9];
510
511 if (!test_bit(HAS_ALARM, &ds1307->flags))
512 return -EINVAL;
513
514 /* read all ALARM1, ALARM2, and status registers at once */
515 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
516 regs, sizeof(regs));
517 if (ret) {
518 dev_err(dev, "%s error %d\n", "alarm read", ret);
519 return ret;
520 }
521
522 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
523 ®s[0], ®s[4], ®s[7]);
524
525 /*
526 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
527 * and that all four fields are checked matches
528 */
529 t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
530 t->time.tm_min = bcd2bin(regs[1] & 0x7f);
531 t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
532 t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
533
534 /* ... and status */
535 t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
536 t->pending = !!(regs[8] & DS1337_BIT_A1I);
537
538 dev_dbg(dev, "%s secs=%d, mins=%d, "
539 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
540 "alarm read", t->time.tm_sec, t->time.tm_min,
541 t->time.tm_hour, t->time.tm_mday,
542 t->enabled, t->pending);
543
544 return 0;
545}
546
547static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
548{
549 struct ds1307 *ds1307 = dev_get_drvdata(dev);
550 unsigned char regs[9];
551 u8 control, status;
552 int ret;
553
554 if (!test_bit(HAS_ALARM, &ds1307->flags))
555 return -EINVAL;
556
557 dev_dbg(dev, "%s secs=%d, mins=%d, "
558 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
559 "alarm set", t->time.tm_sec, t->time.tm_min,
560 t->time.tm_hour, t->time.tm_mday,
561 t->enabled, t->pending);
562
563 /* read current status of both alarms and the chip */
564 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
565 sizeof(regs));
566 if (ret) {
567 dev_err(dev, "%s error %d\n", "alarm write", ret);
568 return ret;
569 }
570 control = regs[7];
571 status = regs[8];
572
573 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
574 ®s[0], ®s[4], control, status);
575
576 /* set ALARM1, using 24 hour and day-of-month modes */
577 regs[0] = bin2bcd(t->time.tm_sec);
578 regs[1] = bin2bcd(t->time.tm_min);
579 regs[2] = bin2bcd(t->time.tm_hour);
580 regs[3] = bin2bcd(t->time.tm_mday);
581
582 /* set ALARM2 to non-garbage */
583 regs[4] = 0;
584 regs[5] = 0;
585 regs[6] = 0;
586
587 /* disable alarms */
588 regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
589 regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
590
591 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
592 sizeof(regs));
593 if (ret) {
594 dev_err(dev, "can't set alarm time\n");
595 return ret;
596 }
597
598 /* optionally enable ALARM1 */
599 if (t->enabled) {
600 dev_dbg(dev, "alarm IRQ armed\n");
601 regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
602 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
603 }
604
605 return 0;
606}
607
608static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
609{
610 struct ds1307 *ds1307 = dev_get_drvdata(dev);
611
612 if (!test_bit(HAS_ALARM, &ds1307->flags))
613 return -ENOTTY;
614
615 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
616 DS1337_BIT_A1IE,
617 enabled ? DS1337_BIT_A1IE : 0);
618}
619
620static const struct rtc_class_ops ds13xx_rtc_ops = {
621 .read_time = ds1307_get_time,
622 .set_time = ds1307_set_time,
623 .read_alarm = ds1337_read_alarm,
624 .set_alarm = ds1337_set_alarm,
625 .alarm_irq_enable = ds1307_alarm_irq_enable,
626};
627
628/*----------------------------------------------------------------------*/
629
630/*
631 * Alarm support for rx8130 devices.
632 */
633
634#define RX8130_REG_ALARM_MIN 0x07
635#define RX8130_REG_ALARM_HOUR 0x08
636#define RX8130_REG_ALARM_WEEK_OR_DAY 0x09
637#define RX8130_REG_EXTENSION 0x0c
638#define RX8130_REG_EXTENSION_WADA BIT(3)
639#define RX8130_REG_FLAG 0x0d
640#define RX8130_REG_FLAG_AF BIT(3)
641#define RX8130_REG_CONTROL0 0x0e
642#define RX8130_REG_CONTROL0_AIE BIT(3)
643
644static irqreturn_t rx8130_irq(int irq, void *dev_id)
645{
646 struct ds1307 *ds1307 = dev_id;
647 struct mutex *lock = &ds1307->rtc->ops_lock;
648 u8 ctl[3];
649 int ret;
650
651 mutex_lock(lock);
652
653 /* Read control registers. */
654 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
655 sizeof(ctl));
656 if (ret < 0)
657 goto out;
658 if (!(ctl[1] & RX8130_REG_FLAG_AF))
659 goto out;
660 ctl[1] &= ~RX8130_REG_FLAG_AF;
661 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
662
663 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
664 sizeof(ctl));
665 if (ret < 0)
666 goto out;
667
668 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
669
670out:
671 mutex_unlock(lock);
672
673 return IRQ_HANDLED;
674}
675
676static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
677{
678 struct ds1307 *ds1307 = dev_get_drvdata(dev);
679 u8 ald[3], ctl[3];
680 int ret;
681
682 if (!test_bit(HAS_ALARM, &ds1307->flags))
683 return -EINVAL;
684
685 /* Read alarm registers. */
686 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
687 sizeof(ald));
688 if (ret < 0)
689 return ret;
690
691 /* Read control registers. */
692 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
693 sizeof(ctl));
694 if (ret < 0)
695 return ret;
696
697 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
698 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
699
700 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
701 t->time.tm_sec = -1;
702 t->time.tm_min = bcd2bin(ald[0] & 0x7f);
703 t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
704 t->time.tm_wday = -1;
705 t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
706 t->time.tm_mon = -1;
707 t->time.tm_year = -1;
708 t->time.tm_yday = -1;
709 t->time.tm_isdst = -1;
710
711 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
712 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
713 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
714
715 return 0;
716}
717
718static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
719{
720 struct ds1307 *ds1307 = dev_get_drvdata(dev);
721 u8 ald[3], ctl[3];
722 int ret;
723
724 if (!test_bit(HAS_ALARM, &ds1307->flags))
725 return -EINVAL;
726
727 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
728 "enabled=%d pending=%d\n", __func__,
729 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
730 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
731 t->enabled, t->pending);
732
733 /* Read control registers. */
734 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
735 sizeof(ctl));
736 if (ret < 0)
737 return ret;
738
739 ctl[0] &= ~RX8130_REG_EXTENSION_WADA;
740 ctl[1] |= RX8130_REG_FLAG_AF;
741 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
742
743 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
744 sizeof(ctl));
745 if (ret < 0)
746 return ret;
747
748 /* Hardware alarm precision is 1 minute! */
749 ald[0] = bin2bcd(t->time.tm_min);
750 ald[1] = bin2bcd(t->time.tm_hour);
751 ald[2] = bin2bcd(t->time.tm_mday);
752
753 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
754 sizeof(ald));
755 if (ret < 0)
756 return ret;
757
758 if (!t->enabled)
759 return 0;
760
761 ctl[2] |= RX8130_REG_CONTROL0_AIE;
762
763 return regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
764 sizeof(ctl));
765}
766
767static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
768{
769 struct ds1307 *ds1307 = dev_get_drvdata(dev);
770 int ret, reg;
771
772 if (!test_bit(HAS_ALARM, &ds1307->flags))
773 return -EINVAL;
774
775 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, ®);
776 if (ret < 0)
777 return ret;
778
779 if (enabled)
780 reg |= RX8130_REG_CONTROL0_AIE;
781 else
782 reg &= ~RX8130_REG_CONTROL0_AIE;
783
784 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
785}
786
787/*----------------------------------------------------------------------*/
788
789/*
790 * Alarm support for mcp794xx devices.
791 */
792
793#define MCP794XX_REG_CONTROL 0x07
794# define MCP794XX_BIT_ALM0_EN 0x10
795# define MCP794XX_BIT_ALM1_EN 0x20
796#define MCP794XX_REG_ALARM0_BASE 0x0a
797#define MCP794XX_REG_ALARM0_CTRL 0x0d
798#define MCP794XX_REG_ALARM1_BASE 0x11
799#define MCP794XX_REG_ALARM1_CTRL 0x14
800# define MCP794XX_BIT_ALMX_IF BIT(3)
801# define MCP794XX_BIT_ALMX_C0 BIT(4)
802# define MCP794XX_BIT_ALMX_C1 BIT(5)
803# define MCP794XX_BIT_ALMX_C2 BIT(6)
804# define MCP794XX_BIT_ALMX_POL BIT(7)
805# define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
806 MCP794XX_BIT_ALMX_C1 | \
807 MCP794XX_BIT_ALMX_C2)
808
809static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
810{
811 struct ds1307 *ds1307 = dev_id;
812 struct mutex *lock = &ds1307->rtc->ops_lock;
813 int reg, ret;
814
815 mutex_lock(lock);
816
817 /* Check and clear alarm 0 interrupt flag. */
818 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, ®);
819 if (ret)
820 goto out;
821 if (!(reg & MCP794XX_BIT_ALMX_IF))
822 goto out;
823 reg &= ~MCP794XX_BIT_ALMX_IF;
824 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
825 if (ret)
826 goto out;
827
828 /* Disable alarm 0. */
829 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
830 MCP794XX_BIT_ALM0_EN, 0);
831 if (ret)
832 goto out;
833
834 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
835
836out:
837 mutex_unlock(lock);
838
839 return IRQ_HANDLED;
840}
841
842static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
843{
844 struct ds1307 *ds1307 = dev_get_drvdata(dev);
845 u8 regs[10];
846 int ret;
847
848 if (!test_bit(HAS_ALARM, &ds1307->flags))
849 return -EINVAL;
850
851 /* Read control and alarm 0 registers. */
852 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
853 sizeof(regs));
854 if (ret)
855 return ret;
856
857 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
858
859 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
860 t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
861 t->time.tm_min = bcd2bin(regs[4] & 0x7f);
862 t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
863 t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
864 t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
865 t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
866 t->time.tm_year = -1;
867 t->time.tm_yday = -1;
868 t->time.tm_isdst = -1;
869
870 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
871 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
872 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
873 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
874 !!(regs[6] & MCP794XX_BIT_ALMX_POL),
875 !!(regs[6] & MCP794XX_BIT_ALMX_IF),
876 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
877
878 return 0;
879}
880
881/*
882 * We may have a random RTC weekday, therefore calculate alarm weekday based
883 * on current weekday we read from the RTC timekeeping regs
884 */
885static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm)
886{
887 struct rtc_time tm_now;
888 int days_now, days_alarm, ret;
889
890 ret = ds1307_get_time(dev, &tm_now);
891 if (ret)
892 return ret;
893
894 days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
895 days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
896
897 return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
898}
899
900static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
901{
902 struct ds1307 *ds1307 = dev_get_drvdata(dev);
903 unsigned char regs[10];
904 int wday, ret;
905
906 if (!test_bit(HAS_ALARM, &ds1307->flags))
907 return -EINVAL;
908
909 wday = mcp794xx_alm_weekday(dev, &t->time);
910 if (wday < 0)
911 return wday;
912
913 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
914 "enabled=%d pending=%d\n", __func__,
915 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
916 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
917 t->enabled, t->pending);
918
919 /* Read control and alarm 0 registers. */
920 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
921 sizeof(regs));
922 if (ret)
923 return ret;
924
925 /* Set alarm 0, using 24-hour and day-of-month modes. */
926 regs[3] = bin2bcd(t->time.tm_sec);
927 regs[4] = bin2bcd(t->time.tm_min);
928 regs[5] = bin2bcd(t->time.tm_hour);
929 regs[6] = wday;
930 regs[7] = bin2bcd(t->time.tm_mday);
931 regs[8] = bin2bcd(t->time.tm_mon + 1);
932
933 /* Clear the alarm 0 interrupt flag. */
934 regs[6] &= ~MCP794XX_BIT_ALMX_IF;
935 /* Set alarm match: second, minute, hour, day, date, month. */
936 regs[6] |= MCP794XX_MSK_ALMX_MATCH;
937 /* Disable interrupt. We will not enable until completely programmed */
938 regs[0] &= ~MCP794XX_BIT_ALM0_EN;
939
940 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
941 sizeof(regs));
942 if (ret)
943 return ret;
944
945 if (!t->enabled)
946 return 0;
947 regs[0] |= MCP794XX_BIT_ALM0_EN;
948 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
949}
950
951static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
952{
953 struct ds1307 *ds1307 = dev_get_drvdata(dev);
954
955 if (!test_bit(HAS_ALARM, &ds1307->flags))
956 return -EINVAL;
957
958 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
959 MCP794XX_BIT_ALM0_EN,
960 enabled ? MCP794XX_BIT_ALM0_EN : 0);
961}
962
963/*----------------------------------------------------------------------*/
964
965static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
966 size_t bytes)
967{
968 struct ds1307 *ds1307 = priv;
969 const struct chip_desc *chip = &chips[ds1307->type];
970
971 return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
972 val, bytes);
973}
974
975static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
976 size_t bytes)
977{
978 struct ds1307 *ds1307 = priv;
979 const struct chip_desc *chip = &chips[ds1307->type];
980
981 return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
982 val, bytes);
983}
984
985/*----------------------------------------------------------------------*/
986
987static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307,
988 u32 ohms, bool diode)
989{
990 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
991 DS1307_TRICKLE_CHARGER_NO_DIODE;
992
993 switch (ohms) {
994 case 250:
995 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
996 break;
997 case 2000:
998 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
999 break;
1000 case 4000:
1001 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
1002 break;
1003 default:
1004 dev_warn(ds1307->dev,
1005 "Unsupported ohm value %u in dt\n", ohms);
1006 return 0;
1007 }
1008 return setup;
1009}
1010
1011static u8 ds1307_trickle_init(struct ds1307 *ds1307,
1012 const struct chip_desc *chip)
1013{
1014 u32 ohms;
1015 bool diode = true;
1016
1017 if (!chip->do_trickle_setup)
1018 return 0;
1019
1020 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
1021 &ohms))
1022 return 0;
1023
1024 if (device_property_read_bool(ds1307->dev, "trickle-diode-disable"))
1025 diode = false;
1026
1027 return chip->do_trickle_setup(ds1307, ohms, diode);
1028}
1029
1030/*----------------------------------------------------------------------*/
1031
1032#ifdef CONFIG_RTC_DRV_DS1307_HWMON
1033
1034/*
1035 * Temperature sensor support for ds3231 devices.
1036 */
1037
1038#define DS3231_REG_TEMPERATURE 0x11
1039
1040/*
1041 * A user-initiated temperature conversion is not started by this function,
1042 * so the temperature is updated once every 64 seconds.
1043 */
1044static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
1045{
1046 struct ds1307 *ds1307 = dev_get_drvdata(dev);
1047 u8 temp_buf[2];
1048 s16 temp;
1049 int ret;
1050
1051 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
1052 temp_buf, sizeof(temp_buf));
1053 if (ret)
1054 return ret;
1055 /*
1056 * Temperature is represented as a 10-bit code with a resolution of
1057 * 0.25 degree celsius and encoded in two's complement format.
1058 */
1059 temp = (temp_buf[0] << 8) | temp_buf[1];
1060 temp >>= 6;
1061 *mC = temp * 250;
1062
1063 return 0;
1064}
1065
1066static ssize_t ds3231_hwmon_show_temp(struct device *dev,
1067 struct device_attribute *attr, char *buf)
1068{
1069 int ret;
1070 s32 temp;
1071
1072 ret = ds3231_hwmon_read_temp(dev, &temp);
1073 if (ret)
1074 return ret;
1075
1076 return sprintf(buf, "%d\n", temp);
1077}
1078static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
1079 NULL, 0);
1080
1081static struct attribute *ds3231_hwmon_attrs[] = {
1082 &sensor_dev_attr_temp1_input.dev_attr.attr,
1083 NULL,
1084};
1085ATTRIBUTE_GROUPS(ds3231_hwmon);
1086
1087static void ds1307_hwmon_register(struct ds1307 *ds1307)
1088{
1089 struct device *dev;
1090
1091 if (ds1307->type != ds_3231)
1092 return;
1093
1094 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
1095 ds1307,
1096 ds3231_hwmon_groups);
1097 if (IS_ERR(dev)) {
1098 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1099 PTR_ERR(dev));
1100 }
1101}
1102
1103#else
1104
1105static void ds1307_hwmon_register(struct ds1307 *ds1307)
1106{
1107}
1108
1109#endif /* CONFIG_RTC_DRV_DS1307_HWMON */
1110
1111/*----------------------------------------------------------------------*/
1112
1113/*
1114 * Square-wave output support for DS3231
1115 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1116 */
1117#ifdef CONFIG_COMMON_CLK
1118
1119enum {
1120 DS3231_CLK_SQW = 0,
1121 DS3231_CLK_32KHZ,
1122};
1123
1124#define clk_sqw_to_ds1307(clk) \
1125 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1126#define clk_32khz_to_ds1307(clk) \
1127 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1128
1129static int ds3231_clk_sqw_rates[] = {
1130 1,
1131 1024,
1132 4096,
1133 8192,
1134};
1135
1136static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1137{
1138 struct mutex *lock = &ds1307->rtc->ops_lock;
1139 int ret;
1140
1141 mutex_lock(lock);
1142 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1143 mask, value);
1144 mutex_unlock(lock);
1145
1146 return ret;
1147}
1148
1149static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1150 unsigned long parent_rate)
1151{
1152 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1153 int control, ret;
1154 int rate_sel = 0;
1155
1156 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1157 if (ret)
1158 return ret;
1159 if (control & DS1337_BIT_RS1)
1160 rate_sel += 1;
1161 if (control & DS1337_BIT_RS2)
1162 rate_sel += 2;
1163
1164 return ds3231_clk_sqw_rates[rate_sel];
1165}
1166
1167static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
1168 unsigned long *prate)
1169{
1170 int i;
1171
1172 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1173 if (ds3231_clk_sqw_rates[i] <= rate)
1174 return ds3231_clk_sqw_rates[i];
1175 }
1176
1177 return 0;
1178}
1179
1180static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1181 unsigned long parent_rate)
1182{
1183 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1184 int control = 0;
1185 int rate_sel;
1186
1187 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1188 rate_sel++) {
1189 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1190 break;
1191 }
1192
1193 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1194 return -EINVAL;
1195
1196 if (rate_sel & 1)
1197 control |= DS1337_BIT_RS1;
1198 if (rate_sel & 2)
1199 control |= DS1337_BIT_RS2;
1200
1201 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1202 control);
1203}
1204
1205static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1206{
1207 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1208
1209 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1210}
1211
1212static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1213{
1214 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1215
1216 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1217}
1218
1219static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1220{
1221 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1222 int control, ret;
1223
1224 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1225 if (ret)
1226 return ret;
1227
1228 return !(control & DS1337_BIT_INTCN);
1229}
1230
1231static const struct clk_ops ds3231_clk_sqw_ops = {
1232 .prepare = ds3231_clk_sqw_prepare,
1233 .unprepare = ds3231_clk_sqw_unprepare,
1234 .is_prepared = ds3231_clk_sqw_is_prepared,
1235 .recalc_rate = ds3231_clk_sqw_recalc_rate,
1236 .round_rate = ds3231_clk_sqw_round_rate,
1237 .set_rate = ds3231_clk_sqw_set_rate,
1238};
1239
1240static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
1241 unsigned long parent_rate)
1242{
1243 return 32768;
1244}
1245
1246static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1247{
1248 struct mutex *lock = &ds1307->rtc->ops_lock;
1249 int ret;
1250
1251 mutex_lock(lock);
1252 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1253 DS3231_BIT_EN32KHZ,
1254 enable ? DS3231_BIT_EN32KHZ : 0);
1255 mutex_unlock(lock);
1256
1257 return ret;
1258}
1259
1260static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1261{
1262 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1263
1264 return ds3231_clk_32khz_control(ds1307, true);
1265}
1266
1267static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1268{
1269 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1270
1271 ds3231_clk_32khz_control(ds1307, false);
1272}
1273
1274static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1275{
1276 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1277 int status, ret;
1278
1279 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1280 if (ret)
1281 return ret;
1282
1283 return !!(status & DS3231_BIT_EN32KHZ);
1284}
1285
1286static const struct clk_ops ds3231_clk_32khz_ops = {
1287 .prepare = ds3231_clk_32khz_prepare,
1288 .unprepare = ds3231_clk_32khz_unprepare,
1289 .is_prepared = ds3231_clk_32khz_is_prepared,
1290 .recalc_rate = ds3231_clk_32khz_recalc_rate,
1291};
1292
1293static struct clk_init_data ds3231_clks_init[] = {
1294 [DS3231_CLK_SQW] = {
1295 .name = "ds3231_clk_sqw",
1296 .ops = &ds3231_clk_sqw_ops,
1297 },
1298 [DS3231_CLK_32KHZ] = {
1299 .name = "ds3231_clk_32khz",
1300 .ops = &ds3231_clk_32khz_ops,
1301 },
1302};
1303
1304static int ds3231_clks_register(struct ds1307 *ds1307)
1305{
1306 struct device_node *node = ds1307->dev->of_node;
1307 struct clk_onecell_data *onecell;
1308 int i;
1309
1310 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
1311 if (!onecell)
1312 return -ENOMEM;
1313
1314 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
1315 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1316 sizeof(onecell->clks[0]), GFP_KERNEL);
1317 if (!onecell->clks)
1318 return -ENOMEM;
1319
1320 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1321 struct clk_init_data init = ds3231_clks_init[i];
1322
1323 /*
1324 * Interrupt signal due to alarm conditions and square-wave
1325 * output share same pin, so don't initialize both.
1326 */
1327 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
1328 continue;
1329
1330 /* optional override of the clockname */
1331 of_property_read_string_index(node, "clock-output-names", i,
1332 &init.name);
1333 ds1307->clks[i].init = &init;
1334
1335 onecell->clks[i] = devm_clk_register(ds1307->dev,
1336 &ds1307->clks[i]);
1337 if (IS_ERR(onecell->clks[i]))
1338 return PTR_ERR(onecell->clks[i]);
1339 }
1340
1341 if (!node)
1342 return 0;
1343
1344 of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1345
1346 return 0;
1347}
1348
1349static void ds1307_clks_register(struct ds1307 *ds1307)
1350{
1351 int ret;
1352
1353 if (ds1307->type != ds_3231)
1354 return;
1355
1356 ret = ds3231_clks_register(ds1307);
1357 if (ret) {
1358 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1359 ret);
1360 }
1361}
1362
1363#else
1364
1365static void ds1307_clks_register(struct ds1307 *ds1307)
1366{
1367}
1368
1369#endif /* CONFIG_COMMON_CLK */
1370
1371static const struct regmap_config regmap_config = {
1372 .reg_bits = 8,
1373 .val_bits = 8,
1374};
1375
1376static int ds1307_probe(struct i2c_client *client,
1377 const struct i2c_device_id *id)
1378{
1379 struct ds1307 *ds1307;
1380 int err = -ENODEV;
1381 int tmp;
1382 const struct chip_desc *chip;
1383 bool want_irq;
1384 bool ds1307_can_wakeup_device = false;
1385 unsigned char regs[8];
1386 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
1387 u8 trickle_charger_setup = 0;
1388
1389 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
1390 if (!ds1307)
1391 return -ENOMEM;
1392
1393 dev_set_drvdata(&client->dev, ds1307);
1394 ds1307->dev = &client->dev;
1395 ds1307->name = client->name;
1396
1397 ds1307->regmap = devm_regmap_init_i2c(client, ®map_config);
1398 if (IS_ERR(ds1307->regmap)) {
1399 dev_err(ds1307->dev, "regmap allocation failed\n");
1400 return PTR_ERR(ds1307->regmap);
1401 }
1402
1403 i2c_set_clientdata(client, ds1307);
1404
1405 if (client->dev.of_node) {
1406 ds1307->type = (enum ds_type)
1407 of_device_get_match_data(&client->dev);
1408 chip = &chips[ds1307->type];
1409 } else if (id) {
1410 chip = &chips[id->driver_data];
1411 ds1307->type = id->driver_data;
1412 } else {
1413 const struct acpi_device_id *acpi_id;
1414
1415 acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids),
1416 ds1307->dev);
1417 if (!acpi_id)
1418 return -ENODEV;
1419 chip = &chips[acpi_id->driver_data];
1420 ds1307->type = acpi_id->driver_data;
1421 }
1422
1423 want_irq = client->irq > 0 && chip->alarm;
1424
1425 if (!pdata)
1426 trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
1427 else if (pdata->trickle_charger_setup)
1428 trickle_charger_setup = pdata->trickle_charger_setup;
1429
1430 if (trickle_charger_setup && chip->trickle_charger_reg) {
1431 trickle_charger_setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
1432 dev_dbg(ds1307->dev,
1433 "writing trickle charger info 0x%x to 0x%x\n",
1434 trickle_charger_setup, chip->trickle_charger_reg);
1435 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
1436 trickle_charger_setup);
1437 }
1438
1439#ifdef CONFIG_OF
1440/*
1441 * For devices with no IRQ directly connected to the SoC, the RTC chip
1442 * can be forced as a wakeup source by stating that explicitly in
1443 * the device's .dts file using the "wakeup-source" boolean property.
1444 * If the "wakeup-source" property is set, don't request an IRQ.
1445 * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1446 * if supported by the RTC.
1447 */
1448 if (chip->alarm && of_property_read_bool(client->dev.of_node,
1449 "wakeup-source"))
1450 ds1307_can_wakeup_device = true;
1451#endif
1452
1453 switch (ds1307->type) {
1454 case ds_1337:
1455 case ds_1339:
1456 case ds_1341:
1457 case ds_3231:
1458 /* get registers that the "rtc" read below won't read... */
1459 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
1460 regs, 2);
1461 if (err) {
1462 dev_dbg(ds1307->dev, "read error %d\n", err);
1463 goto exit;
1464 }
1465
1466 /* oscillator off? turn it on, so clock can tick. */
1467 if (regs[0] & DS1337_BIT_nEOSC)
1468 regs[0] &= ~DS1337_BIT_nEOSC;
1469
1470 /*
1471 * Using IRQ or defined as wakeup-source?
1472 * Disable the square wave and both alarms.
1473 * For some variants, be sure alarms can trigger when we're
1474 * running on Vbackup (BBSQI/BBSQW)
1475 */
1476 if (want_irq || ds1307_can_wakeup_device) {
1477 regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
1478 regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
1479 }
1480
1481 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
1482 regs[0]);
1483
1484 /* oscillator fault? clear flag, and warn */
1485 if (regs[1] & DS1337_BIT_OSF) {
1486 regmap_write(ds1307->regmap, DS1337_REG_STATUS,
1487 regs[1] & ~DS1337_BIT_OSF);
1488 dev_warn(ds1307->dev, "SET TIME!\n");
1489 }
1490 break;
1491
1492 case rx_8025:
1493 err = regmap_bulk_read(ds1307->regmap,
1494 RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
1495 if (err) {
1496 dev_dbg(ds1307->dev, "read error %d\n", err);
1497 goto exit;
1498 }
1499
1500 /* oscillator off? turn it on, so clock can tick. */
1501 if (!(regs[1] & RX8025_BIT_XST)) {
1502 regs[1] |= RX8025_BIT_XST;
1503 regmap_write(ds1307->regmap,
1504 RX8025_REG_CTRL2 << 4 | 0x08,
1505 regs[1]);
1506 dev_warn(ds1307->dev,
1507 "oscillator stop detected - SET TIME!\n");
1508 }
1509
1510 if (regs[1] & RX8025_BIT_PON) {
1511 regs[1] &= ~RX8025_BIT_PON;
1512 regmap_write(ds1307->regmap,
1513 RX8025_REG_CTRL2 << 4 | 0x08,
1514 regs[1]);
1515 dev_warn(ds1307->dev, "power-on detected\n");
1516 }
1517
1518 if (regs[1] & RX8025_BIT_VDET) {
1519 regs[1] &= ~RX8025_BIT_VDET;
1520 regmap_write(ds1307->regmap,
1521 RX8025_REG_CTRL2 << 4 | 0x08,
1522 regs[1]);
1523 dev_warn(ds1307->dev, "voltage drop detected\n");
1524 }
1525
1526 /* make sure we are running in 24hour mode */
1527 if (!(regs[0] & RX8025_BIT_2412)) {
1528 u8 hour;
1529
1530 /* switch to 24 hour mode */
1531 regmap_write(ds1307->regmap,
1532 RX8025_REG_CTRL1 << 4 | 0x08,
1533 regs[0] | RX8025_BIT_2412);
1534
1535 err = regmap_bulk_read(ds1307->regmap,
1536 RX8025_REG_CTRL1 << 4 | 0x08,
1537 regs, 2);
1538 if (err) {
1539 dev_dbg(ds1307->dev, "read error %d\n", err);
1540 goto exit;
1541 }
1542
1543 /* correct hour */
1544 hour = bcd2bin(regs[DS1307_REG_HOUR]);
1545 if (hour == 12)
1546 hour = 0;
1547 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1548 hour += 12;
1549
1550 regmap_write(ds1307->regmap,
1551 DS1307_REG_HOUR << 4 | 0x08, hour);
1552 }
1553 break;
1554 default:
1555 break;
1556 }
1557
1558read_rtc:
1559 /* read RTC registers */
1560 err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
1561 sizeof(regs));
1562 if (err) {
1563 dev_dbg(ds1307->dev, "read error %d\n", err);
1564 goto exit;
1565 }
1566
1567 /*
1568 * minimal sanity checking; some chips (like DS1340) don't
1569 * specify the extra bits as must-be-zero, but there are
1570 * still a few values that are clearly out-of-range.
1571 */
1572 tmp = regs[DS1307_REG_SECS];
1573 switch (ds1307->type) {
1574 case ds_1307:
1575 case m41t0:
1576 case m41t00:
1577 /* clock halted? turn it on, so clock can tick. */
1578 if (tmp & DS1307_BIT_CH) {
1579 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1580 dev_warn(ds1307->dev, "SET TIME!\n");
1581 goto read_rtc;
1582 }
1583 break;
1584 case ds_1308:
1585 case ds_1338:
1586 /* clock halted? turn it on, so clock can tick. */
1587 if (tmp & DS1307_BIT_CH)
1588 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1589
1590 /* oscillator fault? clear flag, and warn */
1591 if (regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
1592 regmap_write(ds1307->regmap, DS1307_REG_CONTROL,
1593 regs[DS1307_REG_CONTROL] &
1594 ~DS1338_BIT_OSF);
1595 dev_warn(ds1307->dev, "SET TIME!\n");
1596 goto read_rtc;
1597 }
1598 break;
1599 case ds_1340:
1600 /* clock halted? turn it on, so clock can tick. */
1601 if (tmp & DS1340_BIT_nEOSC)
1602 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1603
1604 err = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
1605 if (err) {
1606 dev_dbg(ds1307->dev, "read error %d\n", err);
1607 goto exit;
1608 }
1609
1610 /* oscillator fault? clear flag, and warn */
1611 if (tmp & DS1340_BIT_OSF) {
1612 regmap_write(ds1307->regmap, DS1340_REG_FLAG, 0);
1613 dev_warn(ds1307->dev, "SET TIME!\n");
1614 }
1615 break;
1616 case mcp794xx:
1617 /* make sure that the backup battery is enabled */
1618 if (!(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1619 regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1620 regs[DS1307_REG_WDAY] |
1621 MCP794XX_BIT_VBATEN);
1622 }
1623
1624 /* clock halted? turn it on, so clock can tick. */
1625 if (!(tmp & MCP794XX_BIT_ST)) {
1626 regmap_write(ds1307->regmap, DS1307_REG_SECS,
1627 MCP794XX_BIT_ST);
1628 dev_warn(ds1307->dev, "SET TIME!\n");
1629 goto read_rtc;
1630 }
1631
1632 break;
1633 default:
1634 break;
1635 }
1636
1637 tmp = regs[DS1307_REG_HOUR];
1638 switch (ds1307->type) {
1639 case ds_1340:
1640 case m41t0:
1641 case m41t00:
1642 /*
1643 * NOTE: ignores century bits; fix before deploying
1644 * systems that will run through year 2100.
1645 */
1646 break;
1647 case rx_8025:
1648 break;
1649 default:
1650 if (!(tmp & DS1307_BIT_12HR))
1651 break;
1652
1653 /*
1654 * Be sure we're in 24 hour mode. Multi-master systems
1655 * take note...
1656 */
1657 tmp = bcd2bin(tmp & 0x1f);
1658 if (tmp == 12)
1659 tmp = 0;
1660 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1661 tmp += 12;
1662 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
1663 bin2bcd(tmp));
1664 }
1665
1666 if (want_irq || ds1307_can_wakeup_device) {
1667 device_set_wakeup_capable(ds1307->dev, true);
1668 set_bit(HAS_ALARM, &ds1307->flags);
1669 }
1670
1671 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
1672 if (IS_ERR(ds1307->rtc))
1673 return PTR_ERR(ds1307->rtc);
1674
1675 if (ds1307_can_wakeup_device && !want_irq) {
1676 dev_info(ds1307->dev,
1677 "'wakeup-source' is set, request for an IRQ is disabled!\n");
1678 /* We cannot support UIE mode if we do not have an IRQ line */
1679 ds1307->rtc->uie_unsupported = 1;
1680 }
1681
1682 if (want_irq) {
1683 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
1684 chip->irq_handler ?: ds1307_irq,
1685 IRQF_SHARED | IRQF_ONESHOT,
1686 ds1307->name, ds1307);
1687 if (err) {
1688 client->irq = 0;
1689 device_set_wakeup_capable(ds1307->dev, false);
1690 clear_bit(HAS_ALARM, &ds1307->flags);
1691 dev_err(ds1307->dev, "unable to request IRQ!\n");
1692 } else {
1693 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
1694 }
1695 }
1696
1697 ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
1698 err = rtc_register_device(ds1307->rtc);
1699 if (err)
1700 return err;
1701
1702 if (chip->nvram_size) {
1703 struct nvmem_config nvmem_cfg = {
1704 .name = "ds1307_nvram",
1705 .word_size = 1,
1706 .stride = 1,
1707 .size = chip->nvram_size,
1708 .reg_read = ds1307_nvram_read,
1709 .reg_write = ds1307_nvram_write,
1710 .priv = ds1307,
1711 };
1712
1713 ds1307->rtc->nvram_old_abi = true;
1714 rtc_nvmem_register(ds1307->rtc, &nvmem_cfg);
1715 }
1716
1717 ds1307_hwmon_register(ds1307);
1718 ds1307_clks_register(ds1307);
1719
1720 return 0;
1721
1722exit:
1723 return err;
1724}
1725
1726static struct i2c_driver ds1307_driver = {
1727 .driver = {
1728 .name = "rtc-ds1307",
1729 .of_match_table = of_match_ptr(ds1307_of_match),
1730 .acpi_match_table = ACPI_PTR(ds1307_acpi_ids),
1731 },
1732 .probe = ds1307_probe,
1733 .id_table = ds1307_id,
1734};
1735
1736module_i2c_driver(ds1307_driver);
1737
1738MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
1739MODULE_LICENSE("GPL");