Loading...
1/*
2 * SuperH Timer Support - CMT
3 *
4 * Copyright (C) 2008 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/io.h>
26#include <linux/clk.h>
27#include <linux/irq.h>
28#include <linux/err.h>
29#include <linux/delay.h>
30#include <linux/clocksource.h>
31#include <linux/clockchips.h>
32#include <linux/sh_timer.h>
33#include <linux/slab.h>
34
35struct sh_cmt_priv {
36 void __iomem *mapbase;
37 struct clk *clk;
38 unsigned long width; /* 16 or 32 bit version of hardware block */
39 unsigned long overflow_bit;
40 unsigned long clear_bits;
41 struct irqaction irqaction;
42 struct platform_device *pdev;
43
44 unsigned long flags;
45 unsigned long match_value;
46 unsigned long next_match_value;
47 unsigned long max_match_value;
48 unsigned long rate;
49 spinlock_t lock;
50 struct clock_event_device ced;
51 struct clocksource cs;
52 unsigned long total_cycles;
53};
54
55static DEFINE_SPINLOCK(sh_cmt_lock);
56
57#define CMSTR -1 /* shared register */
58#define CMCSR 0 /* channel register */
59#define CMCNT 1 /* channel register */
60#define CMCOR 2 /* channel register */
61
62static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr)
63{
64 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
65 void __iomem *base = p->mapbase;
66 unsigned long offs;
67
68 if (reg_nr == CMSTR) {
69 offs = 0;
70 base -= cfg->channel_offset;
71 } else
72 offs = reg_nr;
73
74 if (p->width == 16)
75 offs <<= 1;
76 else {
77 offs <<= 2;
78 if ((reg_nr == CMCNT) || (reg_nr == CMCOR))
79 return ioread32(base + offs);
80 }
81
82 return ioread16(base + offs);
83}
84
85static inline void sh_cmt_write(struct sh_cmt_priv *p, int reg_nr,
86 unsigned long value)
87{
88 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
89 void __iomem *base = p->mapbase;
90 unsigned long offs;
91
92 if (reg_nr == CMSTR) {
93 offs = 0;
94 base -= cfg->channel_offset;
95 } else
96 offs = reg_nr;
97
98 if (p->width == 16)
99 offs <<= 1;
100 else {
101 offs <<= 2;
102 if ((reg_nr == CMCNT) || (reg_nr == CMCOR)) {
103 iowrite32(value, base + offs);
104 return;
105 }
106 }
107
108 iowrite16(value, base + offs);
109}
110
111static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p,
112 int *has_wrapped)
113{
114 unsigned long v1, v2, v3;
115 int o1, o2;
116
117 o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
118
119 /* Make sure the timer value is stable. Stolen from acpi_pm.c */
120 do {
121 o2 = o1;
122 v1 = sh_cmt_read(p, CMCNT);
123 v2 = sh_cmt_read(p, CMCNT);
124 v3 = sh_cmt_read(p, CMCNT);
125 o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
126 } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
127 || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
128
129 *has_wrapped = o1;
130 return v2;
131}
132
133
134static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
135{
136 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
137 unsigned long flags, value;
138
139 /* start stop register shared by multiple timer channels */
140 spin_lock_irqsave(&sh_cmt_lock, flags);
141 value = sh_cmt_read(p, CMSTR);
142
143 if (start)
144 value |= 1 << cfg->timer_bit;
145 else
146 value &= ~(1 << cfg->timer_bit);
147
148 sh_cmt_write(p, CMSTR, value);
149 spin_unlock_irqrestore(&sh_cmt_lock, flags);
150}
151
152static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
153{
154 int k, ret;
155
156 /* enable clock */
157 ret = clk_enable(p->clk);
158 if (ret) {
159 dev_err(&p->pdev->dev, "cannot enable clock\n");
160 goto err0;
161 }
162
163 /* make sure channel is disabled */
164 sh_cmt_start_stop_ch(p, 0);
165
166 /* configure channel, periodic mode and maximum timeout */
167 if (p->width == 16) {
168 *rate = clk_get_rate(p->clk) / 512;
169 sh_cmt_write(p, CMCSR, 0x43);
170 } else {
171 *rate = clk_get_rate(p->clk) / 8;
172 sh_cmt_write(p, CMCSR, 0x01a4);
173 }
174
175 sh_cmt_write(p, CMCOR, 0xffffffff);
176 sh_cmt_write(p, CMCNT, 0);
177
178 /*
179 * According to the sh73a0 user's manual, as CMCNT can be operated
180 * only by the RCLK (Pseudo 32 KHz), there's one restriction on
181 * modifying CMCNT register; two RCLK cycles are necessary before
182 * this register is either read or any modification of the value
183 * it holds is reflected in the LSI's actual operation.
184 *
185 * While at it, we're supposed to clear out the CMCNT as of this
186 * moment, so make sure it's processed properly here. This will
187 * take RCLKx2 at maximum.
188 */
189 for (k = 0; k < 100; k++) {
190 if (!sh_cmt_read(p, CMCNT))
191 break;
192 udelay(1);
193 }
194
195 if (sh_cmt_read(p, CMCNT)) {
196 dev_err(&p->pdev->dev, "cannot clear CMCNT\n");
197 ret = -ETIMEDOUT;
198 goto err1;
199 }
200
201 /* enable channel */
202 sh_cmt_start_stop_ch(p, 1);
203 return 0;
204 err1:
205 /* stop clock */
206 clk_disable(p->clk);
207
208 err0:
209 return ret;
210}
211
212static void sh_cmt_disable(struct sh_cmt_priv *p)
213{
214 /* disable channel */
215 sh_cmt_start_stop_ch(p, 0);
216
217 /* disable interrupts in CMT block */
218 sh_cmt_write(p, CMCSR, 0);
219
220 /* stop clock */
221 clk_disable(p->clk);
222}
223
224/* private flags */
225#define FLAG_CLOCKEVENT (1 << 0)
226#define FLAG_CLOCKSOURCE (1 << 1)
227#define FLAG_REPROGRAM (1 << 2)
228#define FLAG_SKIPEVENT (1 << 3)
229#define FLAG_IRQCONTEXT (1 << 4)
230
231static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv *p,
232 int absolute)
233{
234 unsigned long new_match;
235 unsigned long value = p->next_match_value;
236 unsigned long delay = 0;
237 unsigned long now = 0;
238 int has_wrapped;
239
240 now = sh_cmt_get_counter(p, &has_wrapped);
241 p->flags |= FLAG_REPROGRAM; /* force reprogram */
242
243 if (has_wrapped) {
244 /* we're competing with the interrupt handler.
245 * -> let the interrupt handler reprogram the timer.
246 * -> interrupt number two handles the event.
247 */
248 p->flags |= FLAG_SKIPEVENT;
249 return;
250 }
251
252 if (absolute)
253 now = 0;
254
255 do {
256 /* reprogram the timer hardware,
257 * but don't save the new match value yet.
258 */
259 new_match = now + value + delay;
260 if (new_match > p->max_match_value)
261 new_match = p->max_match_value;
262
263 sh_cmt_write(p, CMCOR, new_match);
264
265 now = sh_cmt_get_counter(p, &has_wrapped);
266 if (has_wrapped && (new_match > p->match_value)) {
267 /* we are changing to a greater match value,
268 * so this wrap must be caused by the counter
269 * matching the old value.
270 * -> first interrupt reprograms the timer.
271 * -> interrupt number two handles the event.
272 */
273 p->flags |= FLAG_SKIPEVENT;
274 break;
275 }
276
277 if (has_wrapped) {
278 /* we are changing to a smaller match value,
279 * so the wrap must be caused by the counter
280 * matching the new value.
281 * -> save programmed match value.
282 * -> let isr handle the event.
283 */
284 p->match_value = new_match;
285 break;
286 }
287
288 /* be safe: verify hardware settings */
289 if (now < new_match) {
290 /* timer value is below match value, all good.
291 * this makes sure we won't miss any match events.
292 * -> save programmed match value.
293 * -> let isr handle the event.
294 */
295 p->match_value = new_match;
296 break;
297 }
298
299 /* the counter has reached a value greater
300 * than our new match value. and since the
301 * has_wrapped flag isn't set we must have
302 * programmed a too close event.
303 * -> increase delay and retry.
304 */
305 if (delay)
306 delay <<= 1;
307 else
308 delay = 1;
309
310 if (!delay)
311 dev_warn(&p->pdev->dev, "too long delay\n");
312
313 } while (delay);
314}
315
316static void __sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta)
317{
318 if (delta > p->max_match_value)
319 dev_warn(&p->pdev->dev, "delta out of range\n");
320
321 p->next_match_value = delta;
322 sh_cmt_clock_event_program_verify(p, 0);
323}
324
325static void sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta)
326{
327 unsigned long flags;
328
329 spin_lock_irqsave(&p->lock, flags);
330 __sh_cmt_set_next(p, delta);
331 spin_unlock_irqrestore(&p->lock, flags);
332}
333
334static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
335{
336 struct sh_cmt_priv *p = dev_id;
337
338 /* clear flags */
339 sh_cmt_write(p, CMCSR, sh_cmt_read(p, CMCSR) & p->clear_bits);
340
341 /* update clock source counter to begin with if enabled
342 * the wrap flag should be cleared by the timer specific
343 * isr before we end up here.
344 */
345 if (p->flags & FLAG_CLOCKSOURCE)
346 p->total_cycles += p->match_value + 1;
347
348 if (!(p->flags & FLAG_REPROGRAM))
349 p->next_match_value = p->max_match_value;
350
351 p->flags |= FLAG_IRQCONTEXT;
352
353 if (p->flags & FLAG_CLOCKEVENT) {
354 if (!(p->flags & FLAG_SKIPEVENT)) {
355 if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT) {
356 p->next_match_value = p->max_match_value;
357 p->flags |= FLAG_REPROGRAM;
358 }
359
360 p->ced.event_handler(&p->ced);
361 }
362 }
363
364 p->flags &= ~FLAG_SKIPEVENT;
365
366 if (p->flags & FLAG_REPROGRAM) {
367 p->flags &= ~FLAG_REPROGRAM;
368 sh_cmt_clock_event_program_verify(p, 1);
369
370 if (p->flags & FLAG_CLOCKEVENT)
371 if ((p->ced.mode == CLOCK_EVT_MODE_SHUTDOWN)
372 || (p->match_value == p->next_match_value))
373 p->flags &= ~FLAG_REPROGRAM;
374 }
375
376 p->flags &= ~FLAG_IRQCONTEXT;
377
378 return IRQ_HANDLED;
379}
380
381static int sh_cmt_start(struct sh_cmt_priv *p, unsigned long flag)
382{
383 int ret = 0;
384 unsigned long flags;
385
386 spin_lock_irqsave(&p->lock, flags);
387
388 if (!(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
389 ret = sh_cmt_enable(p, &p->rate);
390
391 if (ret)
392 goto out;
393 p->flags |= flag;
394
395 /* setup timeout if no clockevent */
396 if ((flag == FLAG_CLOCKSOURCE) && (!(p->flags & FLAG_CLOCKEVENT)))
397 __sh_cmt_set_next(p, p->max_match_value);
398 out:
399 spin_unlock_irqrestore(&p->lock, flags);
400
401 return ret;
402}
403
404static void sh_cmt_stop(struct sh_cmt_priv *p, unsigned long flag)
405{
406 unsigned long flags;
407 unsigned long f;
408
409 spin_lock_irqsave(&p->lock, flags);
410
411 f = p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
412 p->flags &= ~flag;
413
414 if (f && !(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
415 sh_cmt_disable(p);
416
417 /* adjust the timeout to maximum if only clocksource left */
418 if ((flag == FLAG_CLOCKEVENT) && (p->flags & FLAG_CLOCKSOURCE))
419 __sh_cmt_set_next(p, p->max_match_value);
420
421 spin_unlock_irqrestore(&p->lock, flags);
422}
423
424static struct sh_cmt_priv *cs_to_sh_cmt(struct clocksource *cs)
425{
426 return container_of(cs, struct sh_cmt_priv, cs);
427}
428
429static cycle_t sh_cmt_clocksource_read(struct clocksource *cs)
430{
431 struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
432 unsigned long flags, raw;
433 unsigned long value;
434 int has_wrapped;
435
436 spin_lock_irqsave(&p->lock, flags);
437 value = p->total_cycles;
438 raw = sh_cmt_get_counter(p, &has_wrapped);
439
440 if (unlikely(has_wrapped))
441 raw += p->match_value + 1;
442 spin_unlock_irqrestore(&p->lock, flags);
443
444 return value + raw;
445}
446
447static int sh_cmt_clocksource_enable(struct clocksource *cs)
448{
449 int ret;
450 struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
451
452 p->total_cycles = 0;
453
454 ret = sh_cmt_start(p, FLAG_CLOCKSOURCE);
455 if (!ret)
456 __clocksource_updatefreq_hz(cs, p->rate);
457 return ret;
458}
459
460static void sh_cmt_clocksource_disable(struct clocksource *cs)
461{
462 sh_cmt_stop(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE);
463}
464
465static void sh_cmt_clocksource_resume(struct clocksource *cs)
466{
467 sh_cmt_start(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE);
468}
469
470static int sh_cmt_register_clocksource(struct sh_cmt_priv *p,
471 char *name, unsigned long rating)
472{
473 struct clocksource *cs = &p->cs;
474
475 cs->name = name;
476 cs->rating = rating;
477 cs->read = sh_cmt_clocksource_read;
478 cs->enable = sh_cmt_clocksource_enable;
479 cs->disable = sh_cmt_clocksource_disable;
480 cs->suspend = sh_cmt_clocksource_disable;
481 cs->resume = sh_cmt_clocksource_resume;
482 cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
483 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
484
485 dev_info(&p->pdev->dev, "used as clock source\n");
486
487 /* Register with dummy 1 Hz value, gets updated in ->enable() */
488 clocksource_register_hz(cs, 1);
489 return 0;
490}
491
492static struct sh_cmt_priv *ced_to_sh_cmt(struct clock_event_device *ced)
493{
494 return container_of(ced, struct sh_cmt_priv, ced);
495}
496
497static void sh_cmt_clock_event_start(struct sh_cmt_priv *p, int periodic)
498{
499 struct clock_event_device *ced = &p->ced;
500
501 sh_cmt_start(p, FLAG_CLOCKEVENT);
502
503 /* TODO: calculate good shift from rate and counter bit width */
504
505 ced->shift = 32;
506 ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
507 ced->max_delta_ns = clockevent_delta2ns(p->max_match_value, ced);
508 ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
509
510 if (periodic)
511 sh_cmt_set_next(p, ((p->rate + HZ/2) / HZ) - 1);
512 else
513 sh_cmt_set_next(p, p->max_match_value);
514}
515
516static void sh_cmt_clock_event_mode(enum clock_event_mode mode,
517 struct clock_event_device *ced)
518{
519 struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
520
521 /* deal with old setting first */
522 switch (ced->mode) {
523 case CLOCK_EVT_MODE_PERIODIC:
524 case CLOCK_EVT_MODE_ONESHOT:
525 sh_cmt_stop(p, FLAG_CLOCKEVENT);
526 break;
527 default:
528 break;
529 }
530
531 switch (mode) {
532 case CLOCK_EVT_MODE_PERIODIC:
533 dev_info(&p->pdev->dev, "used for periodic clock events\n");
534 sh_cmt_clock_event_start(p, 1);
535 break;
536 case CLOCK_EVT_MODE_ONESHOT:
537 dev_info(&p->pdev->dev, "used for oneshot clock events\n");
538 sh_cmt_clock_event_start(p, 0);
539 break;
540 case CLOCK_EVT_MODE_SHUTDOWN:
541 case CLOCK_EVT_MODE_UNUSED:
542 sh_cmt_stop(p, FLAG_CLOCKEVENT);
543 break;
544 default:
545 break;
546 }
547}
548
549static int sh_cmt_clock_event_next(unsigned long delta,
550 struct clock_event_device *ced)
551{
552 struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
553
554 BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
555 if (likely(p->flags & FLAG_IRQCONTEXT))
556 p->next_match_value = delta - 1;
557 else
558 sh_cmt_set_next(p, delta - 1);
559
560 return 0;
561}
562
563static void sh_cmt_register_clockevent(struct sh_cmt_priv *p,
564 char *name, unsigned long rating)
565{
566 struct clock_event_device *ced = &p->ced;
567
568 memset(ced, 0, sizeof(*ced));
569
570 ced->name = name;
571 ced->features = CLOCK_EVT_FEAT_PERIODIC;
572 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
573 ced->rating = rating;
574 ced->cpumask = cpumask_of(0);
575 ced->set_next_event = sh_cmt_clock_event_next;
576 ced->set_mode = sh_cmt_clock_event_mode;
577
578 dev_info(&p->pdev->dev, "used for clock events\n");
579 clockevents_register_device(ced);
580}
581
582static int sh_cmt_register(struct sh_cmt_priv *p, char *name,
583 unsigned long clockevent_rating,
584 unsigned long clocksource_rating)
585{
586 if (p->width == (sizeof(p->max_match_value) * 8))
587 p->max_match_value = ~0;
588 else
589 p->max_match_value = (1 << p->width) - 1;
590
591 p->match_value = p->max_match_value;
592 spin_lock_init(&p->lock);
593
594 if (clockevent_rating)
595 sh_cmt_register_clockevent(p, name, clockevent_rating);
596
597 if (clocksource_rating)
598 sh_cmt_register_clocksource(p, name, clocksource_rating);
599
600 return 0;
601}
602
603static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
604{
605 struct sh_timer_config *cfg = pdev->dev.platform_data;
606 struct resource *res;
607 int irq, ret;
608 ret = -ENXIO;
609
610 memset(p, 0, sizeof(*p));
611 p->pdev = pdev;
612
613 if (!cfg) {
614 dev_err(&p->pdev->dev, "missing platform data\n");
615 goto err0;
616 }
617
618 platform_set_drvdata(pdev, p);
619
620 res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
621 if (!res) {
622 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
623 goto err0;
624 }
625
626 irq = platform_get_irq(p->pdev, 0);
627 if (irq < 0) {
628 dev_err(&p->pdev->dev, "failed to get irq\n");
629 goto err0;
630 }
631
632 /* map memory, let mapbase point to our channel */
633 p->mapbase = ioremap_nocache(res->start, resource_size(res));
634 if (p->mapbase == NULL) {
635 dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
636 goto err0;
637 }
638
639 /* request irq using setup_irq() (too early for request_irq()) */
640 p->irqaction.name = dev_name(&p->pdev->dev);
641 p->irqaction.handler = sh_cmt_interrupt;
642 p->irqaction.dev_id = p;
643 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
644 IRQF_IRQPOLL | IRQF_NOBALANCING;
645
646 /* get hold of clock */
647 p->clk = clk_get(&p->pdev->dev, "cmt_fck");
648 if (IS_ERR(p->clk)) {
649 dev_err(&p->pdev->dev, "cannot get clock\n");
650 ret = PTR_ERR(p->clk);
651 goto err1;
652 }
653
654 if (resource_size(res) == 6) {
655 p->width = 16;
656 p->overflow_bit = 0x80;
657 p->clear_bits = ~0x80;
658 } else {
659 p->width = 32;
660 p->overflow_bit = 0x8000;
661 p->clear_bits = ~0xc000;
662 }
663
664 ret = sh_cmt_register(p, (char *)dev_name(&p->pdev->dev),
665 cfg->clockevent_rating,
666 cfg->clocksource_rating);
667 if (ret) {
668 dev_err(&p->pdev->dev, "registration failed\n");
669 goto err1;
670 }
671
672 ret = setup_irq(irq, &p->irqaction);
673 if (ret) {
674 dev_err(&p->pdev->dev, "failed to request irq %d\n", irq);
675 goto err1;
676 }
677
678 return 0;
679
680err1:
681 iounmap(p->mapbase);
682err0:
683 return ret;
684}
685
686static int __devinit sh_cmt_probe(struct platform_device *pdev)
687{
688 struct sh_cmt_priv *p = platform_get_drvdata(pdev);
689 int ret;
690
691 if (p) {
692 dev_info(&pdev->dev, "kept as earlytimer\n");
693 return 0;
694 }
695
696 p = kmalloc(sizeof(*p), GFP_KERNEL);
697 if (p == NULL) {
698 dev_err(&pdev->dev, "failed to allocate driver data\n");
699 return -ENOMEM;
700 }
701
702 ret = sh_cmt_setup(p, pdev);
703 if (ret) {
704 kfree(p);
705 platform_set_drvdata(pdev, NULL);
706 }
707 return ret;
708}
709
710static int __devexit sh_cmt_remove(struct platform_device *pdev)
711{
712 return -EBUSY; /* cannot unregister clockevent and clocksource */
713}
714
715static struct platform_driver sh_cmt_device_driver = {
716 .probe = sh_cmt_probe,
717 .remove = __devexit_p(sh_cmt_remove),
718 .driver = {
719 .name = "sh_cmt",
720 }
721};
722
723static int __init sh_cmt_init(void)
724{
725 return platform_driver_register(&sh_cmt_device_driver);
726}
727
728static void __exit sh_cmt_exit(void)
729{
730 platform_driver_unregister(&sh_cmt_device_driver);
731}
732
733early_platform_init("earlytimer", &sh_cmt_device_driver);
734module_init(sh_cmt_init);
735module_exit(sh_cmt_exit);
736
737MODULE_AUTHOR("Magnus Damm");
738MODULE_DESCRIPTION("SuperH CMT Timer Driver");
739MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SuperH Timer Support - CMT
4 *
5 * Copyright (C) 2008 Magnus Damm
6 */
7
8#include <linux/clk.h>
9#include <linux/clockchips.h>
10#include <linux/clocksource.h>
11#include <linux/delay.h>
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/iopoll.h>
17#include <linux/ioport.h>
18#include <linux/irq.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/platform_device.h>
22#include <linux/pm_domain.h>
23#include <linux/pm_runtime.h>
24#include <linux/sh_timer.h>
25#include <linux/slab.h>
26#include <linux/spinlock.h>
27
28#ifdef CONFIG_SUPERH
29#include <asm/platform_early.h>
30#endif
31
32struct sh_cmt_device;
33
34/*
35 * The CMT comes in 5 different identified flavours, depending not only on the
36 * SoC but also on the particular instance. The following table lists the main
37 * characteristics of those flavours.
38 *
39 * 16B 32B 32B-F 48B R-Car Gen2
40 * -----------------------------------------------------------------------------
41 * Channels 2 1/4 1 6 2/8
42 * Control Width 16 16 16 16 32
43 * Counter Width 16 32 32 32/48 32/48
44 * Shared Start/Stop Y Y Y Y N
45 *
46 * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
47 * located in the channel registers block. All other versions have a shared
48 * start/stop register located in the global space.
49 *
50 * Channels are indexed from 0 to N-1 in the documentation. The channel index
51 * infers the start/stop bit position in the control register and the channel
52 * registers block address. Some CMT instances have a subset of channels
53 * available, in which case the index in the documentation doesn't match the
54 * "real" index as implemented in hardware. This is for instance the case with
55 * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
56 * in the documentation but using start/stop bit 5 and having its registers
57 * block at 0x60.
58 *
59 * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
60 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
61 */
62
63enum sh_cmt_model {
64 SH_CMT_16BIT,
65 SH_CMT_32BIT,
66 SH_CMT_48BIT,
67 SH_CMT0_RCAR_GEN2,
68 SH_CMT1_RCAR_GEN2,
69};
70
71struct sh_cmt_info {
72 enum sh_cmt_model model;
73
74 unsigned int channels_mask;
75
76 unsigned long width; /* 16 or 32 bit version of hardware block */
77 u32 overflow_bit;
78 u32 clear_bits;
79
80 /* callbacks for CMSTR and CMCSR access */
81 u32 (*read_control)(void __iomem *base, unsigned long offs);
82 void (*write_control)(void __iomem *base, unsigned long offs,
83 u32 value);
84
85 /* callbacks for CMCNT and CMCOR access */
86 u32 (*read_count)(void __iomem *base, unsigned long offs);
87 void (*write_count)(void __iomem *base, unsigned long offs, u32 value);
88};
89
90struct sh_cmt_channel {
91 struct sh_cmt_device *cmt;
92
93 unsigned int index; /* Index in the documentation */
94 unsigned int hwidx; /* Real hardware index */
95
96 void __iomem *iostart;
97 void __iomem *ioctrl;
98
99 unsigned int timer_bit;
100 unsigned long flags;
101 u32 match_value;
102 u32 next_match_value;
103 u32 max_match_value;
104 raw_spinlock_t lock;
105 struct clock_event_device ced;
106 struct clocksource cs;
107 u64 total_cycles;
108 bool cs_enabled;
109};
110
111struct sh_cmt_device {
112 struct platform_device *pdev;
113
114 const struct sh_cmt_info *info;
115
116 void __iomem *mapbase;
117 struct clk *clk;
118 unsigned long rate;
119 unsigned int reg_delay;
120
121 raw_spinlock_t lock; /* Protect the shared start/stop register */
122
123 struct sh_cmt_channel *channels;
124 unsigned int num_channels;
125 unsigned int hw_channels;
126
127 bool has_clockevent;
128 bool has_clocksource;
129};
130
131#define SH_CMT16_CMCSR_CMF (1 << 7)
132#define SH_CMT16_CMCSR_CMIE (1 << 6)
133#define SH_CMT16_CMCSR_CKS8 (0 << 0)
134#define SH_CMT16_CMCSR_CKS32 (1 << 0)
135#define SH_CMT16_CMCSR_CKS128 (2 << 0)
136#define SH_CMT16_CMCSR_CKS512 (3 << 0)
137#define SH_CMT16_CMCSR_CKS_MASK (3 << 0)
138
139#define SH_CMT32_CMCSR_CMF (1 << 15)
140#define SH_CMT32_CMCSR_OVF (1 << 14)
141#define SH_CMT32_CMCSR_WRFLG (1 << 13)
142#define SH_CMT32_CMCSR_STTF (1 << 12)
143#define SH_CMT32_CMCSR_STPF (1 << 11)
144#define SH_CMT32_CMCSR_SSIE (1 << 10)
145#define SH_CMT32_CMCSR_CMS (1 << 9)
146#define SH_CMT32_CMCSR_CMM (1 << 8)
147#define SH_CMT32_CMCSR_CMTOUT_IE (1 << 7)
148#define SH_CMT32_CMCSR_CMR_NONE (0 << 4)
149#define SH_CMT32_CMCSR_CMR_DMA (1 << 4)
150#define SH_CMT32_CMCSR_CMR_IRQ (2 << 4)
151#define SH_CMT32_CMCSR_CMR_MASK (3 << 4)
152#define SH_CMT32_CMCSR_DBGIVD (1 << 3)
153#define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0)
154#define SH_CMT32_CMCSR_CKS_RCLK32 (5 << 0)
155#define SH_CMT32_CMCSR_CKS_RCLK128 (6 << 0)
156#define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0)
157#define SH_CMT32_CMCSR_CKS_MASK (7 << 0)
158
159static u32 sh_cmt_read16(void __iomem *base, unsigned long offs)
160{
161 return ioread16(base + (offs << 1));
162}
163
164static u32 sh_cmt_read32(void __iomem *base, unsigned long offs)
165{
166 return ioread32(base + (offs << 2));
167}
168
169static void sh_cmt_write16(void __iomem *base, unsigned long offs, u32 value)
170{
171 iowrite16(value, base + (offs << 1));
172}
173
174static void sh_cmt_write32(void __iomem *base, unsigned long offs, u32 value)
175{
176 iowrite32(value, base + (offs << 2));
177}
178
179static const struct sh_cmt_info sh_cmt_info[] = {
180 [SH_CMT_16BIT] = {
181 .model = SH_CMT_16BIT,
182 .width = 16,
183 .overflow_bit = SH_CMT16_CMCSR_CMF,
184 .clear_bits = ~SH_CMT16_CMCSR_CMF,
185 .read_control = sh_cmt_read16,
186 .write_control = sh_cmt_write16,
187 .read_count = sh_cmt_read16,
188 .write_count = sh_cmt_write16,
189 },
190 [SH_CMT_32BIT] = {
191 .model = SH_CMT_32BIT,
192 .width = 32,
193 .overflow_bit = SH_CMT32_CMCSR_CMF,
194 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
195 .read_control = sh_cmt_read16,
196 .write_control = sh_cmt_write16,
197 .read_count = sh_cmt_read32,
198 .write_count = sh_cmt_write32,
199 },
200 [SH_CMT_48BIT] = {
201 .model = SH_CMT_48BIT,
202 .channels_mask = 0x3f,
203 .width = 32,
204 .overflow_bit = SH_CMT32_CMCSR_CMF,
205 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
206 .read_control = sh_cmt_read32,
207 .write_control = sh_cmt_write32,
208 .read_count = sh_cmt_read32,
209 .write_count = sh_cmt_write32,
210 },
211 [SH_CMT0_RCAR_GEN2] = {
212 .model = SH_CMT0_RCAR_GEN2,
213 .channels_mask = 0x60,
214 .width = 32,
215 .overflow_bit = SH_CMT32_CMCSR_CMF,
216 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
217 .read_control = sh_cmt_read32,
218 .write_control = sh_cmt_write32,
219 .read_count = sh_cmt_read32,
220 .write_count = sh_cmt_write32,
221 },
222 [SH_CMT1_RCAR_GEN2] = {
223 .model = SH_CMT1_RCAR_GEN2,
224 .channels_mask = 0xff,
225 .width = 32,
226 .overflow_bit = SH_CMT32_CMCSR_CMF,
227 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
228 .read_control = sh_cmt_read32,
229 .write_control = sh_cmt_write32,
230 .read_count = sh_cmt_read32,
231 .write_count = sh_cmt_write32,
232 },
233};
234
235#define CMCSR 0 /* channel register */
236#define CMCNT 1 /* channel register */
237#define CMCOR 2 /* channel register */
238
239#define CMCLKE 0x1000 /* CLK Enable Register (R-Car Gen2) */
240
241static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch)
242{
243 if (ch->iostart)
244 return ch->cmt->info->read_control(ch->iostart, 0);
245 else
246 return ch->cmt->info->read_control(ch->cmt->mapbase, 0);
247}
248
249static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value)
250{
251 u32 old_value = sh_cmt_read_cmstr(ch);
252
253 if (value != old_value) {
254 if (ch->iostart) {
255 ch->cmt->info->write_control(ch->iostart, 0, value);
256 udelay(ch->cmt->reg_delay);
257 } else {
258 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);
259 udelay(ch->cmt->reg_delay);
260 }
261 }
262}
263
264static inline u32 sh_cmt_read_cmcsr(struct sh_cmt_channel *ch)
265{
266 return ch->cmt->info->read_control(ch->ioctrl, CMCSR);
267}
268
269static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, u32 value)
270{
271 u32 old_value = sh_cmt_read_cmcsr(ch);
272
273 if (value != old_value) {
274 ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);
275 udelay(ch->cmt->reg_delay);
276 }
277}
278
279static inline u32 sh_cmt_read_cmcnt(struct sh_cmt_channel *ch)
280{
281 return ch->cmt->info->read_count(ch->ioctrl, CMCNT);
282}
283
284static inline int sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value)
285{
286 /* Tests showed that we need to wait 3 clocks here */
287 unsigned int cmcnt_delay = DIV_ROUND_UP(3 * ch->cmt->reg_delay, 2);
288 u32 reg;
289
290 if (ch->cmt->info->model > SH_CMT_16BIT) {
291 int ret = read_poll_timeout_atomic(sh_cmt_read_cmcsr, reg,
292 !(reg & SH_CMT32_CMCSR_WRFLG),
293 1, cmcnt_delay, false, ch);
294 if (ret < 0)
295 return ret;
296 }
297
298 ch->cmt->info->write_count(ch->ioctrl, CMCNT, value);
299 udelay(cmcnt_delay);
300 return 0;
301}
302
303static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, u32 value)
304{
305 u32 old_value = ch->cmt->info->read_count(ch->ioctrl, CMCOR);
306
307 if (value != old_value) {
308 ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);
309 udelay(ch->cmt->reg_delay);
310 }
311}
312
313static u32 sh_cmt_get_counter(struct sh_cmt_channel *ch, u32 *has_wrapped)
314{
315 u32 v1, v2, v3;
316 u32 o1, o2;
317
318 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
319
320 /* Make sure the timer value is stable. Stolen from acpi_pm.c */
321 do {
322 o2 = o1;
323 v1 = sh_cmt_read_cmcnt(ch);
324 v2 = sh_cmt_read_cmcnt(ch);
325 v3 = sh_cmt_read_cmcnt(ch);
326 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
327 } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
328 || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
329
330 *has_wrapped = o1;
331 return v2;
332}
333
334static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start)
335{
336 unsigned long flags;
337 u32 value;
338
339 /* start stop register shared by multiple timer channels */
340 raw_spin_lock_irqsave(&ch->cmt->lock, flags);
341 value = sh_cmt_read_cmstr(ch);
342
343 if (start)
344 value |= 1 << ch->timer_bit;
345 else
346 value &= ~(1 << ch->timer_bit);
347
348 sh_cmt_write_cmstr(ch, value);
349 raw_spin_unlock_irqrestore(&ch->cmt->lock, flags);
350}
351
352static int sh_cmt_enable(struct sh_cmt_channel *ch)
353{
354 int ret;
355
356 dev_pm_syscore_device(&ch->cmt->pdev->dev, true);
357
358 /* enable clock */
359 ret = clk_enable(ch->cmt->clk);
360 if (ret) {
361 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n",
362 ch->index);
363 goto err0;
364 }
365
366 /* make sure channel is disabled */
367 sh_cmt_start_stop_ch(ch, 0);
368
369 /* configure channel, periodic mode and maximum timeout */
370 if (ch->cmt->info->width == 16) {
371 sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE |
372 SH_CMT16_CMCSR_CKS512);
373 } else {
374 u32 cmtout = ch->cmt->info->model <= SH_CMT_48BIT ?
375 SH_CMT32_CMCSR_CMTOUT_IE : 0;
376 sh_cmt_write_cmcsr(ch, cmtout | SH_CMT32_CMCSR_CMM |
377 SH_CMT32_CMCSR_CMR_IRQ |
378 SH_CMT32_CMCSR_CKS_RCLK8);
379 }
380
381 sh_cmt_write_cmcor(ch, 0xffffffff);
382 ret = sh_cmt_write_cmcnt(ch, 0);
383
384 if (ret || sh_cmt_read_cmcnt(ch)) {
385 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n",
386 ch->index);
387 ret = -ETIMEDOUT;
388 goto err1;
389 }
390
391 /* enable channel */
392 sh_cmt_start_stop_ch(ch, 1);
393 return 0;
394 err1:
395 /* stop clock */
396 clk_disable(ch->cmt->clk);
397
398 err0:
399 return ret;
400}
401
402static void sh_cmt_disable(struct sh_cmt_channel *ch)
403{
404 /* disable channel */
405 sh_cmt_start_stop_ch(ch, 0);
406
407 /* disable interrupts in CMT block */
408 sh_cmt_write_cmcsr(ch, 0);
409
410 /* stop clock */
411 clk_disable(ch->cmt->clk);
412
413 dev_pm_syscore_device(&ch->cmt->pdev->dev, false);
414}
415
416/* private flags */
417#define FLAG_CLOCKEVENT (1 << 0)
418#define FLAG_CLOCKSOURCE (1 << 1)
419#define FLAG_REPROGRAM (1 << 2)
420#define FLAG_SKIPEVENT (1 << 3)
421#define FLAG_IRQCONTEXT (1 << 4)
422
423static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch,
424 int absolute)
425{
426 u32 value = ch->next_match_value;
427 u32 new_match;
428 u32 delay = 0;
429 u32 now = 0;
430 u32 has_wrapped;
431
432 now = sh_cmt_get_counter(ch, &has_wrapped);
433 ch->flags |= FLAG_REPROGRAM; /* force reprogram */
434
435 if (has_wrapped) {
436 /* we're competing with the interrupt handler.
437 * -> let the interrupt handler reprogram the timer.
438 * -> interrupt number two handles the event.
439 */
440 ch->flags |= FLAG_SKIPEVENT;
441 return;
442 }
443
444 if (absolute)
445 now = 0;
446
447 do {
448 /* reprogram the timer hardware,
449 * but don't save the new match value yet.
450 */
451 new_match = now + value + delay;
452 if (new_match > ch->max_match_value)
453 new_match = ch->max_match_value;
454
455 sh_cmt_write_cmcor(ch, new_match);
456
457 now = sh_cmt_get_counter(ch, &has_wrapped);
458 if (has_wrapped && (new_match > ch->match_value)) {
459 /* we are changing to a greater match value,
460 * so this wrap must be caused by the counter
461 * matching the old value.
462 * -> first interrupt reprograms the timer.
463 * -> interrupt number two handles the event.
464 */
465 ch->flags |= FLAG_SKIPEVENT;
466 break;
467 }
468
469 if (has_wrapped) {
470 /* we are changing to a smaller match value,
471 * so the wrap must be caused by the counter
472 * matching the new value.
473 * -> save programmed match value.
474 * -> let isr handle the event.
475 */
476 ch->match_value = new_match;
477 break;
478 }
479
480 /* be safe: verify hardware settings */
481 if (now < new_match) {
482 /* timer value is below match value, all good.
483 * this makes sure we won't miss any match events.
484 * -> save programmed match value.
485 * -> let isr handle the event.
486 */
487 ch->match_value = new_match;
488 break;
489 }
490
491 /* the counter has reached a value greater
492 * than our new match value. and since the
493 * has_wrapped flag isn't set we must have
494 * programmed a too close event.
495 * -> increase delay and retry.
496 */
497 if (delay)
498 delay <<= 1;
499 else
500 delay = 1;
501
502 if (!delay)
503 dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n",
504 ch->index);
505
506 } while (delay);
507}
508
509static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
510{
511 if (delta > ch->max_match_value)
512 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n",
513 ch->index);
514
515 ch->next_match_value = delta;
516 sh_cmt_clock_event_program_verify(ch, 0);
517}
518
519static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
520{
521 unsigned long flags;
522
523 raw_spin_lock_irqsave(&ch->lock, flags);
524 __sh_cmt_set_next(ch, delta);
525 raw_spin_unlock_irqrestore(&ch->lock, flags);
526}
527
528static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
529{
530 struct sh_cmt_channel *ch = dev_id;
531
532 /* clear flags */
533 sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) &
534 ch->cmt->info->clear_bits);
535
536 /* update clock source counter to begin with if enabled
537 * the wrap flag should be cleared by the timer specific
538 * isr before we end up here.
539 */
540 if (ch->flags & FLAG_CLOCKSOURCE)
541 ch->total_cycles += ch->match_value + 1;
542
543 if (!(ch->flags & FLAG_REPROGRAM))
544 ch->next_match_value = ch->max_match_value;
545
546 ch->flags |= FLAG_IRQCONTEXT;
547
548 if (ch->flags & FLAG_CLOCKEVENT) {
549 if (!(ch->flags & FLAG_SKIPEVENT)) {
550 if (clockevent_state_oneshot(&ch->ced)) {
551 ch->next_match_value = ch->max_match_value;
552 ch->flags |= FLAG_REPROGRAM;
553 }
554
555 ch->ced.event_handler(&ch->ced);
556 }
557 }
558
559 ch->flags &= ~FLAG_SKIPEVENT;
560
561 if (ch->flags & FLAG_REPROGRAM) {
562 ch->flags &= ~FLAG_REPROGRAM;
563 sh_cmt_clock_event_program_verify(ch, 1);
564
565 if (ch->flags & FLAG_CLOCKEVENT)
566 if ((clockevent_state_shutdown(&ch->ced))
567 || (ch->match_value == ch->next_match_value))
568 ch->flags &= ~FLAG_REPROGRAM;
569 }
570
571 ch->flags &= ~FLAG_IRQCONTEXT;
572
573 return IRQ_HANDLED;
574}
575
576static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag)
577{
578 int ret = 0;
579 unsigned long flags;
580
581 if (flag & FLAG_CLOCKSOURCE)
582 pm_runtime_get_sync(&ch->cmt->pdev->dev);
583
584 raw_spin_lock_irqsave(&ch->lock, flags);
585
586 if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) {
587 if (flag & FLAG_CLOCKEVENT)
588 pm_runtime_get_sync(&ch->cmt->pdev->dev);
589 ret = sh_cmt_enable(ch);
590 }
591
592 if (ret)
593 goto out;
594 ch->flags |= flag;
595
596 /* setup timeout if no clockevent */
597 if (ch->cmt->num_channels == 1 &&
598 flag == FLAG_CLOCKSOURCE && (!(ch->flags & FLAG_CLOCKEVENT)))
599 __sh_cmt_set_next(ch, ch->max_match_value);
600 out:
601 raw_spin_unlock_irqrestore(&ch->lock, flags);
602
603 return ret;
604}
605
606static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag)
607{
608 unsigned long flags;
609 unsigned long f;
610
611 raw_spin_lock_irqsave(&ch->lock, flags);
612
613 f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
614 ch->flags &= ~flag;
615
616 if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) {
617 sh_cmt_disable(ch);
618 if (flag & FLAG_CLOCKEVENT)
619 pm_runtime_put(&ch->cmt->pdev->dev);
620 }
621
622 /* adjust the timeout to maximum if only clocksource left */
623 if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE))
624 __sh_cmt_set_next(ch, ch->max_match_value);
625
626 raw_spin_unlock_irqrestore(&ch->lock, flags);
627
628 if (flag & FLAG_CLOCKSOURCE)
629 pm_runtime_put(&ch->cmt->pdev->dev);
630}
631
632static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs)
633{
634 return container_of(cs, struct sh_cmt_channel, cs);
635}
636
637static u64 sh_cmt_clocksource_read(struct clocksource *cs)
638{
639 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
640 u32 has_wrapped;
641
642 if (ch->cmt->num_channels == 1) {
643 unsigned long flags;
644 u64 value;
645 u32 raw;
646
647 raw_spin_lock_irqsave(&ch->lock, flags);
648 value = ch->total_cycles;
649 raw = sh_cmt_get_counter(ch, &has_wrapped);
650
651 if (unlikely(has_wrapped))
652 raw += ch->match_value + 1;
653 raw_spin_unlock_irqrestore(&ch->lock, flags);
654
655 return value + raw;
656 }
657
658 return sh_cmt_get_counter(ch, &has_wrapped);
659}
660
661static int sh_cmt_clocksource_enable(struct clocksource *cs)
662{
663 int ret;
664 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
665
666 WARN_ON(ch->cs_enabled);
667
668 ch->total_cycles = 0;
669
670 ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE);
671 if (!ret)
672 ch->cs_enabled = true;
673
674 return ret;
675}
676
677static void sh_cmt_clocksource_disable(struct clocksource *cs)
678{
679 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
680
681 WARN_ON(!ch->cs_enabled);
682
683 sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
684 ch->cs_enabled = false;
685}
686
687static void sh_cmt_clocksource_suspend(struct clocksource *cs)
688{
689 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
690
691 if (!ch->cs_enabled)
692 return;
693
694 sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
695 dev_pm_genpd_suspend(&ch->cmt->pdev->dev);
696}
697
698static void sh_cmt_clocksource_resume(struct clocksource *cs)
699{
700 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
701
702 if (!ch->cs_enabled)
703 return;
704
705 dev_pm_genpd_resume(&ch->cmt->pdev->dev);
706 sh_cmt_start(ch, FLAG_CLOCKSOURCE);
707}
708
709static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch,
710 const char *name)
711{
712 struct clocksource *cs = &ch->cs;
713
714 cs->name = name;
715 cs->rating = 125;
716 cs->read = sh_cmt_clocksource_read;
717 cs->enable = sh_cmt_clocksource_enable;
718 cs->disable = sh_cmt_clocksource_disable;
719 cs->suspend = sh_cmt_clocksource_suspend;
720 cs->resume = sh_cmt_clocksource_resume;
721 cs->mask = CLOCKSOURCE_MASK(ch->cmt->info->width);
722 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
723
724 dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",
725 ch->index);
726
727 clocksource_register_hz(cs, ch->cmt->rate);
728 return 0;
729}
730
731static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced)
732{
733 return container_of(ced, struct sh_cmt_channel, ced);
734}
735
736static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic)
737{
738 sh_cmt_start(ch, FLAG_CLOCKEVENT);
739
740 if (periodic)
741 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1);
742 else
743 sh_cmt_set_next(ch, ch->max_match_value);
744}
745
746static int sh_cmt_clock_event_shutdown(struct clock_event_device *ced)
747{
748 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
749
750 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
751 return 0;
752}
753
754static int sh_cmt_clock_event_set_state(struct clock_event_device *ced,
755 int periodic)
756{
757 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
758
759 /* deal with old setting first */
760 if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
761 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
762
763 dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n",
764 ch->index, periodic ? "periodic" : "oneshot");
765 sh_cmt_clock_event_start(ch, periodic);
766 return 0;
767}
768
769static int sh_cmt_clock_event_set_oneshot(struct clock_event_device *ced)
770{
771 return sh_cmt_clock_event_set_state(ced, 0);
772}
773
774static int sh_cmt_clock_event_set_periodic(struct clock_event_device *ced)
775{
776 return sh_cmt_clock_event_set_state(ced, 1);
777}
778
779static int sh_cmt_clock_event_next(unsigned long delta,
780 struct clock_event_device *ced)
781{
782 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
783
784 BUG_ON(!clockevent_state_oneshot(ced));
785 if (likely(ch->flags & FLAG_IRQCONTEXT))
786 ch->next_match_value = delta - 1;
787 else
788 sh_cmt_set_next(ch, delta - 1);
789
790 return 0;
791}
792
793static void sh_cmt_clock_event_suspend(struct clock_event_device *ced)
794{
795 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
796
797 dev_pm_genpd_suspend(&ch->cmt->pdev->dev);
798 clk_unprepare(ch->cmt->clk);
799}
800
801static void sh_cmt_clock_event_resume(struct clock_event_device *ced)
802{
803 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
804
805 clk_prepare(ch->cmt->clk);
806 dev_pm_genpd_resume(&ch->cmt->pdev->dev);
807}
808
809static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch,
810 const char *name)
811{
812 struct clock_event_device *ced = &ch->ced;
813 int irq;
814 int ret;
815
816 irq = platform_get_irq(ch->cmt->pdev, ch->index);
817 if (irq < 0)
818 return irq;
819
820 ret = request_irq(irq, sh_cmt_interrupt,
821 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
822 dev_name(&ch->cmt->pdev->dev), ch);
823 if (ret) {
824 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n",
825 ch->index, irq);
826 return ret;
827 }
828
829 ced->name = name;
830 ced->features = CLOCK_EVT_FEAT_PERIODIC;
831 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
832 ced->rating = 125;
833 ced->cpumask = cpu_possible_mask;
834 ced->set_next_event = sh_cmt_clock_event_next;
835 ced->set_state_shutdown = sh_cmt_clock_event_shutdown;
836 ced->set_state_periodic = sh_cmt_clock_event_set_periodic;
837 ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot;
838 ced->suspend = sh_cmt_clock_event_suspend;
839 ced->resume = sh_cmt_clock_event_resume;
840
841 /* TODO: calculate good shift from rate and counter bit width */
842 ced->shift = 32;
843 ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift);
844 ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced);
845 ced->max_delta_ticks = ch->max_match_value;
846 ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
847 ced->min_delta_ticks = 0x1f;
848
849 dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n",
850 ch->index);
851 clockevents_register_device(ced);
852
853 return 0;
854}
855
856static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name,
857 bool clockevent, bool clocksource)
858{
859 int ret;
860
861 if (clockevent) {
862 ch->cmt->has_clockevent = true;
863 ret = sh_cmt_register_clockevent(ch, name);
864 if (ret < 0)
865 return ret;
866 }
867
868 if (clocksource) {
869 ch->cmt->has_clocksource = true;
870 sh_cmt_register_clocksource(ch, name);
871 }
872
873 return 0;
874}
875
876static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
877 unsigned int hwidx, bool clockevent,
878 bool clocksource, struct sh_cmt_device *cmt)
879{
880 u32 value;
881 int ret;
882
883 /* Skip unused channels. */
884 if (!clockevent && !clocksource)
885 return 0;
886
887 ch->cmt = cmt;
888 ch->index = index;
889 ch->hwidx = hwidx;
890 ch->timer_bit = hwidx;
891
892 /*
893 * Compute the address of the channel control register block. For the
894 * timers with a per-channel start/stop register, compute its address
895 * as well.
896 */
897 switch (cmt->info->model) {
898 case SH_CMT_16BIT:
899 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
900 break;
901 case SH_CMT_32BIT:
902 case SH_CMT_48BIT:
903 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
904 break;
905 case SH_CMT0_RCAR_GEN2:
906 case SH_CMT1_RCAR_GEN2:
907 ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
908 ch->ioctrl = ch->iostart + 0x10;
909 ch->timer_bit = 0;
910
911 /* Enable the clock supply to the channel */
912 value = ioread32(cmt->mapbase + CMCLKE);
913 value |= BIT(hwidx);
914 iowrite32(value, cmt->mapbase + CMCLKE);
915 break;
916 }
917
918 if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
919 ch->max_match_value = ~0;
920 else
921 ch->max_match_value = (1 << cmt->info->width) - 1;
922
923 ch->match_value = ch->max_match_value;
924 raw_spin_lock_init(&ch->lock);
925
926 ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
927 clockevent, clocksource);
928 if (ret) {
929 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n",
930 ch->index);
931 return ret;
932 }
933 ch->cs_enabled = false;
934
935 return 0;
936}
937
938static int sh_cmt_map_memory(struct sh_cmt_device *cmt)
939{
940 struct resource *mem;
941
942 mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);
943 if (!mem) {
944 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");
945 return -ENXIO;
946 }
947
948 cmt->mapbase = ioremap(mem->start, resource_size(mem));
949 if (cmt->mapbase == NULL) {
950 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
951 return -ENXIO;
952 }
953
954 return 0;
955}
956
957static const struct platform_device_id sh_cmt_id_table[] = {
958 { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
959 { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
960 { }
961};
962MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
963
964static const struct of_device_id sh_cmt_of_table[] __maybe_unused = {
965 {
966 /* deprecated, preserved for backward compatibility */
967 .compatible = "renesas,cmt-48",
968 .data = &sh_cmt_info[SH_CMT_48BIT]
969 },
970 {
971 /* deprecated, preserved for backward compatibility */
972 .compatible = "renesas,cmt-48-gen2",
973 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
974 },
975 {
976 .compatible = "renesas,r8a7740-cmt1",
977 .data = &sh_cmt_info[SH_CMT_48BIT]
978 },
979 {
980 .compatible = "renesas,sh73a0-cmt1",
981 .data = &sh_cmt_info[SH_CMT_48BIT]
982 },
983 {
984 .compatible = "renesas,rcar-gen2-cmt0",
985 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
986 },
987 {
988 .compatible = "renesas,rcar-gen2-cmt1",
989 .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2]
990 },
991 {
992 .compatible = "renesas,rcar-gen3-cmt0",
993 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
994 },
995 {
996 .compatible = "renesas,rcar-gen3-cmt1",
997 .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2]
998 },
999 {
1000 .compatible = "renesas,rcar-gen4-cmt0",
1001 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
1002 },
1003 {
1004 .compatible = "renesas,rcar-gen4-cmt1",
1005 .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2]
1006 },
1007 { }
1008};
1009MODULE_DEVICE_TABLE(of, sh_cmt_of_table);
1010
1011static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
1012{
1013 unsigned int mask, i;
1014 unsigned long rate;
1015 int ret;
1016
1017 cmt->pdev = pdev;
1018 raw_spin_lock_init(&cmt->lock);
1019
1020 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
1021 cmt->info = of_device_get_match_data(&pdev->dev);
1022 cmt->hw_channels = cmt->info->channels_mask;
1023 } else if (pdev->dev.platform_data) {
1024 struct sh_timer_config *cfg = pdev->dev.platform_data;
1025 const struct platform_device_id *id = pdev->id_entry;
1026
1027 cmt->info = (const struct sh_cmt_info *)id->driver_data;
1028 cmt->hw_channels = cfg->channels_mask;
1029 } else {
1030 dev_err(&cmt->pdev->dev, "missing platform data\n");
1031 return -ENXIO;
1032 }
1033
1034 /* Get hold of clock. */
1035 cmt->clk = clk_get(&cmt->pdev->dev, "fck");
1036 if (IS_ERR(cmt->clk)) {
1037 dev_err(&cmt->pdev->dev, "cannot get clock\n");
1038 return PTR_ERR(cmt->clk);
1039 }
1040
1041 ret = clk_prepare(cmt->clk);
1042 if (ret < 0)
1043 goto err_clk_put;
1044
1045 /* Determine clock rate. */
1046 ret = clk_enable(cmt->clk);
1047 if (ret < 0)
1048 goto err_clk_unprepare;
1049
1050 rate = clk_get_rate(cmt->clk);
1051 if (!rate) {
1052 ret = -EINVAL;
1053 goto err_clk_disable;
1054 }
1055
1056 /* We shall wait 2 input clks after register writes */
1057 if (cmt->info->model >= SH_CMT_48BIT)
1058 cmt->reg_delay = DIV_ROUND_UP(2UL * USEC_PER_SEC, rate);
1059 cmt->rate = rate / (cmt->info->width == 16 ? 512 : 8);
1060
1061 /* Map the memory resource(s). */
1062 ret = sh_cmt_map_memory(cmt);
1063 if (ret < 0)
1064 goto err_clk_disable;
1065
1066 /* Allocate and setup the channels. */
1067 cmt->num_channels = hweight8(cmt->hw_channels);
1068 cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels),
1069 GFP_KERNEL);
1070 if (cmt->channels == NULL) {
1071 ret = -ENOMEM;
1072 goto err_unmap;
1073 }
1074
1075 /*
1076 * Use the first channel as a clock event device and the second channel
1077 * as a clock source. If only one channel is available use it for both.
1078 */
1079 for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) {
1080 unsigned int hwidx = ffs(mask) - 1;
1081 bool clocksource = i == 1 || cmt->num_channels == 1;
1082 bool clockevent = i == 0;
1083
1084 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,
1085 clockevent, clocksource, cmt);
1086 if (ret < 0)
1087 goto err_unmap;
1088
1089 mask &= ~(1 << hwidx);
1090 }
1091
1092 clk_disable(cmt->clk);
1093
1094 platform_set_drvdata(pdev, cmt);
1095
1096 return 0;
1097
1098err_unmap:
1099 kfree(cmt->channels);
1100 iounmap(cmt->mapbase);
1101err_clk_disable:
1102 clk_disable(cmt->clk);
1103err_clk_unprepare:
1104 clk_unprepare(cmt->clk);
1105err_clk_put:
1106 clk_put(cmt->clk);
1107 return ret;
1108}
1109
1110static int sh_cmt_probe(struct platform_device *pdev)
1111{
1112 struct sh_cmt_device *cmt = platform_get_drvdata(pdev);
1113 int ret;
1114
1115 if (!is_sh_early_platform_device(pdev)) {
1116 pm_runtime_set_active(&pdev->dev);
1117 pm_runtime_enable(&pdev->dev);
1118 }
1119
1120 if (cmt) {
1121 dev_info(&pdev->dev, "kept as earlytimer\n");
1122 goto out;
1123 }
1124
1125 cmt = kzalloc(sizeof(*cmt), GFP_KERNEL);
1126 if (cmt == NULL)
1127 return -ENOMEM;
1128
1129 ret = sh_cmt_setup(cmt, pdev);
1130 if (ret) {
1131 kfree(cmt);
1132 pm_runtime_idle(&pdev->dev);
1133 return ret;
1134 }
1135 if (is_sh_early_platform_device(pdev))
1136 return 0;
1137
1138 out:
1139 if (cmt->has_clockevent || cmt->has_clocksource)
1140 pm_runtime_irq_safe(&pdev->dev);
1141 else
1142 pm_runtime_idle(&pdev->dev);
1143
1144 return 0;
1145}
1146
1147static struct platform_driver sh_cmt_device_driver = {
1148 .probe = sh_cmt_probe,
1149 .driver = {
1150 .name = "sh_cmt",
1151 .of_match_table = of_match_ptr(sh_cmt_of_table),
1152 .suppress_bind_attrs = true,
1153 },
1154 .id_table = sh_cmt_id_table,
1155};
1156
1157static int __init sh_cmt_init(void)
1158{
1159 return platform_driver_register(&sh_cmt_device_driver);
1160}
1161
1162static void __exit sh_cmt_exit(void)
1163{
1164 platform_driver_unregister(&sh_cmt_device_driver);
1165}
1166
1167#ifdef CONFIG_SUPERH
1168sh_early_platform_init("earlytimer", &sh_cmt_device_driver);
1169#endif
1170
1171subsys_initcall(sh_cmt_init);
1172module_exit(sh_cmt_exit);
1173
1174MODULE_AUTHOR("Magnus Damm");
1175MODULE_DESCRIPTION("SuperH CMT Timer Driver");