Loading...
1/*
2 * SuperH Timer Support - CMT
3 *
4 * Copyright (C) 2008 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/io.h>
26#include <linux/clk.h>
27#include <linux/irq.h>
28#include <linux/err.h>
29#include <linux/delay.h>
30#include <linux/clocksource.h>
31#include <linux/clockchips.h>
32#include <linux/sh_timer.h>
33#include <linux/slab.h>
34
35struct sh_cmt_priv {
36 void __iomem *mapbase;
37 struct clk *clk;
38 unsigned long width; /* 16 or 32 bit version of hardware block */
39 unsigned long overflow_bit;
40 unsigned long clear_bits;
41 struct irqaction irqaction;
42 struct platform_device *pdev;
43
44 unsigned long flags;
45 unsigned long match_value;
46 unsigned long next_match_value;
47 unsigned long max_match_value;
48 unsigned long rate;
49 spinlock_t lock;
50 struct clock_event_device ced;
51 struct clocksource cs;
52 unsigned long total_cycles;
53};
54
55static DEFINE_SPINLOCK(sh_cmt_lock);
56
57#define CMSTR -1 /* shared register */
58#define CMCSR 0 /* channel register */
59#define CMCNT 1 /* channel register */
60#define CMCOR 2 /* channel register */
61
62static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr)
63{
64 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
65 void __iomem *base = p->mapbase;
66 unsigned long offs;
67
68 if (reg_nr == CMSTR) {
69 offs = 0;
70 base -= cfg->channel_offset;
71 } else
72 offs = reg_nr;
73
74 if (p->width == 16)
75 offs <<= 1;
76 else {
77 offs <<= 2;
78 if ((reg_nr == CMCNT) || (reg_nr == CMCOR))
79 return ioread32(base + offs);
80 }
81
82 return ioread16(base + offs);
83}
84
85static inline void sh_cmt_write(struct sh_cmt_priv *p, int reg_nr,
86 unsigned long value)
87{
88 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
89 void __iomem *base = p->mapbase;
90 unsigned long offs;
91
92 if (reg_nr == CMSTR) {
93 offs = 0;
94 base -= cfg->channel_offset;
95 } else
96 offs = reg_nr;
97
98 if (p->width == 16)
99 offs <<= 1;
100 else {
101 offs <<= 2;
102 if ((reg_nr == CMCNT) || (reg_nr == CMCOR)) {
103 iowrite32(value, base + offs);
104 return;
105 }
106 }
107
108 iowrite16(value, base + offs);
109}
110
111static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p,
112 int *has_wrapped)
113{
114 unsigned long v1, v2, v3;
115 int o1, o2;
116
117 o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
118
119 /* Make sure the timer value is stable. Stolen from acpi_pm.c */
120 do {
121 o2 = o1;
122 v1 = sh_cmt_read(p, CMCNT);
123 v2 = sh_cmt_read(p, CMCNT);
124 v3 = sh_cmt_read(p, CMCNT);
125 o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
126 } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
127 || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
128
129 *has_wrapped = o1;
130 return v2;
131}
132
133
134static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
135{
136 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
137 unsigned long flags, value;
138
139 /* start stop register shared by multiple timer channels */
140 spin_lock_irqsave(&sh_cmt_lock, flags);
141 value = sh_cmt_read(p, CMSTR);
142
143 if (start)
144 value |= 1 << cfg->timer_bit;
145 else
146 value &= ~(1 << cfg->timer_bit);
147
148 sh_cmt_write(p, CMSTR, value);
149 spin_unlock_irqrestore(&sh_cmt_lock, flags);
150}
151
152static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
153{
154 int k, ret;
155
156 /* enable clock */
157 ret = clk_enable(p->clk);
158 if (ret) {
159 dev_err(&p->pdev->dev, "cannot enable clock\n");
160 goto err0;
161 }
162
163 /* make sure channel is disabled */
164 sh_cmt_start_stop_ch(p, 0);
165
166 /* configure channel, periodic mode and maximum timeout */
167 if (p->width == 16) {
168 *rate = clk_get_rate(p->clk) / 512;
169 sh_cmt_write(p, CMCSR, 0x43);
170 } else {
171 *rate = clk_get_rate(p->clk) / 8;
172 sh_cmt_write(p, CMCSR, 0x01a4);
173 }
174
175 sh_cmt_write(p, CMCOR, 0xffffffff);
176 sh_cmt_write(p, CMCNT, 0);
177
178 /*
179 * According to the sh73a0 user's manual, as CMCNT can be operated
180 * only by the RCLK (Pseudo 32 KHz), there's one restriction on
181 * modifying CMCNT register; two RCLK cycles are necessary before
182 * this register is either read or any modification of the value
183 * it holds is reflected in the LSI's actual operation.
184 *
185 * While at it, we're supposed to clear out the CMCNT as of this
186 * moment, so make sure it's processed properly here. This will
187 * take RCLKx2 at maximum.
188 */
189 for (k = 0; k < 100; k++) {
190 if (!sh_cmt_read(p, CMCNT))
191 break;
192 udelay(1);
193 }
194
195 if (sh_cmt_read(p, CMCNT)) {
196 dev_err(&p->pdev->dev, "cannot clear CMCNT\n");
197 ret = -ETIMEDOUT;
198 goto err1;
199 }
200
201 /* enable channel */
202 sh_cmt_start_stop_ch(p, 1);
203 return 0;
204 err1:
205 /* stop clock */
206 clk_disable(p->clk);
207
208 err0:
209 return ret;
210}
211
212static void sh_cmt_disable(struct sh_cmt_priv *p)
213{
214 /* disable channel */
215 sh_cmt_start_stop_ch(p, 0);
216
217 /* disable interrupts in CMT block */
218 sh_cmt_write(p, CMCSR, 0);
219
220 /* stop clock */
221 clk_disable(p->clk);
222}
223
224/* private flags */
225#define FLAG_CLOCKEVENT (1 << 0)
226#define FLAG_CLOCKSOURCE (1 << 1)
227#define FLAG_REPROGRAM (1 << 2)
228#define FLAG_SKIPEVENT (1 << 3)
229#define FLAG_IRQCONTEXT (1 << 4)
230
231static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv *p,
232 int absolute)
233{
234 unsigned long new_match;
235 unsigned long value = p->next_match_value;
236 unsigned long delay = 0;
237 unsigned long now = 0;
238 int has_wrapped;
239
240 now = sh_cmt_get_counter(p, &has_wrapped);
241 p->flags |= FLAG_REPROGRAM; /* force reprogram */
242
243 if (has_wrapped) {
244 /* we're competing with the interrupt handler.
245 * -> let the interrupt handler reprogram the timer.
246 * -> interrupt number two handles the event.
247 */
248 p->flags |= FLAG_SKIPEVENT;
249 return;
250 }
251
252 if (absolute)
253 now = 0;
254
255 do {
256 /* reprogram the timer hardware,
257 * but don't save the new match value yet.
258 */
259 new_match = now + value + delay;
260 if (new_match > p->max_match_value)
261 new_match = p->max_match_value;
262
263 sh_cmt_write(p, CMCOR, new_match);
264
265 now = sh_cmt_get_counter(p, &has_wrapped);
266 if (has_wrapped && (new_match > p->match_value)) {
267 /* we are changing to a greater match value,
268 * so this wrap must be caused by the counter
269 * matching the old value.
270 * -> first interrupt reprograms the timer.
271 * -> interrupt number two handles the event.
272 */
273 p->flags |= FLAG_SKIPEVENT;
274 break;
275 }
276
277 if (has_wrapped) {
278 /* we are changing to a smaller match value,
279 * so the wrap must be caused by the counter
280 * matching the new value.
281 * -> save programmed match value.
282 * -> let isr handle the event.
283 */
284 p->match_value = new_match;
285 break;
286 }
287
288 /* be safe: verify hardware settings */
289 if (now < new_match) {
290 /* timer value is below match value, all good.
291 * this makes sure we won't miss any match events.
292 * -> save programmed match value.
293 * -> let isr handle the event.
294 */
295 p->match_value = new_match;
296 break;
297 }
298
299 /* the counter has reached a value greater
300 * than our new match value. and since the
301 * has_wrapped flag isn't set we must have
302 * programmed a too close event.
303 * -> increase delay and retry.
304 */
305 if (delay)
306 delay <<= 1;
307 else
308 delay = 1;
309
310 if (!delay)
311 dev_warn(&p->pdev->dev, "too long delay\n");
312
313 } while (delay);
314}
315
316static void __sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta)
317{
318 if (delta > p->max_match_value)
319 dev_warn(&p->pdev->dev, "delta out of range\n");
320
321 p->next_match_value = delta;
322 sh_cmt_clock_event_program_verify(p, 0);
323}
324
325static void sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta)
326{
327 unsigned long flags;
328
329 spin_lock_irqsave(&p->lock, flags);
330 __sh_cmt_set_next(p, delta);
331 spin_unlock_irqrestore(&p->lock, flags);
332}
333
334static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
335{
336 struct sh_cmt_priv *p = dev_id;
337
338 /* clear flags */
339 sh_cmt_write(p, CMCSR, sh_cmt_read(p, CMCSR) & p->clear_bits);
340
341 /* update clock source counter to begin with if enabled
342 * the wrap flag should be cleared by the timer specific
343 * isr before we end up here.
344 */
345 if (p->flags & FLAG_CLOCKSOURCE)
346 p->total_cycles += p->match_value + 1;
347
348 if (!(p->flags & FLAG_REPROGRAM))
349 p->next_match_value = p->max_match_value;
350
351 p->flags |= FLAG_IRQCONTEXT;
352
353 if (p->flags & FLAG_CLOCKEVENT) {
354 if (!(p->flags & FLAG_SKIPEVENT)) {
355 if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT) {
356 p->next_match_value = p->max_match_value;
357 p->flags |= FLAG_REPROGRAM;
358 }
359
360 p->ced.event_handler(&p->ced);
361 }
362 }
363
364 p->flags &= ~FLAG_SKIPEVENT;
365
366 if (p->flags & FLAG_REPROGRAM) {
367 p->flags &= ~FLAG_REPROGRAM;
368 sh_cmt_clock_event_program_verify(p, 1);
369
370 if (p->flags & FLAG_CLOCKEVENT)
371 if ((p->ced.mode == CLOCK_EVT_MODE_SHUTDOWN)
372 || (p->match_value == p->next_match_value))
373 p->flags &= ~FLAG_REPROGRAM;
374 }
375
376 p->flags &= ~FLAG_IRQCONTEXT;
377
378 return IRQ_HANDLED;
379}
380
381static int sh_cmt_start(struct sh_cmt_priv *p, unsigned long flag)
382{
383 int ret = 0;
384 unsigned long flags;
385
386 spin_lock_irqsave(&p->lock, flags);
387
388 if (!(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
389 ret = sh_cmt_enable(p, &p->rate);
390
391 if (ret)
392 goto out;
393 p->flags |= flag;
394
395 /* setup timeout if no clockevent */
396 if ((flag == FLAG_CLOCKSOURCE) && (!(p->flags & FLAG_CLOCKEVENT)))
397 __sh_cmt_set_next(p, p->max_match_value);
398 out:
399 spin_unlock_irqrestore(&p->lock, flags);
400
401 return ret;
402}
403
404static void sh_cmt_stop(struct sh_cmt_priv *p, unsigned long flag)
405{
406 unsigned long flags;
407 unsigned long f;
408
409 spin_lock_irqsave(&p->lock, flags);
410
411 f = p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
412 p->flags &= ~flag;
413
414 if (f && !(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
415 sh_cmt_disable(p);
416
417 /* adjust the timeout to maximum if only clocksource left */
418 if ((flag == FLAG_CLOCKEVENT) && (p->flags & FLAG_CLOCKSOURCE))
419 __sh_cmt_set_next(p, p->max_match_value);
420
421 spin_unlock_irqrestore(&p->lock, flags);
422}
423
424static struct sh_cmt_priv *cs_to_sh_cmt(struct clocksource *cs)
425{
426 return container_of(cs, struct sh_cmt_priv, cs);
427}
428
429static cycle_t sh_cmt_clocksource_read(struct clocksource *cs)
430{
431 struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
432 unsigned long flags, raw;
433 unsigned long value;
434 int has_wrapped;
435
436 spin_lock_irqsave(&p->lock, flags);
437 value = p->total_cycles;
438 raw = sh_cmt_get_counter(p, &has_wrapped);
439
440 if (unlikely(has_wrapped))
441 raw += p->match_value + 1;
442 spin_unlock_irqrestore(&p->lock, flags);
443
444 return value + raw;
445}
446
447static int sh_cmt_clocksource_enable(struct clocksource *cs)
448{
449 int ret;
450 struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
451
452 p->total_cycles = 0;
453
454 ret = sh_cmt_start(p, FLAG_CLOCKSOURCE);
455 if (!ret)
456 __clocksource_updatefreq_hz(cs, p->rate);
457 return ret;
458}
459
460static void sh_cmt_clocksource_disable(struct clocksource *cs)
461{
462 sh_cmt_stop(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE);
463}
464
465static void sh_cmt_clocksource_resume(struct clocksource *cs)
466{
467 sh_cmt_start(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE);
468}
469
470static int sh_cmt_register_clocksource(struct sh_cmt_priv *p,
471 char *name, unsigned long rating)
472{
473 struct clocksource *cs = &p->cs;
474
475 cs->name = name;
476 cs->rating = rating;
477 cs->read = sh_cmt_clocksource_read;
478 cs->enable = sh_cmt_clocksource_enable;
479 cs->disable = sh_cmt_clocksource_disable;
480 cs->suspend = sh_cmt_clocksource_disable;
481 cs->resume = sh_cmt_clocksource_resume;
482 cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
483 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
484
485 dev_info(&p->pdev->dev, "used as clock source\n");
486
487 /* Register with dummy 1 Hz value, gets updated in ->enable() */
488 clocksource_register_hz(cs, 1);
489 return 0;
490}
491
492static struct sh_cmt_priv *ced_to_sh_cmt(struct clock_event_device *ced)
493{
494 return container_of(ced, struct sh_cmt_priv, ced);
495}
496
497static void sh_cmt_clock_event_start(struct sh_cmt_priv *p, int periodic)
498{
499 struct clock_event_device *ced = &p->ced;
500
501 sh_cmt_start(p, FLAG_CLOCKEVENT);
502
503 /* TODO: calculate good shift from rate and counter bit width */
504
505 ced->shift = 32;
506 ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
507 ced->max_delta_ns = clockevent_delta2ns(p->max_match_value, ced);
508 ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
509
510 if (periodic)
511 sh_cmt_set_next(p, ((p->rate + HZ/2) / HZ) - 1);
512 else
513 sh_cmt_set_next(p, p->max_match_value);
514}
515
516static void sh_cmt_clock_event_mode(enum clock_event_mode mode,
517 struct clock_event_device *ced)
518{
519 struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
520
521 /* deal with old setting first */
522 switch (ced->mode) {
523 case CLOCK_EVT_MODE_PERIODIC:
524 case CLOCK_EVT_MODE_ONESHOT:
525 sh_cmt_stop(p, FLAG_CLOCKEVENT);
526 break;
527 default:
528 break;
529 }
530
531 switch (mode) {
532 case CLOCK_EVT_MODE_PERIODIC:
533 dev_info(&p->pdev->dev, "used for periodic clock events\n");
534 sh_cmt_clock_event_start(p, 1);
535 break;
536 case CLOCK_EVT_MODE_ONESHOT:
537 dev_info(&p->pdev->dev, "used for oneshot clock events\n");
538 sh_cmt_clock_event_start(p, 0);
539 break;
540 case CLOCK_EVT_MODE_SHUTDOWN:
541 case CLOCK_EVT_MODE_UNUSED:
542 sh_cmt_stop(p, FLAG_CLOCKEVENT);
543 break;
544 default:
545 break;
546 }
547}
548
549static int sh_cmt_clock_event_next(unsigned long delta,
550 struct clock_event_device *ced)
551{
552 struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
553
554 BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
555 if (likely(p->flags & FLAG_IRQCONTEXT))
556 p->next_match_value = delta - 1;
557 else
558 sh_cmt_set_next(p, delta - 1);
559
560 return 0;
561}
562
563static void sh_cmt_register_clockevent(struct sh_cmt_priv *p,
564 char *name, unsigned long rating)
565{
566 struct clock_event_device *ced = &p->ced;
567
568 memset(ced, 0, sizeof(*ced));
569
570 ced->name = name;
571 ced->features = CLOCK_EVT_FEAT_PERIODIC;
572 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
573 ced->rating = rating;
574 ced->cpumask = cpumask_of(0);
575 ced->set_next_event = sh_cmt_clock_event_next;
576 ced->set_mode = sh_cmt_clock_event_mode;
577
578 dev_info(&p->pdev->dev, "used for clock events\n");
579 clockevents_register_device(ced);
580}
581
582static int sh_cmt_register(struct sh_cmt_priv *p, char *name,
583 unsigned long clockevent_rating,
584 unsigned long clocksource_rating)
585{
586 if (p->width == (sizeof(p->max_match_value) * 8))
587 p->max_match_value = ~0;
588 else
589 p->max_match_value = (1 << p->width) - 1;
590
591 p->match_value = p->max_match_value;
592 spin_lock_init(&p->lock);
593
594 if (clockevent_rating)
595 sh_cmt_register_clockevent(p, name, clockevent_rating);
596
597 if (clocksource_rating)
598 sh_cmt_register_clocksource(p, name, clocksource_rating);
599
600 return 0;
601}
602
603static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
604{
605 struct sh_timer_config *cfg = pdev->dev.platform_data;
606 struct resource *res;
607 int irq, ret;
608 ret = -ENXIO;
609
610 memset(p, 0, sizeof(*p));
611 p->pdev = pdev;
612
613 if (!cfg) {
614 dev_err(&p->pdev->dev, "missing platform data\n");
615 goto err0;
616 }
617
618 platform_set_drvdata(pdev, p);
619
620 res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
621 if (!res) {
622 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
623 goto err0;
624 }
625
626 irq = platform_get_irq(p->pdev, 0);
627 if (irq < 0) {
628 dev_err(&p->pdev->dev, "failed to get irq\n");
629 goto err0;
630 }
631
632 /* map memory, let mapbase point to our channel */
633 p->mapbase = ioremap_nocache(res->start, resource_size(res));
634 if (p->mapbase == NULL) {
635 dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
636 goto err0;
637 }
638
639 /* request irq using setup_irq() (too early for request_irq()) */
640 p->irqaction.name = dev_name(&p->pdev->dev);
641 p->irqaction.handler = sh_cmt_interrupt;
642 p->irqaction.dev_id = p;
643 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
644 IRQF_IRQPOLL | IRQF_NOBALANCING;
645
646 /* get hold of clock */
647 p->clk = clk_get(&p->pdev->dev, "cmt_fck");
648 if (IS_ERR(p->clk)) {
649 dev_err(&p->pdev->dev, "cannot get clock\n");
650 ret = PTR_ERR(p->clk);
651 goto err1;
652 }
653
654 if (resource_size(res) == 6) {
655 p->width = 16;
656 p->overflow_bit = 0x80;
657 p->clear_bits = ~0x80;
658 } else {
659 p->width = 32;
660 p->overflow_bit = 0x8000;
661 p->clear_bits = ~0xc000;
662 }
663
664 ret = sh_cmt_register(p, (char *)dev_name(&p->pdev->dev),
665 cfg->clockevent_rating,
666 cfg->clocksource_rating);
667 if (ret) {
668 dev_err(&p->pdev->dev, "registration failed\n");
669 goto err1;
670 }
671
672 ret = setup_irq(irq, &p->irqaction);
673 if (ret) {
674 dev_err(&p->pdev->dev, "failed to request irq %d\n", irq);
675 goto err1;
676 }
677
678 return 0;
679
680err1:
681 iounmap(p->mapbase);
682err0:
683 return ret;
684}
685
686static int __devinit sh_cmt_probe(struct platform_device *pdev)
687{
688 struct sh_cmt_priv *p = platform_get_drvdata(pdev);
689 int ret;
690
691 if (p) {
692 dev_info(&pdev->dev, "kept as earlytimer\n");
693 return 0;
694 }
695
696 p = kmalloc(sizeof(*p), GFP_KERNEL);
697 if (p == NULL) {
698 dev_err(&pdev->dev, "failed to allocate driver data\n");
699 return -ENOMEM;
700 }
701
702 ret = sh_cmt_setup(p, pdev);
703 if (ret) {
704 kfree(p);
705 platform_set_drvdata(pdev, NULL);
706 }
707 return ret;
708}
709
710static int __devexit sh_cmt_remove(struct platform_device *pdev)
711{
712 return -EBUSY; /* cannot unregister clockevent and clocksource */
713}
714
715static struct platform_driver sh_cmt_device_driver = {
716 .probe = sh_cmt_probe,
717 .remove = __devexit_p(sh_cmt_remove),
718 .driver = {
719 .name = "sh_cmt",
720 }
721};
722
723static int __init sh_cmt_init(void)
724{
725 return platform_driver_register(&sh_cmt_device_driver);
726}
727
728static void __exit sh_cmt_exit(void)
729{
730 platform_driver_unregister(&sh_cmt_device_driver);
731}
732
733early_platform_init("earlytimer", &sh_cmt_device_driver);
734module_init(sh_cmt_init);
735module_exit(sh_cmt_exit);
736
737MODULE_AUTHOR("Magnus Damm");
738MODULE_DESCRIPTION("SuperH CMT Timer Driver");
739MODULE_LICENSE("GPL v2");
1/*
2 * SuperH Timer Support - CMT
3 *
4 * Copyright (C) 2008 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk.h>
17#include <linux/clockchips.h>
18#include <linux/clocksource.h>
19#include <linux/delay.h>
20#include <linux/err.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
24#include <linux/ioport.h>
25#include <linux/irq.h>
26#include <linux/module.h>
27#include <linux/of.h>
28#include <linux/of_device.h>
29#include <linux/platform_device.h>
30#include <linux/pm_domain.h>
31#include <linux/pm_runtime.h>
32#include <linux/sh_timer.h>
33#include <linux/slab.h>
34#include <linux/spinlock.h>
35
36struct sh_cmt_device;
37
38/*
39 * The CMT comes in 5 different identified flavours, depending not only on the
40 * SoC but also on the particular instance. The following table lists the main
41 * characteristics of those flavours.
42 *
43 * 16B 32B 32B-F 48B R-Car Gen2
44 * -----------------------------------------------------------------------------
45 * Channels 2 1/4 1 6 2/8
46 * Control Width 16 16 16 16 32
47 * Counter Width 16 32 32 32/48 32/48
48 * Shared Start/Stop Y Y Y Y N
49 *
50 * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
51 * located in the channel registers block. All other versions have a shared
52 * start/stop register located in the global space.
53 *
54 * Channels are indexed from 0 to N-1 in the documentation. The channel index
55 * infers the start/stop bit position in the control register and the channel
56 * registers block address. Some CMT instances have a subset of channels
57 * available, in which case the index in the documentation doesn't match the
58 * "real" index as implemented in hardware. This is for instance the case with
59 * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
60 * in the documentation but using start/stop bit 5 and having its registers
61 * block at 0x60.
62 *
63 * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
64 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
65 */
66
67enum sh_cmt_model {
68 SH_CMT_16BIT,
69 SH_CMT_32BIT,
70 SH_CMT_48BIT,
71 SH_CMT0_RCAR_GEN2,
72 SH_CMT1_RCAR_GEN2,
73};
74
75struct sh_cmt_info {
76 enum sh_cmt_model model;
77
78 unsigned int channels_mask;
79
80 unsigned long width; /* 16 or 32 bit version of hardware block */
81 unsigned long overflow_bit;
82 unsigned long clear_bits;
83
84 /* callbacks for CMSTR and CMCSR access */
85 unsigned long (*read_control)(void __iomem *base, unsigned long offs);
86 void (*write_control)(void __iomem *base, unsigned long offs,
87 unsigned long value);
88
89 /* callbacks for CMCNT and CMCOR access */
90 unsigned long (*read_count)(void __iomem *base, unsigned long offs);
91 void (*write_count)(void __iomem *base, unsigned long offs,
92 unsigned long value);
93};
94
95struct sh_cmt_channel {
96 struct sh_cmt_device *cmt;
97
98 unsigned int index; /* Index in the documentation */
99 unsigned int hwidx; /* Real hardware index */
100
101 void __iomem *iostart;
102 void __iomem *ioctrl;
103
104 unsigned int timer_bit;
105 unsigned long flags;
106 unsigned long match_value;
107 unsigned long next_match_value;
108 unsigned long max_match_value;
109 raw_spinlock_t lock;
110 struct clock_event_device ced;
111 struct clocksource cs;
112 unsigned long total_cycles;
113 bool cs_enabled;
114};
115
116struct sh_cmt_device {
117 struct platform_device *pdev;
118
119 const struct sh_cmt_info *info;
120
121 void __iomem *mapbase;
122 struct clk *clk;
123 unsigned long rate;
124
125 raw_spinlock_t lock; /* Protect the shared start/stop register */
126
127 struct sh_cmt_channel *channels;
128 unsigned int num_channels;
129 unsigned int hw_channels;
130
131 bool has_clockevent;
132 bool has_clocksource;
133};
134
135#define SH_CMT16_CMCSR_CMF (1 << 7)
136#define SH_CMT16_CMCSR_CMIE (1 << 6)
137#define SH_CMT16_CMCSR_CKS8 (0 << 0)
138#define SH_CMT16_CMCSR_CKS32 (1 << 0)
139#define SH_CMT16_CMCSR_CKS128 (2 << 0)
140#define SH_CMT16_CMCSR_CKS512 (3 << 0)
141#define SH_CMT16_CMCSR_CKS_MASK (3 << 0)
142
143#define SH_CMT32_CMCSR_CMF (1 << 15)
144#define SH_CMT32_CMCSR_OVF (1 << 14)
145#define SH_CMT32_CMCSR_WRFLG (1 << 13)
146#define SH_CMT32_CMCSR_STTF (1 << 12)
147#define SH_CMT32_CMCSR_STPF (1 << 11)
148#define SH_CMT32_CMCSR_SSIE (1 << 10)
149#define SH_CMT32_CMCSR_CMS (1 << 9)
150#define SH_CMT32_CMCSR_CMM (1 << 8)
151#define SH_CMT32_CMCSR_CMTOUT_IE (1 << 7)
152#define SH_CMT32_CMCSR_CMR_NONE (0 << 4)
153#define SH_CMT32_CMCSR_CMR_DMA (1 << 4)
154#define SH_CMT32_CMCSR_CMR_IRQ (2 << 4)
155#define SH_CMT32_CMCSR_CMR_MASK (3 << 4)
156#define SH_CMT32_CMCSR_DBGIVD (1 << 3)
157#define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0)
158#define SH_CMT32_CMCSR_CKS_RCLK32 (5 << 0)
159#define SH_CMT32_CMCSR_CKS_RCLK128 (6 << 0)
160#define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0)
161#define SH_CMT32_CMCSR_CKS_MASK (7 << 0)
162
163static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs)
164{
165 return ioread16(base + (offs << 1));
166}
167
168static unsigned long sh_cmt_read32(void __iomem *base, unsigned long offs)
169{
170 return ioread32(base + (offs << 2));
171}
172
173static void sh_cmt_write16(void __iomem *base, unsigned long offs,
174 unsigned long value)
175{
176 iowrite16(value, base + (offs << 1));
177}
178
179static void sh_cmt_write32(void __iomem *base, unsigned long offs,
180 unsigned long value)
181{
182 iowrite32(value, base + (offs << 2));
183}
184
185static const struct sh_cmt_info sh_cmt_info[] = {
186 [SH_CMT_16BIT] = {
187 .model = SH_CMT_16BIT,
188 .width = 16,
189 .overflow_bit = SH_CMT16_CMCSR_CMF,
190 .clear_bits = ~SH_CMT16_CMCSR_CMF,
191 .read_control = sh_cmt_read16,
192 .write_control = sh_cmt_write16,
193 .read_count = sh_cmt_read16,
194 .write_count = sh_cmt_write16,
195 },
196 [SH_CMT_32BIT] = {
197 .model = SH_CMT_32BIT,
198 .width = 32,
199 .overflow_bit = SH_CMT32_CMCSR_CMF,
200 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
201 .read_control = sh_cmt_read16,
202 .write_control = sh_cmt_write16,
203 .read_count = sh_cmt_read32,
204 .write_count = sh_cmt_write32,
205 },
206 [SH_CMT_48BIT] = {
207 .model = SH_CMT_48BIT,
208 .channels_mask = 0x3f,
209 .width = 32,
210 .overflow_bit = SH_CMT32_CMCSR_CMF,
211 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
212 .read_control = sh_cmt_read32,
213 .write_control = sh_cmt_write32,
214 .read_count = sh_cmt_read32,
215 .write_count = sh_cmt_write32,
216 },
217 [SH_CMT0_RCAR_GEN2] = {
218 .model = SH_CMT0_RCAR_GEN2,
219 .channels_mask = 0x60,
220 .width = 32,
221 .overflow_bit = SH_CMT32_CMCSR_CMF,
222 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
223 .read_control = sh_cmt_read32,
224 .write_control = sh_cmt_write32,
225 .read_count = sh_cmt_read32,
226 .write_count = sh_cmt_write32,
227 },
228 [SH_CMT1_RCAR_GEN2] = {
229 .model = SH_CMT1_RCAR_GEN2,
230 .channels_mask = 0xff,
231 .width = 32,
232 .overflow_bit = SH_CMT32_CMCSR_CMF,
233 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
234 .read_control = sh_cmt_read32,
235 .write_control = sh_cmt_write32,
236 .read_count = sh_cmt_read32,
237 .write_count = sh_cmt_write32,
238 },
239};
240
241#define CMCSR 0 /* channel register */
242#define CMCNT 1 /* channel register */
243#define CMCOR 2 /* channel register */
244
245static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_channel *ch)
246{
247 if (ch->iostart)
248 return ch->cmt->info->read_control(ch->iostart, 0);
249 else
250 return ch->cmt->info->read_control(ch->cmt->mapbase, 0);
251}
252
253static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch,
254 unsigned long value)
255{
256 if (ch->iostart)
257 ch->cmt->info->write_control(ch->iostart, 0, value);
258 else
259 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);
260}
261
262static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_channel *ch)
263{
264 return ch->cmt->info->read_control(ch->ioctrl, CMCSR);
265}
266
267static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch,
268 unsigned long value)
269{
270 ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);
271}
272
273static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_channel *ch)
274{
275 return ch->cmt->info->read_count(ch->ioctrl, CMCNT);
276}
277
278static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch,
279 unsigned long value)
280{
281 ch->cmt->info->write_count(ch->ioctrl, CMCNT, value);
282}
283
284static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch,
285 unsigned long value)
286{
287 ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);
288}
289
290static unsigned long sh_cmt_get_counter(struct sh_cmt_channel *ch,
291 int *has_wrapped)
292{
293 unsigned long v1, v2, v3;
294 int o1, o2;
295
296 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
297
298 /* Make sure the timer value is stable. Stolen from acpi_pm.c */
299 do {
300 o2 = o1;
301 v1 = sh_cmt_read_cmcnt(ch);
302 v2 = sh_cmt_read_cmcnt(ch);
303 v3 = sh_cmt_read_cmcnt(ch);
304 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
305 } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
306 || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
307
308 *has_wrapped = o1;
309 return v2;
310}
311
312static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start)
313{
314 unsigned long flags, value;
315
316 /* start stop register shared by multiple timer channels */
317 raw_spin_lock_irqsave(&ch->cmt->lock, flags);
318 value = sh_cmt_read_cmstr(ch);
319
320 if (start)
321 value |= 1 << ch->timer_bit;
322 else
323 value &= ~(1 << ch->timer_bit);
324
325 sh_cmt_write_cmstr(ch, value);
326 raw_spin_unlock_irqrestore(&ch->cmt->lock, flags);
327}
328
329static int sh_cmt_enable(struct sh_cmt_channel *ch)
330{
331 int k, ret;
332
333 pm_runtime_get_sync(&ch->cmt->pdev->dev);
334 dev_pm_syscore_device(&ch->cmt->pdev->dev, true);
335
336 /* enable clock */
337 ret = clk_enable(ch->cmt->clk);
338 if (ret) {
339 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n",
340 ch->index);
341 goto err0;
342 }
343
344 /* make sure channel is disabled */
345 sh_cmt_start_stop_ch(ch, 0);
346
347 /* configure channel, periodic mode and maximum timeout */
348 if (ch->cmt->info->width == 16) {
349 sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE |
350 SH_CMT16_CMCSR_CKS512);
351 } else {
352 sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM |
353 SH_CMT32_CMCSR_CMTOUT_IE |
354 SH_CMT32_CMCSR_CMR_IRQ |
355 SH_CMT32_CMCSR_CKS_RCLK8);
356 }
357
358 sh_cmt_write_cmcor(ch, 0xffffffff);
359 sh_cmt_write_cmcnt(ch, 0);
360
361 /*
362 * According to the sh73a0 user's manual, as CMCNT can be operated
363 * only by the RCLK (Pseudo 32 KHz), there's one restriction on
364 * modifying CMCNT register; two RCLK cycles are necessary before
365 * this register is either read or any modification of the value
366 * it holds is reflected in the LSI's actual operation.
367 *
368 * While at it, we're supposed to clear out the CMCNT as of this
369 * moment, so make sure it's processed properly here. This will
370 * take RCLKx2 at maximum.
371 */
372 for (k = 0; k < 100; k++) {
373 if (!sh_cmt_read_cmcnt(ch))
374 break;
375 udelay(1);
376 }
377
378 if (sh_cmt_read_cmcnt(ch)) {
379 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n",
380 ch->index);
381 ret = -ETIMEDOUT;
382 goto err1;
383 }
384
385 /* enable channel */
386 sh_cmt_start_stop_ch(ch, 1);
387 return 0;
388 err1:
389 /* stop clock */
390 clk_disable(ch->cmt->clk);
391
392 err0:
393 return ret;
394}
395
396static void sh_cmt_disable(struct sh_cmt_channel *ch)
397{
398 /* disable channel */
399 sh_cmt_start_stop_ch(ch, 0);
400
401 /* disable interrupts in CMT block */
402 sh_cmt_write_cmcsr(ch, 0);
403
404 /* stop clock */
405 clk_disable(ch->cmt->clk);
406
407 dev_pm_syscore_device(&ch->cmt->pdev->dev, false);
408 pm_runtime_put(&ch->cmt->pdev->dev);
409}
410
411/* private flags */
412#define FLAG_CLOCKEVENT (1 << 0)
413#define FLAG_CLOCKSOURCE (1 << 1)
414#define FLAG_REPROGRAM (1 << 2)
415#define FLAG_SKIPEVENT (1 << 3)
416#define FLAG_IRQCONTEXT (1 << 4)
417
418static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch,
419 int absolute)
420{
421 unsigned long new_match;
422 unsigned long value = ch->next_match_value;
423 unsigned long delay = 0;
424 unsigned long now = 0;
425 int has_wrapped;
426
427 now = sh_cmt_get_counter(ch, &has_wrapped);
428 ch->flags |= FLAG_REPROGRAM; /* force reprogram */
429
430 if (has_wrapped) {
431 /* we're competing with the interrupt handler.
432 * -> let the interrupt handler reprogram the timer.
433 * -> interrupt number two handles the event.
434 */
435 ch->flags |= FLAG_SKIPEVENT;
436 return;
437 }
438
439 if (absolute)
440 now = 0;
441
442 do {
443 /* reprogram the timer hardware,
444 * but don't save the new match value yet.
445 */
446 new_match = now + value + delay;
447 if (new_match > ch->max_match_value)
448 new_match = ch->max_match_value;
449
450 sh_cmt_write_cmcor(ch, new_match);
451
452 now = sh_cmt_get_counter(ch, &has_wrapped);
453 if (has_wrapped && (new_match > ch->match_value)) {
454 /* we are changing to a greater match value,
455 * so this wrap must be caused by the counter
456 * matching the old value.
457 * -> first interrupt reprograms the timer.
458 * -> interrupt number two handles the event.
459 */
460 ch->flags |= FLAG_SKIPEVENT;
461 break;
462 }
463
464 if (has_wrapped) {
465 /* we are changing to a smaller match value,
466 * so the wrap must be caused by the counter
467 * matching the new value.
468 * -> save programmed match value.
469 * -> let isr handle the event.
470 */
471 ch->match_value = new_match;
472 break;
473 }
474
475 /* be safe: verify hardware settings */
476 if (now < new_match) {
477 /* timer value is below match value, all good.
478 * this makes sure we won't miss any match events.
479 * -> save programmed match value.
480 * -> let isr handle the event.
481 */
482 ch->match_value = new_match;
483 break;
484 }
485
486 /* the counter has reached a value greater
487 * than our new match value. and since the
488 * has_wrapped flag isn't set we must have
489 * programmed a too close event.
490 * -> increase delay and retry.
491 */
492 if (delay)
493 delay <<= 1;
494 else
495 delay = 1;
496
497 if (!delay)
498 dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n",
499 ch->index);
500
501 } while (delay);
502}
503
504static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
505{
506 if (delta > ch->max_match_value)
507 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n",
508 ch->index);
509
510 ch->next_match_value = delta;
511 sh_cmt_clock_event_program_verify(ch, 0);
512}
513
514static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
515{
516 unsigned long flags;
517
518 raw_spin_lock_irqsave(&ch->lock, flags);
519 __sh_cmt_set_next(ch, delta);
520 raw_spin_unlock_irqrestore(&ch->lock, flags);
521}
522
523static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
524{
525 struct sh_cmt_channel *ch = dev_id;
526
527 /* clear flags */
528 sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) &
529 ch->cmt->info->clear_bits);
530
531 /* update clock source counter to begin with if enabled
532 * the wrap flag should be cleared by the timer specific
533 * isr before we end up here.
534 */
535 if (ch->flags & FLAG_CLOCKSOURCE)
536 ch->total_cycles += ch->match_value + 1;
537
538 if (!(ch->flags & FLAG_REPROGRAM))
539 ch->next_match_value = ch->max_match_value;
540
541 ch->flags |= FLAG_IRQCONTEXT;
542
543 if (ch->flags & FLAG_CLOCKEVENT) {
544 if (!(ch->flags & FLAG_SKIPEVENT)) {
545 if (clockevent_state_oneshot(&ch->ced)) {
546 ch->next_match_value = ch->max_match_value;
547 ch->flags |= FLAG_REPROGRAM;
548 }
549
550 ch->ced.event_handler(&ch->ced);
551 }
552 }
553
554 ch->flags &= ~FLAG_SKIPEVENT;
555
556 if (ch->flags & FLAG_REPROGRAM) {
557 ch->flags &= ~FLAG_REPROGRAM;
558 sh_cmt_clock_event_program_verify(ch, 1);
559
560 if (ch->flags & FLAG_CLOCKEVENT)
561 if ((clockevent_state_shutdown(&ch->ced))
562 || (ch->match_value == ch->next_match_value))
563 ch->flags &= ~FLAG_REPROGRAM;
564 }
565
566 ch->flags &= ~FLAG_IRQCONTEXT;
567
568 return IRQ_HANDLED;
569}
570
571static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag)
572{
573 int ret = 0;
574 unsigned long flags;
575
576 raw_spin_lock_irqsave(&ch->lock, flags);
577
578 if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
579 ret = sh_cmt_enable(ch);
580
581 if (ret)
582 goto out;
583 ch->flags |= flag;
584
585 /* setup timeout if no clockevent */
586 if ((flag == FLAG_CLOCKSOURCE) && (!(ch->flags & FLAG_CLOCKEVENT)))
587 __sh_cmt_set_next(ch, ch->max_match_value);
588 out:
589 raw_spin_unlock_irqrestore(&ch->lock, flags);
590
591 return ret;
592}
593
594static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag)
595{
596 unsigned long flags;
597 unsigned long f;
598
599 raw_spin_lock_irqsave(&ch->lock, flags);
600
601 f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
602 ch->flags &= ~flag;
603
604 if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
605 sh_cmt_disable(ch);
606
607 /* adjust the timeout to maximum if only clocksource left */
608 if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE))
609 __sh_cmt_set_next(ch, ch->max_match_value);
610
611 raw_spin_unlock_irqrestore(&ch->lock, flags);
612}
613
614static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs)
615{
616 return container_of(cs, struct sh_cmt_channel, cs);
617}
618
619static u64 sh_cmt_clocksource_read(struct clocksource *cs)
620{
621 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
622 unsigned long flags, raw;
623 unsigned long value;
624 int has_wrapped;
625
626 raw_spin_lock_irqsave(&ch->lock, flags);
627 value = ch->total_cycles;
628 raw = sh_cmt_get_counter(ch, &has_wrapped);
629
630 if (unlikely(has_wrapped))
631 raw += ch->match_value + 1;
632 raw_spin_unlock_irqrestore(&ch->lock, flags);
633
634 return value + raw;
635}
636
637static int sh_cmt_clocksource_enable(struct clocksource *cs)
638{
639 int ret;
640 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
641
642 WARN_ON(ch->cs_enabled);
643
644 ch->total_cycles = 0;
645
646 ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE);
647 if (!ret)
648 ch->cs_enabled = true;
649
650 return ret;
651}
652
653static void sh_cmt_clocksource_disable(struct clocksource *cs)
654{
655 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
656
657 WARN_ON(!ch->cs_enabled);
658
659 sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
660 ch->cs_enabled = false;
661}
662
663static void sh_cmt_clocksource_suspend(struct clocksource *cs)
664{
665 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
666
667 if (!ch->cs_enabled)
668 return;
669
670 sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
671 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
672}
673
674static void sh_cmt_clocksource_resume(struct clocksource *cs)
675{
676 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
677
678 if (!ch->cs_enabled)
679 return;
680
681 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
682 sh_cmt_start(ch, FLAG_CLOCKSOURCE);
683}
684
685static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch,
686 const char *name)
687{
688 struct clocksource *cs = &ch->cs;
689
690 cs->name = name;
691 cs->rating = 125;
692 cs->read = sh_cmt_clocksource_read;
693 cs->enable = sh_cmt_clocksource_enable;
694 cs->disable = sh_cmt_clocksource_disable;
695 cs->suspend = sh_cmt_clocksource_suspend;
696 cs->resume = sh_cmt_clocksource_resume;
697 cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
698 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
699
700 dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",
701 ch->index);
702
703 clocksource_register_hz(cs, ch->cmt->rate);
704 return 0;
705}
706
707static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced)
708{
709 return container_of(ced, struct sh_cmt_channel, ced);
710}
711
712static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic)
713{
714 sh_cmt_start(ch, FLAG_CLOCKEVENT);
715
716 if (periodic)
717 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1);
718 else
719 sh_cmt_set_next(ch, ch->max_match_value);
720}
721
722static int sh_cmt_clock_event_shutdown(struct clock_event_device *ced)
723{
724 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
725
726 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
727 return 0;
728}
729
730static int sh_cmt_clock_event_set_state(struct clock_event_device *ced,
731 int periodic)
732{
733 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
734
735 /* deal with old setting first */
736 if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
737 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
738
739 dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n",
740 ch->index, periodic ? "periodic" : "oneshot");
741 sh_cmt_clock_event_start(ch, periodic);
742 return 0;
743}
744
745static int sh_cmt_clock_event_set_oneshot(struct clock_event_device *ced)
746{
747 return sh_cmt_clock_event_set_state(ced, 0);
748}
749
750static int sh_cmt_clock_event_set_periodic(struct clock_event_device *ced)
751{
752 return sh_cmt_clock_event_set_state(ced, 1);
753}
754
755static int sh_cmt_clock_event_next(unsigned long delta,
756 struct clock_event_device *ced)
757{
758 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
759
760 BUG_ON(!clockevent_state_oneshot(ced));
761 if (likely(ch->flags & FLAG_IRQCONTEXT))
762 ch->next_match_value = delta - 1;
763 else
764 sh_cmt_set_next(ch, delta - 1);
765
766 return 0;
767}
768
769static void sh_cmt_clock_event_suspend(struct clock_event_device *ced)
770{
771 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
772
773 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
774 clk_unprepare(ch->cmt->clk);
775}
776
777static void sh_cmt_clock_event_resume(struct clock_event_device *ced)
778{
779 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
780
781 clk_prepare(ch->cmt->clk);
782 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
783}
784
785static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch,
786 const char *name)
787{
788 struct clock_event_device *ced = &ch->ced;
789 int irq;
790 int ret;
791
792 irq = platform_get_irq(ch->cmt->pdev, ch->index);
793 if (irq < 0) {
794 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to get irq\n",
795 ch->index);
796 return irq;
797 }
798
799 ret = request_irq(irq, sh_cmt_interrupt,
800 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
801 dev_name(&ch->cmt->pdev->dev), ch);
802 if (ret) {
803 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n",
804 ch->index, irq);
805 return ret;
806 }
807
808 ced->name = name;
809 ced->features = CLOCK_EVT_FEAT_PERIODIC;
810 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
811 ced->rating = 125;
812 ced->cpumask = cpu_possible_mask;
813 ced->set_next_event = sh_cmt_clock_event_next;
814 ced->set_state_shutdown = sh_cmt_clock_event_shutdown;
815 ced->set_state_periodic = sh_cmt_clock_event_set_periodic;
816 ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot;
817 ced->suspend = sh_cmt_clock_event_suspend;
818 ced->resume = sh_cmt_clock_event_resume;
819
820 /* TODO: calculate good shift from rate and counter bit width */
821 ced->shift = 32;
822 ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift);
823 ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced);
824 ced->max_delta_ticks = ch->max_match_value;
825 ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
826 ced->min_delta_ticks = 0x1f;
827
828 dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n",
829 ch->index);
830 clockevents_register_device(ced);
831
832 return 0;
833}
834
835static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name,
836 bool clockevent, bool clocksource)
837{
838 int ret;
839
840 if (clockevent) {
841 ch->cmt->has_clockevent = true;
842 ret = sh_cmt_register_clockevent(ch, name);
843 if (ret < 0)
844 return ret;
845 }
846
847 if (clocksource) {
848 ch->cmt->has_clocksource = true;
849 sh_cmt_register_clocksource(ch, name);
850 }
851
852 return 0;
853}
854
855static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
856 unsigned int hwidx, bool clockevent,
857 bool clocksource, struct sh_cmt_device *cmt)
858{
859 int ret;
860
861 /* Skip unused channels. */
862 if (!clockevent && !clocksource)
863 return 0;
864
865 ch->cmt = cmt;
866 ch->index = index;
867 ch->hwidx = hwidx;
868 ch->timer_bit = hwidx;
869
870 /*
871 * Compute the address of the channel control register block. For the
872 * timers with a per-channel start/stop register, compute its address
873 * as well.
874 */
875 switch (cmt->info->model) {
876 case SH_CMT_16BIT:
877 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
878 break;
879 case SH_CMT_32BIT:
880 case SH_CMT_48BIT:
881 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
882 break;
883 case SH_CMT0_RCAR_GEN2:
884 case SH_CMT1_RCAR_GEN2:
885 ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
886 ch->ioctrl = ch->iostart + 0x10;
887 ch->timer_bit = 0;
888 break;
889 }
890
891 if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
892 ch->max_match_value = ~0;
893 else
894 ch->max_match_value = (1 << cmt->info->width) - 1;
895
896 ch->match_value = ch->max_match_value;
897 raw_spin_lock_init(&ch->lock);
898
899 ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
900 clockevent, clocksource);
901 if (ret) {
902 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n",
903 ch->index);
904 return ret;
905 }
906 ch->cs_enabled = false;
907
908 return 0;
909}
910
911static int sh_cmt_map_memory(struct sh_cmt_device *cmt)
912{
913 struct resource *mem;
914
915 mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);
916 if (!mem) {
917 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");
918 return -ENXIO;
919 }
920
921 cmt->mapbase = ioremap_nocache(mem->start, resource_size(mem));
922 if (cmt->mapbase == NULL) {
923 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
924 return -ENXIO;
925 }
926
927 return 0;
928}
929
930static const struct platform_device_id sh_cmt_id_table[] = {
931 { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
932 { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
933 { }
934};
935MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
936
937static const struct of_device_id sh_cmt_of_table[] __maybe_unused = {
938 { .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] },
939 {
940 /* deprecated, preserved for backward compatibility */
941 .compatible = "renesas,cmt-48-gen2",
942 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
943 },
944 { .compatible = "renesas,rcar-gen2-cmt0", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] },
945 { .compatible = "renesas,rcar-gen2-cmt1", .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] },
946 { }
947};
948MODULE_DEVICE_TABLE(of, sh_cmt_of_table);
949
950static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
951{
952 unsigned int mask;
953 unsigned int i;
954 int ret;
955
956 cmt->pdev = pdev;
957 raw_spin_lock_init(&cmt->lock);
958
959 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
960 cmt->info = of_device_get_match_data(&pdev->dev);
961 cmt->hw_channels = cmt->info->channels_mask;
962 } else if (pdev->dev.platform_data) {
963 struct sh_timer_config *cfg = pdev->dev.platform_data;
964 const struct platform_device_id *id = pdev->id_entry;
965
966 cmt->info = (const struct sh_cmt_info *)id->driver_data;
967 cmt->hw_channels = cfg->channels_mask;
968 } else {
969 dev_err(&cmt->pdev->dev, "missing platform data\n");
970 return -ENXIO;
971 }
972
973 /* Get hold of clock. */
974 cmt->clk = clk_get(&cmt->pdev->dev, "fck");
975 if (IS_ERR(cmt->clk)) {
976 dev_err(&cmt->pdev->dev, "cannot get clock\n");
977 return PTR_ERR(cmt->clk);
978 }
979
980 ret = clk_prepare(cmt->clk);
981 if (ret < 0)
982 goto err_clk_put;
983
984 /* Determine clock rate. */
985 ret = clk_enable(cmt->clk);
986 if (ret < 0)
987 goto err_clk_unprepare;
988
989 if (cmt->info->width == 16)
990 cmt->rate = clk_get_rate(cmt->clk) / 512;
991 else
992 cmt->rate = clk_get_rate(cmt->clk) / 8;
993
994 clk_disable(cmt->clk);
995
996 /* Map the memory resource(s). */
997 ret = sh_cmt_map_memory(cmt);
998 if (ret < 0)
999 goto err_clk_unprepare;
1000
1001 /* Allocate and setup the channels. */
1002 cmt->num_channels = hweight8(cmt->hw_channels);
1003 cmt->channels = kzalloc(cmt->num_channels * sizeof(*cmt->channels),
1004 GFP_KERNEL);
1005 if (cmt->channels == NULL) {
1006 ret = -ENOMEM;
1007 goto err_unmap;
1008 }
1009
1010 /*
1011 * Use the first channel as a clock event device and the second channel
1012 * as a clock source. If only one channel is available use it for both.
1013 */
1014 for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) {
1015 unsigned int hwidx = ffs(mask) - 1;
1016 bool clocksource = i == 1 || cmt->num_channels == 1;
1017 bool clockevent = i == 0;
1018
1019 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,
1020 clockevent, clocksource, cmt);
1021 if (ret < 0)
1022 goto err_unmap;
1023
1024 mask &= ~(1 << hwidx);
1025 }
1026
1027 platform_set_drvdata(pdev, cmt);
1028
1029 return 0;
1030
1031err_unmap:
1032 kfree(cmt->channels);
1033 iounmap(cmt->mapbase);
1034err_clk_unprepare:
1035 clk_unprepare(cmt->clk);
1036err_clk_put:
1037 clk_put(cmt->clk);
1038 return ret;
1039}
1040
1041static int sh_cmt_probe(struct platform_device *pdev)
1042{
1043 struct sh_cmt_device *cmt = platform_get_drvdata(pdev);
1044 int ret;
1045
1046 if (!is_early_platform_device(pdev)) {
1047 pm_runtime_set_active(&pdev->dev);
1048 pm_runtime_enable(&pdev->dev);
1049 }
1050
1051 if (cmt) {
1052 dev_info(&pdev->dev, "kept as earlytimer\n");
1053 goto out;
1054 }
1055
1056 cmt = kzalloc(sizeof(*cmt), GFP_KERNEL);
1057 if (cmt == NULL)
1058 return -ENOMEM;
1059
1060 ret = sh_cmt_setup(cmt, pdev);
1061 if (ret) {
1062 kfree(cmt);
1063 pm_runtime_idle(&pdev->dev);
1064 return ret;
1065 }
1066 if (is_early_platform_device(pdev))
1067 return 0;
1068
1069 out:
1070 if (cmt->has_clockevent || cmt->has_clocksource)
1071 pm_runtime_irq_safe(&pdev->dev);
1072 else
1073 pm_runtime_idle(&pdev->dev);
1074
1075 return 0;
1076}
1077
1078static int sh_cmt_remove(struct platform_device *pdev)
1079{
1080 return -EBUSY; /* cannot unregister clockevent and clocksource */
1081}
1082
1083static struct platform_driver sh_cmt_device_driver = {
1084 .probe = sh_cmt_probe,
1085 .remove = sh_cmt_remove,
1086 .driver = {
1087 .name = "sh_cmt",
1088 .of_match_table = of_match_ptr(sh_cmt_of_table),
1089 },
1090 .id_table = sh_cmt_id_table,
1091};
1092
1093static int __init sh_cmt_init(void)
1094{
1095 return platform_driver_register(&sh_cmt_device_driver);
1096}
1097
1098static void __exit sh_cmt_exit(void)
1099{
1100 platform_driver_unregister(&sh_cmt_device_driver);
1101}
1102
1103early_platform_init("earlytimer", &sh_cmt_device_driver);
1104subsys_initcall(sh_cmt_init);
1105module_exit(sh_cmt_exit);
1106
1107MODULE_AUTHOR("Magnus Damm");
1108MODULE_DESCRIPTION("SuperH CMT Timer Driver");
1109MODULE_LICENSE("GPL v2");