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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (c) 2015, Daniel Thompson
4 */
5
6#include <linux/clk.h>
7#include <linux/delay.h>
8#include <linux/hw_random.h>
9#include <linux/io.h>
10#include <linux/iopoll.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/of_address.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/reset.h>
18#include <linux/slab.h>
19
20#define RNG_CR 0x00
21#define RNG_CR_RNGEN BIT(2)
22#define RNG_CR_CED BIT(5)
23#define RNG_CR_CONFIG1 GENMASK(11, 8)
24#define RNG_CR_NISTC BIT(12)
25#define RNG_CR_CONFIG2 GENMASK(15, 13)
26#define RNG_CR_CLKDIV_SHIFT 16
27#define RNG_CR_CLKDIV GENMASK(19, 16)
28#define RNG_CR_CONFIG3 GENMASK(25, 20)
29#define RNG_CR_CONDRST BIT(30)
30#define RNG_CR_CONFLOCK BIT(31)
31#define RNG_CR_ENTROPY_SRC_MASK (RNG_CR_CONFIG1 | RNG_CR_NISTC | RNG_CR_CONFIG2 | RNG_CR_CONFIG3)
32#define RNG_CR_CONFIG_MASK (RNG_CR_ENTROPY_SRC_MASK | RNG_CR_CED | RNG_CR_CLKDIV)
33
34#define RNG_SR 0x04
35#define RNG_SR_DRDY BIT(0)
36#define RNG_SR_CECS BIT(1)
37#define RNG_SR_SECS BIT(2)
38#define RNG_SR_CEIS BIT(5)
39#define RNG_SR_SEIS BIT(6)
40
41#define RNG_DR 0x08
42
43#define RNG_NSCR 0x0C
44#define RNG_NSCR_MASK GENMASK(17, 0)
45
46#define RNG_HTCR 0x10
47
48#define RNG_NB_RECOVER_TRIES 3
49
50struct stm32_rng_data {
51 uint max_clock_rate;
52 u32 cr;
53 u32 nscr;
54 u32 htcr;
55 bool has_cond_reset;
56};
57
58/**
59 * struct stm32_rng_config - RNG configuration data
60 *
61 * @cr: RNG configuration. 0 means default hardware RNG configuration
62 * @nscr: Noise sources control configuration.
63 * @htcr: Health tests configuration.
64 */
65struct stm32_rng_config {
66 u32 cr;
67 u32 nscr;
68 u32 htcr;
69};
70
71struct stm32_rng_private {
72 struct hwrng rng;
73 void __iomem *base;
74 struct clk *clk;
75 struct reset_control *rst;
76 struct stm32_rng_config pm_conf;
77 const struct stm32_rng_data *data;
78 bool ced;
79 bool lock_conf;
80};
81
82/*
83 * Extracts from the STM32 RNG specification when RNG supports CONDRST.
84 *
85 * When a noise source (or seed) error occurs, the RNG stops generating
86 * random numbers and sets to “1” both SEIS and SECS bits to indicate
87 * that a seed error occurred. (...)
88 *
89 * 1. Software reset by writing CONDRST at 1 and at 0 (see bitfield
90 * description for details). This step is needed only if SECS is set.
91 * Indeed, when SEIS is set and SECS is cleared it means RNG performed
92 * the reset automatically (auto-reset).
93 * 2. If SECS was set in step 1 (no auto-reset) wait for CONDRST
94 * to be cleared in the RNG_CR register, then confirm that SEIS is
95 * cleared in the RNG_SR register. Otherwise just clear SEIS bit in
96 * the RNG_SR register.
97 * 3. If SECS was set in step 1 (no auto-reset) wait for SECS to be
98 * cleared by RNG. The random number generation is now back to normal.
99 */
100static int stm32_rng_conceal_seed_error_cond_reset(struct stm32_rng_private *priv)
101{
102 struct device *dev = (struct device *)priv->rng.priv;
103 u32 sr = readl_relaxed(priv->base + RNG_SR);
104 u32 cr = readl_relaxed(priv->base + RNG_CR);
105 int err;
106
107 if (sr & RNG_SR_SECS) {
108 /* Conceal by resetting the subsystem (step 1.) */
109 writel_relaxed(cr | RNG_CR_CONDRST, priv->base + RNG_CR);
110 writel_relaxed(cr & ~RNG_CR_CONDRST, priv->base + RNG_CR);
111 } else {
112 /* RNG auto-reset (step 2.) */
113 writel_relaxed(sr & ~RNG_SR_SEIS, priv->base + RNG_SR);
114 goto end;
115 }
116
117 err = readl_relaxed_poll_timeout_atomic(priv->base + RNG_CR, cr, !(cr & RNG_CR_CONDRST), 10,
118 100000);
119 if (err) {
120 dev_err(dev, "%s: timeout %x\n", __func__, sr);
121 return err;
122 }
123
124 /* Check SEIS is cleared (step 2.) */
125 if (readl_relaxed(priv->base + RNG_SR) & RNG_SR_SEIS)
126 return -EINVAL;
127
128 err = readl_relaxed_poll_timeout_atomic(priv->base + RNG_SR, sr, !(sr & RNG_SR_SECS), 10,
129 100000);
130 if (err) {
131 dev_err(dev, "%s: timeout %x\n", __func__, sr);
132 return err;
133 }
134
135end:
136 return 0;
137}
138
139/*
140 * Extracts from the STM32 RNG specification, when CONDRST is not supported
141 *
142 * When a noise source (or seed) error occurs, the RNG stops generating
143 * random numbers and sets to “1” both SEIS and SECS bits to indicate
144 * that a seed error occurred. (...)
145 *
146 * The following sequence shall be used to fully recover from a seed
147 * error after the RNG initialization:
148 * 1. Clear the SEIS bit by writing it to “0”.
149 * 2. Read out 12 words from the RNG_DR register, and discard each of
150 * them in order to clean the pipeline.
151 * 3. Confirm that SEIS is still cleared. Random number generation is
152 * back to normal.
153 */
154static int stm32_rng_conceal_seed_error_sw_reset(struct stm32_rng_private *priv)
155{
156 unsigned int i = 0;
157 u32 sr = readl_relaxed(priv->base + RNG_SR);
158
159 writel_relaxed(sr & ~RNG_SR_SEIS, priv->base + RNG_SR);
160
161 for (i = 12; i != 0; i--)
162 (void)readl_relaxed(priv->base + RNG_DR);
163
164 if (readl_relaxed(priv->base + RNG_SR) & RNG_SR_SEIS)
165 return -EINVAL;
166
167 return 0;
168}
169
170static int stm32_rng_conceal_seed_error(struct hwrng *rng)
171{
172 struct stm32_rng_private *priv = container_of(rng, struct stm32_rng_private, rng);
173
174 dev_dbg((struct device *)priv->rng.priv, "Concealing seed error\n");
175
176 if (priv->data->has_cond_reset)
177 return stm32_rng_conceal_seed_error_cond_reset(priv);
178 else
179 return stm32_rng_conceal_seed_error_sw_reset(priv);
180};
181
182
183static int stm32_rng_read(struct hwrng *rng, void *data, size_t max, bool wait)
184{
185 struct stm32_rng_private *priv = container_of(rng, struct stm32_rng_private, rng);
186 unsigned int i = 0;
187 int retval = 0, err = 0;
188 u32 sr;
189
190 pm_runtime_get_sync((struct device *) priv->rng.priv);
191
192 if (readl_relaxed(priv->base + RNG_SR) & RNG_SR_SEIS)
193 stm32_rng_conceal_seed_error(rng);
194
195 while (max >= sizeof(u32)) {
196 sr = readl_relaxed(priv->base + RNG_SR);
197 /*
198 * Manage timeout which is based on timer and take
199 * care of initial delay time when enabling the RNG.
200 */
201 if (!sr && wait) {
202 err = readl_relaxed_poll_timeout_atomic(priv->base
203 + RNG_SR,
204 sr, sr,
205 10, 50000);
206 if (err) {
207 dev_err((struct device *)priv->rng.priv,
208 "%s: timeout %x!\n", __func__, sr);
209 break;
210 }
211 } else if (!sr) {
212 /* The FIFO is being filled up */
213 break;
214 }
215
216 if (sr != RNG_SR_DRDY) {
217 if (sr & RNG_SR_SEIS) {
218 err = stm32_rng_conceal_seed_error(rng);
219 i++;
220 if (err && i > RNG_NB_RECOVER_TRIES) {
221 dev_err((struct device *)priv->rng.priv,
222 "Couldn't recover from seed error\n");
223 retval = -ENOTRECOVERABLE;
224 goto exit_rpm;
225 }
226
227 continue;
228 }
229
230 if (WARN_ONCE((sr & RNG_SR_CEIS), "RNG clock too slow - %x\n", sr))
231 writel_relaxed(0, priv->base + RNG_SR);
232 }
233
234 /* Late seed error case: DR being 0 is an error status */
235 *(u32 *)data = readl_relaxed(priv->base + RNG_DR);
236 if (!*(u32 *)data) {
237 err = stm32_rng_conceal_seed_error(rng);
238 i++;
239 if (err && i > RNG_NB_RECOVER_TRIES) {
240 dev_err((struct device *)priv->rng.priv,
241 "Couldn't recover from seed error");
242 retval = -ENOTRECOVERABLE;
243 goto exit_rpm;
244 }
245
246 continue;
247 }
248
249 i = 0;
250 retval += sizeof(u32);
251 data += sizeof(u32);
252 max -= sizeof(u32);
253 }
254
255exit_rpm:
256 pm_runtime_mark_last_busy((struct device *) priv->rng.priv);
257 pm_runtime_put_sync_autosuspend((struct device *) priv->rng.priv);
258
259 return retval || !wait ? retval : -EIO;
260}
261
262static uint stm32_rng_clock_freq_restrain(struct hwrng *rng)
263{
264 struct stm32_rng_private *priv =
265 container_of(rng, struct stm32_rng_private, rng);
266 unsigned long clock_rate = 0;
267 uint clock_div = 0;
268
269 clock_rate = clk_get_rate(priv->clk);
270
271 /*
272 * Get the exponent to apply on the CLKDIV field in RNG_CR register
273 * No need to handle the case when clock-div > 0xF as it is physically
274 * impossible
275 */
276 while ((clock_rate >> clock_div) > priv->data->max_clock_rate)
277 clock_div++;
278
279 pr_debug("RNG clk rate : %lu\n", clk_get_rate(priv->clk) >> clock_div);
280
281 return clock_div;
282}
283
284static int stm32_rng_init(struct hwrng *rng)
285{
286 struct stm32_rng_private *priv =
287 container_of(rng, struct stm32_rng_private, rng);
288 int err;
289 u32 reg;
290
291 err = clk_prepare_enable(priv->clk);
292 if (err)
293 return err;
294
295 /* clear error indicators */
296 writel_relaxed(0, priv->base + RNG_SR);
297
298 reg = readl_relaxed(priv->base + RNG_CR);
299
300 /*
301 * Keep default RNG configuration if none was specified.
302 * 0 is an invalid value as it disables all entropy sources.
303 */
304 if (priv->data->has_cond_reset && priv->data->cr) {
305 uint clock_div = stm32_rng_clock_freq_restrain(rng);
306
307 reg &= ~RNG_CR_CONFIG_MASK;
308 reg |= RNG_CR_CONDRST | (priv->data->cr & RNG_CR_ENTROPY_SRC_MASK) |
309 (clock_div << RNG_CR_CLKDIV_SHIFT);
310 if (priv->ced)
311 reg &= ~RNG_CR_CED;
312 else
313 reg |= RNG_CR_CED;
314 writel_relaxed(reg, priv->base + RNG_CR);
315
316 /* Health tests and noise control registers */
317 writel_relaxed(priv->data->htcr, priv->base + RNG_HTCR);
318 writel_relaxed(priv->data->nscr & RNG_NSCR_MASK, priv->base + RNG_NSCR);
319
320 reg &= ~RNG_CR_CONDRST;
321 reg |= RNG_CR_RNGEN;
322 if (priv->lock_conf)
323 reg |= RNG_CR_CONFLOCK;
324
325 writel_relaxed(reg, priv->base + RNG_CR);
326
327 err = readl_relaxed_poll_timeout_atomic(priv->base + RNG_CR, reg,
328 (!(reg & RNG_CR_CONDRST)),
329 10, 50000);
330 if (err) {
331 clk_disable_unprepare(priv->clk);
332 dev_err((struct device *)priv->rng.priv,
333 "%s: timeout %x!\n", __func__, reg);
334 return -EINVAL;
335 }
336 } else {
337 /* Handle all RNG versions by checking if conditional reset should be set */
338 if (priv->data->has_cond_reset)
339 reg |= RNG_CR_CONDRST;
340
341 if (priv->ced)
342 reg &= ~RNG_CR_CED;
343 else
344 reg |= RNG_CR_CED;
345
346 writel_relaxed(reg, priv->base + RNG_CR);
347
348 if (priv->data->has_cond_reset)
349 reg &= ~RNG_CR_CONDRST;
350
351 reg |= RNG_CR_RNGEN;
352
353 writel_relaxed(reg, priv->base + RNG_CR);
354 }
355
356 err = readl_relaxed_poll_timeout_atomic(priv->base + RNG_SR, reg,
357 reg & RNG_SR_DRDY,
358 10, 100000);
359 if (err || (reg & ~RNG_SR_DRDY)) {
360 clk_disable_unprepare(priv->clk);
361 dev_err((struct device *)priv->rng.priv,
362 "%s: timeout:%x SR: %x!\n", __func__, err, reg);
363 return -EINVAL;
364 }
365
366 clk_disable_unprepare(priv->clk);
367
368 return 0;
369}
370
371static void stm32_rng_remove(struct platform_device *ofdev)
372{
373 pm_runtime_disable(&ofdev->dev);
374}
375
376static int __maybe_unused stm32_rng_runtime_suspend(struct device *dev)
377{
378 struct stm32_rng_private *priv = dev_get_drvdata(dev);
379 u32 reg;
380
381 reg = readl_relaxed(priv->base + RNG_CR);
382 reg &= ~RNG_CR_RNGEN;
383 writel_relaxed(reg, priv->base + RNG_CR);
384 clk_disable_unprepare(priv->clk);
385
386 return 0;
387}
388
389static int __maybe_unused stm32_rng_suspend(struct device *dev)
390{
391 struct stm32_rng_private *priv = dev_get_drvdata(dev);
392 int err;
393
394 err = clk_prepare_enable(priv->clk);
395 if (err)
396 return err;
397
398 if (priv->data->has_cond_reset) {
399 priv->pm_conf.nscr = readl_relaxed(priv->base + RNG_NSCR);
400 priv->pm_conf.htcr = readl_relaxed(priv->base + RNG_HTCR);
401 }
402
403 /* Do not save that RNG is enabled as it will be handled at resume */
404 priv->pm_conf.cr = readl_relaxed(priv->base + RNG_CR) & ~RNG_CR_RNGEN;
405
406 writel_relaxed(priv->pm_conf.cr, priv->base + RNG_CR);
407
408 clk_disable_unprepare(priv->clk);
409
410 return 0;
411}
412
413static int __maybe_unused stm32_rng_runtime_resume(struct device *dev)
414{
415 struct stm32_rng_private *priv = dev_get_drvdata(dev);
416 int err;
417 u32 reg;
418
419 err = clk_prepare_enable(priv->clk);
420 if (err)
421 return err;
422
423 /* Clean error indications */
424 writel_relaxed(0, priv->base + RNG_SR);
425
426 reg = readl_relaxed(priv->base + RNG_CR);
427 reg |= RNG_CR_RNGEN;
428 writel_relaxed(reg, priv->base + RNG_CR);
429
430 return 0;
431}
432
433static int __maybe_unused stm32_rng_resume(struct device *dev)
434{
435 struct stm32_rng_private *priv = dev_get_drvdata(dev);
436 int err;
437 u32 reg;
438
439 err = clk_prepare_enable(priv->clk);
440 if (err)
441 return err;
442
443 /* Clean error indications */
444 writel_relaxed(0, priv->base + RNG_SR);
445
446 if (priv->data->has_cond_reset) {
447 /*
448 * Correct configuration in bits [29:4] must be set in the same
449 * access that set RNG_CR_CONDRST bit. Else config setting is
450 * not taken into account. CONFIGLOCK bit must also be unset but
451 * it is not handled at the moment.
452 */
453 writel_relaxed(priv->pm_conf.cr | RNG_CR_CONDRST, priv->base + RNG_CR);
454
455 writel_relaxed(priv->pm_conf.nscr, priv->base + RNG_NSCR);
456 writel_relaxed(priv->pm_conf.htcr, priv->base + RNG_HTCR);
457
458 reg = readl_relaxed(priv->base + RNG_CR);
459 reg |= RNG_CR_RNGEN;
460 reg &= ~RNG_CR_CONDRST;
461 writel_relaxed(reg, priv->base + RNG_CR);
462
463 err = readl_relaxed_poll_timeout_atomic(priv->base + RNG_CR, reg,
464 reg & ~RNG_CR_CONDRST, 10, 100000);
465
466 if (err) {
467 clk_disable_unprepare(priv->clk);
468 dev_err((struct device *)priv->rng.priv,
469 "%s: timeout:%x CR: %x!\n", __func__, err, reg);
470 return -EINVAL;
471 }
472 } else {
473 reg = priv->pm_conf.cr;
474 reg |= RNG_CR_RNGEN;
475 writel_relaxed(reg, priv->base + RNG_CR);
476 }
477
478 clk_disable_unprepare(priv->clk);
479
480 return 0;
481}
482
483static const struct dev_pm_ops __maybe_unused stm32_rng_pm_ops = {
484 SET_RUNTIME_PM_OPS(stm32_rng_runtime_suspend,
485 stm32_rng_runtime_resume, NULL)
486 SET_SYSTEM_SLEEP_PM_OPS(stm32_rng_suspend,
487 stm32_rng_resume)
488};
489
490static const struct stm32_rng_data stm32mp13_rng_data = {
491 .has_cond_reset = true,
492 .max_clock_rate = 48000000,
493 .cr = 0x00F00D00,
494 .nscr = 0x2B5BB,
495 .htcr = 0x969D,
496};
497
498static const struct stm32_rng_data stm32_rng_data = {
499 .has_cond_reset = false,
500 .max_clock_rate = 3000000,
501};
502
503static const struct of_device_id stm32_rng_match[] = {
504 {
505 .compatible = "st,stm32mp13-rng",
506 .data = &stm32mp13_rng_data,
507 },
508 {
509 .compatible = "st,stm32-rng",
510 .data = &stm32_rng_data,
511 },
512 {},
513};
514MODULE_DEVICE_TABLE(of, stm32_rng_match);
515
516static int stm32_rng_probe(struct platform_device *ofdev)
517{
518 struct device *dev = &ofdev->dev;
519 struct device_node *np = ofdev->dev.of_node;
520 struct stm32_rng_private *priv;
521 struct resource *res;
522
523 priv = devm_kzalloc(dev, sizeof(struct stm32_rng_private), GFP_KERNEL);
524 if (!priv)
525 return -ENOMEM;
526
527 priv->base = devm_platform_get_and_ioremap_resource(ofdev, 0, &res);
528 if (IS_ERR(priv->base))
529 return PTR_ERR(priv->base);
530
531 priv->clk = devm_clk_get(&ofdev->dev, NULL);
532 if (IS_ERR(priv->clk))
533 return PTR_ERR(priv->clk);
534
535 priv->rst = devm_reset_control_get(&ofdev->dev, NULL);
536 if (!IS_ERR(priv->rst)) {
537 reset_control_assert(priv->rst);
538 udelay(2);
539 reset_control_deassert(priv->rst);
540 }
541
542 priv->ced = of_property_read_bool(np, "clock-error-detect");
543 priv->lock_conf = of_property_read_bool(np, "st,rng-lock-conf");
544
545 priv->data = of_device_get_match_data(dev);
546 if (!priv->data)
547 return -ENODEV;
548
549 dev_set_drvdata(dev, priv);
550
551 priv->rng.name = dev_driver_string(dev);
552 priv->rng.init = stm32_rng_init;
553 priv->rng.read = stm32_rng_read;
554 priv->rng.priv = (unsigned long) dev;
555 priv->rng.quality = 900;
556
557 pm_runtime_set_autosuspend_delay(dev, 100);
558 pm_runtime_use_autosuspend(dev);
559 pm_runtime_enable(dev);
560
561 return devm_hwrng_register(dev, &priv->rng);
562}
563
564static struct platform_driver stm32_rng_driver = {
565 .driver = {
566 .name = "stm32-rng",
567 .pm = pm_ptr(&stm32_rng_pm_ops),
568 .of_match_table = stm32_rng_match,
569 },
570 .probe = stm32_rng_probe,
571 .remove_new = stm32_rng_remove,
572};
573
574module_platform_driver(stm32_rng_driver);
575
576MODULE_LICENSE("GPL");
577MODULE_AUTHOR("Daniel Thompson <daniel.thompson@linaro.org>");
578MODULE_DESCRIPTION("STMicroelectronics STM32 RNG device driver");