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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers.
4 *
5 * (C) Copyright 2014, 2015 Linaro Ltd.
6 * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org>
7 *
8 * CPPC describes a few methods for controlling CPU performance using
9 * information from a per CPU table called CPC. This table is described in
10 * the ACPI v5.0+ specification. The table consists of a list of
11 * registers which may be memory mapped or hardware registers and also may
12 * include some static integer values.
13 *
14 * CPU performance is on an abstract continuous scale as against a discretized
15 * P-state scale which is tied to CPU frequency only. In brief, the basic
16 * operation involves:
17 *
18 * - OS makes a CPU performance request. (Can provide min and max bounds)
19 *
20 * - Platform (such as BMC) is free to optimize request within requested bounds
21 * depending on power/thermal budgets etc.
22 *
23 * - Platform conveys its decision back to OS
24 *
25 * The communication between OS and platform occurs through another medium
26 * called (PCC) Platform Communication Channel. This is a generic mailbox like
27 * mechanism which includes doorbell semantics to indicate register updates.
28 * See drivers/mailbox/pcc.c for details on PCC.
29 *
30 * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
31 * above specifications.
32 */
33
34#define pr_fmt(fmt) "ACPI CPPC: " fmt
35
36#include <linux/delay.h>
37#include <linux/iopoll.h>
38#include <linux/ktime.h>
39#include <linux/rwsem.h>
40#include <linux/wait.h>
41#include <linux/topology.h>
42#include <linux/dmi.h>
43#include <linux/units.h>
44#include <asm/unaligned.h>
45
46#include <acpi/cppc_acpi.h>
47
48struct cppc_pcc_data {
49 struct pcc_mbox_chan *pcc_channel;
50 void __iomem *pcc_comm_addr;
51 bool pcc_channel_acquired;
52 unsigned int deadline_us;
53 unsigned int pcc_mpar, pcc_mrtt, pcc_nominal;
54
55 bool pending_pcc_write_cmd; /* Any pending/batched PCC write cmds? */
56 bool platform_owns_pcc; /* Ownership of PCC subspace */
57 unsigned int pcc_write_cnt; /* Running count of PCC write commands */
58
59 /*
60 * Lock to provide controlled access to the PCC channel.
61 *
62 * For performance critical usecases(currently cppc_set_perf)
63 * We need to take read_lock and check if channel belongs to OSPM
64 * before reading or writing to PCC subspace
65 * We need to take write_lock before transferring the channel
66 * ownership to the platform via a Doorbell
67 * This allows us to batch a number of CPPC requests if they happen
68 * to originate in about the same time
69 *
70 * For non-performance critical usecases(init)
71 * Take write_lock for all purposes which gives exclusive access
72 */
73 struct rw_semaphore pcc_lock;
74
75 /* Wait queue for CPUs whose requests were batched */
76 wait_queue_head_t pcc_write_wait_q;
77 ktime_t last_cmd_cmpl_time;
78 ktime_t last_mpar_reset;
79 int mpar_count;
80 int refcount;
81};
82
83/* Array to represent the PCC channel per subspace ID */
84static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES];
85/* The cpu_pcc_subspace_idx contains per CPU subspace ID */
86static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx);
87
88/*
89 * The cpc_desc structure contains the ACPI register details
90 * as described in the per CPU _CPC tables. The details
91 * include the type of register (e.g. PCC, System IO, FFH etc.)
92 * and destination addresses which lets us READ/WRITE CPU performance
93 * information using the appropriate I/O methods.
94 */
95static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
96
97/* pcc mapped address + header size + offset within PCC subspace */
98#define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \
99 0x8 + (offs))
100
101/* Check if a CPC register is in PCC */
102#define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
103 (cpc)->cpc_entry.reg.space_id == \
104 ACPI_ADR_SPACE_PLATFORM_COMM)
105
106/* Check if a CPC register is in SystemMemory */
107#define CPC_IN_SYSTEM_MEMORY(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
108 (cpc)->cpc_entry.reg.space_id == \
109 ACPI_ADR_SPACE_SYSTEM_MEMORY)
110
111/* Check if a CPC register is in SystemIo */
112#define CPC_IN_SYSTEM_IO(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
113 (cpc)->cpc_entry.reg.space_id == \
114 ACPI_ADR_SPACE_SYSTEM_IO)
115
116/* Evaluates to True if reg is a NULL register descriptor */
117#define IS_NULL_REG(reg) ((reg)->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY && \
118 (reg)->address == 0 && \
119 (reg)->bit_width == 0 && \
120 (reg)->bit_offset == 0 && \
121 (reg)->access_width == 0)
122
123/* Evaluates to True if an optional cpc field is supported */
124#define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \
125 !!(cpc)->cpc_entry.int_value : \
126 !IS_NULL_REG(&(cpc)->cpc_entry.reg))
127/*
128 * Arbitrary Retries in case the remote processor is slow to respond
129 * to PCC commands. Keeping it high enough to cover emulators where
130 * the processors run painfully slow.
131 */
132#define NUM_RETRIES 500ULL
133
134#define OVER_16BTS_MASK ~0xFFFFULL
135
136#define define_one_cppc_ro(_name) \
137static struct kobj_attribute _name = \
138__ATTR(_name, 0444, show_##_name, NULL)
139
140#define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj)
141
142#define show_cppc_data(access_fn, struct_name, member_name) \
143 static ssize_t show_##member_name(struct kobject *kobj, \
144 struct kobj_attribute *attr, char *buf) \
145 { \
146 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); \
147 struct struct_name st_name = {0}; \
148 int ret; \
149 \
150 ret = access_fn(cpc_ptr->cpu_id, &st_name); \
151 if (ret) \
152 return ret; \
153 \
154 return sysfs_emit(buf, "%llu\n", \
155 (u64)st_name.member_name); \
156 } \
157 define_one_cppc_ro(member_name)
158
159show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf);
160show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf);
161show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf);
162show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf);
163show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq);
164show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq);
165
166show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf);
167show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
168
169/* Check for valid access_width, otherwise, fallback to using bit_width */
170#define GET_BIT_WIDTH(reg) ((reg)->access_width ? (8 << ((reg)->access_width - 1)) : (reg)->bit_width)
171
172/* Shift and apply the mask for CPC reads/writes */
173#define MASK_VAL(reg, val) (((val) >> (reg)->bit_offset) & \
174 GENMASK(((reg)->bit_width) - 1, 0))
175
176static ssize_t show_feedback_ctrs(struct kobject *kobj,
177 struct kobj_attribute *attr, char *buf)
178{
179 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
180 struct cppc_perf_fb_ctrs fb_ctrs = {0};
181 int ret;
182
183 ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
184 if (ret)
185 return ret;
186
187 return sysfs_emit(buf, "ref:%llu del:%llu\n",
188 fb_ctrs.reference, fb_ctrs.delivered);
189}
190define_one_cppc_ro(feedback_ctrs);
191
192static struct attribute *cppc_attrs[] = {
193 &feedback_ctrs.attr,
194 &reference_perf.attr,
195 &wraparound_time.attr,
196 &highest_perf.attr,
197 &lowest_perf.attr,
198 &lowest_nonlinear_perf.attr,
199 &nominal_perf.attr,
200 &nominal_freq.attr,
201 &lowest_freq.attr,
202 NULL
203};
204ATTRIBUTE_GROUPS(cppc);
205
206static const struct kobj_type cppc_ktype = {
207 .sysfs_ops = &kobj_sysfs_ops,
208 .default_groups = cppc_groups,
209};
210
211static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit)
212{
213 int ret, status;
214 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
215 struct acpi_pcct_shared_memory __iomem *generic_comm_base =
216 pcc_ss_data->pcc_comm_addr;
217
218 if (!pcc_ss_data->platform_owns_pcc)
219 return 0;
220
221 /*
222 * Poll PCC status register every 3us(delay_us) for maximum of
223 * deadline_us(timeout_us) until PCC command complete bit is set(cond)
224 */
225 ret = readw_relaxed_poll_timeout(&generic_comm_base->status, status,
226 status & PCC_CMD_COMPLETE_MASK, 3,
227 pcc_ss_data->deadline_us);
228
229 if (likely(!ret)) {
230 pcc_ss_data->platform_owns_pcc = false;
231 if (chk_err_bit && (status & PCC_ERROR_MASK))
232 ret = -EIO;
233 }
234
235 if (unlikely(ret))
236 pr_err("PCC check channel failed for ss: %d. ret=%d\n",
237 pcc_ss_id, ret);
238
239 return ret;
240}
241
242/*
243 * This function transfers the ownership of the PCC to the platform
244 * So it must be called while holding write_lock(pcc_lock)
245 */
246static int send_pcc_cmd(int pcc_ss_id, u16 cmd)
247{
248 int ret = -EIO, i;
249 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
250 struct acpi_pcct_shared_memory __iomem *generic_comm_base =
251 pcc_ss_data->pcc_comm_addr;
252 unsigned int time_delta;
253
254 /*
255 * For CMD_WRITE we know for a fact the caller should have checked
256 * the channel before writing to PCC space
257 */
258 if (cmd == CMD_READ) {
259 /*
260 * If there are pending cpc_writes, then we stole the channel
261 * before write completion, so first send a WRITE command to
262 * platform
263 */
264 if (pcc_ss_data->pending_pcc_write_cmd)
265 send_pcc_cmd(pcc_ss_id, CMD_WRITE);
266
267 ret = check_pcc_chan(pcc_ss_id, false);
268 if (ret)
269 goto end;
270 } else /* CMD_WRITE */
271 pcc_ss_data->pending_pcc_write_cmd = FALSE;
272
273 /*
274 * Handle the Minimum Request Turnaround Time(MRTT)
275 * "The minimum amount of time that OSPM must wait after the completion
276 * of a command before issuing the next command, in microseconds"
277 */
278 if (pcc_ss_data->pcc_mrtt) {
279 time_delta = ktime_us_delta(ktime_get(),
280 pcc_ss_data->last_cmd_cmpl_time);
281 if (pcc_ss_data->pcc_mrtt > time_delta)
282 udelay(pcc_ss_data->pcc_mrtt - time_delta);
283 }
284
285 /*
286 * Handle the non-zero Maximum Periodic Access Rate(MPAR)
287 * "The maximum number of periodic requests that the subspace channel can
288 * support, reported in commands per minute. 0 indicates no limitation."
289 *
290 * This parameter should be ideally zero or large enough so that it can
291 * handle maximum number of requests that all the cores in the system can
292 * collectively generate. If it is not, we will follow the spec and just
293 * not send the request to the platform after hitting the MPAR limit in
294 * any 60s window
295 */
296 if (pcc_ss_data->pcc_mpar) {
297 if (pcc_ss_data->mpar_count == 0) {
298 time_delta = ktime_ms_delta(ktime_get(),
299 pcc_ss_data->last_mpar_reset);
300 if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) {
301 pr_debug("PCC cmd for subspace %d not sent due to MPAR limit",
302 pcc_ss_id);
303 ret = -EIO;
304 goto end;
305 }
306 pcc_ss_data->last_mpar_reset = ktime_get();
307 pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar;
308 }
309 pcc_ss_data->mpar_count--;
310 }
311
312 /* Write to the shared comm region. */
313 writew_relaxed(cmd, &generic_comm_base->command);
314
315 /* Flip CMD COMPLETE bit */
316 writew_relaxed(0, &generic_comm_base->status);
317
318 pcc_ss_data->platform_owns_pcc = true;
319
320 /* Ring doorbell */
321 ret = mbox_send_message(pcc_ss_data->pcc_channel->mchan, &cmd);
322 if (ret < 0) {
323 pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n",
324 pcc_ss_id, cmd, ret);
325 goto end;
326 }
327
328 /* wait for completion and check for PCC error bit */
329 ret = check_pcc_chan(pcc_ss_id, true);
330
331 if (pcc_ss_data->pcc_mrtt)
332 pcc_ss_data->last_cmd_cmpl_time = ktime_get();
333
334 if (pcc_ss_data->pcc_channel->mchan->mbox->txdone_irq)
335 mbox_chan_txdone(pcc_ss_data->pcc_channel->mchan, ret);
336 else
337 mbox_client_txdone(pcc_ss_data->pcc_channel->mchan, ret);
338
339end:
340 if (cmd == CMD_WRITE) {
341 if (unlikely(ret)) {
342 for_each_possible_cpu(i) {
343 struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i);
344
345 if (!desc)
346 continue;
347
348 if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt)
349 desc->write_cmd_status = ret;
350 }
351 }
352 pcc_ss_data->pcc_write_cnt++;
353 wake_up_all(&pcc_ss_data->pcc_write_wait_q);
354 }
355
356 return ret;
357}
358
359static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret)
360{
361 if (ret < 0)
362 pr_debug("TX did not complete: CMD sent:%x, ret:%d\n",
363 *(u16 *)msg, ret);
364 else
365 pr_debug("TX completed. CMD sent:%x, ret:%d\n",
366 *(u16 *)msg, ret);
367}
368
369static struct mbox_client cppc_mbox_cl = {
370 .tx_done = cppc_chan_tx_done,
371 .knows_txdone = true,
372};
373
374static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle)
375{
376 int result = -EFAULT;
377 acpi_status status = AE_OK;
378 struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
379 struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"};
380 struct acpi_buffer state = {0, NULL};
381 union acpi_object *psd = NULL;
382 struct acpi_psd_package *pdomain;
383
384 status = acpi_evaluate_object_typed(handle, "_PSD", NULL,
385 &buffer, ACPI_TYPE_PACKAGE);
386 if (status == AE_NOT_FOUND) /* _PSD is optional */
387 return 0;
388 if (ACPI_FAILURE(status))
389 return -ENODEV;
390
391 psd = buffer.pointer;
392 if (!psd || psd->package.count != 1) {
393 pr_debug("Invalid _PSD data\n");
394 goto end;
395 }
396
397 pdomain = &(cpc_ptr->domain_info);
398
399 state.length = sizeof(struct acpi_psd_package);
400 state.pointer = pdomain;
401
402 status = acpi_extract_package(&(psd->package.elements[0]),
403 &format, &state);
404 if (ACPI_FAILURE(status)) {
405 pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id);
406 goto end;
407 }
408
409 if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) {
410 pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id);
411 goto end;
412 }
413
414 if (pdomain->revision != ACPI_PSD_REV0_REVISION) {
415 pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id);
416 goto end;
417 }
418
419 if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL &&
420 pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY &&
421 pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) {
422 pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id);
423 goto end;
424 }
425
426 result = 0;
427end:
428 kfree(buffer.pointer);
429 return result;
430}
431
432bool acpi_cpc_valid(void)
433{
434 struct cpc_desc *cpc_ptr;
435 int cpu;
436
437 if (acpi_disabled)
438 return false;
439
440 for_each_present_cpu(cpu) {
441 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
442 if (!cpc_ptr)
443 return false;
444 }
445
446 return true;
447}
448EXPORT_SYMBOL_GPL(acpi_cpc_valid);
449
450bool cppc_allow_fast_switch(void)
451{
452 struct cpc_register_resource *desired_reg;
453 struct cpc_desc *cpc_ptr;
454 int cpu;
455
456 for_each_possible_cpu(cpu) {
457 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
458 desired_reg = &cpc_ptr->cpc_regs[DESIRED_PERF];
459 if (!CPC_IN_SYSTEM_MEMORY(desired_reg) &&
460 !CPC_IN_SYSTEM_IO(desired_reg))
461 return false;
462 }
463
464 return true;
465}
466EXPORT_SYMBOL_GPL(cppc_allow_fast_switch);
467
468/**
469 * acpi_get_psd_map - Map the CPUs in the freq domain of a given cpu
470 * @cpu: Find all CPUs that share a domain with cpu.
471 * @cpu_data: Pointer to CPU specific CPPC data including PSD info.
472 *
473 * Return: 0 for success or negative value for err.
474 */
475int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data)
476{
477 struct cpc_desc *cpc_ptr, *match_cpc_ptr;
478 struct acpi_psd_package *match_pdomain;
479 struct acpi_psd_package *pdomain;
480 int count_target, i;
481
482 /*
483 * Now that we have _PSD data from all CPUs, let's setup P-state
484 * domain info.
485 */
486 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
487 if (!cpc_ptr)
488 return -EFAULT;
489
490 pdomain = &(cpc_ptr->domain_info);
491 cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
492 if (pdomain->num_processors <= 1)
493 return 0;
494
495 /* Validate the Domain info */
496 count_target = pdomain->num_processors;
497 if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL)
498 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ALL;
499 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL)
500 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_HW;
501 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY)
502 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ANY;
503
504 for_each_possible_cpu(i) {
505 if (i == cpu)
506 continue;
507
508 match_cpc_ptr = per_cpu(cpc_desc_ptr, i);
509 if (!match_cpc_ptr)
510 goto err_fault;
511
512 match_pdomain = &(match_cpc_ptr->domain_info);
513 if (match_pdomain->domain != pdomain->domain)
514 continue;
515
516 /* Here i and cpu are in the same domain */
517 if (match_pdomain->num_processors != count_target)
518 goto err_fault;
519
520 if (pdomain->coord_type != match_pdomain->coord_type)
521 goto err_fault;
522
523 cpumask_set_cpu(i, cpu_data->shared_cpu_map);
524 }
525
526 return 0;
527
528err_fault:
529 /* Assume no coordination on any error parsing domain info */
530 cpumask_clear(cpu_data->shared_cpu_map);
531 cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
532 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_NONE;
533
534 return -EFAULT;
535}
536EXPORT_SYMBOL_GPL(acpi_get_psd_map);
537
538static int register_pcc_channel(int pcc_ss_idx)
539{
540 struct pcc_mbox_chan *pcc_chan;
541 u64 usecs_lat;
542
543 if (pcc_ss_idx >= 0) {
544 pcc_chan = pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx);
545
546 if (IS_ERR(pcc_chan)) {
547 pr_err("Failed to find PCC channel for subspace %d\n",
548 pcc_ss_idx);
549 return -ENODEV;
550 }
551
552 pcc_data[pcc_ss_idx]->pcc_channel = pcc_chan;
553 /*
554 * cppc_ss->latency is just a Nominal value. In reality
555 * the remote processor could be much slower to reply.
556 * So add an arbitrary amount of wait on top of Nominal.
557 */
558 usecs_lat = NUM_RETRIES * pcc_chan->latency;
559 pcc_data[pcc_ss_idx]->deadline_us = usecs_lat;
560 pcc_data[pcc_ss_idx]->pcc_mrtt = pcc_chan->min_turnaround_time;
561 pcc_data[pcc_ss_idx]->pcc_mpar = pcc_chan->max_access_rate;
562 pcc_data[pcc_ss_idx]->pcc_nominal = pcc_chan->latency;
563
564 pcc_data[pcc_ss_idx]->pcc_comm_addr =
565 acpi_os_ioremap(pcc_chan->shmem_base_addr,
566 pcc_chan->shmem_size);
567 if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) {
568 pr_err("Failed to ioremap PCC comm region mem for %d\n",
569 pcc_ss_idx);
570 return -ENOMEM;
571 }
572
573 /* Set flag so that we don't come here for each CPU. */
574 pcc_data[pcc_ss_idx]->pcc_channel_acquired = true;
575 }
576
577 return 0;
578}
579
580/**
581 * cpc_ffh_supported() - check if FFH reading supported
582 *
583 * Check if the architecture has support for functional fixed hardware
584 * read/write capability.
585 *
586 * Return: true for supported, false for not supported
587 */
588bool __weak cpc_ffh_supported(void)
589{
590 return false;
591}
592
593/**
594 * cpc_supported_by_cpu() - check if CPPC is supported by CPU
595 *
596 * Check if the architectural support for CPPC is present even
597 * if the _OSC hasn't prescribed it
598 *
599 * Return: true for supported, false for not supported
600 */
601bool __weak cpc_supported_by_cpu(void)
602{
603 return false;
604}
605
606/**
607 * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace
608 * @pcc_ss_id: PCC Subspace index as in the PCC client ACPI package.
609 *
610 * Check and allocate the cppc_pcc_data memory.
611 * In some processor configurations it is possible that same subspace
612 * is shared between multiple CPUs. This is seen especially in CPUs
613 * with hardware multi-threading support.
614 *
615 * Return: 0 for success, errno for failure
616 */
617static int pcc_data_alloc(int pcc_ss_id)
618{
619 if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES)
620 return -EINVAL;
621
622 if (pcc_data[pcc_ss_id]) {
623 pcc_data[pcc_ss_id]->refcount++;
624 } else {
625 pcc_data[pcc_ss_id] = kzalloc(sizeof(struct cppc_pcc_data),
626 GFP_KERNEL);
627 if (!pcc_data[pcc_ss_id])
628 return -ENOMEM;
629 pcc_data[pcc_ss_id]->refcount++;
630 }
631
632 return 0;
633}
634
635/*
636 * An example CPC table looks like the following.
637 *
638 * Name (_CPC, Package() {
639 * 17, // NumEntries
640 * 1, // Revision
641 * ResourceTemplate() {Register(PCC, 32, 0, 0x120, 2)}, // Highest Performance
642 * ResourceTemplate() {Register(PCC, 32, 0, 0x124, 2)}, // Nominal Performance
643 * ResourceTemplate() {Register(PCC, 32, 0, 0x128, 2)}, // Lowest Nonlinear Performance
644 * ResourceTemplate() {Register(PCC, 32, 0, 0x12C, 2)}, // Lowest Performance
645 * ResourceTemplate() {Register(PCC, 32, 0, 0x130, 2)}, // Guaranteed Performance Register
646 * ResourceTemplate() {Register(PCC, 32, 0, 0x110, 2)}, // Desired Performance Register
647 * ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)},
648 * ...
649 * ...
650 * ...
651 * }
652 * Each Register() encodes how to access that specific register.
653 * e.g. a sample PCC entry has the following encoding:
654 *
655 * Register (
656 * PCC, // AddressSpaceKeyword
657 * 8, // RegisterBitWidth
658 * 8, // RegisterBitOffset
659 * 0x30, // RegisterAddress
660 * 9, // AccessSize (subspace ID)
661 * )
662 */
663
664#ifndef arch_init_invariance_cppc
665static inline void arch_init_invariance_cppc(void) { }
666#endif
667
668/**
669 * acpi_cppc_processor_probe - Search for per CPU _CPC objects.
670 * @pr: Ptr to acpi_processor containing this CPU's logical ID.
671 *
672 * Return: 0 for success or negative value for err.
673 */
674int acpi_cppc_processor_probe(struct acpi_processor *pr)
675{
676 struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL};
677 union acpi_object *out_obj, *cpc_obj;
678 struct cpc_desc *cpc_ptr;
679 struct cpc_reg *gas_t;
680 struct device *cpu_dev;
681 acpi_handle handle = pr->handle;
682 unsigned int num_ent, i, cpc_rev;
683 int pcc_subspace_id = -1;
684 acpi_status status;
685 int ret = -ENODATA;
686
687 if (!osc_sb_cppc2_support_acked) {
688 pr_debug("CPPC v2 _OSC not acked\n");
689 if (!cpc_supported_by_cpu())
690 return -ENODEV;
691 }
692
693 /* Parse the ACPI _CPC table for this CPU. */
694 status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output,
695 ACPI_TYPE_PACKAGE);
696 if (ACPI_FAILURE(status)) {
697 ret = -ENODEV;
698 goto out_buf_free;
699 }
700
701 out_obj = (union acpi_object *) output.pointer;
702
703 cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL);
704 if (!cpc_ptr) {
705 ret = -ENOMEM;
706 goto out_buf_free;
707 }
708
709 /* First entry is NumEntries. */
710 cpc_obj = &out_obj->package.elements[0];
711 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
712 num_ent = cpc_obj->integer.value;
713 if (num_ent <= 1) {
714 pr_debug("Unexpected _CPC NumEntries value (%d) for CPU:%d\n",
715 num_ent, pr->id);
716 goto out_free;
717 }
718 } else {
719 pr_debug("Unexpected _CPC NumEntries entry type (%d) for CPU:%d\n",
720 cpc_obj->type, pr->id);
721 goto out_free;
722 }
723
724 /* Second entry should be revision. */
725 cpc_obj = &out_obj->package.elements[1];
726 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
727 cpc_rev = cpc_obj->integer.value;
728 } else {
729 pr_debug("Unexpected _CPC Revision entry type (%d) for CPU:%d\n",
730 cpc_obj->type, pr->id);
731 goto out_free;
732 }
733
734 if (cpc_rev < CPPC_V2_REV) {
735 pr_debug("Unsupported _CPC Revision (%d) for CPU:%d\n", cpc_rev,
736 pr->id);
737 goto out_free;
738 }
739
740 /*
741 * Disregard _CPC if the number of entries in the return pachage is not
742 * as expected, but support future revisions being proper supersets of
743 * the v3 and only causing more entries to be returned by _CPC.
744 */
745 if ((cpc_rev == CPPC_V2_REV && num_ent != CPPC_V2_NUM_ENT) ||
746 (cpc_rev == CPPC_V3_REV && num_ent != CPPC_V3_NUM_ENT) ||
747 (cpc_rev > CPPC_V3_REV && num_ent <= CPPC_V3_NUM_ENT)) {
748 pr_debug("Unexpected number of _CPC return package entries (%d) for CPU:%d\n",
749 num_ent, pr->id);
750 goto out_free;
751 }
752 if (cpc_rev > CPPC_V3_REV) {
753 num_ent = CPPC_V3_NUM_ENT;
754 cpc_rev = CPPC_V3_REV;
755 }
756
757 cpc_ptr->num_entries = num_ent;
758 cpc_ptr->version = cpc_rev;
759
760 /* Iterate through remaining entries in _CPC */
761 for (i = 2; i < num_ent; i++) {
762 cpc_obj = &out_obj->package.elements[i];
763
764 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
765 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
766 cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
767 } else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
768 gas_t = (struct cpc_reg *)
769 cpc_obj->buffer.pointer;
770
771 /*
772 * The PCC Subspace index is encoded inside
773 * the CPC table entries. The same PCC index
774 * will be used for all the PCC entries,
775 * so extract it only once.
776 */
777 if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
778 if (pcc_subspace_id < 0) {
779 pcc_subspace_id = gas_t->access_width;
780 if (pcc_data_alloc(pcc_subspace_id))
781 goto out_free;
782 } else if (pcc_subspace_id != gas_t->access_width) {
783 pr_debug("Mismatched PCC ids in _CPC for CPU:%d\n",
784 pr->id);
785 goto out_free;
786 }
787 } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
788 if (gas_t->address) {
789 void __iomem *addr;
790 size_t access_width;
791
792 if (!osc_cpc_flexible_adr_space_confirmed) {
793 pr_debug("Flexible address space capability not supported\n");
794 if (!cpc_supported_by_cpu())
795 goto out_free;
796 }
797
798 access_width = GET_BIT_WIDTH(gas_t) / 8;
799 addr = ioremap(gas_t->address, access_width);
800 if (!addr)
801 goto out_free;
802 cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
803 }
804 } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
805 if (gas_t->access_width < 1 || gas_t->access_width > 3) {
806 /*
807 * 1 = 8-bit, 2 = 16-bit, and 3 = 32-bit.
808 * SystemIO doesn't implement 64-bit
809 * registers.
810 */
811 pr_debug("Invalid access width %d for SystemIO register in _CPC\n",
812 gas_t->access_width);
813 goto out_free;
814 }
815 if (gas_t->address & OVER_16BTS_MASK) {
816 /* SystemIO registers use 16-bit integer addresses */
817 pr_debug("Invalid IO port %llu for SystemIO register in _CPC\n",
818 gas_t->address);
819 goto out_free;
820 }
821 if (!osc_cpc_flexible_adr_space_confirmed) {
822 pr_debug("Flexible address space capability not supported\n");
823 if (!cpc_supported_by_cpu())
824 goto out_free;
825 }
826 } else {
827 if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
828 /* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */
829 pr_debug("Unsupported register type (%d) in _CPC\n",
830 gas_t->space_id);
831 goto out_free;
832 }
833 }
834
835 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
836 memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
837 } else {
838 pr_debug("Invalid entry type (%d) in _CPC for CPU:%d\n",
839 i, pr->id);
840 goto out_free;
841 }
842 }
843 per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id;
844
845 /*
846 * Initialize the remaining cpc_regs as unsupported.
847 * Example: In case FW exposes CPPC v2, the below loop will initialize
848 * LOWEST_FREQ and NOMINAL_FREQ regs as unsupported
849 */
850 for (i = num_ent - 2; i < MAX_CPC_REG_ENT; i++) {
851 cpc_ptr->cpc_regs[i].type = ACPI_TYPE_INTEGER;
852 cpc_ptr->cpc_regs[i].cpc_entry.int_value = 0;
853 }
854
855
856 /* Store CPU Logical ID */
857 cpc_ptr->cpu_id = pr->id;
858
859 /* Parse PSD data for this CPU */
860 ret = acpi_get_psd(cpc_ptr, handle);
861 if (ret)
862 goto out_free;
863
864 /* Register PCC channel once for all PCC subspace ID. */
865 if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) {
866 ret = register_pcc_channel(pcc_subspace_id);
867 if (ret)
868 goto out_free;
869
870 init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock);
871 init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q);
872 }
873
874 /* Everything looks okay */
875 pr_debug("Parsed CPC struct for CPU: %d\n", pr->id);
876
877 /* Add per logical CPU nodes for reading its feedback counters. */
878 cpu_dev = get_cpu_device(pr->id);
879 if (!cpu_dev) {
880 ret = -EINVAL;
881 goto out_free;
882 }
883
884 /* Plug PSD data into this CPU's CPC descriptor. */
885 per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr;
886
887 ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj,
888 "acpi_cppc");
889 if (ret) {
890 per_cpu(cpc_desc_ptr, pr->id) = NULL;
891 kobject_put(&cpc_ptr->kobj);
892 goto out_free;
893 }
894
895 arch_init_invariance_cppc();
896
897 kfree(output.pointer);
898 return 0;
899
900out_free:
901 /* Free all the mapped sys mem areas for this CPU */
902 for (i = 2; i < cpc_ptr->num_entries; i++) {
903 void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
904
905 if (addr)
906 iounmap(addr);
907 }
908 kfree(cpc_ptr);
909
910out_buf_free:
911 kfree(output.pointer);
912 return ret;
913}
914EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe);
915
916/**
917 * acpi_cppc_processor_exit - Cleanup CPC structs.
918 * @pr: Ptr to acpi_processor containing this CPU's logical ID.
919 *
920 * Return: Void
921 */
922void acpi_cppc_processor_exit(struct acpi_processor *pr)
923{
924 struct cpc_desc *cpc_ptr;
925 unsigned int i;
926 void __iomem *addr;
927 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id);
928
929 if (pcc_ss_id >= 0 && pcc_data[pcc_ss_id]) {
930 if (pcc_data[pcc_ss_id]->pcc_channel_acquired) {
931 pcc_data[pcc_ss_id]->refcount--;
932 if (!pcc_data[pcc_ss_id]->refcount) {
933 pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel);
934 kfree(pcc_data[pcc_ss_id]);
935 pcc_data[pcc_ss_id] = NULL;
936 }
937 }
938 }
939
940 cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
941 if (!cpc_ptr)
942 return;
943
944 /* Free all the mapped sys mem areas for this CPU */
945 for (i = 2; i < cpc_ptr->num_entries; i++) {
946 addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
947 if (addr)
948 iounmap(addr);
949 }
950
951 kobject_put(&cpc_ptr->kobj);
952 kfree(cpc_ptr);
953}
954EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit);
955
956/**
957 * cpc_read_ffh() - Read FFH register
958 * @cpunum: CPU number to read
959 * @reg: cppc register information
960 * @val: place holder for return value
961 *
962 * Read bit_width bits from a specified address and bit_offset
963 *
964 * Return: 0 for success and error code
965 */
966int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
967{
968 return -ENOTSUPP;
969}
970
971/**
972 * cpc_write_ffh() - Write FFH register
973 * @cpunum: CPU number to write
974 * @reg: cppc register information
975 * @val: value to write
976 *
977 * Write value of bit_width bits to a specified address and bit_offset
978 *
979 * Return: 0 for success and error code
980 */
981int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
982{
983 return -ENOTSUPP;
984}
985
986/*
987 * Since cpc_read and cpc_write are called while holding pcc_lock, it should be
988 * as fast as possible. We have already mapped the PCC subspace during init, so
989 * we can directly write to it.
990 */
991
992static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
993{
994 void __iomem *vaddr = NULL;
995 int size;
996 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
997 struct cpc_reg *reg = ®_res->cpc_entry.reg;
998
999 if (reg_res->type == ACPI_TYPE_INTEGER) {
1000 *val = reg_res->cpc_entry.int_value;
1001 return 0;
1002 }
1003
1004 *val = 0;
1005 size = GET_BIT_WIDTH(reg);
1006
1007 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
1008 u32 val_u32;
1009 acpi_status status;
1010
1011 status = acpi_os_read_port((acpi_io_address)reg->address,
1012 &val_u32, size);
1013 if (ACPI_FAILURE(status)) {
1014 pr_debug("Error: Failed to read SystemIO port %llx\n",
1015 reg->address);
1016 return -EFAULT;
1017 }
1018
1019 *val = val_u32;
1020 return 0;
1021 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) {
1022 /*
1023 * For registers in PCC space, the register size is determined
1024 * by the bit width field; the access size is used to indicate
1025 * the PCC subspace id.
1026 */
1027 size = reg->bit_width;
1028 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
1029 }
1030 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1031 vaddr = reg_res->sys_mem_vaddr;
1032 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
1033 return cpc_read_ffh(cpu, reg, val);
1034 else
1035 return acpi_os_read_memory((acpi_physical_address)reg->address,
1036 val, size);
1037
1038 switch (size) {
1039 case 8:
1040 *val = readb_relaxed(vaddr);
1041 break;
1042 case 16:
1043 *val = readw_relaxed(vaddr);
1044 break;
1045 case 32:
1046 *val = readl_relaxed(vaddr);
1047 break;
1048 case 64:
1049 *val = readq_relaxed(vaddr);
1050 break;
1051 default:
1052 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
1053 pr_debug("Error: Cannot read %u bit width from system memory: 0x%llx\n",
1054 size, reg->address);
1055 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
1056 pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n",
1057 size, pcc_ss_id);
1058 }
1059 return -EFAULT;
1060 }
1061
1062 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1063 *val = MASK_VAL(reg, *val);
1064
1065 return 0;
1066}
1067
1068static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
1069{
1070 int ret_val = 0;
1071 int size;
1072 void __iomem *vaddr = NULL;
1073 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1074 struct cpc_reg *reg = ®_res->cpc_entry.reg;
1075
1076 size = GET_BIT_WIDTH(reg);
1077
1078 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
1079 acpi_status status;
1080
1081 status = acpi_os_write_port((acpi_io_address)reg->address,
1082 (u32)val, size);
1083 if (ACPI_FAILURE(status)) {
1084 pr_debug("Error: Failed to write SystemIO port %llx\n",
1085 reg->address);
1086 return -EFAULT;
1087 }
1088
1089 return 0;
1090 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) {
1091 /*
1092 * For registers in PCC space, the register size is determined
1093 * by the bit width field; the access size is used to indicate
1094 * the PCC subspace id.
1095 */
1096 size = reg->bit_width;
1097 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
1098 }
1099 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1100 vaddr = reg_res->sys_mem_vaddr;
1101 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
1102 return cpc_write_ffh(cpu, reg, val);
1103 else
1104 return acpi_os_write_memory((acpi_physical_address)reg->address,
1105 val, size);
1106
1107 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1108 val = MASK_VAL(reg, val);
1109
1110 switch (size) {
1111 case 8:
1112 writeb_relaxed(val, vaddr);
1113 break;
1114 case 16:
1115 writew_relaxed(val, vaddr);
1116 break;
1117 case 32:
1118 writel_relaxed(val, vaddr);
1119 break;
1120 case 64:
1121 writeq_relaxed(val, vaddr);
1122 break;
1123 default:
1124 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
1125 pr_debug("Error: Cannot write %u bit width to system memory: 0x%llx\n",
1126 size, reg->address);
1127 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
1128 pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n",
1129 size, pcc_ss_id);
1130 }
1131 ret_val = -EFAULT;
1132 break;
1133 }
1134
1135 return ret_val;
1136}
1137
1138static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf)
1139{
1140 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1141 struct cpc_register_resource *reg;
1142
1143 if (!cpc_desc) {
1144 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1145 return -ENODEV;
1146 }
1147
1148 reg = &cpc_desc->cpc_regs[reg_idx];
1149
1150 if (CPC_IN_PCC(reg)) {
1151 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1152 struct cppc_pcc_data *pcc_ss_data = NULL;
1153 int ret = 0;
1154
1155 if (pcc_ss_id < 0)
1156 return -EIO;
1157
1158 pcc_ss_data = pcc_data[pcc_ss_id];
1159
1160 down_write(&pcc_ss_data->pcc_lock);
1161
1162 if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0)
1163 cpc_read(cpunum, reg, perf);
1164 else
1165 ret = -EIO;
1166
1167 up_write(&pcc_ss_data->pcc_lock);
1168
1169 return ret;
1170 }
1171
1172 cpc_read(cpunum, reg, perf);
1173
1174 return 0;
1175}
1176
1177/**
1178 * cppc_get_desired_perf - Get the desired performance register value.
1179 * @cpunum: CPU from which to get desired performance.
1180 * @desired_perf: Return address.
1181 *
1182 * Return: 0 for success, -EIO otherwise.
1183 */
1184int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
1185{
1186 return cppc_get_perf(cpunum, DESIRED_PERF, desired_perf);
1187}
1188EXPORT_SYMBOL_GPL(cppc_get_desired_perf);
1189
1190/**
1191 * cppc_get_nominal_perf - Get the nominal performance register value.
1192 * @cpunum: CPU from which to get nominal performance.
1193 * @nominal_perf: Return address.
1194 *
1195 * Return: 0 for success, -EIO otherwise.
1196 */
1197int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf)
1198{
1199 return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf);
1200}
1201
1202/**
1203 * cppc_get_highest_perf - Get the highest performance register value.
1204 * @cpunum: CPU from which to get highest performance.
1205 * @highest_perf: Return address.
1206 *
1207 * Return: 0 for success, -EIO otherwise.
1208 */
1209int cppc_get_highest_perf(int cpunum, u64 *highest_perf)
1210{
1211 return cppc_get_perf(cpunum, HIGHEST_PERF, highest_perf);
1212}
1213EXPORT_SYMBOL_GPL(cppc_get_highest_perf);
1214
1215/**
1216 * cppc_get_epp_perf - Get the epp register value.
1217 * @cpunum: CPU from which to get epp preference value.
1218 * @epp_perf: Return address.
1219 *
1220 * Return: 0 for success, -EIO otherwise.
1221 */
1222int cppc_get_epp_perf(int cpunum, u64 *epp_perf)
1223{
1224 return cppc_get_perf(cpunum, ENERGY_PERF, epp_perf);
1225}
1226EXPORT_SYMBOL_GPL(cppc_get_epp_perf);
1227
1228/**
1229 * cppc_get_perf_caps - Get a CPU's performance capabilities.
1230 * @cpunum: CPU from which to get capabilities info.
1231 * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h
1232 *
1233 * Return: 0 for success with perf_caps populated else -ERRNO.
1234 */
1235int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
1236{
1237 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1238 struct cpc_register_resource *highest_reg, *lowest_reg,
1239 *lowest_non_linear_reg, *nominal_reg, *guaranteed_reg,
1240 *low_freq_reg = NULL, *nom_freq_reg = NULL;
1241 u64 high, low, guaranteed, nom, min_nonlinear, low_f = 0, nom_f = 0;
1242 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1243 struct cppc_pcc_data *pcc_ss_data = NULL;
1244 int ret = 0, regs_in_pcc = 0;
1245
1246 if (!cpc_desc) {
1247 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1248 return -ENODEV;
1249 }
1250
1251 highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF];
1252 lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF];
1253 lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF];
1254 nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1255 low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ];
1256 nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ];
1257 guaranteed_reg = &cpc_desc->cpc_regs[GUARANTEED_PERF];
1258
1259 /* Are any of the regs PCC ?*/
1260 if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) ||
1261 CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) ||
1262 CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) {
1263 if (pcc_ss_id < 0) {
1264 pr_debug("Invalid pcc_ss_id\n");
1265 return -ENODEV;
1266 }
1267 pcc_ss_data = pcc_data[pcc_ss_id];
1268 regs_in_pcc = 1;
1269 down_write(&pcc_ss_data->pcc_lock);
1270 /* Ring doorbell once to update PCC subspace */
1271 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1272 ret = -EIO;
1273 goto out_err;
1274 }
1275 }
1276
1277 cpc_read(cpunum, highest_reg, &high);
1278 perf_caps->highest_perf = high;
1279
1280 cpc_read(cpunum, lowest_reg, &low);
1281 perf_caps->lowest_perf = low;
1282
1283 cpc_read(cpunum, nominal_reg, &nom);
1284 perf_caps->nominal_perf = nom;
1285
1286 if (guaranteed_reg->type != ACPI_TYPE_BUFFER ||
1287 IS_NULL_REG(&guaranteed_reg->cpc_entry.reg)) {
1288 perf_caps->guaranteed_perf = 0;
1289 } else {
1290 cpc_read(cpunum, guaranteed_reg, &guaranteed);
1291 perf_caps->guaranteed_perf = guaranteed;
1292 }
1293
1294 cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear);
1295 perf_caps->lowest_nonlinear_perf = min_nonlinear;
1296
1297 if (!high || !low || !nom || !min_nonlinear)
1298 ret = -EFAULT;
1299
1300 /* Read optional lowest and nominal frequencies if present */
1301 if (CPC_SUPPORTED(low_freq_reg))
1302 cpc_read(cpunum, low_freq_reg, &low_f);
1303
1304 if (CPC_SUPPORTED(nom_freq_reg))
1305 cpc_read(cpunum, nom_freq_reg, &nom_f);
1306
1307 perf_caps->lowest_freq = low_f;
1308 perf_caps->nominal_freq = nom_f;
1309
1310
1311out_err:
1312 if (regs_in_pcc)
1313 up_write(&pcc_ss_data->pcc_lock);
1314 return ret;
1315}
1316EXPORT_SYMBOL_GPL(cppc_get_perf_caps);
1317
1318/**
1319 * cppc_perf_ctrs_in_pcc - Check if any perf counters are in a PCC region.
1320 *
1321 * CPPC has flexibility about how CPU performance counters are accessed.
1322 * One of the choices is PCC regions, which can have a high access latency. This
1323 * routine allows callers of cppc_get_perf_ctrs() to know this ahead of time.
1324 *
1325 * Return: true if any of the counters are in PCC regions, false otherwise
1326 */
1327bool cppc_perf_ctrs_in_pcc(void)
1328{
1329 int cpu;
1330
1331 for_each_present_cpu(cpu) {
1332 struct cpc_register_resource *ref_perf_reg;
1333 struct cpc_desc *cpc_desc;
1334
1335 cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1336
1337 if (CPC_IN_PCC(&cpc_desc->cpc_regs[DELIVERED_CTR]) ||
1338 CPC_IN_PCC(&cpc_desc->cpc_regs[REFERENCE_CTR]) ||
1339 CPC_IN_PCC(&cpc_desc->cpc_regs[CTR_WRAP_TIME]))
1340 return true;
1341
1342
1343 ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
1344
1345 /*
1346 * If reference perf register is not supported then we should
1347 * use the nominal perf value
1348 */
1349 if (!CPC_SUPPORTED(ref_perf_reg))
1350 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1351
1352 if (CPC_IN_PCC(ref_perf_reg))
1353 return true;
1354 }
1355
1356 return false;
1357}
1358EXPORT_SYMBOL_GPL(cppc_perf_ctrs_in_pcc);
1359
1360/**
1361 * cppc_get_perf_ctrs - Read a CPU's performance feedback counters.
1362 * @cpunum: CPU from which to read counters.
1363 * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h
1364 *
1365 * Return: 0 for success with perf_fb_ctrs populated else -ERRNO.
1366 */
1367int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
1368{
1369 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1370 struct cpc_register_resource *delivered_reg, *reference_reg,
1371 *ref_perf_reg, *ctr_wrap_reg;
1372 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1373 struct cppc_pcc_data *pcc_ss_data = NULL;
1374 u64 delivered, reference, ref_perf, ctr_wrap_time;
1375 int ret = 0, regs_in_pcc = 0;
1376
1377 if (!cpc_desc) {
1378 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1379 return -ENODEV;
1380 }
1381
1382 delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
1383 reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
1384 ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
1385 ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME];
1386
1387 /*
1388 * If reference perf register is not supported then we should
1389 * use the nominal perf value
1390 */
1391 if (!CPC_SUPPORTED(ref_perf_reg))
1392 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1393
1394 /* Are any of the regs PCC ?*/
1395 if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) ||
1396 CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) {
1397 if (pcc_ss_id < 0) {
1398 pr_debug("Invalid pcc_ss_id\n");
1399 return -ENODEV;
1400 }
1401 pcc_ss_data = pcc_data[pcc_ss_id];
1402 down_write(&pcc_ss_data->pcc_lock);
1403 regs_in_pcc = 1;
1404 /* Ring doorbell once to update PCC subspace */
1405 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1406 ret = -EIO;
1407 goto out_err;
1408 }
1409 }
1410
1411 cpc_read(cpunum, delivered_reg, &delivered);
1412 cpc_read(cpunum, reference_reg, &reference);
1413 cpc_read(cpunum, ref_perf_reg, &ref_perf);
1414
1415 /*
1416 * Per spec, if ctr_wrap_time optional register is unsupported, then the
1417 * performance counters are assumed to never wrap during the lifetime of
1418 * platform
1419 */
1420 ctr_wrap_time = (u64)(~((u64)0));
1421 if (CPC_SUPPORTED(ctr_wrap_reg))
1422 cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time);
1423
1424 if (!delivered || !reference || !ref_perf) {
1425 ret = -EFAULT;
1426 goto out_err;
1427 }
1428
1429 perf_fb_ctrs->delivered = delivered;
1430 perf_fb_ctrs->reference = reference;
1431 perf_fb_ctrs->reference_perf = ref_perf;
1432 perf_fb_ctrs->wraparound_time = ctr_wrap_time;
1433out_err:
1434 if (regs_in_pcc)
1435 up_write(&pcc_ss_data->pcc_lock);
1436 return ret;
1437}
1438EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
1439
1440/*
1441 * Set Energy Performance Preference Register value through
1442 * Performance Controls Interface
1443 */
1444int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable)
1445{
1446 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1447 struct cpc_register_resource *epp_set_reg;
1448 struct cpc_register_resource *auto_sel_reg;
1449 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1450 struct cppc_pcc_data *pcc_ss_data = NULL;
1451 int ret;
1452
1453 if (!cpc_desc) {
1454 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1455 return -ENODEV;
1456 }
1457
1458 auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
1459 epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
1460
1461 if (CPC_IN_PCC(epp_set_reg) || CPC_IN_PCC(auto_sel_reg)) {
1462 if (pcc_ss_id < 0) {
1463 pr_debug("Invalid pcc_ss_id for CPU:%d\n", cpu);
1464 return -ENODEV;
1465 }
1466
1467 if (CPC_SUPPORTED(auto_sel_reg)) {
1468 ret = cpc_write(cpu, auto_sel_reg, enable);
1469 if (ret)
1470 return ret;
1471 }
1472
1473 if (CPC_SUPPORTED(epp_set_reg)) {
1474 ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
1475 if (ret)
1476 return ret;
1477 }
1478
1479 pcc_ss_data = pcc_data[pcc_ss_id];
1480
1481 down_write(&pcc_ss_data->pcc_lock);
1482 /* after writing CPC, transfer the ownership of PCC to platform */
1483 ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1484 up_write(&pcc_ss_data->pcc_lock);
1485 } else {
1486 ret = -ENOTSUPP;
1487 pr_debug("_CPC in PCC is not supported\n");
1488 }
1489
1490 return ret;
1491}
1492EXPORT_SYMBOL_GPL(cppc_set_epp_perf);
1493
1494/**
1495 * cppc_get_auto_sel_caps - Read autonomous selection register.
1496 * @cpunum : CPU from which to read register.
1497 * @perf_caps : struct where autonomous selection register value is updated.
1498 */
1499int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps)
1500{
1501 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1502 struct cpc_register_resource *auto_sel_reg;
1503 u64 auto_sel;
1504
1505 if (!cpc_desc) {
1506 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1507 return -ENODEV;
1508 }
1509
1510 auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
1511
1512 if (!CPC_SUPPORTED(auto_sel_reg))
1513 pr_warn_once("Autonomous mode is not unsupported!\n");
1514
1515 if (CPC_IN_PCC(auto_sel_reg)) {
1516 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1517 struct cppc_pcc_data *pcc_ss_data = NULL;
1518 int ret = 0;
1519
1520 if (pcc_ss_id < 0)
1521 return -ENODEV;
1522
1523 pcc_ss_data = pcc_data[pcc_ss_id];
1524
1525 down_write(&pcc_ss_data->pcc_lock);
1526
1527 if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) {
1528 cpc_read(cpunum, auto_sel_reg, &auto_sel);
1529 perf_caps->auto_sel = (bool)auto_sel;
1530 } else {
1531 ret = -EIO;
1532 }
1533
1534 up_write(&pcc_ss_data->pcc_lock);
1535
1536 return ret;
1537 }
1538
1539 return 0;
1540}
1541EXPORT_SYMBOL_GPL(cppc_get_auto_sel_caps);
1542
1543/**
1544 * cppc_set_auto_sel - Write autonomous selection register.
1545 * @cpu : CPU to which to write register.
1546 * @enable : the desired value of autonomous selection resiter to be updated.
1547 */
1548int cppc_set_auto_sel(int cpu, bool enable)
1549{
1550 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1551 struct cpc_register_resource *auto_sel_reg;
1552 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1553 struct cppc_pcc_data *pcc_ss_data = NULL;
1554 int ret = -EINVAL;
1555
1556 if (!cpc_desc) {
1557 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1558 return -ENODEV;
1559 }
1560
1561 auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
1562
1563 if (CPC_IN_PCC(auto_sel_reg)) {
1564 if (pcc_ss_id < 0) {
1565 pr_debug("Invalid pcc_ss_id\n");
1566 return -ENODEV;
1567 }
1568
1569 if (CPC_SUPPORTED(auto_sel_reg)) {
1570 ret = cpc_write(cpu, auto_sel_reg, enable);
1571 if (ret)
1572 return ret;
1573 }
1574
1575 pcc_ss_data = pcc_data[pcc_ss_id];
1576
1577 down_write(&pcc_ss_data->pcc_lock);
1578 /* after writing CPC, transfer the ownership of PCC to platform */
1579 ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1580 up_write(&pcc_ss_data->pcc_lock);
1581 } else {
1582 ret = -ENOTSUPP;
1583 pr_debug("_CPC in PCC is not supported\n");
1584 }
1585
1586 return ret;
1587}
1588EXPORT_SYMBOL_GPL(cppc_set_auto_sel);
1589
1590/**
1591 * cppc_set_enable - Set to enable CPPC on the processor by writing the
1592 * Continuous Performance Control package EnableRegister field.
1593 * @cpu: CPU for which to enable CPPC register.
1594 * @enable: 0 - disable, 1 - enable CPPC feature on the processor.
1595 *
1596 * Return: 0 for success, -ERRNO or -EIO otherwise.
1597 */
1598int cppc_set_enable(int cpu, bool enable)
1599{
1600 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1601 struct cpc_register_resource *enable_reg;
1602 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1603 struct cppc_pcc_data *pcc_ss_data = NULL;
1604 int ret = -EINVAL;
1605
1606 if (!cpc_desc) {
1607 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1608 return -EINVAL;
1609 }
1610
1611 enable_reg = &cpc_desc->cpc_regs[ENABLE];
1612
1613 if (CPC_IN_PCC(enable_reg)) {
1614
1615 if (pcc_ss_id < 0)
1616 return -EIO;
1617
1618 ret = cpc_write(cpu, enable_reg, enable);
1619 if (ret)
1620 return ret;
1621
1622 pcc_ss_data = pcc_data[pcc_ss_id];
1623
1624 down_write(&pcc_ss_data->pcc_lock);
1625 /* after writing CPC, transfer the ownership of PCC to platfrom */
1626 ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1627 up_write(&pcc_ss_data->pcc_lock);
1628 return ret;
1629 }
1630
1631 return cpc_write(cpu, enable_reg, enable);
1632}
1633EXPORT_SYMBOL_GPL(cppc_set_enable);
1634
1635/**
1636 * cppc_set_perf - Set a CPU's performance controls.
1637 * @cpu: CPU for which to set performance controls.
1638 * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h
1639 *
1640 * Return: 0 for success, -ERRNO otherwise.
1641 */
1642int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
1643{
1644 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1645 struct cpc_register_resource *desired_reg, *min_perf_reg, *max_perf_reg;
1646 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1647 struct cppc_pcc_data *pcc_ss_data = NULL;
1648 int ret = 0;
1649
1650 if (!cpc_desc) {
1651 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1652 return -ENODEV;
1653 }
1654
1655 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1656 min_perf_reg = &cpc_desc->cpc_regs[MIN_PERF];
1657 max_perf_reg = &cpc_desc->cpc_regs[MAX_PERF];
1658
1659 /*
1660 * This is Phase-I where we want to write to CPC registers
1661 * -> We want all CPUs to be able to execute this phase in parallel
1662 *
1663 * Since read_lock can be acquired by multiple CPUs simultaneously we
1664 * achieve that goal here
1665 */
1666 if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg)) {
1667 if (pcc_ss_id < 0) {
1668 pr_debug("Invalid pcc_ss_id\n");
1669 return -ENODEV;
1670 }
1671 pcc_ss_data = pcc_data[pcc_ss_id];
1672 down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */
1673 if (pcc_ss_data->platform_owns_pcc) {
1674 ret = check_pcc_chan(pcc_ss_id, false);
1675 if (ret) {
1676 up_read(&pcc_ss_data->pcc_lock);
1677 return ret;
1678 }
1679 }
1680 /*
1681 * Update the pending_write to make sure a PCC CMD_READ will not
1682 * arrive and steal the channel during the switch to write lock
1683 */
1684 pcc_ss_data->pending_pcc_write_cmd = true;
1685 cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt;
1686 cpc_desc->write_cmd_status = 0;
1687 }
1688
1689 cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
1690
1691 /*
1692 * Only write if min_perf and max_perf not zero. Some drivers pass zero
1693 * value to min and max perf, but they don't mean to set the zero value,
1694 * they just don't want to write to those registers.
1695 */
1696 if (perf_ctrls->min_perf)
1697 cpc_write(cpu, min_perf_reg, perf_ctrls->min_perf);
1698 if (perf_ctrls->max_perf)
1699 cpc_write(cpu, max_perf_reg, perf_ctrls->max_perf);
1700
1701 if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg))
1702 up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */
1703 /*
1704 * This is Phase-II where we transfer the ownership of PCC to Platform
1705 *
1706 * Short Summary: Basically if we think of a group of cppc_set_perf
1707 * requests that happened in short overlapping interval. The last CPU to
1708 * come out of Phase-I will enter Phase-II and ring the doorbell.
1709 *
1710 * We have the following requirements for Phase-II:
1711 * 1. We want to execute Phase-II only when there are no CPUs
1712 * currently executing in Phase-I
1713 * 2. Once we start Phase-II we want to avoid all other CPUs from
1714 * entering Phase-I.
1715 * 3. We want only one CPU among all those who went through Phase-I
1716 * to run phase-II
1717 *
1718 * If write_trylock fails to get the lock and doesn't transfer the
1719 * PCC ownership to the platform, then one of the following will be TRUE
1720 * 1. There is at-least one CPU in Phase-I which will later execute
1721 * write_trylock, so the CPUs in Phase-I will be responsible for
1722 * executing the Phase-II.
1723 * 2. Some other CPU has beaten this CPU to successfully execute the
1724 * write_trylock and has already acquired the write_lock. We know for a
1725 * fact it (other CPU acquiring the write_lock) couldn't have happened
1726 * before this CPU's Phase-I as we held the read_lock.
1727 * 3. Some other CPU executing pcc CMD_READ has stolen the
1728 * down_write, in which case, send_pcc_cmd will check for pending
1729 * CMD_WRITE commands by checking the pending_pcc_write_cmd.
1730 * So this CPU can be certain that its request will be delivered
1731 * So in all cases, this CPU knows that its request will be delivered
1732 * by another CPU and can return
1733 *
1734 * After getting the down_write we still need to check for
1735 * pending_pcc_write_cmd to take care of the following scenario
1736 * The thread running this code could be scheduled out between
1737 * Phase-I and Phase-II. Before it is scheduled back on, another CPU
1738 * could have delivered the request to Platform by triggering the
1739 * doorbell and transferred the ownership of PCC to platform. So this
1740 * avoids triggering an unnecessary doorbell and more importantly before
1741 * triggering the doorbell it makes sure that the PCC channel ownership
1742 * is still with OSPM.
1743 * pending_pcc_write_cmd can also be cleared by a different CPU, if
1744 * there was a pcc CMD_READ waiting on down_write and it steals the lock
1745 * before the pcc CMD_WRITE is completed. send_pcc_cmd checks for this
1746 * case during a CMD_READ and if there are pending writes it delivers
1747 * the write command before servicing the read command
1748 */
1749 if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg)) {
1750 if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */
1751 /* Update only if there are pending write commands */
1752 if (pcc_ss_data->pending_pcc_write_cmd)
1753 send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1754 up_write(&pcc_ss_data->pcc_lock); /* END Phase-II */
1755 } else
1756 /* Wait until pcc_write_cnt is updated by send_pcc_cmd */
1757 wait_event(pcc_ss_data->pcc_write_wait_q,
1758 cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt);
1759
1760 /* send_pcc_cmd updates the status in case of failure */
1761 ret = cpc_desc->write_cmd_status;
1762 }
1763 return ret;
1764}
1765EXPORT_SYMBOL_GPL(cppc_set_perf);
1766
1767/**
1768 * cppc_get_transition_latency - returns frequency transition latency in ns
1769 * @cpu_num: CPU number for per_cpu().
1770 *
1771 * ACPI CPPC does not explicitly specify how a platform can specify the
1772 * transition latency for performance change requests. The closest we have
1773 * is the timing information from the PCCT tables which provides the info
1774 * on the number and frequency of PCC commands the platform can handle.
1775 *
1776 * If desired_reg is in the SystemMemory or SystemIo ACPI address space,
1777 * then assume there is no latency.
1778 */
1779unsigned int cppc_get_transition_latency(int cpu_num)
1780{
1781 /*
1782 * Expected transition latency is based on the PCCT timing values
1783 * Below are definition from ACPI spec:
1784 * pcc_nominal- Expected latency to process a command, in microseconds
1785 * pcc_mpar - The maximum number of periodic requests that the subspace
1786 * channel can support, reported in commands per minute. 0
1787 * indicates no limitation.
1788 * pcc_mrtt - The minimum amount of time that OSPM must wait after the
1789 * completion of a command before issuing the next command,
1790 * in microseconds.
1791 */
1792 unsigned int latency_ns = 0;
1793 struct cpc_desc *cpc_desc;
1794 struct cpc_register_resource *desired_reg;
1795 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num);
1796 struct cppc_pcc_data *pcc_ss_data;
1797
1798 cpc_desc = per_cpu(cpc_desc_ptr, cpu_num);
1799 if (!cpc_desc)
1800 return CPUFREQ_ETERNAL;
1801
1802 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1803 if (CPC_IN_SYSTEM_MEMORY(desired_reg) || CPC_IN_SYSTEM_IO(desired_reg))
1804 return 0;
1805 else if (!CPC_IN_PCC(desired_reg))
1806 return CPUFREQ_ETERNAL;
1807
1808 if (pcc_ss_id < 0)
1809 return CPUFREQ_ETERNAL;
1810
1811 pcc_ss_data = pcc_data[pcc_ss_id];
1812 if (pcc_ss_data->pcc_mpar)
1813 latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar);
1814
1815 latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000);
1816 latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000);
1817
1818 return latency_ns;
1819}
1820EXPORT_SYMBOL_GPL(cppc_get_transition_latency);
1821
1822/* Minimum struct length needed for the DMI processor entry we want */
1823#define DMI_ENTRY_PROCESSOR_MIN_LENGTH 48
1824
1825/* Offset in the DMI processor structure for the max frequency */
1826#define DMI_PROCESSOR_MAX_SPEED 0x14
1827
1828/* Callback function used to retrieve the max frequency from DMI */
1829static void cppc_find_dmi_mhz(const struct dmi_header *dm, void *private)
1830{
1831 const u8 *dmi_data = (const u8 *)dm;
1832 u16 *mhz = (u16 *)private;
1833
1834 if (dm->type == DMI_ENTRY_PROCESSOR &&
1835 dm->length >= DMI_ENTRY_PROCESSOR_MIN_LENGTH) {
1836 u16 val = (u16)get_unaligned((const u16 *)
1837 (dmi_data + DMI_PROCESSOR_MAX_SPEED));
1838 *mhz = val > *mhz ? val : *mhz;
1839 }
1840}
1841
1842/* Look up the max frequency in DMI */
1843static u64 cppc_get_dmi_max_khz(void)
1844{
1845 u16 mhz = 0;
1846
1847 dmi_walk(cppc_find_dmi_mhz, &mhz);
1848
1849 /*
1850 * Real stupid fallback value, just in case there is no
1851 * actual value set.
1852 */
1853 mhz = mhz ? mhz : 1;
1854
1855 return KHZ_PER_MHZ * mhz;
1856}
1857
1858/*
1859 * If CPPC lowest_freq and nominal_freq registers are exposed then we can
1860 * use them to convert perf to freq and vice versa. The conversion is
1861 * extrapolated as an affine function passing by the 2 points:
1862 * - (Low perf, Low freq)
1863 * - (Nominal perf, Nominal freq)
1864 */
1865unsigned int cppc_perf_to_khz(struct cppc_perf_caps *caps, unsigned int perf)
1866{
1867 s64 retval, offset = 0;
1868 static u64 max_khz;
1869 u64 mul, div;
1870
1871 if (caps->lowest_freq && caps->nominal_freq) {
1872 mul = caps->nominal_freq - caps->lowest_freq;
1873 mul *= KHZ_PER_MHZ;
1874 div = caps->nominal_perf - caps->lowest_perf;
1875 offset = caps->nominal_freq * KHZ_PER_MHZ -
1876 div64_u64(caps->nominal_perf * mul, div);
1877 } else {
1878 if (!max_khz)
1879 max_khz = cppc_get_dmi_max_khz();
1880 mul = max_khz;
1881 div = caps->highest_perf;
1882 }
1883
1884 retval = offset + div64_u64(perf * mul, div);
1885 if (retval >= 0)
1886 return retval;
1887 return 0;
1888}
1889EXPORT_SYMBOL_GPL(cppc_perf_to_khz);
1890
1891unsigned int cppc_khz_to_perf(struct cppc_perf_caps *caps, unsigned int freq)
1892{
1893 s64 retval, offset = 0;
1894 static u64 max_khz;
1895 u64 mul, div;
1896
1897 if (caps->lowest_freq && caps->nominal_freq) {
1898 mul = caps->nominal_perf - caps->lowest_perf;
1899 div = caps->nominal_freq - caps->lowest_freq;
1900 /*
1901 * We don't need to convert to kHz for computing offset and can
1902 * directly use nominal_freq and lowest_freq as the div64_u64
1903 * will remove the frequency unit.
1904 */
1905 offset = caps->nominal_perf -
1906 div64_u64(caps->nominal_freq * mul, div);
1907 /* But we need it for computing the perf level. */
1908 div *= KHZ_PER_MHZ;
1909 } else {
1910 if (!max_khz)
1911 max_khz = cppc_get_dmi_max_khz();
1912 mul = caps->highest_perf;
1913 div = max_khz;
1914 }
1915
1916 retval = offset + div64_u64(freq * mul, div);
1917 if (retval >= 0)
1918 return retval;
1919 return 0;
1920}
1921EXPORT_SYMBOL_GPL(cppc_khz_to_perf);