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1/*
2 * Open Host Controller Interface (OHCI) driver for USB.
3 *
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
5 *
6 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
7 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
8 *
9 * [ Initialisation is based on Linus' ]
10 * [ uhci code and gregs ohci fragments ]
11 * [ (C) Copyright 1999 Linus Torvalds ]
12 * [ (C) Copyright 1999 Gregory P. Smith]
13 *
14 *
15 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
16 * interfaces (though some non-x86 Intel chips use it). It supports
17 * smarter hardware than UHCI. A download link for the spec available
18 * through the http://www.usb.org website.
19 *
20 * This file is licenced under the GPL.
21 */
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/pci.h>
26#include <linux/kernel.h>
27#include <linux/delay.h>
28#include <linux/ioport.h>
29#include <linux/sched.h>
30#include <linux/slab.h>
31#include <linux/errno.h>
32#include <linux/init.h>
33#include <linux/timer.h>
34#include <linux/list.h>
35#include <linux/usb.h>
36#include <linux/usb/otg.h>
37#include <linux/usb/hcd.h>
38#include <linux/dma-mapping.h>
39#include <linux/dmapool.h>
40#include <linux/workqueue.h>
41#include <linux/debugfs.h>
42
43#include <asm/io.h>
44#include <asm/irq.h>
45#include <asm/system.h>
46#include <asm/unaligned.h>
47#include <asm/byteorder.h>
48
49
50#define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
51#define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
52
53/*-------------------------------------------------------------------------*/
54
55#undef OHCI_VERBOSE_DEBUG /* not always helpful */
56
57/* For initializing controller (mask in an HCFS mode too) */
58#define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
59#define OHCI_INTR_INIT \
60 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
61 | OHCI_INTR_RD | OHCI_INTR_WDH)
62
63#ifdef __hppa__
64/* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
65#define IR_DISABLE
66#endif
67
68#ifdef CONFIG_ARCH_OMAP
69/* OMAP doesn't support IR (no SMM; not needed) */
70#define IR_DISABLE
71#endif
72
73/*-------------------------------------------------------------------------*/
74
75static const char hcd_name [] = "ohci_hcd";
76
77#define STATECHANGE_DELAY msecs_to_jiffies(300)
78
79#include "ohci.h"
80#include "pci-quirks.h"
81
82static void ohci_dump (struct ohci_hcd *ohci, int verbose);
83static int ohci_init (struct ohci_hcd *ohci);
84static void ohci_stop (struct usb_hcd *hcd);
85
86#if defined(CONFIG_PM) || defined(CONFIG_PCI)
87static int ohci_restart (struct ohci_hcd *ohci);
88#endif
89
90#ifdef CONFIG_PCI
91static void sb800_prefetch(struct ohci_hcd *ohci, int on);
92#else
93static inline void sb800_prefetch(struct ohci_hcd *ohci, int on)
94{
95 return;
96}
97#endif
98
99
100#include "ohci-hub.c"
101#include "ohci-dbg.c"
102#include "ohci-mem.c"
103#include "ohci-q.c"
104
105
106/*
107 * On architectures with edge-triggered interrupts we must never return
108 * IRQ_NONE.
109 */
110#if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
111#define IRQ_NOTMINE IRQ_HANDLED
112#else
113#define IRQ_NOTMINE IRQ_NONE
114#endif
115
116
117/* Some boards misreport power switching/overcurrent */
118static int distrust_firmware = 1;
119module_param (distrust_firmware, bool, 0);
120MODULE_PARM_DESC (distrust_firmware,
121 "true to distrust firmware power/overcurrent setup");
122
123/* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
124static int no_handshake = 0;
125module_param (no_handshake, bool, 0);
126MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
127
128/*-------------------------------------------------------------------------*/
129
130/*
131 * queue up an urb for anything except the root hub
132 */
133static int ohci_urb_enqueue (
134 struct usb_hcd *hcd,
135 struct urb *urb,
136 gfp_t mem_flags
137) {
138 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
139 struct ed *ed;
140 urb_priv_t *urb_priv;
141 unsigned int pipe = urb->pipe;
142 int i, size = 0;
143 unsigned long flags;
144 int retval = 0;
145
146#ifdef OHCI_VERBOSE_DEBUG
147 urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS);
148#endif
149
150 /* every endpoint has a ed, locate and maybe (re)initialize it */
151 if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval)))
152 return -ENOMEM;
153
154 /* for the private part of the URB we need the number of TDs (size) */
155 switch (ed->type) {
156 case PIPE_CONTROL:
157 /* td_submit_urb() doesn't yet handle these */
158 if (urb->transfer_buffer_length > 4096)
159 return -EMSGSIZE;
160
161 /* 1 TD for setup, 1 for ACK, plus ... */
162 size = 2;
163 /* FALLTHROUGH */
164 // case PIPE_INTERRUPT:
165 // case PIPE_BULK:
166 default:
167 /* one TD for every 4096 Bytes (can be up to 8K) */
168 size += urb->transfer_buffer_length / 4096;
169 /* ... and for any remaining bytes ... */
170 if ((urb->transfer_buffer_length % 4096) != 0)
171 size++;
172 /* ... and maybe a zero length packet to wrap it up */
173 if (size == 0)
174 size++;
175 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
176 && (urb->transfer_buffer_length
177 % usb_maxpacket (urb->dev, pipe,
178 usb_pipeout (pipe))) == 0)
179 size++;
180 break;
181 case PIPE_ISOCHRONOUS: /* number of packets from URB */
182 size = urb->number_of_packets;
183 break;
184 }
185
186 /* allocate the private part of the URB */
187 urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
188 mem_flags);
189 if (!urb_priv)
190 return -ENOMEM;
191 INIT_LIST_HEAD (&urb_priv->pending);
192 urb_priv->length = size;
193 urb_priv->ed = ed;
194
195 /* allocate the TDs (deferring hash chain updates) */
196 for (i = 0; i < size; i++) {
197 urb_priv->td [i] = td_alloc (ohci, mem_flags);
198 if (!urb_priv->td [i]) {
199 urb_priv->length = i;
200 urb_free_priv (ohci, urb_priv);
201 return -ENOMEM;
202 }
203 }
204
205 spin_lock_irqsave (&ohci->lock, flags);
206
207 /* don't submit to a dead HC */
208 if (!HCD_HW_ACCESSIBLE(hcd)) {
209 retval = -ENODEV;
210 goto fail;
211 }
212 if (!HC_IS_RUNNING(hcd->state)) {
213 retval = -ENODEV;
214 goto fail;
215 }
216 retval = usb_hcd_link_urb_to_ep(hcd, urb);
217 if (retval)
218 goto fail;
219
220 /* schedule the ed if needed */
221 if (ed->state == ED_IDLE) {
222 retval = ed_schedule (ohci, ed);
223 if (retval < 0) {
224 usb_hcd_unlink_urb_from_ep(hcd, urb);
225 goto fail;
226 }
227 if (ed->type == PIPE_ISOCHRONOUS) {
228 u16 frame = ohci_frame_no(ohci);
229
230 /* delay a few frames before the first TD */
231 frame += max_t (u16, 8, ed->interval);
232 frame &= ~(ed->interval - 1);
233 frame |= ed->branch;
234 urb->start_frame = frame;
235
236 /* yes, only URB_ISO_ASAP is supported, and
237 * urb->start_frame is never used as input.
238 */
239 }
240 } else if (ed->type == PIPE_ISOCHRONOUS)
241 urb->start_frame = ed->last_iso + ed->interval;
242
243 /* fill the TDs and link them to the ed; and
244 * enable that part of the schedule, if needed
245 * and update count of queued periodic urbs
246 */
247 urb->hcpriv = urb_priv;
248 td_submit_urb (ohci, urb);
249
250fail:
251 if (retval)
252 urb_free_priv (ohci, urb_priv);
253 spin_unlock_irqrestore (&ohci->lock, flags);
254 return retval;
255}
256
257/*
258 * decouple the URB from the HC queues (TDs, urb_priv).
259 * reporting is always done
260 * asynchronously, and we might be dealing with an urb that's
261 * partially transferred, or an ED with other urbs being unlinked.
262 */
263static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
264{
265 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
266 unsigned long flags;
267 int rc;
268
269#ifdef OHCI_VERBOSE_DEBUG
270 urb_print(urb, "UNLINK", 1, status);
271#endif
272
273 spin_lock_irqsave (&ohci->lock, flags);
274 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
275 if (rc) {
276 ; /* Do nothing */
277 } else if (HC_IS_RUNNING(hcd->state)) {
278 urb_priv_t *urb_priv;
279
280 /* Unless an IRQ completed the unlink while it was being
281 * handed to us, flag it for unlink and giveback, and force
282 * some upcoming INTR_SF to call finish_unlinks()
283 */
284 urb_priv = urb->hcpriv;
285 if (urb_priv) {
286 if (urb_priv->ed->state == ED_OPER)
287 start_ed_unlink (ohci, urb_priv->ed);
288 }
289 } else {
290 /*
291 * with HC dead, we won't respect hc queue pointers
292 * any more ... just clean up every urb's memory.
293 */
294 if (urb->hcpriv)
295 finish_urb(ohci, urb, status);
296 }
297 spin_unlock_irqrestore (&ohci->lock, flags);
298 return rc;
299}
300
301/*-------------------------------------------------------------------------*/
302
303/* frees config/altsetting state for endpoints,
304 * including ED memory, dummy TD, and bulk/intr data toggle
305 */
306
307static void
308ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
309{
310 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
311 unsigned long flags;
312 struct ed *ed = ep->hcpriv;
313 unsigned limit = 1000;
314
315 /* ASSERT: any requests/urbs are being unlinked */
316 /* ASSERT: nobody can be submitting urbs for this any more */
317
318 if (!ed)
319 return;
320
321rescan:
322 spin_lock_irqsave (&ohci->lock, flags);
323
324 if (!HC_IS_RUNNING (hcd->state)) {
325sanitize:
326 ed->state = ED_IDLE;
327 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
328 ohci->eds_scheduled--;
329 finish_unlinks (ohci, 0);
330 }
331
332 switch (ed->state) {
333 case ED_UNLINK: /* wait for hw to finish? */
334 /* major IRQ delivery trouble loses INTR_SF too... */
335 if (limit-- == 0) {
336 ohci_warn(ohci, "ED unlink timeout\n");
337 if (quirk_zfmicro(ohci)) {
338 ohci_warn(ohci, "Attempting ZF TD recovery\n");
339 ohci->ed_to_check = ed;
340 ohci->zf_delay = 2;
341 }
342 goto sanitize;
343 }
344 spin_unlock_irqrestore (&ohci->lock, flags);
345 schedule_timeout_uninterruptible(1);
346 goto rescan;
347 case ED_IDLE: /* fully unlinked */
348 if (list_empty (&ed->td_list)) {
349 td_free (ohci, ed->dummy);
350 ed_free (ohci, ed);
351 break;
352 }
353 /* else FALL THROUGH */
354 default:
355 /* caller was supposed to have unlinked any requests;
356 * that's not our job. can't recover; must leak ed.
357 */
358 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
359 ed, ep->desc.bEndpointAddress, ed->state,
360 list_empty (&ed->td_list) ? "" : " (has tds)");
361 td_free (ohci, ed->dummy);
362 break;
363 }
364 ep->hcpriv = NULL;
365 spin_unlock_irqrestore (&ohci->lock, flags);
366}
367
368static int ohci_get_frame (struct usb_hcd *hcd)
369{
370 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
371
372 return ohci_frame_no(ohci);
373}
374
375static void ohci_usb_reset (struct ohci_hcd *ohci)
376{
377 ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
378 ohci->hc_control &= OHCI_CTRL_RWC;
379 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
380}
381
382/* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
383 * other cases where the next software may expect clean state from the
384 * "firmware". this is bus-neutral, unlike shutdown() methods.
385 */
386static void
387ohci_shutdown (struct usb_hcd *hcd)
388{
389 struct ohci_hcd *ohci;
390
391 ohci = hcd_to_ohci (hcd);
392 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
393 ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
394
395 /* If the SHUTDOWN quirk is set, don't put the controller in RESET */
396 ohci->hc_control &= (ohci->flags & OHCI_QUIRK_SHUTDOWN ?
397 OHCI_CTRL_RWC | OHCI_CTRL_HCFS :
398 OHCI_CTRL_RWC);
399 ohci_writel(ohci, ohci->hc_control, &ohci->regs->control);
400
401 /* flush the writes */
402 (void) ohci_readl (ohci, &ohci->regs->control);
403}
404
405static int check_ed(struct ohci_hcd *ohci, struct ed *ed)
406{
407 return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0
408 && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK)
409 == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK)
410 && !list_empty(&ed->td_list);
411}
412
413/* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes
414 * an interrupt TD but neglects to add it to the donelist. On systems with
415 * this chipset, we need to periodically check the state of the queues to look
416 * for such "lost" TDs.
417 */
418static void unlink_watchdog_func(unsigned long _ohci)
419{
420 unsigned long flags;
421 unsigned max;
422 unsigned seen_count = 0;
423 unsigned i;
424 struct ed **seen = NULL;
425 struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci;
426
427 spin_lock_irqsave(&ohci->lock, flags);
428 max = ohci->eds_scheduled;
429 if (!max)
430 goto done;
431
432 if (ohci->ed_to_check)
433 goto out;
434
435 seen = kcalloc(max, sizeof *seen, GFP_ATOMIC);
436 if (!seen)
437 goto out;
438
439 for (i = 0; i < NUM_INTS; i++) {
440 struct ed *ed = ohci->periodic[i];
441
442 while (ed) {
443 unsigned temp;
444
445 /* scan this branch of the periodic schedule tree */
446 for (temp = 0; temp < seen_count; temp++) {
447 if (seen[temp] == ed) {
448 /* we've checked it and what's after */
449 ed = NULL;
450 break;
451 }
452 }
453 if (!ed)
454 break;
455 seen[seen_count++] = ed;
456 if (!check_ed(ohci, ed)) {
457 ed = ed->ed_next;
458 continue;
459 }
460
461 /* HC's TD list is empty, but HCD sees at least one
462 * TD that's not been sent through the donelist.
463 */
464 ohci->ed_to_check = ed;
465 ohci->zf_delay = 2;
466
467 /* The HC may wait until the next frame to report the
468 * TD as done through the donelist and INTR_WDH. (We
469 * just *assume* it's not a multi-TD interrupt URB;
470 * those could defer the IRQ more than one frame, using
471 * DI...) Check again after the next INTR_SF.
472 */
473 ohci_writel(ohci, OHCI_INTR_SF,
474 &ohci->regs->intrstatus);
475 ohci_writel(ohci, OHCI_INTR_SF,
476 &ohci->regs->intrenable);
477
478 /* flush those writes */
479 (void) ohci_readl(ohci, &ohci->regs->control);
480
481 goto out;
482 }
483 }
484out:
485 kfree(seen);
486 if (ohci->eds_scheduled)
487 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
488done:
489 spin_unlock_irqrestore(&ohci->lock, flags);
490}
491
492/*-------------------------------------------------------------------------*
493 * HC functions
494 *-------------------------------------------------------------------------*/
495
496/* init memory, and kick BIOS/SMM off */
497
498static int ohci_init (struct ohci_hcd *ohci)
499{
500 int ret;
501 struct usb_hcd *hcd = ohci_to_hcd(ohci);
502
503 if (distrust_firmware)
504 ohci->flags |= OHCI_QUIRK_HUB_POWER;
505
506 disable (ohci);
507 ohci->regs = hcd->regs;
508
509 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
510 * was never needed for most non-PCI systems ... remove the code?
511 */
512
513#ifndef IR_DISABLE
514 /* SMM owns the HC? not for long! */
515 if (!no_handshake && ohci_readl (ohci,
516 &ohci->regs->control) & OHCI_CTRL_IR) {
517 u32 temp;
518
519 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
520
521 /* this timeout is arbitrary. we make it long, so systems
522 * depending on usb keyboards may be usable even if the
523 * BIOS/SMM code seems pretty broken.
524 */
525 temp = 500; /* arbitrary: five seconds */
526
527 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
528 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
529 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
530 msleep (10);
531 if (--temp == 0) {
532 ohci_err (ohci, "USB HC takeover failed!"
533 " (BIOS/SMM bug)\n");
534 return -EBUSY;
535 }
536 }
537 ohci_usb_reset (ohci);
538 }
539#endif
540
541 /* Disable HC interrupts */
542 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
543
544 /* flush the writes, and save key bits like RWC */
545 if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
546 ohci->hc_control |= OHCI_CTRL_RWC;
547
548 /* Read the number of ports unless overridden */
549 if (ohci->num_ports == 0)
550 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
551
552 if (ohci->hcca)
553 return 0;
554
555 ohci->hcca = dma_alloc_coherent (hcd->self.controller,
556 sizeof *ohci->hcca, &ohci->hcca_dma, 0);
557 if (!ohci->hcca)
558 return -ENOMEM;
559
560 if ((ret = ohci_mem_init (ohci)) < 0)
561 ohci_stop (hcd);
562 else {
563 create_debug_files (ohci);
564 }
565
566 return ret;
567}
568
569/*-------------------------------------------------------------------------*/
570
571/* Start an OHCI controller, set the BUS operational
572 * resets USB and controller
573 * enable interrupts
574 */
575static int ohci_run (struct ohci_hcd *ohci)
576{
577 u32 mask, val;
578 int first = ohci->fminterval == 0;
579 struct usb_hcd *hcd = ohci_to_hcd(ohci);
580
581 disable (ohci);
582
583 /* boot firmware should have set this up (5.1.1.3.1) */
584 if (first) {
585
586 val = ohci_readl (ohci, &ohci->regs->fminterval);
587 ohci->fminterval = val & 0x3fff;
588 if (ohci->fminterval != FI)
589 ohci_dbg (ohci, "fminterval delta %d\n",
590 ohci->fminterval - FI);
591 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
592 /* also: power/overcurrent flags in roothub.a */
593 }
594
595 /* Reset USB nearly "by the book". RemoteWakeupConnected has
596 * to be checked in case boot firmware (BIOS/SMM/...) has set up
597 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
598 * If the bus glue detected wakeup capability then it should
599 * already be enabled; if so we'll just enable it again.
600 */
601 if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
602 device_set_wakeup_capable(hcd->self.controller, 1);
603
604 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
605 case OHCI_USB_OPER:
606 val = 0;
607 break;
608 case OHCI_USB_SUSPEND:
609 case OHCI_USB_RESUME:
610 ohci->hc_control &= OHCI_CTRL_RWC;
611 ohci->hc_control |= OHCI_USB_RESUME;
612 val = 10 /* msec wait */;
613 break;
614 // case OHCI_USB_RESET:
615 default:
616 ohci->hc_control &= OHCI_CTRL_RWC;
617 ohci->hc_control |= OHCI_USB_RESET;
618 val = 50 /* msec wait */;
619 break;
620 }
621 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
622 // flush the writes
623 (void) ohci_readl (ohci, &ohci->regs->control);
624 msleep(val);
625
626 memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
627
628 /* 2msec timelimit here means no irqs/preempt */
629 spin_lock_irq (&ohci->lock);
630
631retry:
632 /* HC Reset requires max 10 us delay */
633 ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus);
634 val = 30; /* ... allow extra time */
635 while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
636 if (--val == 0) {
637 spin_unlock_irq (&ohci->lock);
638 ohci_err (ohci, "USB HC reset timed out!\n");
639 return -1;
640 }
641 udelay (1);
642 }
643
644 /* now we're in the SUSPEND state ... must go OPERATIONAL
645 * within 2msec else HC enters RESUME
646 *
647 * ... but some hardware won't init fmInterval "by the book"
648 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
649 * this if we write fmInterval after we're OPERATIONAL.
650 * Unclear about ALi, ServerWorks, and others ... this could
651 * easily be a longstanding bug in chip init on Linux.
652 */
653 if (ohci->flags & OHCI_QUIRK_INITRESET) {
654 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
655 // flush those writes
656 (void) ohci_readl (ohci, &ohci->regs->control);
657 }
658
659 /* Tell the controller where the control and bulk lists are
660 * The lists are empty now. */
661 ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
662 ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
663
664 /* a reset clears this */
665 ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
666
667 periodic_reinit (ohci);
668
669 /* some OHCI implementations are finicky about how they init.
670 * bogus values here mean not even enumeration could work.
671 */
672 if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
673 || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
674 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
675 ohci->flags |= OHCI_QUIRK_INITRESET;
676 ohci_dbg (ohci, "enabling initreset quirk\n");
677 goto retry;
678 }
679 spin_unlock_irq (&ohci->lock);
680 ohci_err (ohci, "init err (%08x %04x)\n",
681 ohci_readl (ohci, &ohci->regs->fminterval),
682 ohci_readl (ohci, &ohci->regs->periodicstart));
683 return -EOVERFLOW;
684 }
685
686 /* use rhsc irqs after khubd is fully initialized */
687 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
688 hcd->uses_new_polling = 1;
689
690 /* start controller operations */
691 ohci->hc_control &= OHCI_CTRL_RWC;
692 ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
693 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
694 hcd->state = HC_STATE_RUNNING;
695
696 /* wake on ConnectStatusChange, matching external hubs */
697 ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
698
699 /* Choose the interrupts we care about now, others later on demand */
700 mask = OHCI_INTR_INIT;
701 ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
702 ohci_writel (ohci, mask, &ohci->regs->intrenable);
703
704 /* handle root hub init quirks ... */
705 val = roothub_a (ohci);
706 val &= ~(RH_A_PSM | RH_A_OCPM);
707 if (ohci->flags & OHCI_QUIRK_SUPERIO) {
708 /* NSC 87560 and maybe others */
709 val |= RH_A_NOCP;
710 val &= ~(RH_A_POTPGT | RH_A_NPS);
711 ohci_writel (ohci, val, &ohci->regs->roothub.a);
712 } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
713 (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
714 /* hub power always on; required for AMD-756 and some
715 * Mac platforms. ganged overcurrent reporting, if any.
716 */
717 val |= RH_A_NPS;
718 ohci_writel (ohci, val, &ohci->regs->roothub.a);
719 }
720 ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
721 ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
722 &ohci->regs->roothub.b);
723 // flush those writes
724 (void) ohci_readl (ohci, &ohci->regs->control);
725
726 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
727 spin_unlock_irq (&ohci->lock);
728
729 // POTPGT delay is bits 24-31, in 2 ms units.
730 mdelay ((val >> 23) & 0x1fe);
731 hcd->state = HC_STATE_RUNNING;
732
733 if (quirk_zfmicro(ohci)) {
734 /* Create timer to watch for bad queue state on ZF Micro */
735 setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func,
736 (unsigned long) ohci);
737
738 ohci->eds_scheduled = 0;
739 ohci->ed_to_check = NULL;
740 }
741
742 ohci_dump (ohci, 1);
743
744 return 0;
745}
746
747/*-------------------------------------------------------------------------*/
748
749/* an interrupt happens */
750
751static irqreturn_t ohci_irq (struct usb_hcd *hcd)
752{
753 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
754 struct ohci_regs __iomem *regs = ohci->regs;
755 int ints;
756
757 /* Read interrupt status (and flush pending writes). We ignore the
758 * optimization of checking the LSB of hcca->done_head; it doesn't
759 * work on all systems (edge triggering for OHCI can be a factor).
760 */
761 ints = ohci_readl(ohci, ®s->intrstatus);
762
763 /* Check for an all 1's result which is a typical consequence
764 * of dead, unclocked, or unplugged (CardBus...) devices
765 */
766 if (ints == ~(u32)0) {
767 disable (ohci);
768 ohci_dbg (ohci, "device removed!\n");
769 usb_hc_died(hcd);
770 return IRQ_HANDLED;
771 }
772
773 /* We only care about interrupts that are enabled */
774 ints &= ohci_readl(ohci, ®s->intrenable);
775
776 /* interrupt for some other device? */
777 if (ints == 0 || unlikely(hcd->state == HC_STATE_HALT))
778 return IRQ_NOTMINE;
779
780 if (ints & OHCI_INTR_UE) {
781 // e.g. due to PCI Master/Target Abort
782 if (quirk_nec(ohci)) {
783 /* Workaround for a silicon bug in some NEC chips used
784 * in Apple's PowerBooks. Adapted from Darwin code.
785 */
786 ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
787
788 ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable);
789
790 schedule_work (&ohci->nec_work);
791 } else {
792 disable (ohci);
793 ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
794 usb_hc_died(hcd);
795 }
796
797 ohci_dump (ohci, 1);
798 ohci_usb_reset (ohci);
799 }
800
801 if (ints & OHCI_INTR_RHSC) {
802 ohci_vdbg(ohci, "rhsc\n");
803 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
804 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
805 ®s->intrstatus);
806
807 /* NOTE: Vendors didn't always make the same implementation
808 * choices for RHSC. Many followed the spec; RHSC triggers
809 * on an edge, like setting and maybe clearing a port status
810 * change bit. With others it's level-triggered, active
811 * until khubd clears all the port status change bits. We'll
812 * always disable it here and rely on polling until khubd
813 * re-enables it.
814 */
815 ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable);
816 usb_hcd_poll_rh_status(hcd);
817 }
818
819 /* For connect and disconnect events, we expect the controller
820 * to turn on RHSC along with RD. But for remote wakeup events
821 * this might not happen.
822 */
823 else if (ints & OHCI_INTR_RD) {
824 ohci_vdbg(ohci, "resume detect\n");
825 ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus);
826 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
827 if (ohci->autostop) {
828 spin_lock (&ohci->lock);
829 ohci_rh_resume (ohci);
830 spin_unlock (&ohci->lock);
831 } else
832 usb_hcd_resume_root_hub(hcd);
833 }
834
835 if (ints & OHCI_INTR_WDH) {
836 spin_lock (&ohci->lock);
837 dl_done_list (ohci);
838 spin_unlock (&ohci->lock);
839 }
840
841 if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) {
842 spin_lock(&ohci->lock);
843 if (ohci->ed_to_check) {
844 struct ed *ed = ohci->ed_to_check;
845
846 if (check_ed(ohci, ed)) {
847 /* HC thinks the TD list is empty; HCD knows
848 * at least one TD is outstanding
849 */
850 if (--ohci->zf_delay == 0) {
851 struct td *td = list_entry(
852 ed->td_list.next,
853 struct td, td_list);
854 ohci_warn(ohci,
855 "Reclaiming orphan TD %p\n",
856 td);
857 takeback_td(ohci, td);
858 ohci->ed_to_check = NULL;
859 }
860 } else
861 ohci->ed_to_check = NULL;
862 }
863 spin_unlock(&ohci->lock);
864 }
865
866 /* could track INTR_SO to reduce available PCI/... bandwidth */
867
868 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
869 * when there's still unlinking to be done (next frame).
870 */
871 spin_lock (&ohci->lock);
872 if (ohci->ed_rm_list)
873 finish_unlinks (ohci, ohci_frame_no(ohci));
874 if ((ints & OHCI_INTR_SF) != 0
875 && !ohci->ed_rm_list
876 && !ohci->ed_to_check
877 && HC_IS_RUNNING(hcd->state))
878 ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable);
879 spin_unlock (&ohci->lock);
880
881 if (HC_IS_RUNNING(hcd->state)) {
882 ohci_writel (ohci, ints, ®s->intrstatus);
883 ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable);
884 // flush those writes
885 (void) ohci_readl (ohci, &ohci->regs->control);
886 }
887
888 return IRQ_HANDLED;
889}
890
891/*-------------------------------------------------------------------------*/
892
893static void ohci_stop (struct usb_hcd *hcd)
894{
895 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
896
897 ohci_dump (ohci, 1);
898
899 if (quirk_nec(ohci))
900 flush_work_sync(&ohci->nec_work);
901
902 ohci_usb_reset (ohci);
903 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
904 free_irq(hcd->irq, hcd);
905 hcd->irq = -1;
906
907 if (quirk_zfmicro(ohci))
908 del_timer(&ohci->unlink_watchdog);
909 if (quirk_amdiso(ohci))
910 usb_amd_dev_put();
911
912 remove_debug_files (ohci);
913 ohci_mem_cleanup (ohci);
914 if (ohci->hcca) {
915 dma_free_coherent (hcd->self.controller,
916 sizeof *ohci->hcca,
917 ohci->hcca, ohci->hcca_dma);
918 ohci->hcca = NULL;
919 ohci->hcca_dma = 0;
920 }
921}
922
923/*-------------------------------------------------------------------------*/
924
925#if defined(CONFIG_PM) || defined(CONFIG_PCI)
926
927/* must not be called from interrupt context */
928static int ohci_restart (struct ohci_hcd *ohci)
929{
930 int temp;
931 int i;
932 struct urb_priv *priv;
933
934 spin_lock_irq(&ohci->lock);
935 disable (ohci);
936
937 /* Recycle any "live" eds/tds (and urbs). */
938 if (!list_empty (&ohci->pending))
939 ohci_dbg(ohci, "abort schedule...\n");
940 list_for_each_entry (priv, &ohci->pending, pending) {
941 struct urb *urb = priv->td[0]->urb;
942 struct ed *ed = priv->ed;
943
944 switch (ed->state) {
945 case ED_OPER:
946 ed->state = ED_UNLINK;
947 ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
948 ed_deschedule (ohci, ed);
949
950 ed->ed_next = ohci->ed_rm_list;
951 ed->ed_prev = NULL;
952 ohci->ed_rm_list = ed;
953 /* FALLTHROUGH */
954 case ED_UNLINK:
955 break;
956 default:
957 ohci_dbg(ohci, "bogus ed %p state %d\n",
958 ed, ed->state);
959 }
960
961 if (!urb->unlinked)
962 urb->unlinked = -ESHUTDOWN;
963 }
964 finish_unlinks (ohci, 0);
965 spin_unlock_irq(&ohci->lock);
966
967 /* paranoia, in case that didn't work: */
968
969 /* empty the interrupt branches */
970 for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
971 for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
972
973 /* no EDs to remove */
974 ohci->ed_rm_list = NULL;
975
976 /* empty control and bulk lists */
977 ohci->ed_controltail = NULL;
978 ohci->ed_bulktail = NULL;
979
980 if ((temp = ohci_run (ohci)) < 0) {
981 ohci_err (ohci, "can't restart, %d\n", temp);
982 return temp;
983 }
984 ohci_dbg(ohci, "restart complete\n");
985 return 0;
986}
987
988#endif
989
990/*-------------------------------------------------------------------------*/
991
992MODULE_AUTHOR (DRIVER_AUTHOR);
993MODULE_DESCRIPTION(DRIVER_DESC);
994MODULE_LICENSE ("GPL");
995
996#ifdef CONFIG_PCI
997#include "ohci-pci.c"
998#define PCI_DRIVER ohci_pci_driver
999#endif
1000
1001#if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1002#include "ohci-sa1111.c"
1003#define SA1111_DRIVER ohci_hcd_sa1111_driver
1004#endif
1005
1006#if defined(CONFIG_ARCH_S3C2410) || defined(CONFIG_ARCH_S3C64XX)
1007#include "ohci-s3c2410.c"
1008#define PLATFORM_DRIVER ohci_hcd_s3c2410_driver
1009#endif
1010
1011#ifdef CONFIG_USB_OHCI_HCD_OMAP1
1012#include "ohci-omap.c"
1013#define OMAP1_PLATFORM_DRIVER ohci_hcd_omap_driver
1014#endif
1015
1016#ifdef CONFIG_USB_OHCI_HCD_OMAP3
1017#include "ohci-omap3.c"
1018#define OMAP3_PLATFORM_DRIVER ohci_hcd_omap3_driver
1019#endif
1020
1021#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
1022#include "ohci-pxa27x.c"
1023#define PLATFORM_DRIVER ohci_hcd_pxa27x_driver
1024#endif
1025
1026#ifdef CONFIG_ARCH_EP93XX
1027#include "ohci-ep93xx.c"
1028#define PLATFORM_DRIVER ohci_hcd_ep93xx_driver
1029#endif
1030
1031#ifdef CONFIG_MIPS_ALCHEMY
1032#include "ohci-au1xxx.c"
1033#define PLATFORM_DRIVER ohci_hcd_au1xxx_driver
1034#endif
1035
1036#ifdef CONFIG_PNX8550
1037#include "ohci-pnx8550.c"
1038#define PLATFORM_DRIVER ohci_hcd_pnx8550_driver
1039#endif
1040
1041#ifdef CONFIG_USB_OHCI_HCD_PPC_SOC
1042#include "ohci-ppc-soc.c"
1043#define PLATFORM_DRIVER ohci_hcd_ppc_soc_driver
1044#endif
1045
1046#ifdef CONFIG_ARCH_AT91
1047#include "ohci-at91.c"
1048#define PLATFORM_DRIVER ohci_hcd_at91_driver
1049#endif
1050
1051#ifdef CONFIG_ARCH_PNX4008
1052#include "ohci-pnx4008.c"
1053#define PLATFORM_DRIVER usb_hcd_pnx4008_driver
1054#endif
1055
1056#ifdef CONFIG_ARCH_DAVINCI_DA8XX
1057#include "ohci-da8xx.c"
1058#define PLATFORM_DRIVER ohci_hcd_da8xx_driver
1059#endif
1060
1061#ifdef CONFIG_USB_OHCI_SH
1062#include "ohci-sh.c"
1063#define PLATFORM_DRIVER ohci_hcd_sh_driver
1064#endif
1065
1066
1067#ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1068#include "ohci-ppc-of.c"
1069#define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1070#endif
1071
1072#ifdef CONFIG_PLAT_SPEAR
1073#include "ohci-spear.c"
1074#define PLATFORM_DRIVER spear_ohci_hcd_driver
1075#endif
1076
1077#ifdef CONFIG_PPC_PS3
1078#include "ohci-ps3.c"
1079#define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1080#endif
1081
1082#ifdef CONFIG_USB_OHCI_HCD_SSB
1083#include "ohci-ssb.c"
1084#define SSB_OHCI_DRIVER ssb_ohci_driver
1085#endif
1086
1087#ifdef CONFIG_MFD_SM501
1088#include "ohci-sm501.c"
1089#define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1090#endif
1091
1092#ifdef CONFIG_MFD_TC6393XB
1093#include "ohci-tmio.c"
1094#define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
1095#endif
1096
1097#ifdef CONFIG_MACH_JZ4740
1098#include "ohci-jz4740.c"
1099#define PLATFORM_DRIVER ohci_hcd_jz4740_driver
1100#endif
1101
1102#ifdef CONFIG_USB_OCTEON_OHCI
1103#include "ohci-octeon.c"
1104#define PLATFORM_DRIVER ohci_octeon_driver
1105#endif
1106
1107#ifdef CONFIG_USB_CNS3XXX_OHCI
1108#include "ohci-cns3xxx.c"
1109#define PLATFORM_DRIVER ohci_hcd_cns3xxx_driver
1110#endif
1111
1112#ifdef CONFIG_USB_OHCI_ATH79
1113#include "ohci-ath79.c"
1114#define PLATFORM_DRIVER ohci_hcd_ath79_driver
1115#endif
1116
1117#if !defined(PCI_DRIVER) && \
1118 !defined(PLATFORM_DRIVER) && \
1119 !defined(OMAP1_PLATFORM_DRIVER) && \
1120 !defined(OMAP3_PLATFORM_DRIVER) && \
1121 !defined(OF_PLATFORM_DRIVER) && \
1122 !defined(SA1111_DRIVER) && \
1123 !defined(PS3_SYSTEM_BUS_DRIVER) && \
1124 !defined(SM501_OHCI_DRIVER) && \
1125 !defined(TMIO_OHCI_DRIVER) && \
1126 !defined(SSB_OHCI_DRIVER)
1127#error "missing bus glue for ohci-hcd"
1128#endif
1129
1130static int __init ohci_hcd_mod_init(void)
1131{
1132 int retval = 0;
1133
1134 if (usb_disabled())
1135 return -ENODEV;
1136
1137 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1138 pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
1139 sizeof (struct ed), sizeof (struct td));
1140 set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1141
1142#ifdef DEBUG
1143 ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1144 if (!ohci_debug_root) {
1145 retval = -ENOENT;
1146 goto error_debug;
1147 }
1148#endif
1149
1150#ifdef PS3_SYSTEM_BUS_DRIVER
1151 retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1152 if (retval < 0)
1153 goto error_ps3;
1154#endif
1155
1156#ifdef PLATFORM_DRIVER
1157 retval = platform_driver_register(&PLATFORM_DRIVER);
1158 if (retval < 0)
1159 goto error_platform;
1160#endif
1161
1162#ifdef OMAP1_PLATFORM_DRIVER
1163 retval = platform_driver_register(&OMAP1_PLATFORM_DRIVER);
1164 if (retval < 0)
1165 goto error_omap1_platform;
1166#endif
1167
1168#ifdef OMAP3_PLATFORM_DRIVER
1169 retval = platform_driver_register(&OMAP3_PLATFORM_DRIVER);
1170 if (retval < 0)
1171 goto error_omap3_platform;
1172#endif
1173
1174#ifdef OF_PLATFORM_DRIVER
1175 retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1176 if (retval < 0)
1177 goto error_of_platform;
1178#endif
1179
1180#ifdef SA1111_DRIVER
1181 retval = sa1111_driver_register(&SA1111_DRIVER);
1182 if (retval < 0)
1183 goto error_sa1111;
1184#endif
1185
1186#ifdef PCI_DRIVER
1187 retval = pci_register_driver(&PCI_DRIVER);
1188 if (retval < 0)
1189 goto error_pci;
1190#endif
1191
1192#ifdef SSB_OHCI_DRIVER
1193 retval = ssb_driver_register(&SSB_OHCI_DRIVER);
1194 if (retval)
1195 goto error_ssb;
1196#endif
1197
1198#ifdef SM501_OHCI_DRIVER
1199 retval = platform_driver_register(&SM501_OHCI_DRIVER);
1200 if (retval < 0)
1201 goto error_sm501;
1202#endif
1203
1204#ifdef TMIO_OHCI_DRIVER
1205 retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1206 if (retval < 0)
1207 goto error_tmio;
1208#endif
1209
1210 return retval;
1211
1212 /* Error path */
1213#ifdef TMIO_OHCI_DRIVER
1214 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1215 error_tmio:
1216#endif
1217#ifdef SM501_OHCI_DRIVER
1218 platform_driver_unregister(&SM501_OHCI_DRIVER);
1219 error_sm501:
1220#endif
1221#ifdef SSB_OHCI_DRIVER
1222 ssb_driver_unregister(&SSB_OHCI_DRIVER);
1223 error_ssb:
1224#endif
1225#ifdef PCI_DRIVER
1226 pci_unregister_driver(&PCI_DRIVER);
1227 error_pci:
1228#endif
1229#ifdef SA1111_DRIVER
1230 sa1111_driver_unregister(&SA1111_DRIVER);
1231 error_sa1111:
1232#endif
1233#ifdef OF_PLATFORM_DRIVER
1234 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1235 error_of_platform:
1236#endif
1237#ifdef PLATFORM_DRIVER
1238 platform_driver_unregister(&PLATFORM_DRIVER);
1239 error_platform:
1240#endif
1241#ifdef OMAP1_PLATFORM_DRIVER
1242 platform_driver_unregister(&OMAP1_PLATFORM_DRIVER);
1243 error_omap1_platform:
1244#endif
1245#ifdef OMAP3_PLATFORM_DRIVER
1246 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
1247 error_omap3_platform:
1248#endif
1249#ifdef PS3_SYSTEM_BUS_DRIVER
1250 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1251 error_ps3:
1252#endif
1253#ifdef DEBUG
1254 debugfs_remove(ohci_debug_root);
1255 ohci_debug_root = NULL;
1256 error_debug:
1257#endif
1258
1259 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1260 return retval;
1261}
1262module_init(ohci_hcd_mod_init);
1263
1264static void __exit ohci_hcd_mod_exit(void)
1265{
1266#ifdef TMIO_OHCI_DRIVER
1267 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1268#endif
1269#ifdef SM501_OHCI_DRIVER
1270 platform_driver_unregister(&SM501_OHCI_DRIVER);
1271#endif
1272#ifdef SSB_OHCI_DRIVER
1273 ssb_driver_unregister(&SSB_OHCI_DRIVER);
1274#endif
1275#ifdef PCI_DRIVER
1276 pci_unregister_driver(&PCI_DRIVER);
1277#endif
1278#ifdef SA1111_DRIVER
1279 sa1111_driver_unregister(&SA1111_DRIVER);
1280#endif
1281#ifdef OF_PLATFORM_DRIVER
1282 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1283#endif
1284#ifdef PLATFORM_DRIVER
1285 platform_driver_unregister(&PLATFORM_DRIVER);
1286#endif
1287#ifdef OMAP3_PLATFORM_DRIVER
1288 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
1289#endif
1290#ifdef PS3_SYSTEM_BUS_DRIVER
1291 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1292#endif
1293#ifdef DEBUG
1294 debugfs_remove(ohci_debug_root);
1295#endif
1296 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1297}
1298module_exit(ohci_hcd_mod_exit);
1299
1// SPDX-License-Identifier: GPL-1.0+
2/*
3 * Open Host Controller Interface (OHCI) driver for USB.
4 *
5 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 *
7 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
8 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
9 *
10 * [ Initialisation is based on Linus' ]
11 * [ uhci code and gregs ohci fragments ]
12 * [ (C) Copyright 1999 Linus Torvalds ]
13 * [ (C) Copyright 1999 Gregory P. Smith]
14 *
15 *
16 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
17 * interfaces (though some non-x86 Intel chips use it). It supports
18 * smarter hardware than UHCI. A download link for the spec available
19 * through the https://www.usb.org website.
20 *
21 * This file is licenced under the GPL.
22 */
23
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/pci.h>
27#include <linux/kernel.h>
28#include <linux/delay.h>
29#include <linux/ioport.h>
30#include <linux/sched.h>
31#include <linux/slab.h>
32#include <linux/errno.h>
33#include <linux/init.h>
34#include <linux/timer.h>
35#include <linux/list.h>
36#include <linux/usb.h>
37#include <linux/usb/otg.h>
38#include <linux/usb/hcd.h>
39#include <linux/dma-mapping.h>
40#include <linux/dmapool.h>
41#include <linux/workqueue.h>
42#include <linux/debugfs.h>
43#include <linux/genalloc.h>
44
45#include <asm/io.h>
46#include <asm/irq.h>
47#include <asm/unaligned.h>
48#include <asm/byteorder.h>
49
50
51#define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
52#define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
53
54/*-------------------------------------------------------------------------*/
55
56/* For initializing controller (mask in an HCFS mode too) */
57#define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
58#define OHCI_INTR_INIT \
59 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
60 | OHCI_INTR_RD | OHCI_INTR_WDH)
61
62#ifdef __hppa__
63/* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
64#define IR_DISABLE
65#endif
66
67#ifdef CONFIG_ARCH_OMAP
68/* OMAP doesn't support IR (no SMM; not needed) */
69#define IR_DISABLE
70#endif
71
72/*-------------------------------------------------------------------------*/
73
74static const char hcd_name [] = "ohci_hcd";
75
76#define STATECHANGE_DELAY msecs_to_jiffies(300)
77#define IO_WATCHDOG_DELAY msecs_to_jiffies(275)
78#define IO_WATCHDOG_OFF 0xffffff00
79
80#include "ohci.h"
81#include "pci-quirks.h"
82
83static void ohci_dump(struct ohci_hcd *ohci);
84static void ohci_stop(struct usb_hcd *hcd);
85static void io_watchdog_func(struct timer_list *t);
86
87#include "ohci-hub.c"
88#include "ohci-dbg.c"
89#include "ohci-mem.c"
90#include "ohci-q.c"
91
92
93/*
94 * On architectures with edge-triggered interrupts we must never return
95 * IRQ_NONE.
96 */
97#if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
98#define IRQ_NOTMINE IRQ_HANDLED
99#else
100#define IRQ_NOTMINE IRQ_NONE
101#endif
102
103
104/* Some boards misreport power switching/overcurrent */
105static bool distrust_firmware;
106module_param (distrust_firmware, bool, 0);
107MODULE_PARM_DESC (distrust_firmware,
108 "true to distrust firmware power/overcurrent setup");
109
110/* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
111static bool no_handshake;
112module_param (no_handshake, bool, 0);
113MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
114
115/*-------------------------------------------------------------------------*/
116
117static int number_of_tds(struct urb *urb)
118{
119 int len, i, num, this_sg_len;
120 struct scatterlist *sg;
121
122 len = urb->transfer_buffer_length;
123 i = urb->num_mapped_sgs;
124
125 if (len > 0 && i > 0) { /* Scatter-gather transfer */
126 num = 0;
127 sg = urb->sg;
128 for (;;) {
129 this_sg_len = min_t(int, sg_dma_len(sg), len);
130 num += DIV_ROUND_UP(this_sg_len, 4096);
131 len -= this_sg_len;
132 if (--i <= 0 || len <= 0)
133 break;
134 sg = sg_next(sg);
135 }
136
137 } else { /* Non-SG transfer */
138 /* one TD for every 4096 Bytes (could be up to 8K) */
139 num = DIV_ROUND_UP(len, 4096);
140 }
141 return num;
142}
143
144/*
145 * queue up an urb for anything except the root hub
146 */
147static int ohci_urb_enqueue (
148 struct usb_hcd *hcd,
149 struct urb *urb,
150 gfp_t mem_flags
151) {
152 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
153 struct ed *ed;
154 urb_priv_t *urb_priv;
155 unsigned int pipe = urb->pipe;
156 int i, size = 0;
157 unsigned long flags;
158 int retval = 0;
159
160 /* every endpoint has a ed, locate and maybe (re)initialize it */
161 ed = ed_get(ohci, urb->ep, urb->dev, pipe, urb->interval);
162 if (! ed)
163 return -ENOMEM;
164
165 /* for the private part of the URB we need the number of TDs (size) */
166 switch (ed->type) {
167 case PIPE_CONTROL:
168 /* td_submit_urb() doesn't yet handle these */
169 if (urb->transfer_buffer_length > 4096)
170 return -EMSGSIZE;
171
172 /* 1 TD for setup, 1 for ACK, plus ... */
173 size = 2;
174 fallthrough;
175 // case PIPE_INTERRUPT:
176 // case PIPE_BULK:
177 default:
178 size += number_of_tds(urb);
179 /* maybe a zero-length packet to wrap it up */
180 if (size == 0)
181 size++;
182 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
183 && (urb->transfer_buffer_length
184 % usb_maxpacket(urb->dev, pipe)) == 0)
185 size++;
186 break;
187 case PIPE_ISOCHRONOUS: /* number of packets from URB */
188 size = urb->number_of_packets;
189 break;
190 }
191
192 /* allocate the private part of the URB */
193 urb_priv = kzalloc(struct_size(urb_priv, td, size), mem_flags);
194 if (!urb_priv)
195 return -ENOMEM;
196 INIT_LIST_HEAD (&urb_priv->pending);
197 urb_priv->length = size;
198 urb_priv->ed = ed;
199
200 /* allocate the TDs (deferring hash chain updates) */
201 for (i = 0; i < size; i++) {
202 urb_priv->td [i] = td_alloc (ohci, mem_flags);
203 if (!urb_priv->td [i]) {
204 urb_priv->length = i;
205 urb_free_priv (ohci, urb_priv);
206 return -ENOMEM;
207 }
208 }
209
210 spin_lock_irqsave (&ohci->lock, flags);
211
212 /* don't submit to a dead HC */
213 if (!HCD_HW_ACCESSIBLE(hcd)) {
214 retval = -ENODEV;
215 goto fail;
216 }
217 if (ohci->rh_state != OHCI_RH_RUNNING) {
218 retval = -ENODEV;
219 goto fail;
220 }
221 retval = usb_hcd_link_urb_to_ep(hcd, urb);
222 if (retval)
223 goto fail;
224
225 /* schedule the ed if needed */
226 if (ed->state == ED_IDLE) {
227 retval = ed_schedule (ohci, ed);
228 if (retval < 0) {
229 usb_hcd_unlink_urb_from_ep(hcd, urb);
230 goto fail;
231 }
232
233 /* Start up the I/O watchdog timer, if it's not running */
234 if (ohci->prev_frame_no == IO_WATCHDOG_OFF &&
235 list_empty(&ohci->eds_in_use) &&
236 !(ohci->flags & OHCI_QUIRK_QEMU)) {
237 ohci->prev_frame_no = ohci_frame_no(ohci);
238 mod_timer(&ohci->io_watchdog,
239 jiffies + IO_WATCHDOG_DELAY);
240 }
241 list_add(&ed->in_use_list, &ohci->eds_in_use);
242
243 if (ed->type == PIPE_ISOCHRONOUS) {
244 u16 frame = ohci_frame_no(ohci);
245
246 /* delay a few frames before the first TD */
247 frame += max_t (u16, 8, ed->interval);
248 frame &= ~(ed->interval - 1);
249 frame |= ed->branch;
250 urb->start_frame = frame;
251 ed->last_iso = frame + ed->interval * (size - 1);
252 }
253 } else if (ed->type == PIPE_ISOCHRONOUS) {
254 u16 next = ohci_frame_no(ohci) + 1;
255 u16 frame = ed->last_iso + ed->interval;
256 u16 length = ed->interval * (size - 1);
257
258 /* Behind the scheduling threshold? */
259 if (unlikely(tick_before(frame, next))) {
260
261 /* URB_ISO_ASAP: Round up to the first available slot */
262 if (urb->transfer_flags & URB_ISO_ASAP) {
263 frame += (next - frame + ed->interval - 1) &
264 -ed->interval;
265
266 /*
267 * Not ASAP: Use the next slot in the stream,
268 * no matter what.
269 */
270 } else {
271 /*
272 * Some OHCI hardware doesn't handle late TDs
273 * correctly. After retiring them it proceeds
274 * to the next ED instead of the next TD.
275 * Therefore we have to omit the late TDs
276 * entirely.
277 */
278 urb_priv->td_cnt = DIV_ROUND_UP(
279 (u16) (next - frame),
280 ed->interval);
281 if (urb_priv->td_cnt >= urb_priv->length) {
282 ++urb_priv->td_cnt; /* Mark it */
283 ohci_dbg(ohci, "iso underrun %p (%u+%u < %u)\n",
284 urb, frame, length,
285 next);
286 }
287 }
288 }
289 urb->start_frame = frame;
290 ed->last_iso = frame + length;
291 }
292
293 /* fill the TDs and link them to the ed; and
294 * enable that part of the schedule, if needed
295 * and update count of queued periodic urbs
296 */
297 urb->hcpriv = urb_priv;
298 td_submit_urb (ohci, urb);
299
300fail:
301 if (retval)
302 urb_free_priv (ohci, urb_priv);
303 spin_unlock_irqrestore (&ohci->lock, flags);
304 return retval;
305}
306
307/*
308 * decouple the URB from the HC queues (TDs, urb_priv).
309 * reporting is always done
310 * asynchronously, and we might be dealing with an urb that's
311 * partially transferred, or an ED with other urbs being unlinked.
312 */
313static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
314{
315 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
316 unsigned long flags;
317 int rc;
318 urb_priv_t *urb_priv;
319
320 spin_lock_irqsave (&ohci->lock, flags);
321 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
322 if (rc == 0) {
323
324 /* Unless an IRQ completed the unlink while it was being
325 * handed to us, flag it for unlink and giveback, and force
326 * some upcoming INTR_SF to call finish_unlinks()
327 */
328 urb_priv = urb->hcpriv;
329 if (urb_priv->ed->state == ED_OPER)
330 start_ed_unlink(ohci, urb_priv->ed);
331
332 if (ohci->rh_state != OHCI_RH_RUNNING) {
333 /* With HC dead, we can clean up right away */
334 ohci_work(ohci);
335 }
336 }
337 spin_unlock_irqrestore (&ohci->lock, flags);
338 return rc;
339}
340
341/*-------------------------------------------------------------------------*/
342
343/* frees config/altsetting state for endpoints,
344 * including ED memory, dummy TD, and bulk/intr data toggle
345 */
346
347static void
348ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
349{
350 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
351 unsigned long flags;
352 struct ed *ed = ep->hcpriv;
353 unsigned limit = 1000;
354
355 /* ASSERT: any requests/urbs are being unlinked */
356 /* ASSERT: nobody can be submitting urbs for this any more */
357
358 if (!ed)
359 return;
360
361rescan:
362 spin_lock_irqsave (&ohci->lock, flags);
363
364 if (ohci->rh_state != OHCI_RH_RUNNING) {
365sanitize:
366 ed->state = ED_IDLE;
367 ohci_work(ohci);
368 }
369
370 switch (ed->state) {
371 case ED_UNLINK: /* wait for hw to finish? */
372 /* major IRQ delivery trouble loses INTR_SF too... */
373 if (limit-- == 0) {
374 ohci_warn(ohci, "ED unlink timeout\n");
375 goto sanitize;
376 }
377 spin_unlock_irqrestore (&ohci->lock, flags);
378 schedule_timeout_uninterruptible(1);
379 goto rescan;
380 case ED_IDLE: /* fully unlinked */
381 if (list_empty (&ed->td_list)) {
382 td_free (ohci, ed->dummy);
383 ed_free (ohci, ed);
384 break;
385 }
386 fallthrough;
387 default:
388 /* caller was supposed to have unlinked any requests;
389 * that's not our job. can't recover; must leak ed.
390 */
391 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
392 ed, ep->desc.bEndpointAddress, ed->state,
393 list_empty (&ed->td_list) ? "" : " (has tds)");
394 td_free (ohci, ed->dummy);
395 break;
396 }
397 ep->hcpriv = NULL;
398 spin_unlock_irqrestore (&ohci->lock, flags);
399}
400
401static int ohci_get_frame (struct usb_hcd *hcd)
402{
403 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
404
405 return ohci_frame_no(ohci);
406}
407
408static void ohci_usb_reset (struct ohci_hcd *ohci)
409{
410 ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
411 ohci->hc_control &= OHCI_CTRL_RWC;
412 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
413 ohci->rh_state = OHCI_RH_HALTED;
414}
415
416/* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
417 * other cases where the next software may expect clean state from the
418 * "firmware". this is bus-neutral, unlike shutdown() methods.
419 */
420static void _ohci_shutdown(struct usb_hcd *hcd)
421{
422 struct ohci_hcd *ohci;
423
424 ohci = hcd_to_ohci (hcd);
425 ohci_writel(ohci, (u32) ~0, &ohci->regs->intrdisable);
426
427 /* Software reset, after which the controller goes into SUSPEND */
428 ohci_writel(ohci, OHCI_HCR, &ohci->regs->cmdstatus);
429 ohci_readl(ohci, &ohci->regs->cmdstatus); /* flush the writes */
430 udelay(10);
431
432 ohci_writel(ohci, ohci->fminterval, &ohci->regs->fminterval);
433 ohci->rh_state = OHCI_RH_HALTED;
434}
435
436static void ohci_shutdown(struct usb_hcd *hcd)
437{
438 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
439 unsigned long flags;
440
441 spin_lock_irqsave(&ohci->lock, flags);
442 _ohci_shutdown(hcd);
443 spin_unlock_irqrestore(&ohci->lock, flags);
444}
445
446/*-------------------------------------------------------------------------*
447 * HC functions
448 *-------------------------------------------------------------------------*/
449
450/* init memory, and kick BIOS/SMM off */
451
452static int ohci_init (struct ohci_hcd *ohci)
453{
454 int ret;
455 struct usb_hcd *hcd = ohci_to_hcd(ohci);
456
457 /* Accept arbitrarily long scatter-gather lists */
458 if (!hcd->localmem_pool)
459 hcd->self.sg_tablesize = ~0;
460
461 if (distrust_firmware)
462 ohci->flags |= OHCI_QUIRK_HUB_POWER;
463
464 ohci->rh_state = OHCI_RH_HALTED;
465 ohci->regs = hcd->regs;
466
467 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
468 * was never needed for most non-PCI systems ... remove the code?
469 */
470
471#ifndef IR_DISABLE
472 /* SMM owns the HC? not for long! */
473 if (!no_handshake && ohci_readl (ohci,
474 &ohci->regs->control) & OHCI_CTRL_IR) {
475 u32 temp;
476
477 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
478
479 /* this timeout is arbitrary. we make it long, so systems
480 * depending on usb keyboards may be usable even if the
481 * BIOS/SMM code seems pretty broken.
482 */
483 temp = 500; /* arbitrary: five seconds */
484
485 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
486 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
487 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
488 msleep (10);
489 if (--temp == 0) {
490 ohci_err (ohci, "USB HC takeover failed!"
491 " (BIOS/SMM bug)\n");
492 return -EBUSY;
493 }
494 }
495 ohci_usb_reset (ohci);
496 }
497#endif
498
499 /* Disable HC interrupts */
500 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
501
502 /* flush the writes, and save key bits like RWC */
503 if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
504 ohci->hc_control |= OHCI_CTRL_RWC;
505
506 /* Read the number of ports unless overridden */
507 if (ohci->num_ports == 0)
508 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
509
510 if (ohci->hcca)
511 return 0;
512
513 timer_setup(&ohci->io_watchdog, io_watchdog_func, 0);
514 ohci->prev_frame_no = IO_WATCHDOG_OFF;
515
516 if (hcd->localmem_pool)
517 ohci->hcca = gen_pool_dma_alloc_align(hcd->localmem_pool,
518 sizeof(*ohci->hcca),
519 &ohci->hcca_dma, 256);
520 else
521 ohci->hcca = dma_alloc_coherent(hcd->self.controller,
522 sizeof(*ohci->hcca),
523 &ohci->hcca_dma,
524 GFP_KERNEL);
525 if (!ohci->hcca)
526 return -ENOMEM;
527
528 if ((ret = ohci_mem_init (ohci)) < 0)
529 ohci_stop (hcd);
530 else {
531 create_debug_files (ohci);
532 }
533
534 return ret;
535}
536
537/*-------------------------------------------------------------------------*/
538
539/* Start an OHCI controller, set the BUS operational
540 * resets USB and controller
541 * enable interrupts
542 */
543static int ohci_run (struct ohci_hcd *ohci)
544{
545 u32 mask, val;
546 int first = ohci->fminterval == 0;
547 struct usb_hcd *hcd = ohci_to_hcd(ohci);
548
549 ohci->rh_state = OHCI_RH_HALTED;
550
551 /* boot firmware should have set this up (5.1.1.3.1) */
552 if (first) {
553
554 val = ohci_readl (ohci, &ohci->regs->fminterval);
555 ohci->fminterval = val & 0x3fff;
556 if (ohci->fminterval != FI)
557 ohci_dbg (ohci, "fminterval delta %d\n",
558 ohci->fminterval - FI);
559 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
560 /* also: power/overcurrent flags in roothub.a */
561 }
562
563 /* Reset USB nearly "by the book". RemoteWakeupConnected has
564 * to be checked in case boot firmware (BIOS/SMM/...) has set up
565 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
566 * If the bus glue detected wakeup capability then it should
567 * already be enabled; if so we'll just enable it again.
568 */
569 if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
570 device_set_wakeup_capable(hcd->self.controller, 1);
571
572 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
573 case OHCI_USB_OPER:
574 val = 0;
575 break;
576 case OHCI_USB_SUSPEND:
577 case OHCI_USB_RESUME:
578 ohci->hc_control &= OHCI_CTRL_RWC;
579 ohci->hc_control |= OHCI_USB_RESUME;
580 val = 10 /* msec wait */;
581 break;
582 // case OHCI_USB_RESET:
583 default:
584 ohci->hc_control &= OHCI_CTRL_RWC;
585 ohci->hc_control |= OHCI_USB_RESET;
586 val = 50 /* msec wait */;
587 break;
588 }
589 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
590 // flush the writes
591 (void) ohci_readl (ohci, &ohci->regs->control);
592 msleep(val);
593
594 memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
595
596 /* 2msec timelimit here means no irqs/preempt */
597 spin_lock_irq (&ohci->lock);
598
599retry:
600 /* HC Reset requires max 10 us delay */
601 ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus);
602 val = 30; /* ... allow extra time */
603 while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
604 if (--val == 0) {
605 spin_unlock_irq (&ohci->lock);
606 ohci_err (ohci, "USB HC reset timed out!\n");
607 return -1;
608 }
609 udelay (1);
610 }
611
612 /* now we're in the SUSPEND state ... must go OPERATIONAL
613 * within 2msec else HC enters RESUME
614 *
615 * ... but some hardware won't init fmInterval "by the book"
616 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
617 * this if we write fmInterval after we're OPERATIONAL.
618 * Unclear about ALi, ServerWorks, and others ... this could
619 * easily be a longstanding bug in chip init on Linux.
620 */
621 if (ohci->flags & OHCI_QUIRK_INITRESET) {
622 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
623 // flush those writes
624 (void) ohci_readl (ohci, &ohci->regs->control);
625 }
626
627 /* Tell the controller where the control and bulk lists are
628 * The lists are empty now. */
629 ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
630 ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
631
632 /* a reset clears this */
633 ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
634
635 periodic_reinit (ohci);
636
637 /* some OHCI implementations are finicky about how they init.
638 * bogus values here mean not even enumeration could work.
639 */
640 if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
641 || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
642 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
643 ohci->flags |= OHCI_QUIRK_INITRESET;
644 ohci_dbg (ohci, "enabling initreset quirk\n");
645 goto retry;
646 }
647 spin_unlock_irq (&ohci->lock);
648 ohci_err (ohci, "init err (%08x %04x)\n",
649 ohci_readl (ohci, &ohci->regs->fminterval),
650 ohci_readl (ohci, &ohci->regs->periodicstart));
651 return -EOVERFLOW;
652 }
653
654 /* use rhsc irqs after hub_wq is allocated */
655 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
656 hcd->uses_new_polling = 1;
657
658 /* start controller operations */
659 ohci->hc_control &= OHCI_CTRL_RWC;
660 ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
661 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
662 ohci->rh_state = OHCI_RH_RUNNING;
663
664 /* wake on ConnectStatusChange, matching external hubs */
665 ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
666
667 /* Choose the interrupts we care about now, others later on demand */
668 mask = OHCI_INTR_INIT;
669 ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
670 ohci_writel (ohci, mask, &ohci->regs->intrenable);
671
672 /* handle root hub init quirks ... */
673 val = roothub_a (ohci);
674 /* Configure for per-port over-current protection by default */
675 val &= ~RH_A_NOCP;
676 val |= RH_A_OCPM;
677 if (ohci->flags & OHCI_QUIRK_SUPERIO) {
678 /* NSC 87560 and maybe others.
679 * Ganged power switching, no over-current protection.
680 */
681 val |= RH_A_NOCP;
682 val &= ~(RH_A_POTPGT | RH_A_NPS | RH_A_PSM | RH_A_OCPM);
683 } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
684 (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
685 /* hub power always on; required for AMD-756 and some
686 * Mac platforms.
687 */
688 val |= RH_A_NPS;
689 }
690 ohci_writel(ohci, val, &ohci->regs->roothub.a);
691
692 ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
693 ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
694 &ohci->regs->roothub.b);
695 // flush those writes
696 (void) ohci_readl (ohci, &ohci->regs->control);
697
698 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
699 spin_unlock_irq (&ohci->lock);
700
701 // POTPGT delay is bits 24-31, in 2 ms units.
702 mdelay ((val >> 23) & 0x1fe);
703
704 ohci_dump(ohci);
705
706 return 0;
707}
708
709/* ohci_setup routine for generic controller initialization */
710
711int ohci_setup(struct usb_hcd *hcd)
712{
713 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
714
715 ohci_hcd_init(ohci);
716
717 return ohci_init(ohci);
718}
719EXPORT_SYMBOL_GPL(ohci_setup);
720
721/* ohci_start routine for generic controller start of all OHCI bus glue */
722static int ohci_start(struct usb_hcd *hcd)
723{
724 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
725 int ret;
726
727 ret = ohci_run(ohci);
728 if (ret < 0) {
729 ohci_err(ohci, "can't start\n");
730 ohci_stop(hcd);
731 }
732 return ret;
733}
734
735/*-------------------------------------------------------------------------*/
736
737/*
738 * Some OHCI controllers are known to lose track of completed TDs. They
739 * don't add the TDs to the hardware done queue, which means we never see
740 * them as being completed.
741 *
742 * This watchdog routine checks for such problems. Without some way to
743 * tell when those TDs have completed, we would never take their EDs off
744 * the unlink list. As a result, URBs could never be dequeued and
745 * endpoints could never be released.
746 */
747static void io_watchdog_func(struct timer_list *t)
748{
749 struct ohci_hcd *ohci = from_timer(ohci, t, io_watchdog);
750 bool takeback_all_pending = false;
751 u32 status;
752 u32 head;
753 struct ed *ed;
754 struct td *td, *td_start, *td_next;
755 unsigned frame_no, prev_frame_no = IO_WATCHDOG_OFF;
756 unsigned long flags;
757
758 spin_lock_irqsave(&ohci->lock, flags);
759
760 /*
761 * One way to lose track of completed TDs is if the controller
762 * never writes back the done queue head. If it hasn't been
763 * written back since the last time this function ran and if it
764 * was non-empty at that time, something is badly wrong with the
765 * hardware.
766 */
767 status = ohci_readl(ohci, &ohci->regs->intrstatus);
768 if (!(status & OHCI_INTR_WDH) && ohci->wdh_cnt == ohci->prev_wdh_cnt) {
769 if (ohci->prev_donehead) {
770 ohci_err(ohci, "HcDoneHead not written back; disabled\n");
771 died:
772 usb_hc_died(ohci_to_hcd(ohci));
773 ohci_dump(ohci);
774 _ohci_shutdown(ohci_to_hcd(ohci));
775 goto done;
776 } else {
777 /* No write back because the done queue was empty */
778 takeback_all_pending = true;
779 }
780 }
781
782 /* Check every ED which might have pending TDs */
783 list_for_each_entry(ed, &ohci->eds_in_use, in_use_list) {
784 if (ed->pending_td) {
785 if (takeback_all_pending ||
786 OKAY_TO_TAKEBACK(ohci, ed)) {
787 unsigned tmp = hc32_to_cpu(ohci, ed->hwINFO);
788
789 ohci_dbg(ohci, "takeback pending TD for dev %d ep 0x%x\n",
790 0x007f & tmp,
791 (0x000f & (tmp >> 7)) +
792 ((tmp & ED_IN) >> 5));
793 add_to_done_list(ohci, ed->pending_td);
794 }
795 }
796
797 /* Starting from the latest pending TD, */
798 td = ed->pending_td;
799
800 /* or the last TD on the done list, */
801 if (!td) {
802 list_for_each_entry(td_next, &ed->td_list, td_list) {
803 if (!td_next->next_dl_td)
804 break;
805 td = td_next;
806 }
807 }
808
809 /* find the last TD processed by the controller. */
810 head = hc32_to_cpu(ohci, READ_ONCE(ed->hwHeadP)) & TD_MASK;
811 td_start = td;
812 td_next = list_prepare_entry(td, &ed->td_list, td_list);
813 list_for_each_entry_continue(td_next, &ed->td_list, td_list) {
814 if (head == (u32) td_next->td_dma)
815 break;
816 td = td_next; /* head pointer has passed this TD */
817 }
818 if (td != td_start) {
819 /*
820 * In case a WDH cycle is in progress, we will wait
821 * for the next two cycles to complete before assuming
822 * this TD will never get on the done queue.
823 */
824 ed->takeback_wdh_cnt = ohci->wdh_cnt + 2;
825 ed->pending_td = td;
826 }
827 }
828
829 ohci_work(ohci);
830
831 if (ohci->rh_state == OHCI_RH_RUNNING) {
832
833 /*
834 * Sometimes a controller just stops working. We can tell
835 * by checking that the frame counter has advanced since
836 * the last time we ran.
837 *
838 * But be careful: Some controllers violate the spec by
839 * stopping their frame counter when no ports are active.
840 */
841 frame_no = ohci_frame_no(ohci);
842 if (frame_no == ohci->prev_frame_no) {
843 int active_cnt = 0;
844 int i;
845 unsigned tmp;
846
847 for (i = 0; i < ohci->num_ports; ++i) {
848 tmp = roothub_portstatus(ohci, i);
849 /* Enabled and not suspended? */
850 if ((tmp & RH_PS_PES) && !(tmp & RH_PS_PSS))
851 ++active_cnt;
852 }
853
854 if (active_cnt > 0) {
855 ohci_err(ohci, "frame counter not updating; disabled\n");
856 goto died;
857 }
858 }
859 if (!list_empty(&ohci->eds_in_use)) {
860 prev_frame_no = frame_no;
861 ohci->prev_wdh_cnt = ohci->wdh_cnt;
862 ohci->prev_donehead = ohci_readl(ohci,
863 &ohci->regs->donehead);
864 mod_timer(&ohci->io_watchdog,
865 jiffies + IO_WATCHDOG_DELAY);
866 }
867 }
868
869 done:
870 ohci->prev_frame_no = prev_frame_no;
871 spin_unlock_irqrestore(&ohci->lock, flags);
872}
873
874/* an interrupt happens */
875
876static irqreturn_t ohci_irq (struct usb_hcd *hcd)
877{
878 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
879 struct ohci_regs __iomem *regs = ohci->regs;
880 int ints;
881
882 /* Read interrupt status (and flush pending writes). We ignore the
883 * optimization of checking the LSB of hcca->done_head; it doesn't
884 * work on all systems (edge triggering for OHCI can be a factor).
885 */
886 ints = ohci_readl(ohci, ®s->intrstatus);
887
888 /* Check for an all 1's result which is a typical consequence
889 * of dead, unclocked, or unplugged (CardBus...) devices
890 */
891 if (ints == ~(u32)0) {
892 ohci->rh_state = OHCI_RH_HALTED;
893 ohci_dbg (ohci, "device removed!\n");
894 usb_hc_died(hcd);
895 return IRQ_HANDLED;
896 }
897
898 /* We only care about interrupts that are enabled */
899 ints &= ohci_readl(ohci, ®s->intrenable);
900
901 /* interrupt for some other device? */
902 if (ints == 0 || unlikely(ohci->rh_state == OHCI_RH_HALTED))
903 return IRQ_NOTMINE;
904
905 if (ints & OHCI_INTR_UE) {
906 // e.g. due to PCI Master/Target Abort
907 if (quirk_nec(ohci)) {
908 /* Workaround for a silicon bug in some NEC chips used
909 * in Apple's PowerBooks. Adapted from Darwin code.
910 */
911 ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
912
913 ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable);
914
915 schedule_work (&ohci->nec_work);
916 } else {
917 ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
918 ohci->rh_state = OHCI_RH_HALTED;
919 usb_hc_died(hcd);
920 }
921
922 ohci_dump(ohci);
923 ohci_usb_reset (ohci);
924 }
925
926 if (ints & OHCI_INTR_RHSC) {
927 ohci_dbg(ohci, "rhsc\n");
928 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
929 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
930 ®s->intrstatus);
931
932 /* NOTE: Vendors didn't always make the same implementation
933 * choices for RHSC. Many followed the spec; RHSC triggers
934 * on an edge, like setting and maybe clearing a port status
935 * change bit. With others it's level-triggered, active
936 * until hub_wq clears all the port status change bits. We'll
937 * always disable it here and rely on polling until hub_wq
938 * re-enables it.
939 */
940 ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable);
941 usb_hcd_poll_rh_status(hcd);
942 }
943
944 /* For connect and disconnect events, we expect the controller
945 * to turn on RHSC along with RD. But for remote wakeup events
946 * this might not happen.
947 */
948 else if (ints & OHCI_INTR_RD) {
949 ohci_dbg(ohci, "resume detect\n");
950 ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus);
951 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
952 if (ohci->autostop) {
953 spin_lock (&ohci->lock);
954 ohci_rh_resume (ohci);
955 spin_unlock (&ohci->lock);
956 } else
957 usb_hcd_resume_root_hub(hcd);
958 }
959
960 spin_lock(&ohci->lock);
961 if (ints & OHCI_INTR_WDH)
962 update_done_list(ohci);
963
964 /* could track INTR_SO to reduce available PCI/... bandwidth */
965
966 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
967 * when there's still unlinking to be done (next frame).
968 */
969 ohci_work(ohci);
970 if ((ints & OHCI_INTR_SF) != 0 && !ohci->ed_rm_list
971 && ohci->rh_state == OHCI_RH_RUNNING)
972 ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable);
973
974 if (ohci->rh_state == OHCI_RH_RUNNING) {
975 ohci_writel (ohci, ints, ®s->intrstatus);
976 if (ints & OHCI_INTR_WDH)
977 ++ohci->wdh_cnt;
978
979 ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable);
980 // flush those writes
981 (void) ohci_readl (ohci, &ohci->regs->control);
982 }
983 spin_unlock(&ohci->lock);
984
985 return IRQ_HANDLED;
986}
987
988/*-------------------------------------------------------------------------*/
989
990static void ohci_stop (struct usb_hcd *hcd)
991{
992 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
993
994 ohci_dump(ohci);
995
996 if (quirk_nec(ohci))
997 flush_work(&ohci->nec_work);
998 del_timer_sync(&ohci->io_watchdog);
999 ohci->prev_frame_no = IO_WATCHDOG_OFF;
1000
1001 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
1002 ohci_usb_reset(ohci);
1003 free_irq(hcd->irq, hcd);
1004 hcd->irq = 0;
1005
1006 if (quirk_amdiso(ohci))
1007 usb_amd_dev_put();
1008
1009 remove_debug_files (ohci);
1010 ohci_mem_cleanup (ohci);
1011 if (ohci->hcca) {
1012 if (hcd->localmem_pool)
1013 gen_pool_free(hcd->localmem_pool,
1014 (unsigned long)ohci->hcca,
1015 sizeof(*ohci->hcca));
1016 else
1017 dma_free_coherent(hcd->self.controller,
1018 sizeof(*ohci->hcca),
1019 ohci->hcca, ohci->hcca_dma);
1020 ohci->hcca = NULL;
1021 ohci->hcca_dma = 0;
1022 }
1023}
1024
1025/*-------------------------------------------------------------------------*/
1026
1027#if defined(CONFIG_PM) || defined(CONFIG_USB_PCI)
1028
1029/* must not be called from interrupt context */
1030int ohci_restart(struct ohci_hcd *ohci)
1031{
1032 int temp;
1033 int i;
1034 struct urb_priv *priv;
1035
1036 ohci_init(ohci);
1037 spin_lock_irq(&ohci->lock);
1038 ohci->rh_state = OHCI_RH_HALTED;
1039
1040 /* Recycle any "live" eds/tds (and urbs). */
1041 if (!list_empty (&ohci->pending))
1042 ohci_dbg(ohci, "abort schedule...\n");
1043 list_for_each_entry (priv, &ohci->pending, pending) {
1044 struct urb *urb = priv->td[0]->urb;
1045 struct ed *ed = priv->ed;
1046
1047 switch (ed->state) {
1048 case ED_OPER:
1049 ed->state = ED_UNLINK;
1050 ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
1051 ed_deschedule (ohci, ed);
1052
1053 ed->ed_next = ohci->ed_rm_list;
1054 ed->ed_prev = NULL;
1055 ohci->ed_rm_list = ed;
1056 fallthrough;
1057 case ED_UNLINK:
1058 break;
1059 default:
1060 ohci_dbg(ohci, "bogus ed %p state %d\n",
1061 ed, ed->state);
1062 }
1063
1064 if (!urb->unlinked)
1065 urb->unlinked = -ESHUTDOWN;
1066 }
1067 ohci_work(ohci);
1068 spin_unlock_irq(&ohci->lock);
1069
1070 /* paranoia, in case that didn't work: */
1071
1072 /* empty the interrupt branches */
1073 for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
1074 for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
1075
1076 /* no EDs to remove */
1077 ohci->ed_rm_list = NULL;
1078
1079 /* empty control and bulk lists */
1080 ohci->ed_controltail = NULL;
1081 ohci->ed_bulktail = NULL;
1082
1083 if ((temp = ohci_run (ohci)) < 0) {
1084 ohci_err (ohci, "can't restart, %d\n", temp);
1085 return temp;
1086 }
1087 ohci_dbg(ohci, "restart complete\n");
1088 return 0;
1089}
1090EXPORT_SYMBOL_GPL(ohci_restart);
1091
1092#endif
1093
1094#ifdef CONFIG_PM
1095
1096int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
1097{
1098 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
1099 unsigned long flags;
1100 int rc = 0;
1101
1102 /* Disable irq emission and mark HW unaccessible. Use
1103 * the spinlock to properly synchronize with possible pending
1104 * RH suspend or resume activity.
1105 */
1106 spin_lock_irqsave (&ohci->lock, flags);
1107 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
1108 (void)ohci_readl(ohci, &ohci->regs->intrdisable);
1109
1110 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1111 spin_unlock_irqrestore (&ohci->lock, flags);
1112
1113 synchronize_irq(hcd->irq);
1114
1115 if (do_wakeup && HCD_WAKEUP_PENDING(hcd)) {
1116 ohci_resume(hcd, false);
1117 rc = -EBUSY;
1118 }
1119 return rc;
1120}
1121EXPORT_SYMBOL_GPL(ohci_suspend);
1122
1123
1124int ohci_resume(struct usb_hcd *hcd, bool hibernated)
1125{
1126 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
1127 int port;
1128 bool need_reinit = false;
1129
1130 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1131
1132 /* Make sure resume from hibernation re-enumerates everything */
1133 if (hibernated)
1134 ohci_usb_reset(ohci);
1135
1136 /* See if the controller is already running or has been reset */
1137 ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
1138 if (ohci->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) {
1139 need_reinit = true;
1140 } else {
1141 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
1142 case OHCI_USB_OPER:
1143 case OHCI_USB_RESET:
1144 need_reinit = true;
1145 }
1146 }
1147
1148 /* If needed, reinitialize and suspend the root hub */
1149 if (need_reinit) {
1150 spin_lock_irq(&ohci->lock);
1151 ohci_rh_resume(ohci);
1152 ohci_rh_suspend(ohci, 0);
1153 spin_unlock_irq(&ohci->lock);
1154 }
1155
1156 /* Normally just turn on port power and enable interrupts */
1157 else {
1158 ohci_dbg(ohci, "powerup ports\n");
1159 for (port = 0; port < ohci->num_ports; port++)
1160 ohci_writel(ohci, RH_PS_PPS,
1161 &ohci->regs->roothub.portstatus[port]);
1162
1163 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrenable);
1164 ohci_readl(ohci, &ohci->regs->intrenable);
1165 msleep(20);
1166 }
1167
1168 usb_hcd_resume_root_hub(hcd);
1169
1170 return 0;
1171}
1172EXPORT_SYMBOL_GPL(ohci_resume);
1173
1174#endif
1175
1176/*-------------------------------------------------------------------------*/
1177
1178/*
1179 * Generic structure: This gets copied for platform drivers so that
1180 * individual entries can be overridden as needed.
1181 */
1182
1183static const struct hc_driver ohci_hc_driver = {
1184 .description = hcd_name,
1185 .product_desc = "OHCI Host Controller",
1186 .hcd_priv_size = sizeof(struct ohci_hcd),
1187
1188 /*
1189 * generic hardware linkage
1190 */
1191 .irq = ohci_irq,
1192 .flags = HCD_MEMORY | HCD_DMA | HCD_USB11,
1193
1194 /*
1195 * basic lifecycle operations
1196 */
1197 .reset = ohci_setup,
1198 .start = ohci_start,
1199 .stop = ohci_stop,
1200 .shutdown = ohci_shutdown,
1201
1202 /*
1203 * managing i/o requests and associated device resources
1204 */
1205 .urb_enqueue = ohci_urb_enqueue,
1206 .urb_dequeue = ohci_urb_dequeue,
1207 .endpoint_disable = ohci_endpoint_disable,
1208
1209 /*
1210 * scheduling support
1211 */
1212 .get_frame_number = ohci_get_frame,
1213
1214 /*
1215 * root hub support
1216 */
1217 .hub_status_data = ohci_hub_status_data,
1218 .hub_control = ohci_hub_control,
1219#ifdef CONFIG_PM
1220 .bus_suspend = ohci_bus_suspend,
1221 .bus_resume = ohci_bus_resume,
1222#endif
1223 .start_port_reset = ohci_start_port_reset,
1224};
1225
1226void ohci_init_driver(struct hc_driver *drv,
1227 const struct ohci_driver_overrides *over)
1228{
1229 /* Copy the generic table to drv and then apply the overrides */
1230 *drv = ohci_hc_driver;
1231
1232 if (over) {
1233 drv->product_desc = over->product_desc;
1234 drv->hcd_priv_size += over->extra_priv_size;
1235 if (over->reset)
1236 drv->reset = over->reset;
1237 }
1238}
1239EXPORT_SYMBOL_GPL(ohci_init_driver);
1240
1241/*-------------------------------------------------------------------------*/
1242
1243MODULE_AUTHOR (DRIVER_AUTHOR);
1244MODULE_DESCRIPTION(DRIVER_DESC);
1245MODULE_LICENSE ("GPL");
1246
1247#if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1248#include "ohci-sa1111.c"
1249#define SA1111_DRIVER ohci_hcd_sa1111_driver
1250#endif
1251
1252#ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1253#include "ohci-ppc-of.c"
1254#define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1255#endif
1256
1257#ifdef CONFIG_PPC_PS3
1258#include "ohci-ps3.c"
1259#define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1260#endif
1261
1262#ifdef CONFIG_MFD_SM501
1263#include "ohci-sm501.c"
1264#define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1265#endif
1266
1267static int __init ohci_hcd_mod_init(void)
1268{
1269 int retval = 0;
1270
1271 if (usb_disabled())
1272 return -ENODEV;
1273
1274 pr_debug ("%s: block sizes: ed %zd td %zd\n", hcd_name,
1275 sizeof (struct ed), sizeof (struct td));
1276 set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1277
1278 ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1279
1280#ifdef PS3_SYSTEM_BUS_DRIVER
1281 retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1282 if (retval < 0)
1283 goto error_ps3;
1284#endif
1285
1286#ifdef OF_PLATFORM_DRIVER
1287 retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1288 if (retval < 0)
1289 goto error_of_platform;
1290#endif
1291
1292#ifdef SA1111_DRIVER
1293 retval = sa1111_driver_register(&SA1111_DRIVER);
1294 if (retval < 0)
1295 goto error_sa1111;
1296#endif
1297
1298#ifdef SM501_OHCI_DRIVER
1299 retval = platform_driver_register(&SM501_OHCI_DRIVER);
1300 if (retval < 0)
1301 goto error_sm501;
1302#endif
1303
1304 return retval;
1305
1306 /* Error path */
1307#ifdef SM501_OHCI_DRIVER
1308 platform_driver_unregister(&SM501_OHCI_DRIVER);
1309 error_sm501:
1310#endif
1311#ifdef SA1111_DRIVER
1312 sa1111_driver_unregister(&SA1111_DRIVER);
1313 error_sa1111:
1314#endif
1315#ifdef OF_PLATFORM_DRIVER
1316 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1317 error_of_platform:
1318#endif
1319#ifdef PS3_SYSTEM_BUS_DRIVER
1320 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1321 error_ps3:
1322#endif
1323 debugfs_remove(ohci_debug_root);
1324 ohci_debug_root = NULL;
1325
1326 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1327 return retval;
1328}
1329module_init(ohci_hcd_mod_init);
1330
1331static void __exit ohci_hcd_mod_exit(void)
1332{
1333#ifdef SM501_OHCI_DRIVER
1334 platform_driver_unregister(&SM501_OHCI_DRIVER);
1335#endif
1336#ifdef SA1111_DRIVER
1337 sa1111_driver_unregister(&SA1111_DRIVER);
1338#endif
1339#ifdef OF_PLATFORM_DRIVER
1340 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1341#endif
1342#ifdef PS3_SYSTEM_BUS_DRIVER
1343 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1344#endif
1345 debugfs_remove(ohci_debug_root);
1346 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1347}
1348module_exit(ohci_hcd_mod_exit);
1349