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1/*
2 * Open Host Controller Interface (OHCI) driver for USB.
3 *
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
5 *
6 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
7 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
8 *
9 * [ Initialisation is based on Linus' ]
10 * [ uhci code and gregs ohci fragments ]
11 * [ (C) Copyright 1999 Linus Torvalds ]
12 * [ (C) Copyright 1999 Gregory P. Smith]
13 *
14 *
15 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
16 * interfaces (though some non-x86 Intel chips use it). It supports
17 * smarter hardware than UHCI. A download link for the spec available
18 * through the http://www.usb.org website.
19 *
20 * This file is licenced under the GPL.
21 */
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/pci.h>
26#include <linux/kernel.h>
27#include <linux/delay.h>
28#include <linux/ioport.h>
29#include <linux/sched.h>
30#include <linux/slab.h>
31#include <linux/errno.h>
32#include <linux/init.h>
33#include <linux/timer.h>
34#include <linux/list.h>
35#include <linux/usb.h>
36#include <linux/usb/otg.h>
37#include <linux/usb/hcd.h>
38#include <linux/dma-mapping.h>
39#include <linux/dmapool.h>
40#include <linux/workqueue.h>
41#include <linux/debugfs.h>
42
43#include <asm/io.h>
44#include <asm/irq.h>
45#include <asm/system.h>
46#include <asm/unaligned.h>
47#include <asm/byteorder.h>
48
49
50#define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
51#define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
52
53/*-------------------------------------------------------------------------*/
54
55#undef OHCI_VERBOSE_DEBUG /* not always helpful */
56
57/* For initializing controller (mask in an HCFS mode too) */
58#define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
59#define OHCI_INTR_INIT \
60 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
61 | OHCI_INTR_RD | OHCI_INTR_WDH)
62
63#ifdef __hppa__
64/* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
65#define IR_DISABLE
66#endif
67
68#ifdef CONFIG_ARCH_OMAP
69/* OMAP doesn't support IR (no SMM; not needed) */
70#define IR_DISABLE
71#endif
72
73/*-------------------------------------------------------------------------*/
74
75static const char hcd_name [] = "ohci_hcd";
76
77#define STATECHANGE_DELAY msecs_to_jiffies(300)
78
79#include "ohci.h"
80#include "pci-quirks.h"
81
82static void ohci_dump (struct ohci_hcd *ohci, int verbose);
83static int ohci_init (struct ohci_hcd *ohci);
84static void ohci_stop (struct usb_hcd *hcd);
85
86#if defined(CONFIG_PM) || defined(CONFIG_PCI)
87static int ohci_restart (struct ohci_hcd *ohci);
88#endif
89
90#ifdef CONFIG_PCI
91static void sb800_prefetch(struct ohci_hcd *ohci, int on);
92#else
93static inline void sb800_prefetch(struct ohci_hcd *ohci, int on)
94{
95 return;
96}
97#endif
98
99
100#include "ohci-hub.c"
101#include "ohci-dbg.c"
102#include "ohci-mem.c"
103#include "ohci-q.c"
104
105
106/*
107 * On architectures with edge-triggered interrupts we must never return
108 * IRQ_NONE.
109 */
110#if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
111#define IRQ_NOTMINE IRQ_HANDLED
112#else
113#define IRQ_NOTMINE IRQ_NONE
114#endif
115
116
117/* Some boards misreport power switching/overcurrent */
118static int distrust_firmware = 1;
119module_param (distrust_firmware, bool, 0);
120MODULE_PARM_DESC (distrust_firmware,
121 "true to distrust firmware power/overcurrent setup");
122
123/* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
124static int no_handshake = 0;
125module_param (no_handshake, bool, 0);
126MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
127
128/*-------------------------------------------------------------------------*/
129
130/*
131 * queue up an urb for anything except the root hub
132 */
133static int ohci_urb_enqueue (
134 struct usb_hcd *hcd,
135 struct urb *urb,
136 gfp_t mem_flags
137) {
138 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
139 struct ed *ed;
140 urb_priv_t *urb_priv;
141 unsigned int pipe = urb->pipe;
142 int i, size = 0;
143 unsigned long flags;
144 int retval = 0;
145
146#ifdef OHCI_VERBOSE_DEBUG
147 urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS);
148#endif
149
150 /* every endpoint has a ed, locate and maybe (re)initialize it */
151 if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval)))
152 return -ENOMEM;
153
154 /* for the private part of the URB we need the number of TDs (size) */
155 switch (ed->type) {
156 case PIPE_CONTROL:
157 /* td_submit_urb() doesn't yet handle these */
158 if (urb->transfer_buffer_length > 4096)
159 return -EMSGSIZE;
160
161 /* 1 TD for setup, 1 for ACK, plus ... */
162 size = 2;
163 /* FALLTHROUGH */
164 // case PIPE_INTERRUPT:
165 // case PIPE_BULK:
166 default:
167 /* one TD for every 4096 Bytes (can be up to 8K) */
168 size += urb->transfer_buffer_length / 4096;
169 /* ... and for any remaining bytes ... */
170 if ((urb->transfer_buffer_length % 4096) != 0)
171 size++;
172 /* ... and maybe a zero length packet to wrap it up */
173 if (size == 0)
174 size++;
175 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
176 && (urb->transfer_buffer_length
177 % usb_maxpacket (urb->dev, pipe,
178 usb_pipeout (pipe))) == 0)
179 size++;
180 break;
181 case PIPE_ISOCHRONOUS: /* number of packets from URB */
182 size = urb->number_of_packets;
183 break;
184 }
185
186 /* allocate the private part of the URB */
187 urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
188 mem_flags);
189 if (!urb_priv)
190 return -ENOMEM;
191 INIT_LIST_HEAD (&urb_priv->pending);
192 urb_priv->length = size;
193 urb_priv->ed = ed;
194
195 /* allocate the TDs (deferring hash chain updates) */
196 for (i = 0; i < size; i++) {
197 urb_priv->td [i] = td_alloc (ohci, mem_flags);
198 if (!urb_priv->td [i]) {
199 urb_priv->length = i;
200 urb_free_priv (ohci, urb_priv);
201 return -ENOMEM;
202 }
203 }
204
205 spin_lock_irqsave (&ohci->lock, flags);
206
207 /* don't submit to a dead HC */
208 if (!HCD_HW_ACCESSIBLE(hcd)) {
209 retval = -ENODEV;
210 goto fail;
211 }
212 if (!HC_IS_RUNNING(hcd->state)) {
213 retval = -ENODEV;
214 goto fail;
215 }
216 retval = usb_hcd_link_urb_to_ep(hcd, urb);
217 if (retval)
218 goto fail;
219
220 /* schedule the ed if needed */
221 if (ed->state == ED_IDLE) {
222 retval = ed_schedule (ohci, ed);
223 if (retval < 0) {
224 usb_hcd_unlink_urb_from_ep(hcd, urb);
225 goto fail;
226 }
227 if (ed->type == PIPE_ISOCHRONOUS) {
228 u16 frame = ohci_frame_no(ohci);
229
230 /* delay a few frames before the first TD */
231 frame += max_t (u16, 8, ed->interval);
232 frame &= ~(ed->interval - 1);
233 frame |= ed->branch;
234 urb->start_frame = frame;
235
236 /* yes, only URB_ISO_ASAP is supported, and
237 * urb->start_frame is never used as input.
238 */
239 }
240 } else if (ed->type == PIPE_ISOCHRONOUS)
241 urb->start_frame = ed->last_iso + ed->interval;
242
243 /* fill the TDs and link them to the ed; and
244 * enable that part of the schedule, if needed
245 * and update count of queued periodic urbs
246 */
247 urb->hcpriv = urb_priv;
248 td_submit_urb (ohci, urb);
249
250fail:
251 if (retval)
252 urb_free_priv (ohci, urb_priv);
253 spin_unlock_irqrestore (&ohci->lock, flags);
254 return retval;
255}
256
257/*
258 * decouple the URB from the HC queues (TDs, urb_priv).
259 * reporting is always done
260 * asynchronously, and we might be dealing with an urb that's
261 * partially transferred, or an ED with other urbs being unlinked.
262 */
263static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
264{
265 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
266 unsigned long flags;
267 int rc;
268
269#ifdef OHCI_VERBOSE_DEBUG
270 urb_print(urb, "UNLINK", 1, status);
271#endif
272
273 spin_lock_irqsave (&ohci->lock, flags);
274 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
275 if (rc) {
276 ; /* Do nothing */
277 } else if (HC_IS_RUNNING(hcd->state)) {
278 urb_priv_t *urb_priv;
279
280 /* Unless an IRQ completed the unlink while it was being
281 * handed to us, flag it for unlink and giveback, and force
282 * some upcoming INTR_SF to call finish_unlinks()
283 */
284 urb_priv = urb->hcpriv;
285 if (urb_priv) {
286 if (urb_priv->ed->state == ED_OPER)
287 start_ed_unlink (ohci, urb_priv->ed);
288 }
289 } else {
290 /*
291 * with HC dead, we won't respect hc queue pointers
292 * any more ... just clean up every urb's memory.
293 */
294 if (urb->hcpriv)
295 finish_urb(ohci, urb, status);
296 }
297 spin_unlock_irqrestore (&ohci->lock, flags);
298 return rc;
299}
300
301/*-------------------------------------------------------------------------*/
302
303/* frees config/altsetting state for endpoints,
304 * including ED memory, dummy TD, and bulk/intr data toggle
305 */
306
307static void
308ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
309{
310 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
311 unsigned long flags;
312 struct ed *ed = ep->hcpriv;
313 unsigned limit = 1000;
314
315 /* ASSERT: any requests/urbs are being unlinked */
316 /* ASSERT: nobody can be submitting urbs for this any more */
317
318 if (!ed)
319 return;
320
321rescan:
322 spin_lock_irqsave (&ohci->lock, flags);
323
324 if (!HC_IS_RUNNING (hcd->state)) {
325sanitize:
326 ed->state = ED_IDLE;
327 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
328 ohci->eds_scheduled--;
329 finish_unlinks (ohci, 0);
330 }
331
332 switch (ed->state) {
333 case ED_UNLINK: /* wait for hw to finish? */
334 /* major IRQ delivery trouble loses INTR_SF too... */
335 if (limit-- == 0) {
336 ohci_warn(ohci, "ED unlink timeout\n");
337 if (quirk_zfmicro(ohci)) {
338 ohci_warn(ohci, "Attempting ZF TD recovery\n");
339 ohci->ed_to_check = ed;
340 ohci->zf_delay = 2;
341 }
342 goto sanitize;
343 }
344 spin_unlock_irqrestore (&ohci->lock, flags);
345 schedule_timeout_uninterruptible(1);
346 goto rescan;
347 case ED_IDLE: /* fully unlinked */
348 if (list_empty (&ed->td_list)) {
349 td_free (ohci, ed->dummy);
350 ed_free (ohci, ed);
351 break;
352 }
353 /* else FALL THROUGH */
354 default:
355 /* caller was supposed to have unlinked any requests;
356 * that's not our job. can't recover; must leak ed.
357 */
358 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
359 ed, ep->desc.bEndpointAddress, ed->state,
360 list_empty (&ed->td_list) ? "" : " (has tds)");
361 td_free (ohci, ed->dummy);
362 break;
363 }
364 ep->hcpriv = NULL;
365 spin_unlock_irqrestore (&ohci->lock, flags);
366}
367
368static int ohci_get_frame (struct usb_hcd *hcd)
369{
370 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
371
372 return ohci_frame_no(ohci);
373}
374
375static void ohci_usb_reset (struct ohci_hcd *ohci)
376{
377 ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
378 ohci->hc_control &= OHCI_CTRL_RWC;
379 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
380}
381
382/* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
383 * other cases where the next software may expect clean state from the
384 * "firmware". this is bus-neutral, unlike shutdown() methods.
385 */
386static void
387ohci_shutdown (struct usb_hcd *hcd)
388{
389 struct ohci_hcd *ohci;
390
391 ohci = hcd_to_ohci (hcd);
392 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
393 ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
394
395 /* If the SHUTDOWN quirk is set, don't put the controller in RESET */
396 ohci->hc_control &= (ohci->flags & OHCI_QUIRK_SHUTDOWN ?
397 OHCI_CTRL_RWC | OHCI_CTRL_HCFS :
398 OHCI_CTRL_RWC);
399 ohci_writel(ohci, ohci->hc_control, &ohci->regs->control);
400
401 /* flush the writes */
402 (void) ohci_readl (ohci, &ohci->regs->control);
403}
404
405static int check_ed(struct ohci_hcd *ohci, struct ed *ed)
406{
407 return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0
408 && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK)
409 == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK)
410 && !list_empty(&ed->td_list);
411}
412
413/* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes
414 * an interrupt TD but neglects to add it to the donelist. On systems with
415 * this chipset, we need to periodically check the state of the queues to look
416 * for such "lost" TDs.
417 */
418static void unlink_watchdog_func(unsigned long _ohci)
419{
420 unsigned long flags;
421 unsigned max;
422 unsigned seen_count = 0;
423 unsigned i;
424 struct ed **seen = NULL;
425 struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci;
426
427 spin_lock_irqsave(&ohci->lock, flags);
428 max = ohci->eds_scheduled;
429 if (!max)
430 goto done;
431
432 if (ohci->ed_to_check)
433 goto out;
434
435 seen = kcalloc(max, sizeof *seen, GFP_ATOMIC);
436 if (!seen)
437 goto out;
438
439 for (i = 0; i < NUM_INTS; i++) {
440 struct ed *ed = ohci->periodic[i];
441
442 while (ed) {
443 unsigned temp;
444
445 /* scan this branch of the periodic schedule tree */
446 for (temp = 0; temp < seen_count; temp++) {
447 if (seen[temp] == ed) {
448 /* we've checked it and what's after */
449 ed = NULL;
450 break;
451 }
452 }
453 if (!ed)
454 break;
455 seen[seen_count++] = ed;
456 if (!check_ed(ohci, ed)) {
457 ed = ed->ed_next;
458 continue;
459 }
460
461 /* HC's TD list is empty, but HCD sees at least one
462 * TD that's not been sent through the donelist.
463 */
464 ohci->ed_to_check = ed;
465 ohci->zf_delay = 2;
466
467 /* The HC may wait until the next frame to report the
468 * TD as done through the donelist and INTR_WDH. (We
469 * just *assume* it's not a multi-TD interrupt URB;
470 * those could defer the IRQ more than one frame, using
471 * DI...) Check again after the next INTR_SF.
472 */
473 ohci_writel(ohci, OHCI_INTR_SF,
474 &ohci->regs->intrstatus);
475 ohci_writel(ohci, OHCI_INTR_SF,
476 &ohci->regs->intrenable);
477
478 /* flush those writes */
479 (void) ohci_readl(ohci, &ohci->regs->control);
480
481 goto out;
482 }
483 }
484out:
485 kfree(seen);
486 if (ohci->eds_scheduled)
487 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
488done:
489 spin_unlock_irqrestore(&ohci->lock, flags);
490}
491
492/*-------------------------------------------------------------------------*
493 * HC functions
494 *-------------------------------------------------------------------------*/
495
496/* init memory, and kick BIOS/SMM off */
497
498static int ohci_init (struct ohci_hcd *ohci)
499{
500 int ret;
501 struct usb_hcd *hcd = ohci_to_hcd(ohci);
502
503 if (distrust_firmware)
504 ohci->flags |= OHCI_QUIRK_HUB_POWER;
505
506 disable (ohci);
507 ohci->regs = hcd->regs;
508
509 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
510 * was never needed for most non-PCI systems ... remove the code?
511 */
512
513#ifndef IR_DISABLE
514 /* SMM owns the HC? not for long! */
515 if (!no_handshake && ohci_readl (ohci,
516 &ohci->regs->control) & OHCI_CTRL_IR) {
517 u32 temp;
518
519 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
520
521 /* this timeout is arbitrary. we make it long, so systems
522 * depending on usb keyboards may be usable even if the
523 * BIOS/SMM code seems pretty broken.
524 */
525 temp = 500; /* arbitrary: five seconds */
526
527 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
528 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
529 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
530 msleep (10);
531 if (--temp == 0) {
532 ohci_err (ohci, "USB HC takeover failed!"
533 " (BIOS/SMM bug)\n");
534 return -EBUSY;
535 }
536 }
537 ohci_usb_reset (ohci);
538 }
539#endif
540
541 /* Disable HC interrupts */
542 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
543
544 /* flush the writes, and save key bits like RWC */
545 if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
546 ohci->hc_control |= OHCI_CTRL_RWC;
547
548 /* Read the number of ports unless overridden */
549 if (ohci->num_ports == 0)
550 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
551
552 if (ohci->hcca)
553 return 0;
554
555 ohci->hcca = dma_alloc_coherent (hcd->self.controller,
556 sizeof *ohci->hcca, &ohci->hcca_dma, 0);
557 if (!ohci->hcca)
558 return -ENOMEM;
559
560 if ((ret = ohci_mem_init (ohci)) < 0)
561 ohci_stop (hcd);
562 else {
563 create_debug_files (ohci);
564 }
565
566 return ret;
567}
568
569/*-------------------------------------------------------------------------*/
570
571/* Start an OHCI controller, set the BUS operational
572 * resets USB and controller
573 * enable interrupts
574 */
575static int ohci_run (struct ohci_hcd *ohci)
576{
577 u32 mask, val;
578 int first = ohci->fminterval == 0;
579 struct usb_hcd *hcd = ohci_to_hcd(ohci);
580
581 disable (ohci);
582
583 /* boot firmware should have set this up (5.1.1.3.1) */
584 if (first) {
585
586 val = ohci_readl (ohci, &ohci->regs->fminterval);
587 ohci->fminterval = val & 0x3fff;
588 if (ohci->fminterval != FI)
589 ohci_dbg (ohci, "fminterval delta %d\n",
590 ohci->fminterval - FI);
591 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
592 /* also: power/overcurrent flags in roothub.a */
593 }
594
595 /* Reset USB nearly "by the book". RemoteWakeupConnected has
596 * to be checked in case boot firmware (BIOS/SMM/...) has set up
597 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
598 * If the bus glue detected wakeup capability then it should
599 * already be enabled; if so we'll just enable it again.
600 */
601 if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
602 device_set_wakeup_capable(hcd->self.controller, 1);
603
604 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
605 case OHCI_USB_OPER:
606 val = 0;
607 break;
608 case OHCI_USB_SUSPEND:
609 case OHCI_USB_RESUME:
610 ohci->hc_control &= OHCI_CTRL_RWC;
611 ohci->hc_control |= OHCI_USB_RESUME;
612 val = 10 /* msec wait */;
613 break;
614 // case OHCI_USB_RESET:
615 default:
616 ohci->hc_control &= OHCI_CTRL_RWC;
617 ohci->hc_control |= OHCI_USB_RESET;
618 val = 50 /* msec wait */;
619 break;
620 }
621 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
622 // flush the writes
623 (void) ohci_readl (ohci, &ohci->regs->control);
624 msleep(val);
625
626 memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
627
628 /* 2msec timelimit here means no irqs/preempt */
629 spin_lock_irq (&ohci->lock);
630
631retry:
632 /* HC Reset requires max 10 us delay */
633 ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus);
634 val = 30; /* ... allow extra time */
635 while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
636 if (--val == 0) {
637 spin_unlock_irq (&ohci->lock);
638 ohci_err (ohci, "USB HC reset timed out!\n");
639 return -1;
640 }
641 udelay (1);
642 }
643
644 /* now we're in the SUSPEND state ... must go OPERATIONAL
645 * within 2msec else HC enters RESUME
646 *
647 * ... but some hardware won't init fmInterval "by the book"
648 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
649 * this if we write fmInterval after we're OPERATIONAL.
650 * Unclear about ALi, ServerWorks, and others ... this could
651 * easily be a longstanding bug in chip init on Linux.
652 */
653 if (ohci->flags & OHCI_QUIRK_INITRESET) {
654 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
655 // flush those writes
656 (void) ohci_readl (ohci, &ohci->regs->control);
657 }
658
659 /* Tell the controller where the control and bulk lists are
660 * The lists are empty now. */
661 ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
662 ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
663
664 /* a reset clears this */
665 ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
666
667 periodic_reinit (ohci);
668
669 /* some OHCI implementations are finicky about how they init.
670 * bogus values here mean not even enumeration could work.
671 */
672 if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
673 || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
674 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
675 ohci->flags |= OHCI_QUIRK_INITRESET;
676 ohci_dbg (ohci, "enabling initreset quirk\n");
677 goto retry;
678 }
679 spin_unlock_irq (&ohci->lock);
680 ohci_err (ohci, "init err (%08x %04x)\n",
681 ohci_readl (ohci, &ohci->regs->fminterval),
682 ohci_readl (ohci, &ohci->regs->periodicstart));
683 return -EOVERFLOW;
684 }
685
686 /* use rhsc irqs after khubd is fully initialized */
687 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
688 hcd->uses_new_polling = 1;
689
690 /* start controller operations */
691 ohci->hc_control &= OHCI_CTRL_RWC;
692 ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
693 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
694 hcd->state = HC_STATE_RUNNING;
695
696 /* wake on ConnectStatusChange, matching external hubs */
697 ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
698
699 /* Choose the interrupts we care about now, others later on demand */
700 mask = OHCI_INTR_INIT;
701 ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
702 ohci_writel (ohci, mask, &ohci->regs->intrenable);
703
704 /* handle root hub init quirks ... */
705 val = roothub_a (ohci);
706 val &= ~(RH_A_PSM | RH_A_OCPM);
707 if (ohci->flags & OHCI_QUIRK_SUPERIO) {
708 /* NSC 87560 and maybe others */
709 val |= RH_A_NOCP;
710 val &= ~(RH_A_POTPGT | RH_A_NPS);
711 ohci_writel (ohci, val, &ohci->regs->roothub.a);
712 } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
713 (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
714 /* hub power always on; required for AMD-756 and some
715 * Mac platforms. ganged overcurrent reporting, if any.
716 */
717 val |= RH_A_NPS;
718 ohci_writel (ohci, val, &ohci->regs->roothub.a);
719 }
720 ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
721 ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
722 &ohci->regs->roothub.b);
723 // flush those writes
724 (void) ohci_readl (ohci, &ohci->regs->control);
725
726 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
727 spin_unlock_irq (&ohci->lock);
728
729 // POTPGT delay is bits 24-31, in 2 ms units.
730 mdelay ((val >> 23) & 0x1fe);
731 hcd->state = HC_STATE_RUNNING;
732
733 if (quirk_zfmicro(ohci)) {
734 /* Create timer to watch for bad queue state on ZF Micro */
735 setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func,
736 (unsigned long) ohci);
737
738 ohci->eds_scheduled = 0;
739 ohci->ed_to_check = NULL;
740 }
741
742 ohci_dump (ohci, 1);
743
744 return 0;
745}
746
747/*-------------------------------------------------------------------------*/
748
749/* an interrupt happens */
750
751static irqreturn_t ohci_irq (struct usb_hcd *hcd)
752{
753 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
754 struct ohci_regs __iomem *regs = ohci->regs;
755 int ints;
756
757 /* Read interrupt status (and flush pending writes). We ignore the
758 * optimization of checking the LSB of hcca->done_head; it doesn't
759 * work on all systems (edge triggering for OHCI can be a factor).
760 */
761 ints = ohci_readl(ohci, ®s->intrstatus);
762
763 /* Check for an all 1's result which is a typical consequence
764 * of dead, unclocked, or unplugged (CardBus...) devices
765 */
766 if (ints == ~(u32)0) {
767 disable (ohci);
768 ohci_dbg (ohci, "device removed!\n");
769 usb_hc_died(hcd);
770 return IRQ_HANDLED;
771 }
772
773 /* We only care about interrupts that are enabled */
774 ints &= ohci_readl(ohci, ®s->intrenable);
775
776 /* interrupt for some other device? */
777 if (ints == 0 || unlikely(hcd->state == HC_STATE_HALT))
778 return IRQ_NOTMINE;
779
780 if (ints & OHCI_INTR_UE) {
781 // e.g. due to PCI Master/Target Abort
782 if (quirk_nec(ohci)) {
783 /* Workaround for a silicon bug in some NEC chips used
784 * in Apple's PowerBooks. Adapted from Darwin code.
785 */
786 ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
787
788 ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable);
789
790 schedule_work (&ohci->nec_work);
791 } else {
792 disable (ohci);
793 ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
794 usb_hc_died(hcd);
795 }
796
797 ohci_dump (ohci, 1);
798 ohci_usb_reset (ohci);
799 }
800
801 if (ints & OHCI_INTR_RHSC) {
802 ohci_vdbg(ohci, "rhsc\n");
803 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
804 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
805 ®s->intrstatus);
806
807 /* NOTE: Vendors didn't always make the same implementation
808 * choices for RHSC. Many followed the spec; RHSC triggers
809 * on an edge, like setting and maybe clearing a port status
810 * change bit. With others it's level-triggered, active
811 * until khubd clears all the port status change bits. We'll
812 * always disable it here and rely on polling until khubd
813 * re-enables it.
814 */
815 ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable);
816 usb_hcd_poll_rh_status(hcd);
817 }
818
819 /* For connect and disconnect events, we expect the controller
820 * to turn on RHSC along with RD. But for remote wakeup events
821 * this might not happen.
822 */
823 else if (ints & OHCI_INTR_RD) {
824 ohci_vdbg(ohci, "resume detect\n");
825 ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus);
826 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
827 if (ohci->autostop) {
828 spin_lock (&ohci->lock);
829 ohci_rh_resume (ohci);
830 spin_unlock (&ohci->lock);
831 } else
832 usb_hcd_resume_root_hub(hcd);
833 }
834
835 if (ints & OHCI_INTR_WDH) {
836 spin_lock (&ohci->lock);
837 dl_done_list (ohci);
838 spin_unlock (&ohci->lock);
839 }
840
841 if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) {
842 spin_lock(&ohci->lock);
843 if (ohci->ed_to_check) {
844 struct ed *ed = ohci->ed_to_check;
845
846 if (check_ed(ohci, ed)) {
847 /* HC thinks the TD list is empty; HCD knows
848 * at least one TD is outstanding
849 */
850 if (--ohci->zf_delay == 0) {
851 struct td *td = list_entry(
852 ed->td_list.next,
853 struct td, td_list);
854 ohci_warn(ohci,
855 "Reclaiming orphan TD %p\n",
856 td);
857 takeback_td(ohci, td);
858 ohci->ed_to_check = NULL;
859 }
860 } else
861 ohci->ed_to_check = NULL;
862 }
863 spin_unlock(&ohci->lock);
864 }
865
866 /* could track INTR_SO to reduce available PCI/... bandwidth */
867
868 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
869 * when there's still unlinking to be done (next frame).
870 */
871 spin_lock (&ohci->lock);
872 if (ohci->ed_rm_list)
873 finish_unlinks (ohci, ohci_frame_no(ohci));
874 if ((ints & OHCI_INTR_SF) != 0
875 && !ohci->ed_rm_list
876 && !ohci->ed_to_check
877 && HC_IS_RUNNING(hcd->state))
878 ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable);
879 spin_unlock (&ohci->lock);
880
881 if (HC_IS_RUNNING(hcd->state)) {
882 ohci_writel (ohci, ints, ®s->intrstatus);
883 ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable);
884 // flush those writes
885 (void) ohci_readl (ohci, &ohci->regs->control);
886 }
887
888 return IRQ_HANDLED;
889}
890
891/*-------------------------------------------------------------------------*/
892
893static void ohci_stop (struct usb_hcd *hcd)
894{
895 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
896
897 ohci_dump (ohci, 1);
898
899 if (quirk_nec(ohci))
900 flush_work_sync(&ohci->nec_work);
901
902 ohci_usb_reset (ohci);
903 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
904 free_irq(hcd->irq, hcd);
905 hcd->irq = -1;
906
907 if (quirk_zfmicro(ohci))
908 del_timer(&ohci->unlink_watchdog);
909 if (quirk_amdiso(ohci))
910 usb_amd_dev_put();
911
912 remove_debug_files (ohci);
913 ohci_mem_cleanup (ohci);
914 if (ohci->hcca) {
915 dma_free_coherent (hcd->self.controller,
916 sizeof *ohci->hcca,
917 ohci->hcca, ohci->hcca_dma);
918 ohci->hcca = NULL;
919 ohci->hcca_dma = 0;
920 }
921}
922
923/*-------------------------------------------------------------------------*/
924
925#if defined(CONFIG_PM) || defined(CONFIG_PCI)
926
927/* must not be called from interrupt context */
928static int ohci_restart (struct ohci_hcd *ohci)
929{
930 int temp;
931 int i;
932 struct urb_priv *priv;
933
934 spin_lock_irq(&ohci->lock);
935 disable (ohci);
936
937 /* Recycle any "live" eds/tds (and urbs). */
938 if (!list_empty (&ohci->pending))
939 ohci_dbg(ohci, "abort schedule...\n");
940 list_for_each_entry (priv, &ohci->pending, pending) {
941 struct urb *urb = priv->td[0]->urb;
942 struct ed *ed = priv->ed;
943
944 switch (ed->state) {
945 case ED_OPER:
946 ed->state = ED_UNLINK;
947 ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
948 ed_deschedule (ohci, ed);
949
950 ed->ed_next = ohci->ed_rm_list;
951 ed->ed_prev = NULL;
952 ohci->ed_rm_list = ed;
953 /* FALLTHROUGH */
954 case ED_UNLINK:
955 break;
956 default:
957 ohci_dbg(ohci, "bogus ed %p state %d\n",
958 ed, ed->state);
959 }
960
961 if (!urb->unlinked)
962 urb->unlinked = -ESHUTDOWN;
963 }
964 finish_unlinks (ohci, 0);
965 spin_unlock_irq(&ohci->lock);
966
967 /* paranoia, in case that didn't work: */
968
969 /* empty the interrupt branches */
970 for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
971 for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
972
973 /* no EDs to remove */
974 ohci->ed_rm_list = NULL;
975
976 /* empty control and bulk lists */
977 ohci->ed_controltail = NULL;
978 ohci->ed_bulktail = NULL;
979
980 if ((temp = ohci_run (ohci)) < 0) {
981 ohci_err (ohci, "can't restart, %d\n", temp);
982 return temp;
983 }
984 ohci_dbg(ohci, "restart complete\n");
985 return 0;
986}
987
988#endif
989
990/*-------------------------------------------------------------------------*/
991
992MODULE_AUTHOR (DRIVER_AUTHOR);
993MODULE_DESCRIPTION(DRIVER_DESC);
994MODULE_LICENSE ("GPL");
995
996#ifdef CONFIG_PCI
997#include "ohci-pci.c"
998#define PCI_DRIVER ohci_pci_driver
999#endif
1000
1001#if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1002#include "ohci-sa1111.c"
1003#define SA1111_DRIVER ohci_hcd_sa1111_driver
1004#endif
1005
1006#if defined(CONFIG_ARCH_S3C2410) || defined(CONFIG_ARCH_S3C64XX)
1007#include "ohci-s3c2410.c"
1008#define PLATFORM_DRIVER ohci_hcd_s3c2410_driver
1009#endif
1010
1011#ifdef CONFIG_USB_OHCI_HCD_OMAP1
1012#include "ohci-omap.c"
1013#define OMAP1_PLATFORM_DRIVER ohci_hcd_omap_driver
1014#endif
1015
1016#ifdef CONFIG_USB_OHCI_HCD_OMAP3
1017#include "ohci-omap3.c"
1018#define OMAP3_PLATFORM_DRIVER ohci_hcd_omap3_driver
1019#endif
1020
1021#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
1022#include "ohci-pxa27x.c"
1023#define PLATFORM_DRIVER ohci_hcd_pxa27x_driver
1024#endif
1025
1026#ifdef CONFIG_ARCH_EP93XX
1027#include "ohci-ep93xx.c"
1028#define PLATFORM_DRIVER ohci_hcd_ep93xx_driver
1029#endif
1030
1031#ifdef CONFIG_MIPS_ALCHEMY
1032#include "ohci-au1xxx.c"
1033#define PLATFORM_DRIVER ohci_hcd_au1xxx_driver
1034#endif
1035
1036#ifdef CONFIG_PNX8550
1037#include "ohci-pnx8550.c"
1038#define PLATFORM_DRIVER ohci_hcd_pnx8550_driver
1039#endif
1040
1041#ifdef CONFIG_USB_OHCI_HCD_PPC_SOC
1042#include "ohci-ppc-soc.c"
1043#define PLATFORM_DRIVER ohci_hcd_ppc_soc_driver
1044#endif
1045
1046#ifdef CONFIG_ARCH_AT91
1047#include "ohci-at91.c"
1048#define PLATFORM_DRIVER ohci_hcd_at91_driver
1049#endif
1050
1051#ifdef CONFIG_ARCH_PNX4008
1052#include "ohci-pnx4008.c"
1053#define PLATFORM_DRIVER usb_hcd_pnx4008_driver
1054#endif
1055
1056#ifdef CONFIG_ARCH_DAVINCI_DA8XX
1057#include "ohci-da8xx.c"
1058#define PLATFORM_DRIVER ohci_hcd_da8xx_driver
1059#endif
1060
1061#ifdef CONFIG_USB_OHCI_SH
1062#include "ohci-sh.c"
1063#define PLATFORM_DRIVER ohci_hcd_sh_driver
1064#endif
1065
1066
1067#ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1068#include "ohci-ppc-of.c"
1069#define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1070#endif
1071
1072#ifdef CONFIG_PLAT_SPEAR
1073#include "ohci-spear.c"
1074#define PLATFORM_DRIVER spear_ohci_hcd_driver
1075#endif
1076
1077#ifdef CONFIG_PPC_PS3
1078#include "ohci-ps3.c"
1079#define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1080#endif
1081
1082#ifdef CONFIG_USB_OHCI_HCD_SSB
1083#include "ohci-ssb.c"
1084#define SSB_OHCI_DRIVER ssb_ohci_driver
1085#endif
1086
1087#ifdef CONFIG_MFD_SM501
1088#include "ohci-sm501.c"
1089#define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1090#endif
1091
1092#ifdef CONFIG_MFD_TC6393XB
1093#include "ohci-tmio.c"
1094#define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
1095#endif
1096
1097#ifdef CONFIG_MACH_JZ4740
1098#include "ohci-jz4740.c"
1099#define PLATFORM_DRIVER ohci_hcd_jz4740_driver
1100#endif
1101
1102#ifdef CONFIG_USB_OCTEON_OHCI
1103#include "ohci-octeon.c"
1104#define PLATFORM_DRIVER ohci_octeon_driver
1105#endif
1106
1107#ifdef CONFIG_USB_CNS3XXX_OHCI
1108#include "ohci-cns3xxx.c"
1109#define PLATFORM_DRIVER ohci_hcd_cns3xxx_driver
1110#endif
1111
1112#ifdef CONFIG_USB_OHCI_ATH79
1113#include "ohci-ath79.c"
1114#define PLATFORM_DRIVER ohci_hcd_ath79_driver
1115#endif
1116
1117#if !defined(PCI_DRIVER) && \
1118 !defined(PLATFORM_DRIVER) && \
1119 !defined(OMAP1_PLATFORM_DRIVER) && \
1120 !defined(OMAP3_PLATFORM_DRIVER) && \
1121 !defined(OF_PLATFORM_DRIVER) && \
1122 !defined(SA1111_DRIVER) && \
1123 !defined(PS3_SYSTEM_BUS_DRIVER) && \
1124 !defined(SM501_OHCI_DRIVER) && \
1125 !defined(TMIO_OHCI_DRIVER) && \
1126 !defined(SSB_OHCI_DRIVER)
1127#error "missing bus glue for ohci-hcd"
1128#endif
1129
1130static int __init ohci_hcd_mod_init(void)
1131{
1132 int retval = 0;
1133
1134 if (usb_disabled())
1135 return -ENODEV;
1136
1137 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1138 pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
1139 sizeof (struct ed), sizeof (struct td));
1140 set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1141
1142#ifdef DEBUG
1143 ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1144 if (!ohci_debug_root) {
1145 retval = -ENOENT;
1146 goto error_debug;
1147 }
1148#endif
1149
1150#ifdef PS3_SYSTEM_BUS_DRIVER
1151 retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1152 if (retval < 0)
1153 goto error_ps3;
1154#endif
1155
1156#ifdef PLATFORM_DRIVER
1157 retval = platform_driver_register(&PLATFORM_DRIVER);
1158 if (retval < 0)
1159 goto error_platform;
1160#endif
1161
1162#ifdef OMAP1_PLATFORM_DRIVER
1163 retval = platform_driver_register(&OMAP1_PLATFORM_DRIVER);
1164 if (retval < 0)
1165 goto error_omap1_platform;
1166#endif
1167
1168#ifdef OMAP3_PLATFORM_DRIVER
1169 retval = platform_driver_register(&OMAP3_PLATFORM_DRIVER);
1170 if (retval < 0)
1171 goto error_omap3_platform;
1172#endif
1173
1174#ifdef OF_PLATFORM_DRIVER
1175 retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1176 if (retval < 0)
1177 goto error_of_platform;
1178#endif
1179
1180#ifdef SA1111_DRIVER
1181 retval = sa1111_driver_register(&SA1111_DRIVER);
1182 if (retval < 0)
1183 goto error_sa1111;
1184#endif
1185
1186#ifdef PCI_DRIVER
1187 retval = pci_register_driver(&PCI_DRIVER);
1188 if (retval < 0)
1189 goto error_pci;
1190#endif
1191
1192#ifdef SSB_OHCI_DRIVER
1193 retval = ssb_driver_register(&SSB_OHCI_DRIVER);
1194 if (retval)
1195 goto error_ssb;
1196#endif
1197
1198#ifdef SM501_OHCI_DRIVER
1199 retval = platform_driver_register(&SM501_OHCI_DRIVER);
1200 if (retval < 0)
1201 goto error_sm501;
1202#endif
1203
1204#ifdef TMIO_OHCI_DRIVER
1205 retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1206 if (retval < 0)
1207 goto error_tmio;
1208#endif
1209
1210 return retval;
1211
1212 /* Error path */
1213#ifdef TMIO_OHCI_DRIVER
1214 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1215 error_tmio:
1216#endif
1217#ifdef SM501_OHCI_DRIVER
1218 platform_driver_unregister(&SM501_OHCI_DRIVER);
1219 error_sm501:
1220#endif
1221#ifdef SSB_OHCI_DRIVER
1222 ssb_driver_unregister(&SSB_OHCI_DRIVER);
1223 error_ssb:
1224#endif
1225#ifdef PCI_DRIVER
1226 pci_unregister_driver(&PCI_DRIVER);
1227 error_pci:
1228#endif
1229#ifdef SA1111_DRIVER
1230 sa1111_driver_unregister(&SA1111_DRIVER);
1231 error_sa1111:
1232#endif
1233#ifdef OF_PLATFORM_DRIVER
1234 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1235 error_of_platform:
1236#endif
1237#ifdef PLATFORM_DRIVER
1238 platform_driver_unregister(&PLATFORM_DRIVER);
1239 error_platform:
1240#endif
1241#ifdef OMAP1_PLATFORM_DRIVER
1242 platform_driver_unregister(&OMAP1_PLATFORM_DRIVER);
1243 error_omap1_platform:
1244#endif
1245#ifdef OMAP3_PLATFORM_DRIVER
1246 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
1247 error_omap3_platform:
1248#endif
1249#ifdef PS3_SYSTEM_BUS_DRIVER
1250 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1251 error_ps3:
1252#endif
1253#ifdef DEBUG
1254 debugfs_remove(ohci_debug_root);
1255 ohci_debug_root = NULL;
1256 error_debug:
1257#endif
1258
1259 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1260 return retval;
1261}
1262module_init(ohci_hcd_mod_init);
1263
1264static void __exit ohci_hcd_mod_exit(void)
1265{
1266#ifdef TMIO_OHCI_DRIVER
1267 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1268#endif
1269#ifdef SM501_OHCI_DRIVER
1270 platform_driver_unregister(&SM501_OHCI_DRIVER);
1271#endif
1272#ifdef SSB_OHCI_DRIVER
1273 ssb_driver_unregister(&SSB_OHCI_DRIVER);
1274#endif
1275#ifdef PCI_DRIVER
1276 pci_unregister_driver(&PCI_DRIVER);
1277#endif
1278#ifdef SA1111_DRIVER
1279 sa1111_driver_unregister(&SA1111_DRIVER);
1280#endif
1281#ifdef OF_PLATFORM_DRIVER
1282 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1283#endif
1284#ifdef PLATFORM_DRIVER
1285 platform_driver_unregister(&PLATFORM_DRIVER);
1286#endif
1287#ifdef OMAP3_PLATFORM_DRIVER
1288 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
1289#endif
1290#ifdef PS3_SYSTEM_BUS_DRIVER
1291 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1292#endif
1293#ifdef DEBUG
1294 debugfs_remove(ohci_debug_root);
1295#endif
1296 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1297}
1298module_exit(ohci_hcd_mod_exit);
1299
1/*
2 * Open Host Controller Interface (OHCI) driver for USB.
3 *
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
5 *
6 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
7 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
8 *
9 * [ Initialisation is based on Linus' ]
10 * [ uhci code and gregs ohci fragments ]
11 * [ (C) Copyright 1999 Linus Torvalds ]
12 * [ (C) Copyright 1999 Gregory P. Smith]
13 *
14 *
15 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
16 * interfaces (though some non-x86 Intel chips use it). It supports
17 * smarter hardware than UHCI. A download link for the spec available
18 * through the http://www.usb.org website.
19 *
20 * This file is licenced under the GPL.
21 */
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/pci.h>
26#include <linux/kernel.h>
27#include <linux/delay.h>
28#include <linux/ioport.h>
29#include <linux/sched.h>
30#include <linux/slab.h>
31#include <linux/errno.h>
32#include <linux/init.h>
33#include <linux/timer.h>
34#include <linux/list.h>
35#include <linux/usb.h>
36#include <linux/usb/otg.h>
37#include <linux/usb/hcd.h>
38#include <linux/dma-mapping.h>
39#include <linux/dmapool.h>
40#include <linux/workqueue.h>
41#include <linux/debugfs.h>
42
43#include <asm/io.h>
44#include <asm/irq.h>
45#include <asm/unaligned.h>
46#include <asm/byteorder.h>
47
48
49#define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
50#define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
51
52/*-------------------------------------------------------------------------*/
53
54/* For initializing controller (mask in an HCFS mode too) */
55#define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
56#define OHCI_INTR_INIT \
57 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
58 | OHCI_INTR_RD | OHCI_INTR_WDH)
59
60#ifdef __hppa__
61/* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
62#define IR_DISABLE
63#endif
64
65#ifdef CONFIG_ARCH_OMAP
66/* OMAP doesn't support IR (no SMM; not needed) */
67#define IR_DISABLE
68#endif
69
70/*-------------------------------------------------------------------------*/
71
72static const char hcd_name [] = "ohci_hcd";
73
74#define STATECHANGE_DELAY msecs_to_jiffies(300)
75
76#include "ohci.h"
77#include "pci-quirks.h"
78
79static void ohci_dump (struct ohci_hcd *ohci, int verbose);
80static void ohci_stop (struct usb_hcd *hcd);
81
82#include "ohci-hub.c"
83#include "ohci-dbg.c"
84#include "ohci-mem.c"
85#include "ohci-q.c"
86
87
88/*
89 * On architectures with edge-triggered interrupts we must never return
90 * IRQ_NONE.
91 */
92#if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
93#define IRQ_NOTMINE IRQ_HANDLED
94#else
95#define IRQ_NOTMINE IRQ_NONE
96#endif
97
98
99/* Some boards misreport power switching/overcurrent */
100static bool distrust_firmware = 1;
101module_param (distrust_firmware, bool, 0);
102MODULE_PARM_DESC (distrust_firmware,
103 "true to distrust firmware power/overcurrent setup");
104
105/* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
106static bool no_handshake = 0;
107module_param (no_handshake, bool, 0);
108MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
109
110/*-------------------------------------------------------------------------*/
111
112/*
113 * queue up an urb for anything except the root hub
114 */
115static int ohci_urb_enqueue (
116 struct usb_hcd *hcd,
117 struct urb *urb,
118 gfp_t mem_flags
119) {
120 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
121 struct ed *ed;
122 urb_priv_t *urb_priv;
123 unsigned int pipe = urb->pipe;
124 int i, size = 0;
125 unsigned long flags;
126 int retval = 0;
127
128 /* every endpoint has a ed, locate and maybe (re)initialize it */
129 if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval)))
130 return -ENOMEM;
131
132 /* for the private part of the URB we need the number of TDs (size) */
133 switch (ed->type) {
134 case PIPE_CONTROL:
135 /* td_submit_urb() doesn't yet handle these */
136 if (urb->transfer_buffer_length > 4096)
137 return -EMSGSIZE;
138
139 /* 1 TD for setup, 1 for ACK, plus ... */
140 size = 2;
141 /* FALLTHROUGH */
142 // case PIPE_INTERRUPT:
143 // case PIPE_BULK:
144 default:
145 /* one TD for every 4096 Bytes (can be up to 8K) */
146 size += urb->transfer_buffer_length / 4096;
147 /* ... and for any remaining bytes ... */
148 if ((urb->transfer_buffer_length % 4096) != 0)
149 size++;
150 /* ... and maybe a zero length packet to wrap it up */
151 if (size == 0)
152 size++;
153 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
154 && (urb->transfer_buffer_length
155 % usb_maxpacket (urb->dev, pipe,
156 usb_pipeout (pipe))) == 0)
157 size++;
158 break;
159 case PIPE_ISOCHRONOUS: /* number of packets from URB */
160 size = urb->number_of_packets;
161 break;
162 }
163
164 /* allocate the private part of the URB */
165 urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
166 mem_flags);
167 if (!urb_priv)
168 return -ENOMEM;
169 INIT_LIST_HEAD (&urb_priv->pending);
170 urb_priv->length = size;
171 urb_priv->ed = ed;
172
173 /* allocate the TDs (deferring hash chain updates) */
174 for (i = 0; i < size; i++) {
175 urb_priv->td [i] = td_alloc (ohci, mem_flags);
176 if (!urb_priv->td [i]) {
177 urb_priv->length = i;
178 urb_free_priv (ohci, urb_priv);
179 return -ENOMEM;
180 }
181 }
182
183 spin_lock_irqsave (&ohci->lock, flags);
184
185 /* don't submit to a dead HC */
186 if (!HCD_HW_ACCESSIBLE(hcd)) {
187 retval = -ENODEV;
188 goto fail;
189 }
190 if (ohci->rh_state != OHCI_RH_RUNNING) {
191 retval = -ENODEV;
192 goto fail;
193 }
194 retval = usb_hcd_link_urb_to_ep(hcd, urb);
195 if (retval)
196 goto fail;
197
198 /* schedule the ed if needed */
199 if (ed->state == ED_IDLE) {
200 retval = ed_schedule (ohci, ed);
201 if (retval < 0) {
202 usb_hcd_unlink_urb_from_ep(hcd, urb);
203 goto fail;
204 }
205 if (ed->type == PIPE_ISOCHRONOUS) {
206 u16 frame = ohci_frame_no(ohci);
207
208 /* delay a few frames before the first TD */
209 frame += max_t (u16, 8, ed->interval);
210 frame &= ~(ed->interval - 1);
211 frame |= ed->branch;
212 urb->start_frame = frame;
213 ed->last_iso = frame + ed->interval * (size - 1);
214 }
215 } else if (ed->type == PIPE_ISOCHRONOUS) {
216 u16 next = ohci_frame_no(ohci) + 1;
217 u16 frame = ed->last_iso + ed->interval;
218 u16 length = ed->interval * (size - 1);
219
220 /* Behind the scheduling threshold? */
221 if (unlikely(tick_before(frame, next))) {
222
223 /* URB_ISO_ASAP: Round up to the first available slot */
224 if (urb->transfer_flags & URB_ISO_ASAP) {
225 frame += (next - frame + ed->interval - 1) &
226 -ed->interval;
227
228 /*
229 * Not ASAP: Use the next slot in the stream,
230 * no matter what.
231 */
232 } else {
233 /*
234 * Some OHCI hardware doesn't handle late TDs
235 * correctly. After retiring them it proceeds
236 * to the next ED instead of the next TD.
237 * Therefore we have to omit the late TDs
238 * entirely.
239 */
240 urb_priv->td_cnt = DIV_ROUND_UP(
241 (u16) (next - frame),
242 ed->interval);
243 if (urb_priv->td_cnt >= urb_priv->length) {
244 ++urb_priv->td_cnt; /* Mark it */
245 ohci_dbg(ohci, "iso underrun %p (%u+%u < %u)\n",
246 urb, frame, length,
247 next);
248 }
249 }
250 }
251 urb->start_frame = frame;
252 ed->last_iso = frame + length;
253 }
254
255 /* fill the TDs and link them to the ed; and
256 * enable that part of the schedule, if needed
257 * and update count of queued periodic urbs
258 */
259 urb->hcpriv = urb_priv;
260 td_submit_urb (ohci, urb);
261
262fail:
263 if (retval)
264 urb_free_priv (ohci, urb_priv);
265 spin_unlock_irqrestore (&ohci->lock, flags);
266 return retval;
267}
268
269/*
270 * decouple the URB from the HC queues (TDs, urb_priv).
271 * reporting is always done
272 * asynchronously, and we might be dealing with an urb that's
273 * partially transferred, or an ED with other urbs being unlinked.
274 */
275static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
276{
277 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
278 unsigned long flags;
279 int rc;
280
281 spin_lock_irqsave (&ohci->lock, flags);
282 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
283 if (rc) {
284 ; /* Do nothing */
285 } else if (ohci->rh_state == OHCI_RH_RUNNING) {
286 urb_priv_t *urb_priv;
287
288 /* Unless an IRQ completed the unlink while it was being
289 * handed to us, flag it for unlink and giveback, and force
290 * some upcoming INTR_SF to call finish_unlinks()
291 */
292 urb_priv = urb->hcpriv;
293 if (urb_priv) {
294 if (urb_priv->ed->state == ED_OPER)
295 start_ed_unlink (ohci, urb_priv->ed);
296 }
297 } else {
298 /*
299 * with HC dead, we won't respect hc queue pointers
300 * any more ... just clean up every urb's memory.
301 */
302 if (urb->hcpriv)
303 finish_urb(ohci, urb, status);
304 }
305 spin_unlock_irqrestore (&ohci->lock, flags);
306 return rc;
307}
308
309/*-------------------------------------------------------------------------*/
310
311/* frees config/altsetting state for endpoints,
312 * including ED memory, dummy TD, and bulk/intr data toggle
313 */
314
315static void
316ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
317{
318 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
319 unsigned long flags;
320 struct ed *ed = ep->hcpriv;
321 unsigned limit = 1000;
322
323 /* ASSERT: any requests/urbs are being unlinked */
324 /* ASSERT: nobody can be submitting urbs for this any more */
325
326 if (!ed)
327 return;
328
329rescan:
330 spin_lock_irqsave (&ohci->lock, flags);
331
332 if (ohci->rh_state != OHCI_RH_RUNNING) {
333sanitize:
334 ed->state = ED_IDLE;
335 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
336 ohci->eds_scheduled--;
337 finish_unlinks (ohci, 0);
338 }
339
340 switch (ed->state) {
341 case ED_UNLINK: /* wait for hw to finish? */
342 /* major IRQ delivery trouble loses INTR_SF too... */
343 if (limit-- == 0) {
344 ohci_warn(ohci, "ED unlink timeout\n");
345 if (quirk_zfmicro(ohci)) {
346 ohci_warn(ohci, "Attempting ZF TD recovery\n");
347 ohci->ed_to_check = ed;
348 ohci->zf_delay = 2;
349 }
350 goto sanitize;
351 }
352 spin_unlock_irqrestore (&ohci->lock, flags);
353 schedule_timeout_uninterruptible(1);
354 goto rescan;
355 case ED_IDLE: /* fully unlinked */
356 if (list_empty (&ed->td_list)) {
357 td_free (ohci, ed->dummy);
358 ed_free (ohci, ed);
359 break;
360 }
361 /* else FALL THROUGH */
362 default:
363 /* caller was supposed to have unlinked any requests;
364 * that's not our job. can't recover; must leak ed.
365 */
366 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
367 ed, ep->desc.bEndpointAddress, ed->state,
368 list_empty (&ed->td_list) ? "" : " (has tds)");
369 td_free (ohci, ed->dummy);
370 break;
371 }
372 ep->hcpriv = NULL;
373 spin_unlock_irqrestore (&ohci->lock, flags);
374}
375
376static int ohci_get_frame (struct usb_hcd *hcd)
377{
378 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
379
380 return ohci_frame_no(ohci);
381}
382
383static void ohci_usb_reset (struct ohci_hcd *ohci)
384{
385 ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
386 ohci->hc_control &= OHCI_CTRL_RWC;
387 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
388 ohci->rh_state = OHCI_RH_HALTED;
389}
390
391/* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
392 * other cases where the next software may expect clean state from the
393 * "firmware". this is bus-neutral, unlike shutdown() methods.
394 */
395static void
396ohci_shutdown (struct usb_hcd *hcd)
397{
398 struct ohci_hcd *ohci;
399
400 ohci = hcd_to_ohci (hcd);
401 ohci_writel(ohci, (u32) ~0, &ohci->regs->intrdisable);
402
403 /* Software reset, after which the controller goes into SUSPEND */
404 ohci_writel(ohci, OHCI_HCR, &ohci->regs->cmdstatus);
405 ohci_readl(ohci, &ohci->regs->cmdstatus); /* flush the writes */
406 udelay(10);
407
408 ohci_writel(ohci, ohci->fminterval, &ohci->regs->fminterval);
409}
410
411static int check_ed(struct ohci_hcd *ohci, struct ed *ed)
412{
413 return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0
414 && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK)
415 == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK)
416 && !list_empty(&ed->td_list);
417}
418
419/* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes
420 * an interrupt TD but neglects to add it to the donelist. On systems with
421 * this chipset, we need to periodically check the state of the queues to look
422 * for such "lost" TDs.
423 */
424static void unlink_watchdog_func(unsigned long _ohci)
425{
426 unsigned long flags;
427 unsigned max;
428 unsigned seen_count = 0;
429 unsigned i;
430 struct ed **seen = NULL;
431 struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci;
432
433 spin_lock_irqsave(&ohci->lock, flags);
434 max = ohci->eds_scheduled;
435 if (!max)
436 goto done;
437
438 if (ohci->ed_to_check)
439 goto out;
440
441 seen = kcalloc(max, sizeof *seen, GFP_ATOMIC);
442 if (!seen)
443 goto out;
444
445 for (i = 0; i < NUM_INTS; i++) {
446 struct ed *ed = ohci->periodic[i];
447
448 while (ed) {
449 unsigned temp;
450
451 /* scan this branch of the periodic schedule tree */
452 for (temp = 0; temp < seen_count; temp++) {
453 if (seen[temp] == ed) {
454 /* we've checked it and what's after */
455 ed = NULL;
456 break;
457 }
458 }
459 if (!ed)
460 break;
461 seen[seen_count++] = ed;
462 if (!check_ed(ohci, ed)) {
463 ed = ed->ed_next;
464 continue;
465 }
466
467 /* HC's TD list is empty, but HCD sees at least one
468 * TD that's not been sent through the donelist.
469 */
470 ohci->ed_to_check = ed;
471 ohci->zf_delay = 2;
472
473 /* The HC may wait until the next frame to report the
474 * TD as done through the donelist and INTR_WDH. (We
475 * just *assume* it's not a multi-TD interrupt URB;
476 * those could defer the IRQ more than one frame, using
477 * DI...) Check again after the next INTR_SF.
478 */
479 ohci_writel(ohci, OHCI_INTR_SF,
480 &ohci->regs->intrstatus);
481 ohci_writel(ohci, OHCI_INTR_SF,
482 &ohci->regs->intrenable);
483
484 /* flush those writes */
485 (void) ohci_readl(ohci, &ohci->regs->control);
486
487 goto out;
488 }
489 }
490out:
491 kfree(seen);
492 if (ohci->eds_scheduled)
493 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
494done:
495 spin_unlock_irqrestore(&ohci->lock, flags);
496}
497
498/*-------------------------------------------------------------------------*
499 * HC functions
500 *-------------------------------------------------------------------------*/
501
502/* init memory, and kick BIOS/SMM off */
503
504static int ohci_init (struct ohci_hcd *ohci)
505{
506 int ret;
507 struct usb_hcd *hcd = ohci_to_hcd(ohci);
508
509 if (distrust_firmware)
510 ohci->flags |= OHCI_QUIRK_HUB_POWER;
511
512 ohci->rh_state = OHCI_RH_HALTED;
513 ohci->regs = hcd->regs;
514
515 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
516 * was never needed for most non-PCI systems ... remove the code?
517 */
518
519#ifndef IR_DISABLE
520 /* SMM owns the HC? not for long! */
521 if (!no_handshake && ohci_readl (ohci,
522 &ohci->regs->control) & OHCI_CTRL_IR) {
523 u32 temp;
524
525 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
526
527 /* this timeout is arbitrary. we make it long, so systems
528 * depending on usb keyboards may be usable even if the
529 * BIOS/SMM code seems pretty broken.
530 */
531 temp = 500; /* arbitrary: five seconds */
532
533 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
534 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
535 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
536 msleep (10);
537 if (--temp == 0) {
538 ohci_err (ohci, "USB HC takeover failed!"
539 " (BIOS/SMM bug)\n");
540 return -EBUSY;
541 }
542 }
543 ohci_usb_reset (ohci);
544 }
545#endif
546
547 /* Disable HC interrupts */
548 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
549
550 /* flush the writes, and save key bits like RWC */
551 if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
552 ohci->hc_control |= OHCI_CTRL_RWC;
553
554 /* Read the number of ports unless overridden */
555 if (ohci->num_ports == 0)
556 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
557
558 if (ohci->hcca)
559 return 0;
560
561 ohci->hcca = dma_alloc_coherent (hcd->self.controller,
562 sizeof *ohci->hcca, &ohci->hcca_dma, 0);
563 if (!ohci->hcca)
564 return -ENOMEM;
565
566 if ((ret = ohci_mem_init (ohci)) < 0)
567 ohci_stop (hcd);
568 else {
569 create_debug_files (ohci);
570 }
571
572 return ret;
573}
574
575/*-------------------------------------------------------------------------*/
576
577/* Start an OHCI controller, set the BUS operational
578 * resets USB and controller
579 * enable interrupts
580 */
581static int ohci_run (struct ohci_hcd *ohci)
582{
583 u32 mask, val;
584 int first = ohci->fminterval == 0;
585 struct usb_hcd *hcd = ohci_to_hcd(ohci);
586
587 ohci->rh_state = OHCI_RH_HALTED;
588
589 /* boot firmware should have set this up (5.1.1.3.1) */
590 if (first) {
591
592 val = ohci_readl (ohci, &ohci->regs->fminterval);
593 ohci->fminterval = val & 0x3fff;
594 if (ohci->fminterval != FI)
595 ohci_dbg (ohci, "fminterval delta %d\n",
596 ohci->fminterval - FI);
597 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
598 /* also: power/overcurrent flags in roothub.a */
599 }
600
601 /* Reset USB nearly "by the book". RemoteWakeupConnected has
602 * to be checked in case boot firmware (BIOS/SMM/...) has set up
603 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
604 * If the bus glue detected wakeup capability then it should
605 * already be enabled; if so we'll just enable it again.
606 */
607 if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
608 device_set_wakeup_capable(hcd->self.controller, 1);
609
610 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
611 case OHCI_USB_OPER:
612 val = 0;
613 break;
614 case OHCI_USB_SUSPEND:
615 case OHCI_USB_RESUME:
616 ohci->hc_control &= OHCI_CTRL_RWC;
617 ohci->hc_control |= OHCI_USB_RESUME;
618 val = 10 /* msec wait */;
619 break;
620 // case OHCI_USB_RESET:
621 default:
622 ohci->hc_control &= OHCI_CTRL_RWC;
623 ohci->hc_control |= OHCI_USB_RESET;
624 val = 50 /* msec wait */;
625 break;
626 }
627 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
628 // flush the writes
629 (void) ohci_readl (ohci, &ohci->regs->control);
630 msleep(val);
631
632 memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
633
634 /* 2msec timelimit here means no irqs/preempt */
635 spin_lock_irq (&ohci->lock);
636
637retry:
638 /* HC Reset requires max 10 us delay */
639 ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus);
640 val = 30; /* ... allow extra time */
641 while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
642 if (--val == 0) {
643 spin_unlock_irq (&ohci->lock);
644 ohci_err (ohci, "USB HC reset timed out!\n");
645 return -1;
646 }
647 udelay (1);
648 }
649
650 /* now we're in the SUSPEND state ... must go OPERATIONAL
651 * within 2msec else HC enters RESUME
652 *
653 * ... but some hardware won't init fmInterval "by the book"
654 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
655 * this if we write fmInterval after we're OPERATIONAL.
656 * Unclear about ALi, ServerWorks, and others ... this could
657 * easily be a longstanding bug in chip init on Linux.
658 */
659 if (ohci->flags & OHCI_QUIRK_INITRESET) {
660 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
661 // flush those writes
662 (void) ohci_readl (ohci, &ohci->regs->control);
663 }
664
665 /* Tell the controller where the control and bulk lists are
666 * The lists are empty now. */
667 ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
668 ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
669
670 /* a reset clears this */
671 ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
672
673 periodic_reinit (ohci);
674
675 /* some OHCI implementations are finicky about how they init.
676 * bogus values here mean not even enumeration could work.
677 */
678 if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
679 || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
680 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
681 ohci->flags |= OHCI_QUIRK_INITRESET;
682 ohci_dbg (ohci, "enabling initreset quirk\n");
683 goto retry;
684 }
685 spin_unlock_irq (&ohci->lock);
686 ohci_err (ohci, "init err (%08x %04x)\n",
687 ohci_readl (ohci, &ohci->regs->fminterval),
688 ohci_readl (ohci, &ohci->regs->periodicstart));
689 return -EOVERFLOW;
690 }
691
692 /* use rhsc irqs after khubd is fully initialized */
693 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
694 hcd->uses_new_polling = 1;
695
696 /* start controller operations */
697 ohci->hc_control &= OHCI_CTRL_RWC;
698 ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
699 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
700 ohci->rh_state = OHCI_RH_RUNNING;
701
702 /* wake on ConnectStatusChange, matching external hubs */
703 ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
704
705 /* Choose the interrupts we care about now, others later on demand */
706 mask = OHCI_INTR_INIT;
707 ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
708 ohci_writel (ohci, mask, &ohci->regs->intrenable);
709
710 /* handle root hub init quirks ... */
711 val = roothub_a (ohci);
712 val &= ~(RH_A_PSM | RH_A_OCPM);
713 if (ohci->flags & OHCI_QUIRK_SUPERIO) {
714 /* NSC 87560 and maybe others */
715 val |= RH_A_NOCP;
716 val &= ~(RH_A_POTPGT | RH_A_NPS);
717 ohci_writel (ohci, val, &ohci->regs->roothub.a);
718 } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
719 (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
720 /* hub power always on; required for AMD-756 and some
721 * Mac platforms. ganged overcurrent reporting, if any.
722 */
723 val |= RH_A_NPS;
724 ohci_writel (ohci, val, &ohci->regs->roothub.a);
725 }
726 ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
727 ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
728 &ohci->regs->roothub.b);
729 // flush those writes
730 (void) ohci_readl (ohci, &ohci->regs->control);
731
732 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
733 spin_unlock_irq (&ohci->lock);
734
735 // POTPGT delay is bits 24-31, in 2 ms units.
736 mdelay ((val >> 23) & 0x1fe);
737
738 if (quirk_zfmicro(ohci)) {
739 /* Create timer to watch for bad queue state on ZF Micro */
740 setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func,
741 (unsigned long) ohci);
742
743 ohci->eds_scheduled = 0;
744 ohci->ed_to_check = NULL;
745 }
746
747 ohci_dump (ohci, 1);
748
749 return 0;
750}
751
752/* ohci_setup routine for generic controller initialization */
753
754int ohci_setup(struct usb_hcd *hcd)
755{
756 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
757
758 ohci_hcd_init(ohci);
759
760 return ohci_init(ohci);
761}
762EXPORT_SYMBOL_GPL(ohci_setup);
763
764/* ohci_start routine for generic controller start of all OHCI bus glue */
765static int ohci_start(struct usb_hcd *hcd)
766{
767 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
768 int ret;
769
770 ret = ohci_run(ohci);
771 if (ret < 0) {
772 ohci_err(ohci, "can't start\n");
773 ohci_stop(hcd);
774 }
775 return ret;
776}
777
778/*-------------------------------------------------------------------------*/
779
780/* an interrupt happens */
781
782static irqreturn_t ohci_irq (struct usb_hcd *hcd)
783{
784 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
785 struct ohci_regs __iomem *regs = ohci->regs;
786 int ints;
787
788 /* Read interrupt status (and flush pending writes). We ignore the
789 * optimization of checking the LSB of hcca->done_head; it doesn't
790 * work on all systems (edge triggering for OHCI can be a factor).
791 */
792 ints = ohci_readl(ohci, ®s->intrstatus);
793
794 /* Check for an all 1's result which is a typical consequence
795 * of dead, unclocked, or unplugged (CardBus...) devices
796 */
797 if (ints == ~(u32)0) {
798 ohci->rh_state = OHCI_RH_HALTED;
799 ohci_dbg (ohci, "device removed!\n");
800 usb_hc_died(hcd);
801 return IRQ_HANDLED;
802 }
803
804 /* We only care about interrupts that are enabled */
805 ints &= ohci_readl(ohci, ®s->intrenable);
806
807 /* interrupt for some other device? */
808 if (ints == 0 || unlikely(ohci->rh_state == OHCI_RH_HALTED))
809 return IRQ_NOTMINE;
810
811 if (ints & OHCI_INTR_UE) {
812 // e.g. due to PCI Master/Target Abort
813 if (quirk_nec(ohci)) {
814 /* Workaround for a silicon bug in some NEC chips used
815 * in Apple's PowerBooks. Adapted from Darwin code.
816 */
817 ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
818
819 ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable);
820
821 schedule_work (&ohci->nec_work);
822 } else {
823 ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
824 ohci->rh_state = OHCI_RH_HALTED;
825 usb_hc_died(hcd);
826 }
827
828 ohci_dump (ohci, 1);
829 ohci_usb_reset (ohci);
830 }
831
832 if (ints & OHCI_INTR_RHSC) {
833 ohci_dbg(ohci, "rhsc\n");
834 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
835 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
836 ®s->intrstatus);
837
838 /* NOTE: Vendors didn't always make the same implementation
839 * choices for RHSC. Many followed the spec; RHSC triggers
840 * on an edge, like setting and maybe clearing a port status
841 * change bit. With others it's level-triggered, active
842 * until khubd clears all the port status change bits. We'll
843 * always disable it here and rely on polling until khubd
844 * re-enables it.
845 */
846 ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable);
847 usb_hcd_poll_rh_status(hcd);
848 }
849
850 /* For connect and disconnect events, we expect the controller
851 * to turn on RHSC along with RD. But for remote wakeup events
852 * this might not happen.
853 */
854 else if (ints & OHCI_INTR_RD) {
855 ohci_dbg(ohci, "resume detect\n");
856 ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus);
857 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
858 if (ohci->autostop) {
859 spin_lock (&ohci->lock);
860 ohci_rh_resume (ohci);
861 spin_unlock (&ohci->lock);
862 } else
863 usb_hcd_resume_root_hub(hcd);
864 }
865
866 if (ints & OHCI_INTR_WDH) {
867 spin_lock (&ohci->lock);
868 dl_done_list (ohci);
869 spin_unlock (&ohci->lock);
870 }
871
872 if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) {
873 spin_lock(&ohci->lock);
874 if (ohci->ed_to_check) {
875 struct ed *ed = ohci->ed_to_check;
876
877 if (check_ed(ohci, ed)) {
878 /* HC thinks the TD list is empty; HCD knows
879 * at least one TD is outstanding
880 */
881 if (--ohci->zf_delay == 0) {
882 struct td *td = list_entry(
883 ed->td_list.next,
884 struct td, td_list);
885 ohci_warn(ohci,
886 "Reclaiming orphan TD %p\n",
887 td);
888 takeback_td(ohci, td);
889 ohci->ed_to_check = NULL;
890 }
891 } else
892 ohci->ed_to_check = NULL;
893 }
894 spin_unlock(&ohci->lock);
895 }
896
897 /* could track INTR_SO to reduce available PCI/... bandwidth */
898
899 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
900 * when there's still unlinking to be done (next frame).
901 */
902 spin_lock (&ohci->lock);
903 if (ohci->ed_rm_list)
904 finish_unlinks (ohci, ohci_frame_no(ohci));
905 if ((ints & OHCI_INTR_SF) != 0
906 && !ohci->ed_rm_list
907 && !ohci->ed_to_check
908 && ohci->rh_state == OHCI_RH_RUNNING)
909 ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable);
910 spin_unlock (&ohci->lock);
911
912 if (ohci->rh_state == OHCI_RH_RUNNING) {
913 ohci_writel (ohci, ints, ®s->intrstatus);
914 ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable);
915 // flush those writes
916 (void) ohci_readl (ohci, &ohci->regs->control);
917 }
918
919 return IRQ_HANDLED;
920}
921
922/*-------------------------------------------------------------------------*/
923
924static void ohci_stop (struct usb_hcd *hcd)
925{
926 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
927
928 ohci_dump (ohci, 1);
929
930 if (quirk_nec(ohci))
931 flush_work(&ohci->nec_work);
932
933 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
934 ohci_usb_reset(ohci);
935 free_irq(hcd->irq, hcd);
936 hcd->irq = 0;
937
938 if (quirk_zfmicro(ohci))
939 del_timer(&ohci->unlink_watchdog);
940 if (quirk_amdiso(ohci))
941 usb_amd_dev_put();
942
943 remove_debug_files (ohci);
944 ohci_mem_cleanup (ohci);
945 if (ohci->hcca) {
946 dma_free_coherent (hcd->self.controller,
947 sizeof *ohci->hcca,
948 ohci->hcca, ohci->hcca_dma);
949 ohci->hcca = NULL;
950 ohci->hcca_dma = 0;
951 }
952}
953
954/*-------------------------------------------------------------------------*/
955
956#if defined(CONFIG_PM) || defined(CONFIG_PCI)
957
958/* must not be called from interrupt context */
959int ohci_restart(struct ohci_hcd *ohci)
960{
961 int temp;
962 int i;
963 struct urb_priv *priv;
964
965 ohci_init(ohci);
966 spin_lock_irq(&ohci->lock);
967 ohci->rh_state = OHCI_RH_HALTED;
968
969 /* Recycle any "live" eds/tds (and urbs). */
970 if (!list_empty (&ohci->pending))
971 ohci_dbg(ohci, "abort schedule...\n");
972 list_for_each_entry (priv, &ohci->pending, pending) {
973 struct urb *urb = priv->td[0]->urb;
974 struct ed *ed = priv->ed;
975
976 switch (ed->state) {
977 case ED_OPER:
978 ed->state = ED_UNLINK;
979 ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
980 ed_deschedule (ohci, ed);
981
982 ed->ed_next = ohci->ed_rm_list;
983 ed->ed_prev = NULL;
984 ohci->ed_rm_list = ed;
985 /* FALLTHROUGH */
986 case ED_UNLINK:
987 break;
988 default:
989 ohci_dbg(ohci, "bogus ed %p state %d\n",
990 ed, ed->state);
991 }
992
993 if (!urb->unlinked)
994 urb->unlinked = -ESHUTDOWN;
995 }
996 finish_unlinks (ohci, 0);
997 spin_unlock_irq(&ohci->lock);
998
999 /* paranoia, in case that didn't work: */
1000
1001 /* empty the interrupt branches */
1002 for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
1003 for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
1004
1005 /* no EDs to remove */
1006 ohci->ed_rm_list = NULL;
1007
1008 /* empty control and bulk lists */
1009 ohci->ed_controltail = NULL;
1010 ohci->ed_bulktail = NULL;
1011
1012 if ((temp = ohci_run (ohci)) < 0) {
1013 ohci_err (ohci, "can't restart, %d\n", temp);
1014 return temp;
1015 }
1016 ohci_dbg(ohci, "restart complete\n");
1017 return 0;
1018}
1019EXPORT_SYMBOL_GPL(ohci_restart);
1020
1021#endif
1022
1023#ifdef CONFIG_PM
1024
1025int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
1026{
1027 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
1028 unsigned long flags;
1029 int rc = 0;
1030
1031 /* Disable irq emission and mark HW unaccessible. Use
1032 * the spinlock to properly synchronize with possible pending
1033 * RH suspend or resume activity.
1034 */
1035 spin_lock_irqsave (&ohci->lock, flags);
1036 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
1037 (void)ohci_readl(ohci, &ohci->regs->intrdisable);
1038
1039 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1040 spin_unlock_irqrestore (&ohci->lock, flags);
1041
1042 synchronize_irq(hcd->irq);
1043
1044 if (do_wakeup && HCD_WAKEUP_PENDING(hcd)) {
1045 ohci_resume(hcd, false);
1046 rc = -EBUSY;
1047 }
1048 return rc;
1049}
1050EXPORT_SYMBOL_GPL(ohci_suspend);
1051
1052
1053int ohci_resume(struct usb_hcd *hcd, bool hibernated)
1054{
1055 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
1056 int port;
1057 bool need_reinit = false;
1058
1059 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1060
1061 /* Make sure resume from hibernation re-enumerates everything */
1062 if (hibernated)
1063 ohci_usb_reset(ohci);
1064
1065 /* See if the controller is already running or has been reset */
1066 ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
1067 if (ohci->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) {
1068 need_reinit = true;
1069 } else {
1070 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
1071 case OHCI_USB_OPER:
1072 case OHCI_USB_RESET:
1073 need_reinit = true;
1074 }
1075 }
1076
1077 /* If needed, reinitialize and suspend the root hub */
1078 if (need_reinit) {
1079 spin_lock_irq(&ohci->lock);
1080 ohci_rh_resume(ohci);
1081 ohci_rh_suspend(ohci, 0);
1082 spin_unlock_irq(&ohci->lock);
1083 }
1084
1085 /* Normally just turn on port power and enable interrupts */
1086 else {
1087 ohci_dbg(ohci, "powerup ports\n");
1088 for (port = 0; port < ohci->num_ports; port++)
1089 ohci_writel(ohci, RH_PS_PPS,
1090 &ohci->regs->roothub.portstatus[port]);
1091
1092 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrenable);
1093 ohci_readl(ohci, &ohci->regs->intrenable);
1094 msleep(20);
1095 }
1096
1097 usb_hcd_resume_root_hub(hcd);
1098
1099 return 0;
1100}
1101EXPORT_SYMBOL_GPL(ohci_resume);
1102
1103#endif
1104
1105/*-------------------------------------------------------------------------*/
1106
1107/*
1108 * Generic structure: This gets copied for platform drivers so that
1109 * individual entries can be overridden as needed.
1110 */
1111
1112static const struct hc_driver ohci_hc_driver = {
1113 .description = hcd_name,
1114 .product_desc = "OHCI Host Controller",
1115 .hcd_priv_size = sizeof(struct ohci_hcd),
1116
1117 /*
1118 * generic hardware linkage
1119 */
1120 .irq = ohci_irq,
1121 .flags = HCD_MEMORY | HCD_USB11,
1122
1123 /*
1124 * basic lifecycle operations
1125 */
1126 .reset = ohci_setup,
1127 .start = ohci_start,
1128 .stop = ohci_stop,
1129 .shutdown = ohci_shutdown,
1130
1131 /*
1132 * managing i/o requests and associated device resources
1133 */
1134 .urb_enqueue = ohci_urb_enqueue,
1135 .urb_dequeue = ohci_urb_dequeue,
1136 .endpoint_disable = ohci_endpoint_disable,
1137
1138 /*
1139 * scheduling support
1140 */
1141 .get_frame_number = ohci_get_frame,
1142
1143 /*
1144 * root hub support
1145 */
1146 .hub_status_data = ohci_hub_status_data,
1147 .hub_control = ohci_hub_control,
1148#ifdef CONFIG_PM
1149 .bus_suspend = ohci_bus_suspend,
1150 .bus_resume = ohci_bus_resume,
1151#endif
1152 .start_port_reset = ohci_start_port_reset,
1153};
1154
1155void ohci_init_driver(struct hc_driver *drv,
1156 const struct ohci_driver_overrides *over)
1157{
1158 /* Copy the generic table to drv and then apply the overrides */
1159 *drv = ohci_hc_driver;
1160
1161 if (over) {
1162 drv->product_desc = over->product_desc;
1163 drv->hcd_priv_size += over->extra_priv_size;
1164 if (over->reset)
1165 drv->reset = over->reset;
1166 }
1167}
1168EXPORT_SYMBOL_GPL(ohci_init_driver);
1169
1170/*-------------------------------------------------------------------------*/
1171
1172MODULE_AUTHOR (DRIVER_AUTHOR);
1173MODULE_DESCRIPTION(DRIVER_DESC);
1174MODULE_LICENSE ("GPL");
1175
1176#if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1177#include "ohci-sa1111.c"
1178#define SA1111_DRIVER ohci_hcd_sa1111_driver
1179#endif
1180
1181#ifdef CONFIG_ARCH_DAVINCI_DA8XX
1182#include "ohci-da8xx.c"
1183#define DAVINCI_PLATFORM_DRIVER ohci_hcd_da8xx_driver
1184#endif
1185
1186#ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1187#include "ohci-ppc-of.c"
1188#define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1189#endif
1190
1191#ifdef CONFIG_PPC_PS3
1192#include "ohci-ps3.c"
1193#define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1194#endif
1195
1196#ifdef CONFIG_MFD_SM501
1197#include "ohci-sm501.c"
1198#define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1199#endif
1200
1201#ifdef CONFIG_MFD_TC6393XB
1202#include "ohci-tmio.c"
1203#define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
1204#endif
1205
1206#ifdef CONFIG_MACH_JZ4740
1207#include "ohci-jz4740.c"
1208#define PLATFORM_DRIVER ohci_hcd_jz4740_driver
1209#endif
1210
1211#ifdef CONFIG_USB_OCTEON_OHCI
1212#include "ohci-octeon.c"
1213#define PLATFORM_DRIVER ohci_octeon_driver
1214#endif
1215
1216#ifdef CONFIG_TILE_USB
1217#include "ohci-tilegx.c"
1218#define PLATFORM_DRIVER ohci_hcd_tilegx_driver
1219#endif
1220
1221static int __init ohci_hcd_mod_init(void)
1222{
1223 int retval = 0;
1224
1225 if (usb_disabled())
1226 return -ENODEV;
1227
1228 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1229 pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
1230 sizeof (struct ed), sizeof (struct td));
1231 set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1232
1233 ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1234 if (!ohci_debug_root) {
1235 retval = -ENOENT;
1236 goto error_debug;
1237 }
1238
1239#ifdef PS3_SYSTEM_BUS_DRIVER
1240 retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1241 if (retval < 0)
1242 goto error_ps3;
1243#endif
1244
1245#ifdef PLATFORM_DRIVER
1246 retval = platform_driver_register(&PLATFORM_DRIVER);
1247 if (retval < 0)
1248 goto error_platform;
1249#endif
1250
1251#ifdef OF_PLATFORM_DRIVER
1252 retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1253 if (retval < 0)
1254 goto error_of_platform;
1255#endif
1256
1257#ifdef SA1111_DRIVER
1258 retval = sa1111_driver_register(&SA1111_DRIVER);
1259 if (retval < 0)
1260 goto error_sa1111;
1261#endif
1262
1263#ifdef SM501_OHCI_DRIVER
1264 retval = platform_driver_register(&SM501_OHCI_DRIVER);
1265 if (retval < 0)
1266 goto error_sm501;
1267#endif
1268
1269#ifdef TMIO_OHCI_DRIVER
1270 retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1271 if (retval < 0)
1272 goto error_tmio;
1273#endif
1274
1275#ifdef DAVINCI_PLATFORM_DRIVER
1276 retval = platform_driver_register(&DAVINCI_PLATFORM_DRIVER);
1277 if (retval < 0)
1278 goto error_davinci;
1279#endif
1280
1281 return retval;
1282
1283 /* Error path */
1284#ifdef DAVINCI_PLATFORM_DRIVER
1285 platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER);
1286 error_davinci:
1287#endif
1288#ifdef TMIO_OHCI_DRIVER
1289 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1290 error_tmio:
1291#endif
1292#ifdef SM501_OHCI_DRIVER
1293 platform_driver_unregister(&SM501_OHCI_DRIVER);
1294 error_sm501:
1295#endif
1296#ifdef SA1111_DRIVER
1297 sa1111_driver_unregister(&SA1111_DRIVER);
1298 error_sa1111:
1299#endif
1300#ifdef OF_PLATFORM_DRIVER
1301 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1302 error_of_platform:
1303#endif
1304#ifdef PLATFORM_DRIVER
1305 platform_driver_unregister(&PLATFORM_DRIVER);
1306 error_platform:
1307#endif
1308#ifdef PS3_SYSTEM_BUS_DRIVER
1309 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1310 error_ps3:
1311#endif
1312 debugfs_remove(ohci_debug_root);
1313 ohci_debug_root = NULL;
1314 error_debug:
1315
1316 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1317 return retval;
1318}
1319module_init(ohci_hcd_mod_init);
1320
1321static void __exit ohci_hcd_mod_exit(void)
1322{
1323#ifdef DAVINCI_PLATFORM_DRIVER
1324 platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER);
1325#endif
1326#ifdef TMIO_OHCI_DRIVER
1327 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1328#endif
1329#ifdef SM501_OHCI_DRIVER
1330 platform_driver_unregister(&SM501_OHCI_DRIVER);
1331#endif
1332#ifdef SA1111_DRIVER
1333 sa1111_driver_unregister(&SA1111_DRIVER);
1334#endif
1335#ifdef OF_PLATFORM_DRIVER
1336 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1337#endif
1338#ifdef PLATFORM_DRIVER
1339 platform_driver_unregister(&PLATFORM_DRIVER);
1340#endif
1341#ifdef PS3_SYSTEM_BUS_DRIVER
1342 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1343#endif
1344 debugfs_remove(ohci_debug_root);
1345 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1346}
1347module_exit(ohci_hcd_mod_exit);
1348