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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
7 */
8
9/**
10 * DOC: VC4 Falcon HDMI module
11 *
12 * The HDMI core has a state machine and a PHY. On BCM2835, most of
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
15 *
16 * HDMI infoframes are kept within a small packet ram, where each
17 * packet can be individually enabled for including in a frame.
18 *
19 * HDMI audio is implemented entirely within the HDMI IP block. A
20 * register in the HDMI encoder takes SPDIF frames from the DMA engine
21 * and transfers them over an internal MAI (multi-channel audio
22 * interconnect) bus to the encoder side for insertion into the video
23 * blank regions.
24 *
25 * The driver's HDMI encoder does not yet support power management.
26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27 * continuously running, and only the HDMI logic and packet ram are
28 * powered off/on at disable/enable time.
29 *
30 * The driver does not yet support CEC control, though the HDMI
31 * encoder block has CEC support.
32 */
33
34#include <drm/display/drm_hdmi_helper.h>
35#include <drm/display/drm_scdc_helper.h>
36#include <drm/drm_atomic_helper.h>
37#include <drm/drm_drv.h>
38#include <drm/drm_probe_helper.h>
39#include <drm/drm_simple_kms_helper.h>
40#include <linux/clk.h>
41#include <linux/component.h>
42#include <linux/gpio/consumer.h>
43#include <linux/i2c.h>
44#include <linux/of.h>
45#include <linux/of_address.h>
46#include <linux/pm_runtime.h>
47#include <linux/rational.h>
48#include <linux/reset.h>
49#include <sound/dmaengine_pcm.h>
50#include <sound/hdmi-codec.h>
51#include <sound/pcm_drm_eld.h>
52#include <sound/pcm_params.h>
53#include <sound/soc.h>
54#include "media/cec.h"
55#include "vc4_drv.h"
56#include "vc4_hdmi.h"
57#include "vc4_hdmi_regs.h"
58#include "vc4_regs.h"
59
60#define VC5_HDMI_HORZA_HFP_SHIFT 16
61#define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
62#define VC5_HDMI_HORZA_VPOS BIT(15)
63#define VC5_HDMI_HORZA_HPOS BIT(14)
64#define VC5_HDMI_HORZA_HAP_SHIFT 0
65#define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
66
67#define VC5_HDMI_HORZB_HBP_SHIFT 16
68#define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
69#define VC5_HDMI_HORZB_HSP_SHIFT 0
70#define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
71
72#define VC5_HDMI_VERTA_VSP_SHIFT 24
73#define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
74#define VC5_HDMI_VERTA_VFP_SHIFT 16
75#define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
76#define VC5_HDMI_VERTA_VAL_SHIFT 0
77#define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
78
79#define VC5_HDMI_VERTB_VSPO_SHIFT 16
80#define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
81
82#define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
83#define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
84#define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
85#define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
86
87#define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0)
88
89#define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8
90#define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8)
91
92#define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0
93#define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0)
94
95#define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31)
96
97#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8
98#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8)
99
100#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK VC4_MASK(7, 0)
101#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE BIT(0)
102#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE BIT(4)
103
104# define VC4_HD_M_SW_RST BIT(2)
105# define VC4_HD_M_ENABLE BIT(0)
106
107#define HSM_MIN_CLOCK_FREQ 120000000
108#define CEC_CLOCK_FREQ 40000
109
110#define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
111
112static const char * const output_format_str[] = {
113 [VC4_HDMI_OUTPUT_RGB] = "RGB",
114 [VC4_HDMI_OUTPUT_YUV420] = "YUV 4:2:0",
115 [VC4_HDMI_OUTPUT_YUV422] = "YUV 4:2:2",
116 [VC4_HDMI_OUTPUT_YUV444] = "YUV 4:4:4",
117};
118
119static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt)
120{
121 if (fmt >= ARRAY_SIZE(output_format_str))
122 return "invalid";
123
124 return output_format_str[fmt];
125}
126
127static unsigned long long
128vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
129 unsigned int bpc, enum vc4_hdmi_output_format fmt);
130
131static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi)
132{
133 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
134
135 lockdep_assert_held(&vc4_hdmi->mutex);
136
137 if (!display->is_hdmi)
138 return false;
139
140 if (!display->hdmi.scdc.supported ||
141 !display->hdmi.scdc.scrambling.supported)
142 return false;
143
144 return true;
145}
146
147static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
148 unsigned int bpc,
149 enum vc4_hdmi_output_format fmt)
150{
151 unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
152
153 return clock > HDMI_14_MAX_TMDS_CLK;
154}
155
156static bool vc4_hdmi_is_full_range(struct vc4_hdmi *vc4_hdmi,
157 struct vc4_hdmi_connector_state *vc4_state)
158{
159 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
160 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
161
162 if (vc4_state->broadcast_rgb == VC4_HDMI_BROADCAST_RGB_LIMITED)
163 return false;
164 else if (vc4_state->broadcast_rgb == VC4_HDMI_BROADCAST_RGB_FULL)
165 return true;
166
167 return !display->is_hdmi ||
168 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL;
169}
170
171static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
172{
173 struct drm_debugfs_entry *entry = m->private;
174 struct vc4_hdmi *vc4_hdmi = entry->file.data;
175 struct drm_device *drm = vc4_hdmi->connector.dev;
176 struct drm_printer p = drm_seq_file_printer(m);
177 int idx;
178
179 if (!drm_dev_enter(drm, &idx))
180 return -ENODEV;
181
182 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
183 drm_print_regset32(&p, &vc4_hdmi->hd_regset);
184 drm_print_regset32(&p, &vc4_hdmi->cec_regset);
185 drm_print_regset32(&p, &vc4_hdmi->csc_regset);
186 drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
187 drm_print_regset32(&p, &vc4_hdmi->phy_regset);
188 drm_print_regset32(&p, &vc4_hdmi->ram_regset);
189 drm_print_regset32(&p, &vc4_hdmi->rm_regset);
190
191 drm_dev_exit(idx);
192
193 return 0;
194}
195
196static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
197{
198 struct drm_device *drm = vc4_hdmi->connector.dev;
199 unsigned long flags;
200 int idx;
201
202 /*
203 * We can be called by our bind callback, when the
204 * connector->dev pointer might not be initialised yet.
205 */
206 if (drm && !drm_dev_enter(drm, &idx))
207 return;
208
209 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
210
211 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
212 udelay(1);
213 HDMI_WRITE(HDMI_M_CTL, 0);
214
215 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
216
217 HDMI_WRITE(HDMI_SW_RESET_CONTROL,
218 VC4_HDMI_SW_RESET_HDMI |
219 VC4_HDMI_SW_RESET_FORMAT_DETECT);
220
221 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
222
223 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
224
225 if (drm)
226 drm_dev_exit(idx);
227}
228
229static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
230{
231 struct drm_device *drm = vc4_hdmi->connector.dev;
232 unsigned long flags;
233 int idx;
234
235 /*
236 * We can be called by our bind callback, when the
237 * connector->dev pointer might not be initialised yet.
238 */
239 if (drm && !drm_dev_enter(drm, &idx))
240 return;
241
242 reset_control_reset(vc4_hdmi->reset);
243
244 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
245
246 HDMI_WRITE(HDMI_DVP_CTL, 0);
247
248 HDMI_WRITE(HDMI_CLOCK_STOP,
249 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
250
251 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
252
253 if (drm)
254 drm_dev_exit(idx);
255}
256
257#ifdef CONFIG_DRM_VC4_HDMI_CEC
258static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
259{
260 struct drm_device *drm = vc4_hdmi->connector.dev;
261 unsigned long cec_rate;
262 unsigned long flags;
263 u16 clk_cnt;
264 u32 value;
265 int idx;
266
267 /*
268 * This function is called by our runtime_resume implementation
269 * and thus at bind time, when we haven't registered our
270 * connector yet and thus don't have a pointer to the DRM
271 * device.
272 */
273 if (drm && !drm_dev_enter(drm, &idx))
274 return;
275
276 cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
277
278 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
279
280 value = HDMI_READ(HDMI_CEC_CNTRL_1);
281 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
282
283 /*
284 * Set the clock divider: the hsm_clock rate and this divider
285 * setting will give a 40 kHz CEC clock.
286 */
287 clk_cnt = cec_rate / CEC_CLOCK_FREQ;
288 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
289 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
290
291 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
292
293 if (drm)
294 drm_dev_exit(idx);
295}
296#else
297static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
298#endif
299
300static int reset_pipe(struct drm_crtc *crtc,
301 struct drm_modeset_acquire_ctx *ctx)
302{
303 struct drm_atomic_state *state;
304 struct drm_crtc_state *crtc_state;
305 int ret;
306
307 state = drm_atomic_state_alloc(crtc->dev);
308 if (!state)
309 return -ENOMEM;
310
311 state->acquire_ctx = ctx;
312
313 crtc_state = drm_atomic_get_crtc_state(state, crtc);
314 if (IS_ERR(crtc_state)) {
315 ret = PTR_ERR(crtc_state);
316 goto out;
317 }
318
319 crtc_state->connectors_changed = true;
320
321 ret = drm_atomic_commit(state);
322out:
323 drm_atomic_state_put(state);
324
325 return ret;
326}
327
328static int vc4_hdmi_reset_link(struct drm_connector *connector,
329 struct drm_modeset_acquire_ctx *ctx)
330{
331 struct drm_device *drm;
332 struct vc4_hdmi *vc4_hdmi;
333 struct drm_connector_state *conn_state;
334 struct drm_crtc_state *crtc_state;
335 struct drm_crtc *crtc;
336 bool scrambling_needed;
337 u8 config;
338 int ret;
339
340 if (!connector)
341 return 0;
342
343 drm = connector->dev;
344 ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx);
345 if (ret)
346 return ret;
347
348 conn_state = connector->state;
349 crtc = conn_state->crtc;
350 if (!crtc)
351 return 0;
352
353 ret = drm_modeset_lock(&crtc->mutex, ctx);
354 if (ret)
355 return ret;
356
357 crtc_state = crtc->state;
358 if (!crtc_state->active)
359 return 0;
360
361 vc4_hdmi = connector_to_vc4_hdmi(connector);
362 mutex_lock(&vc4_hdmi->mutex);
363
364 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) {
365 mutex_unlock(&vc4_hdmi->mutex);
366 return 0;
367 }
368
369 scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode,
370 vc4_hdmi->output_bpc,
371 vc4_hdmi->output_format);
372 if (!scrambling_needed) {
373 mutex_unlock(&vc4_hdmi->mutex);
374 return 0;
375 }
376
377 if (conn_state->commit &&
378 !try_wait_for_completion(&conn_state->commit->hw_done)) {
379 mutex_unlock(&vc4_hdmi->mutex);
380 return 0;
381 }
382
383 ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);
384 if (ret < 0) {
385 drm_err(drm, "Failed to read TMDS config: %d\n", ret);
386 mutex_unlock(&vc4_hdmi->mutex);
387 return 0;
388 }
389
390 if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) {
391 mutex_unlock(&vc4_hdmi->mutex);
392 return 0;
393 }
394
395 mutex_unlock(&vc4_hdmi->mutex);
396
397 /*
398 * HDMI 2.0 says that one should not send scrambled data
399 * prior to configuring the sink scrambling, and that
400 * TMDS clock/data transmission should be suspended when
401 * changing the TMDS clock rate in the sink. So let's
402 * just do a full modeset here, even though some sinks
403 * would be perfectly happy if were to just reconfigure
404 * the SCDC settings on the fly.
405 */
406 return reset_pipe(crtc, ctx);
407}
408
409static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi,
410 struct drm_modeset_acquire_ctx *ctx,
411 enum drm_connector_status status)
412{
413 struct drm_connector *connector = &vc4_hdmi->connector;
414 struct edid *edid;
415 int ret;
416
417 /*
418 * NOTE: This function should really be called with
419 * vc4_hdmi->mutex held, but doing so results in reentrancy
420 * issues since cec_s_phys_addr_from_edid might call
421 * .adap_enable, which leads to that funtion being called with
422 * our mutex held.
423 *
424 * A similar situation occurs with vc4_hdmi_reset_link() that
425 * will call into our KMS hooks if the scrambling was enabled.
426 *
427 * Concurrency isn't an issue at the moment since we don't share
428 * any state with any of the other frameworks so we can ignore
429 * the lock for now.
430 */
431
432 if (status == connector_status_disconnected) {
433 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
434 return;
435 }
436
437 edid = drm_get_edid(connector, vc4_hdmi->ddc);
438 if (!edid)
439 return;
440
441 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
442 kfree(edid);
443
444 for (;;) {
445 ret = vc4_hdmi_reset_link(connector, ctx);
446 if (ret == -EDEADLK) {
447 drm_modeset_backoff(ctx);
448 continue;
449 }
450
451 break;
452 }
453}
454
455static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector,
456 struct drm_modeset_acquire_ctx *ctx,
457 bool force)
458{
459 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
460 enum drm_connector_status status = connector_status_disconnected;
461
462 /*
463 * NOTE: This function should really take vc4_hdmi->mutex, but
464 * doing so results in reentrancy issues since
465 * vc4_hdmi_handle_hotplug() can call into other functions that
466 * would take the mutex while it's held here.
467 *
468 * Concurrency isn't an issue at the moment since we don't share
469 * any state with any of the other frameworks so we can ignore
470 * the lock for now.
471 */
472
473 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
474
475 if (vc4_hdmi->hpd_gpio) {
476 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
477 status = connector_status_connected;
478 } else {
479 if (vc4_hdmi->variant->hp_detect &&
480 vc4_hdmi->variant->hp_detect(vc4_hdmi))
481 status = connector_status_connected;
482 }
483
484 vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status);
485 pm_runtime_put(&vc4_hdmi->pdev->dev);
486
487 return status;
488}
489
490static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
491{
492 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
493 struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
494 int ret = 0;
495 struct edid *edid;
496
497 /*
498 * NOTE: This function should really take vc4_hdmi->mutex, but
499 * doing so results in reentrancy issues since
500 * cec_s_phys_addr_from_edid might call .adap_enable, which
501 * leads to that funtion being called with our mutex held.
502 *
503 * Concurrency isn't an issue at the moment since we don't share
504 * any state with any of the other frameworks so we can ignore
505 * the lock for now.
506 */
507
508 edid = drm_get_edid(connector, vc4_hdmi->ddc);
509 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
510 if (!edid)
511 return -ENODEV;
512
513 drm_connector_update_edid_property(connector, edid);
514 ret = drm_add_edid_modes(connector, edid);
515 kfree(edid);
516
517 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) {
518 struct drm_device *drm = connector->dev;
519 const struct drm_display_mode *mode;
520
521 list_for_each_entry(mode, &connector->probed_modes, head) {
522 if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) {
523 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
524 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
525 }
526 }
527 }
528
529 return ret;
530}
531
532static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
533 struct drm_atomic_state *state)
534{
535 struct drm_connector_state *old_state =
536 drm_atomic_get_old_connector_state(state, connector);
537 struct vc4_hdmi_connector_state *old_vc4_state =
538 conn_state_to_vc4_hdmi_conn_state(old_state);
539 struct drm_connector_state *new_state =
540 drm_atomic_get_new_connector_state(state, connector);
541 struct vc4_hdmi_connector_state *new_vc4_state =
542 conn_state_to_vc4_hdmi_conn_state(new_state);
543 struct drm_crtc *crtc = new_state->crtc;
544
545 if (!crtc)
546 return 0;
547
548 if (old_state->tv.margins.left != new_state->tv.margins.left ||
549 old_state->tv.margins.right != new_state->tv.margins.right ||
550 old_state->tv.margins.top != new_state->tv.margins.top ||
551 old_state->tv.margins.bottom != new_state->tv.margins.bottom) {
552 struct drm_crtc_state *crtc_state;
553 int ret;
554
555 crtc_state = drm_atomic_get_crtc_state(state, crtc);
556 if (IS_ERR(crtc_state))
557 return PTR_ERR(crtc_state);
558
559 /*
560 * Strictly speaking, we should be calling
561 * drm_atomic_helper_check_planes() after our call to
562 * drm_atomic_add_affected_planes(). However, the
563 * connector atomic_check is called as part of
564 * drm_atomic_helper_check_modeset() that already
565 * happens before a call to
566 * drm_atomic_helper_check_planes() in
567 * drm_atomic_helper_check().
568 */
569 ret = drm_atomic_add_affected_planes(state, crtc);
570 if (ret)
571 return ret;
572 }
573
574 if (old_state->colorspace != new_state->colorspace ||
575 old_vc4_state->broadcast_rgb != new_vc4_state->broadcast_rgb ||
576 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
577 struct drm_crtc_state *crtc_state;
578
579 crtc_state = drm_atomic_get_crtc_state(state, crtc);
580 if (IS_ERR(crtc_state))
581 return PTR_ERR(crtc_state);
582
583 crtc_state->mode_changed = true;
584 }
585
586 return 0;
587}
588
589static int vc4_hdmi_connector_get_property(struct drm_connector *connector,
590 const struct drm_connector_state *state,
591 struct drm_property *property,
592 uint64_t *val)
593{
594 struct drm_device *drm = connector->dev;
595 struct vc4_hdmi *vc4_hdmi =
596 connector_to_vc4_hdmi(connector);
597 const struct vc4_hdmi_connector_state *vc4_conn_state =
598 conn_state_to_vc4_hdmi_conn_state(state);
599
600 if (property == vc4_hdmi->broadcast_rgb_property) {
601 *val = vc4_conn_state->broadcast_rgb;
602 } else {
603 drm_dbg(drm, "Unknown property [PROP:%d:%s]\n",
604 property->base.id, property->name);
605 return -EINVAL;
606 }
607
608 return 0;
609}
610
611static int vc4_hdmi_connector_set_property(struct drm_connector *connector,
612 struct drm_connector_state *state,
613 struct drm_property *property,
614 uint64_t val)
615{
616 struct drm_device *drm = connector->dev;
617 struct vc4_hdmi *vc4_hdmi =
618 connector_to_vc4_hdmi(connector);
619 struct vc4_hdmi_connector_state *vc4_conn_state =
620 conn_state_to_vc4_hdmi_conn_state(state);
621
622 if (property == vc4_hdmi->broadcast_rgb_property) {
623 vc4_conn_state->broadcast_rgb = val;
624 return 0;
625 }
626
627 drm_dbg(drm, "Unknown property [PROP:%d:%s]\n",
628 property->base.id, property->name);
629 return -EINVAL;
630}
631
632static void vc4_hdmi_connector_reset(struct drm_connector *connector)
633{
634 struct vc4_hdmi_connector_state *old_state =
635 conn_state_to_vc4_hdmi_conn_state(connector->state);
636 struct vc4_hdmi_connector_state *new_state =
637 kzalloc(sizeof(*new_state), GFP_KERNEL);
638
639 if (connector->state)
640 __drm_atomic_helper_connector_destroy_state(connector->state);
641
642 kfree(old_state);
643 __drm_atomic_helper_connector_reset(connector, &new_state->base);
644
645 if (!new_state)
646 return;
647
648 new_state->base.max_bpc = 8;
649 new_state->base.max_requested_bpc = 8;
650 new_state->output_format = VC4_HDMI_OUTPUT_RGB;
651 new_state->broadcast_rgb = VC4_HDMI_BROADCAST_RGB_AUTO;
652 drm_atomic_helper_connector_tv_margins_reset(connector);
653}
654
655static struct drm_connector_state *
656vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
657{
658 struct drm_connector_state *conn_state = connector->state;
659 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
660 struct vc4_hdmi_connector_state *new_state;
661
662 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
663 if (!new_state)
664 return NULL;
665
666 new_state->tmds_char_rate = vc4_state->tmds_char_rate;
667 new_state->output_bpc = vc4_state->output_bpc;
668 new_state->output_format = vc4_state->output_format;
669 new_state->broadcast_rgb = vc4_state->broadcast_rgb;
670 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
671
672 return &new_state->base;
673}
674
675static void vc4_hdmi_connector_destroy_state(struct drm_connector *connector,
676 struct drm_connector_state *state)
677{
678 struct vc4_hdmi_connector_state *vc4_state =
679 conn_state_to_vc4_hdmi_conn_state(state);
680
681 __drm_atomic_helper_connector_destroy_state(state);
682 kfree(vc4_state);
683}
684
685static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
686 .fill_modes = drm_helper_probe_single_connector_modes,
687 .reset = vc4_hdmi_connector_reset,
688 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
689 .atomic_destroy_state = vc4_hdmi_connector_destroy_state,
690 .atomic_get_property = vc4_hdmi_connector_get_property,
691 .atomic_set_property = vc4_hdmi_connector_set_property,
692};
693
694static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
695 .detect_ctx = vc4_hdmi_connector_detect_ctx,
696 .get_modes = vc4_hdmi_connector_get_modes,
697 .atomic_check = vc4_hdmi_connector_atomic_check,
698};
699
700static const struct drm_prop_enum_list broadcast_rgb_names[] = {
701 { VC4_HDMI_BROADCAST_RGB_AUTO, "Automatic" },
702 { VC4_HDMI_BROADCAST_RGB_FULL, "Full" },
703 { VC4_HDMI_BROADCAST_RGB_LIMITED, "Limited 16:235" },
704};
705
706static void
707vc4_hdmi_attach_broadcast_rgb_property(struct drm_device *dev,
708 struct vc4_hdmi *vc4_hdmi)
709{
710 struct drm_property *prop = vc4_hdmi->broadcast_rgb_property;
711
712 if (!prop) {
713 prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,
714 "Broadcast RGB",
715 broadcast_rgb_names,
716 ARRAY_SIZE(broadcast_rgb_names));
717 if (!prop)
718 return;
719
720 vc4_hdmi->broadcast_rgb_property = prop;
721 }
722
723 drm_object_attach_property(&vc4_hdmi->connector.base, prop,
724 VC4_HDMI_BROADCAST_RGB_AUTO);
725}
726
727static int vc4_hdmi_connector_init(struct drm_device *dev,
728 struct vc4_hdmi *vc4_hdmi)
729{
730 struct drm_connector *connector = &vc4_hdmi->connector;
731 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
732 int ret;
733
734 ret = drmm_connector_init(dev, connector,
735 &vc4_hdmi_connector_funcs,
736 DRM_MODE_CONNECTOR_HDMIA,
737 vc4_hdmi->ddc);
738 if (ret)
739 return ret;
740
741 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
742
743 /*
744 * Some of the properties below require access to state, like bpc.
745 * Allocate some default initial connector state with our reset helper.
746 */
747 if (connector->funcs->reset)
748 connector->funcs->reset(connector);
749
750 /* Create and attach TV margin props to this connector. */
751 ret = drm_mode_create_tv_margin_properties(dev);
752 if (ret)
753 return ret;
754
755 ret = drm_mode_create_hdmi_colorspace_property(connector, 0);
756 if (ret)
757 return ret;
758
759 drm_connector_attach_colorspace_property(connector);
760 drm_connector_attach_tv_margin_properties(connector);
761 drm_connector_attach_max_bpc_property(connector, 8, 12);
762
763 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
764 DRM_CONNECTOR_POLL_DISCONNECT);
765
766 connector->interlace_allowed = 1;
767 connector->doublescan_allowed = 0;
768 connector->stereo_allowed = 1;
769
770 if (vc4_hdmi->variant->supports_hdr)
771 drm_connector_attach_hdr_output_metadata_property(connector);
772
773 vc4_hdmi_attach_broadcast_rgb_property(dev, vc4_hdmi);
774
775 drm_connector_attach_encoder(connector, encoder);
776
777 return 0;
778}
779
780static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
781 enum hdmi_infoframe_type type,
782 bool poll)
783{
784 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
785 struct drm_device *drm = vc4_hdmi->connector.dev;
786 u32 packet_id = type - 0x80;
787 unsigned long flags;
788 int ret = 0;
789 int idx;
790
791 if (!drm_dev_enter(drm, &idx))
792 return -ENODEV;
793
794 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
795 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
796 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
797 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
798
799 if (poll) {
800 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
801 BIT(packet_id)), 100);
802 }
803
804 drm_dev_exit(idx);
805 return ret;
806}
807
808static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
809 union hdmi_infoframe *frame)
810{
811 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
812 struct drm_device *drm = vc4_hdmi->connector.dev;
813 u32 packet_id = frame->any.type - 0x80;
814 const struct vc4_hdmi_register *ram_packet_start =
815 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
816 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
817 u32 packet_reg_next = ram_packet_start->offset +
818 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
819 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
820 ram_packet_start->reg);
821 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
822 unsigned long flags;
823 ssize_t len, i;
824 int ret;
825 int idx;
826
827 if (!drm_dev_enter(drm, &idx))
828 return;
829
830 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
831 VC4_HDMI_RAM_PACKET_ENABLE),
832 "Packet RAM has to be on to store the packet.");
833
834 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
835 if (len < 0)
836 goto out;
837
838 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
839 if (ret) {
840 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
841 goto out;
842 }
843
844 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
845
846 for (i = 0; i < len; i += 7) {
847 writel(buffer[i + 0] << 0 |
848 buffer[i + 1] << 8 |
849 buffer[i + 2] << 16,
850 base + packet_reg);
851 packet_reg += 4;
852
853 writel(buffer[i + 3] << 0 |
854 buffer[i + 4] << 8 |
855 buffer[i + 5] << 16 |
856 buffer[i + 6] << 24,
857 base + packet_reg);
858 packet_reg += 4;
859 }
860
861 /*
862 * clear remainder of packet ram as it's included in the
863 * infoframe and triggers a checksum error on hdmi analyser
864 */
865 for (; packet_reg < packet_reg_next; packet_reg += 4)
866 writel(0, base + packet_reg);
867
868 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
869 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
870
871 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
872
873 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
874 BIT(packet_id)), 100);
875 if (ret)
876 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
877
878out:
879 drm_dev_exit(idx);
880}
881
882static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
883 enum vc4_hdmi_output_format fmt)
884{
885 switch (fmt) {
886 case VC4_HDMI_OUTPUT_RGB:
887 frame->colorspace = HDMI_COLORSPACE_RGB;
888 break;
889
890 case VC4_HDMI_OUTPUT_YUV420:
891 frame->colorspace = HDMI_COLORSPACE_YUV420;
892 break;
893
894 case VC4_HDMI_OUTPUT_YUV422:
895 frame->colorspace = HDMI_COLORSPACE_YUV422;
896 break;
897
898 case VC4_HDMI_OUTPUT_YUV444:
899 frame->colorspace = HDMI_COLORSPACE_YUV444;
900 break;
901
902 default:
903 break;
904 }
905}
906
907static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
908{
909 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
910 struct drm_connector *connector = &vc4_hdmi->connector;
911 struct drm_connector_state *cstate = connector->state;
912 struct vc4_hdmi_connector_state *vc4_state =
913 conn_state_to_vc4_hdmi_conn_state(cstate);
914 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
915 union hdmi_infoframe frame;
916 int ret;
917
918 lockdep_assert_held(&vc4_hdmi->mutex);
919
920 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
921 connector, mode);
922 if (ret < 0) {
923 DRM_ERROR("couldn't fill AVI infoframe\n");
924 return;
925 }
926
927 drm_hdmi_avi_infoframe_quant_range(&frame.avi,
928 connector, mode,
929 vc4_hdmi_is_full_range(vc4_hdmi, vc4_state) ?
930 HDMI_QUANTIZATION_RANGE_FULL :
931 HDMI_QUANTIZATION_RANGE_LIMITED);
932 drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate);
933 vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format);
934 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
935
936 vc4_hdmi_write_infoframe(encoder, &frame);
937}
938
939static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
940{
941 union hdmi_infoframe frame;
942 int ret;
943
944 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
945 if (ret < 0) {
946 DRM_ERROR("couldn't fill SPD infoframe\n");
947 return;
948 }
949
950 frame.spd.sdi = HDMI_SPD_SDI_PC;
951
952 vc4_hdmi_write_infoframe(encoder, &frame);
953}
954
955static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
956{
957 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
958 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
959 union hdmi_infoframe frame;
960
961 memcpy(&frame.audio, audio, sizeof(*audio));
962
963 if (vc4_hdmi->packet_ram_enabled)
964 vc4_hdmi_write_infoframe(encoder, &frame);
965}
966
967static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
968{
969 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
970 struct drm_connector *connector = &vc4_hdmi->connector;
971 struct drm_connector_state *conn_state = connector->state;
972 union hdmi_infoframe frame;
973
974 lockdep_assert_held(&vc4_hdmi->mutex);
975
976 if (!vc4_hdmi->variant->supports_hdr)
977 return;
978
979 if (!conn_state->hdr_output_metadata)
980 return;
981
982 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
983 return;
984
985 vc4_hdmi_write_infoframe(encoder, &frame);
986}
987
988static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
989{
990 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
991
992 lockdep_assert_held(&vc4_hdmi->mutex);
993
994 vc4_hdmi_set_avi_infoframe(encoder);
995 vc4_hdmi_set_spd_infoframe(encoder);
996 /*
997 * If audio was streaming, then we need to reenabled the audio
998 * infoframe here during encoder_enable.
999 */
1000 if (vc4_hdmi->audio.streaming)
1001 vc4_hdmi_set_audio_infoframe(encoder);
1002
1003 vc4_hdmi_set_hdr_infoframe(encoder);
1004}
1005
1006#define SCRAMBLING_POLLING_DELAY_MS 1000
1007
1008static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
1009{
1010 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1011 struct drm_connector *connector = &vc4_hdmi->connector;
1012 struct drm_device *drm = connector->dev;
1013 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1014 unsigned long flags;
1015 int idx;
1016
1017 lockdep_assert_held(&vc4_hdmi->mutex);
1018
1019 if (!vc4_hdmi_supports_scrambling(vc4_hdmi))
1020 return;
1021
1022 if (!vc4_hdmi_mode_needs_scrambling(mode,
1023 vc4_hdmi->output_bpc,
1024 vc4_hdmi->output_format))
1025 return;
1026
1027 if (!drm_dev_enter(drm, &idx))
1028 return;
1029
1030 drm_scdc_set_high_tmds_clock_ratio(connector, true);
1031 drm_scdc_set_scrambling(connector, true);
1032
1033 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1034 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
1035 VC5_HDMI_SCRAMBLER_CTL_ENABLE);
1036 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1037
1038 drm_dev_exit(idx);
1039
1040 vc4_hdmi->scdc_enabled = true;
1041
1042 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
1043 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
1044}
1045
1046static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
1047{
1048 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1049 struct drm_connector *connector = &vc4_hdmi->connector;
1050 struct drm_device *drm = connector->dev;
1051 unsigned long flags;
1052 int idx;
1053
1054 lockdep_assert_held(&vc4_hdmi->mutex);
1055
1056 if (!vc4_hdmi->scdc_enabled)
1057 return;
1058
1059 vc4_hdmi->scdc_enabled = false;
1060
1061 if (delayed_work_pending(&vc4_hdmi->scrambling_work))
1062 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
1063
1064 if (!drm_dev_enter(drm, &idx))
1065 return;
1066
1067 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1068 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
1069 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
1070 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1071
1072 drm_scdc_set_scrambling(connector, false);
1073 drm_scdc_set_high_tmds_clock_ratio(connector, false);
1074
1075 drm_dev_exit(idx);
1076}
1077
1078static void vc4_hdmi_scrambling_wq(struct work_struct *work)
1079{
1080 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
1081 struct vc4_hdmi,
1082 scrambling_work);
1083 struct drm_connector *connector = &vc4_hdmi->connector;
1084
1085 if (drm_scdc_get_scrambling_status(connector))
1086 return;
1087
1088 drm_scdc_set_high_tmds_clock_ratio(connector, true);
1089 drm_scdc_set_scrambling(connector, true);
1090
1091 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
1092 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
1093}
1094
1095static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
1096 struct drm_atomic_state *state)
1097{
1098 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1099 struct drm_device *drm = vc4_hdmi->connector.dev;
1100 unsigned long flags;
1101 int idx;
1102
1103 mutex_lock(&vc4_hdmi->mutex);
1104
1105 vc4_hdmi->packet_ram_enabled = false;
1106
1107 if (!drm_dev_enter(drm, &idx))
1108 goto out;
1109
1110 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1111
1112 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
1113
1114 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
1115
1116 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1117
1118 mdelay(1);
1119
1120 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1121 HDMI_WRITE(HDMI_VID_CTL,
1122 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
1123 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1124
1125 vc4_hdmi_disable_scrambling(encoder);
1126
1127 drm_dev_exit(idx);
1128
1129out:
1130 mutex_unlock(&vc4_hdmi->mutex);
1131}
1132
1133static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
1134 struct drm_atomic_state *state)
1135{
1136 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1137 struct drm_device *drm = vc4_hdmi->connector.dev;
1138 unsigned long flags;
1139 int ret;
1140 int idx;
1141
1142 mutex_lock(&vc4_hdmi->mutex);
1143
1144 if (!drm_dev_enter(drm, &idx))
1145 goto out;
1146
1147 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1148 HDMI_WRITE(HDMI_VID_CTL,
1149 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
1150 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1151
1152 if (vc4_hdmi->variant->phy_disable)
1153 vc4_hdmi->variant->phy_disable(vc4_hdmi);
1154
1155 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
1156 clk_disable_unprepare(vc4_hdmi->pixel_clock);
1157
1158 ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
1159 if (ret < 0)
1160 DRM_ERROR("Failed to release power domain: %d\n", ret);
1161
1162 drm_dev_exit(idx);
1163
1164out:
1165 mutex_unlock(&vc4_hdmi->mutex);
1166}
1167
1168static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1169 struct drm_connector_state *state,
1170 const struct drm_display_mode *mode)
1171{
1172 struct vc4_hdmi_connector_state *vc4_state =
1173 conn_state_to_vc4_hdmi_conn_state(state);
1174 struct drm_device *drm = vc4_hdmi->connector.dev;
1175 unsigned long flags;
1176 u32 csc_ctl;
1177 int idx;
1178
1179 if (!drm_dev_enter(drm, &idx))
1180 return;
1181
1182 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1183
1184 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
1185 VC4_HD_CSC_CTL_ORDER);
1186
1187 if (!vc4_hdmi_is_full_range(vc4_hdmi, vc4_state)) {
1188 /* CEA VICs other than #1 requre limited range RGB
1189 * output unless overridden by an AVI infoframe.
1190 * Apply a colorspace conversion to squash 0-255 down
1191 * to 16-235. The matrix here is:
1192 *
1193 * [ 0 0 0.8594 16]
1194 * [ 0 0.8594 0 16]
1195 * [ 0.8594 0 0 16]
1196 * [ 0 0 0 1]
1197 */
1198 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
1199 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
1200 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1201 VC4_HD_CSC_CTL_MODE);
1202
1203 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
1204 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
1205 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
1206 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
1207 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
1208 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
1209 }
1210
1211 /* The RGB order applies even when CSC is disabled. */
1212 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1213
1214 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1215
1216 drm_dev_exit(idx);
1217}
1218
1219/*
1220 * Matrices for (internal) RGB to RGB output.
1221 *
1222 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1223 */
1224static const u16 vc5_hdmi_csc_full_rgb_to_rgb[2][3][4] = {
1225 {
1226 /*
1227 * Full range - unity
1228 *
1229 * [ 1 0 0 0]
1230 * [ 0 1 0 0]
1231 * [ 0 0 1 0]
1232 */
1233 { 0x2000, 0x0000, 0x0000, 0x0000 },
1234 { 0x0000, 0x2000, 0x0000, 0x0000 },
1235 { 0x0000, 0x0000, 0x2000, 0x0000 },
1236 },
1237 {
1238 /*
1239 * Limited range
1240 *
1241 * CEA VICs other than #1 require limited range RGB
1242 * output unless overridden by an AVI infoframe. Apply a
1243 * colorspace conversion to squash 0-255 down to 16-235.
1244 * The matrix here is:
1245 *
1246 * [ 0.8594 0 0 16]
1247 * [ 0 0.8594 0 16]
1248 * [ 0 0 0.8594 16]
1249 */
1250 { 0x1b80, 0x0000, 0x0000, 0x0400 },
1251 { 0x0000, 0x1b80, 0x0000, 0x0400 },
1252 { 0x0000, 0x0000, 0x1b80, 0x0400 },
1253 },
1254};
1255
1256/*
1257 * Conversion between Full Range RGB and YUV using the BT.601 Colorspace
1258 *
1259 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1260 */
1261static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt601[2][3][4] = {
1262 {
1263 /*
1264 * Full Range
1265 *
1266 * [ 0.299000 0.587000 0.114000 0 ]
1267 * [ -0.168736 -0.331264 0.500000 128 ]
1268 * [ 0.500000 -0.418688 -0.081312 128 ]
1269 */
1270 { 0x0991, 0x12c9, 0x03a6, 0x0000 },
1271 { 0xfa9b, 0xf567, 0x1000, 0x2000 },
1272 { 0x1000, 0xf29b, 0xfd67, 0x2000 },
1273 },
1274 {
1275 /* Limited Range
1276 *
1277 * [ 0.255785 0.502160 0.097523 16 ]
1278 * [ -0.147644 -0.289856 0.437500 128 ]
1279 * [ 0.437500 -0.366352 -0.071148 128 ]
1280 */
1281 { 0x082f, 0x1012, 0x031f, 0x0400 },
1282 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 },
1283 { 0x0e00, 0xf448, 0xfdba, 0x2000 },
1284 },
1285};
1286
1287/*
1288 * Conversion between Full Range RGB and YUV using the BT.709 Colorspace
1289 *
1290 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1291 */
1292static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt709[2][3][4] = {
1293 {
1294 /*
1295 * Full Range
1296 *
1297 * [ 0.212600 0.715200 0.072200 0 ]
1298 * [ -0.114572 -0.385428 0.500000 128 ]
1299 * [ 0.500000 -0.454153 -0.045847 128 ]
1300 */
1301 { 0x06ce, 0x16e3, 0x024f, 0x0000 },
1302 { 0xfc56, 0xf3ac, 0x1000, 0x2000 },
1303 { 0x1000, 0xf179, 0xfe89, 0x2000 },
1304 },
1305 {
1306 /*
1307 * Limited Range
1308 *
1309 * [ 0.181906 0.611804 0.061758 16 ]
1310 * [ -0.100268 -0.337232 0.437500 128 ]
1311 * [ 0.437500 -0.397386 -0.040114 128 ]
1312 */
1313 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1314 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1315 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1316 },
1317};
1318
1319/*
1320 * Conversion between Full Range RGB and YUV using the BT.2020 Colorspace
1321 *
1322 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1323 */
1324static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt2020[2][3][4] = {
1325 {
1326 /*
1327 * Full Range
1328 *
1329 * [ 0.262700 0.678000 0.059300 0 ]
1330 * [ -0.139630 -0.360370 0.500000 128 ]
1331 * [ 0.500000 -0.459786 -0.040214 128 ]
1332 */
1333 { 0x0868, 0x15b2, 0x01e6, 0x0000 },
1334 { 0xfb89, 0xf479, 0x1000, 0x2000 },
1335 { 0x1000, 0xf14a, 0xfeb8, 0x2000 },
1336 },
1337 {
1338 /* Limited Range
1339 *
1340 * [ 0.224732 0.580008 0.050729 16 ]
1341 * [ -0.122176 -0.315324 0.437500 128 ]
1342 * [ 0.437500 -0.402312 -0.035188 128 ]
1343 */
1344 { 0x082f, 0x1012, 0x031f, 0x0400 },
1345 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 },
1346 { 0x0e00, 0xf448, 0xfdba, 0x2000 },
1347 },
1348};
1349
1350static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
1351 const u16 coeffs[3][4])
1352{
1353 lockdep_assert_held(&vc4_hdmi->hw_lock);
1354
1355 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
1356 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
1357 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
1358 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
1359 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
1360 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
1361}
1362
1363static void vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi *vc4_hdmi,
1364 const u16 coeffs[3][4])
1365{
1366 lockdep_assert_held(&vc4_hdmi->hw_lock);
1367
1368 /* YUV444 needs the CSC matrices using the channels in a different order */
1369 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[1][1] << 16) | coeffs[1][0]);
1370 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[1][3] << 16) | coeffs[1][2]);
1371 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[2][1] << 16) | coeffs[2][0]);
1372 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[2][3] << 16) | coeffs[2][2]);
1373 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[0][1] << 16) | coeffs[0][0]);
1374 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[0][3] << 16) | coeffs[0][2]);
1375}
1376
1377static const u16
1378(*vc5_hdmi_find_yuv_csc_coeffs(struct vc4_hdmi *vc4_hdmi, u32 colorspace, bool limited))[4]
1379{
1380 switch (colorspace) {
1381 case DRM_MODE_COLORIMETRY_SMPTE_170M_YCC:
1382 case DRM_MODE_COLORIMETRY_XVYCC_601:
1383 case DRM_MODE_COLORIMETRY_SYCC_601:
1384 case DRM_MODE_COLORIMETRY_OPYCC_601:
1385 case DRM_MODE_COLORIMETRY_BT601_YCC:
1386 return vc5_hdmi_csc_full_rgb_to_yuv_bt601[limited];
1387
1388 default:
1389 case DRM_MODE_COLORIMETRY_NO_DATA:
1390 case DRM_MODE_COLORIMETRY_BT709_YCC:
1391 case DRM_MODE_COLORIMETRY_XVYCC_709:
1392 case DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED:
1393 case DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT:
1394 return vc5_hdmi_csc_full_rgb_to_yuv_bt709[limited];
1395
1396 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1397 case DRM_MODE_COLORIMETRY_BT2020_YCC:
1398 case DRM_MODE_COLORIMETRY_BT2020_RGB:
1399 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1400 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1401 return vc5_hdmi_csc_full_rgb_to_yuv_bt2020[limited];
1402 }
1403}
1404
1405static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1406 struct drm_connector_state *state,
1407 const struct drm_display_mode *mode)
1408{
1409 struct drm_device *drm = vc4_hdmi->connector.dev;
1410 struct vc4_hdmi_connector_state *vc4_state =
1411 conn_state_to_vc4_hdmi_conn_state(state);
1412 unsigned int lim_range = vc4_hdmi_is_full_range(vc4_hdmi, vc4_state) ? 0 : 1;
1413 unsigned long flags;
1414 const u16 (*csc)[4];
1415 u32 if_cfg = 0;
1416 u32 if_xbar = 0x543210;
1417 u32 csc_chan_ctl = 0;
1418 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1419 VC5_MT_CP_CSC_CTL_MODE);
1420 int idx;
1421
1422 if (!drm_dev_enter(drm, &idx))
1423 return;
1424
1425 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1426
1427 switch (vc4_state->output_format) {
1428 case VC4_HDMI_OUTPUT_YUV444:
1429 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range);
1430
1431 vc5_hdmi_set_csc_coeffs_swap(vc4_hdmi, csc);
1432 break;
1433
1434 case VC4_HDMI_OUTPUT_YUV422:
1435 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range);
1436
1437 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
1438 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) |
1439 VC5_MT_CP_CSC_CTL_USE_444_TO_422 |
1440 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION;
1441
1442 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
1443 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP);
1444
1445 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
1446 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422);
1447
1448 vc5_hdmi_set_csc_coeffs(vc4_hdmi, csc);
1449 break;
1450
1451 case VC4_HDMI_OUTPUT_RGB:
1452 if_xbar = 0x354021;
1453
1454 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_rgb[lim_range]);
1455 break;
1456
1457 default:
1458 break;
1459 }
1460
1461 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg);
1462 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar);
1463 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl);
1464 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1465
1466 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1467
1468 drm_dev_exit(idx);
1469}
1470
1471static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1472 struct drm_connector_state *state,
1473 const struct drm_display_mode *mode)
1474{
1475 struct drm_device *drm = vc4_hdmi->connector.dev;
1476 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1477 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1478 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1479 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1480 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1481 VC4_HDMI_VERTA_VSP) |
1482 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1483 VC4_HDMI_VERTA_VFP) |
1484 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
1485 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1486 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1487 interlaced,
1488 VC4_HDMI_VERTB_VBP));
1489 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1490 VC4_SET_FIELD(mode->crtc_vtotal -
1491 mode->crtc_vsync_end,
1492 VC4_HDMI_VERTB_VBP));
1493 unsigned long flags;
1494 u32 reg;
1495 int idx;
1496
1497 if (!drm_dev_enter(drm, &idx))
1498 return;
1499
1500 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1501
1502 HDMI_WRITE(HDMI_HORZA,
1503 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
1504 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
1505 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1506 VC4_HDMI_HORZA_HAP));
1507
1508 HDMI_WRITE(HDMI_HORZB,
1509 VC4_SET_FIELD((mode->htotal -
1510 mode->hsync_end) * pixel_rep,
1511 VC4_HDMI_HORZB_HBP) |
1512 VC4_SET_FIELD((mode->hsync_end -
1513 mode->hsync_start) * pixel_rep,
1514 VC4_HDMI_HORZB_HSP) |
1515 VC4_SET_FIELD((mode->hsync_start -
1516 mode->hdisplay) * pixel_rep,
1517 VC4_HDMI_HORZB_HFP));
1518
1519 HDMI_WRITE(HDMI_VERTA0, verta);
1520 HDMI_WRITE(HDMI_VERTA1, verta);
1521
1522 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1523 HDMI_WRITE(HDMI_VERTB1, vertb);
1524
1525 reg = HDMI_READ(HDMI_MISC_CONTROL);
1526 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1527 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP);
1528 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1529
1530 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1531
1532 drm_dev_exit(idx);
1533}
1534
1535static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1536 struct drm_connector_state *state,
1537 const struct drm_display_mode *mode)
1538{
1539 struct drm_device *drm = vc4_hdmi->connector.dev;
1540 const struct vc4_hdmi_connector_state *vc4_state =
1541 conn_state_to_vc4_hdmi_conn_state(state);
1542 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1543 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1544 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1545 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1546 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1547 VC5_HDMI_VERTA_VSP) |
1548 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1549 VC5_HDMI_VERTA_VFP) |
1550 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
1551 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
1552 VC5_HDMI_VERTB_VSPO) |
1553 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1554 interlaced,
1555 VC4_HDMI_VERTB_VBP));
1556 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
1557 VC4_SET_FIELD(mode->crtc_vtotal -
1558 mode->crtc_vsync_end,
1559 VC4_HDMI_VERTB_VBP));
1560 unsigned long flags;
1561 unsigned char gcp;
1562 u32 reg;
1563 int idx;
1564
1565 if (!drm_dev_enter(drm, &idx))
1566 return;
1567
1568 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1569
1570 HDMI_WRITE(HDMI_HORZA,
1571 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
1572 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
1573 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1574 VC5_HDMI_HORZA_HAP) |
1575 VC4_SET_FIELD((mode->hsync_start -
1576 mode->hdisplay) * pixel_rep,
1577 VC5_HDMI_HORZA_HFP));
1578
1579 HDMI_WRITE(HDMI_HORZB,
1580 VC4_SET_FIELD((mode->htotal -
1581 mode->hsync_end) * pixel_rep,
1582 VC5_HDMI_HORZB_HBP) |
1583 VC4_SET_FIELD((mode->hsync_end -
1584 mode->hsync_start) * pixel_rep,
1585 VC5_HDMI_HORZB_HSP));
1586
1587 HDMI_WRITE(HDMI_VERTA0, verta);
1588 HDMI_WRITE(HDMI_VERTA1, verta);
1589
1590 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1591 HDMI_WRITE(HDMI_VERTB1, vertb);
1592
1593 switch (vc4_state->output_bpc) {
1594 case 12:
1595 gcp = 6;
1596 break;
1597 case 10:
1598 gcp = 5;
1599 break;
1600 case 8:
1601 default:
1602 gcp = 0;
1603 break;
1604 }
1605
1606 /*
1607 * YCC422 is always 36-bit and not considered deep colour so
1608 * doesn't signal in GCP.
1609 */
1610 if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) {
1611 gcp = 0;
1612 }
1613
1614 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
1615 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
1616 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
1617 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
1618 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
1619 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
1620
1621 reg = HDMI_READ(HDMI_GCP_WORD_1);
1622 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
1623 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
1624 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK;
1625 reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE;
1626 HDMI_WRITE(HDMI_GCP_WORD_1, reg);
1627
1628 reg = HDMI_READ(HDMI_GCP_CONFIG);
1629 reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
1630 HDMI_WRITE(HDMI_GCP_CONFIG, reg);
1631
1632 reg = HDMI_READ(HDMI_MISC_CONTROL);
1633 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1634 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
1635 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1636
1637 HDMI_WRITE(HDMI_CLOCK_STOP, 0);
1638
1639 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1640
1641 drm_dev_exit(idx);
1642}
1643
1644static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
1645{
1646 struct drm_device *drm = vc4_hdmi->connector.dev;
1647 unsigned long flags;
1648 u32 drift;
1649 int ret;
1650 int idx;
1651
1652 if (!drm_dev_enter(drm, &idx))
1653 return;
1654
1655 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1656
1657 drift = HDMI_READ(HDMI_FIFO_CTL);
1658 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1659
1660 HDMI_WRITE(HDMI_FIFO_CTL,
1661 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1662 HDMI_WRITE(HDMI_FIFO_CTL,
1663 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1664
1665 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1666
1667 usleep_range(1000, 1100);
1668
1669 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1670
1671 HDMI_WRITE(HDMI_FIFO_CTL,
1672 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1673 HDMI_WRITE(HDMI_FIFO_CTL,
1674 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1675
1676 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1677
1678 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1679 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1680 WARN_ONCE(ret, "Timeout waiting for "
1681 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1682
1683 drm_dev_exit(idx);
1684}
1685
1686static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1687 struct drm_atomic_state *state)
1688{
1689 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1690 struct drm_device *drm = vc4_hdmi->connector.dev;
1691 struct drm_connector *connector = &vc4_hdmi->connector;
1692 struct drm_connector_state *conn_state =
1693 drm_atomic_get_new_connector_state(state, connector);
1694 struct vc4_hdmi_connector_state *vc4_conn_state =
1695 conn_state_to_vc4_hdmi_conn_state(conn_state);
1696 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1697 unsigned long tmds_char_rate = vc4_conn_state->tmds_char_rate;
1698 unsigned long bvb_rate, hsm_rate;
1699 unsigned long flags;
1700 int ret;
1701 int idx;
1702
1703 mutex_lock(&vc4_hdmi->mutex);
1704
1705 if (!drm_dev_enter(drm, &idx))
1706 goto out;
1707
1708 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1709 if (ret < 0) {
1710 DRM_ERROR("Failed to retain power domain: %d\n", ret);
1711 goto err_dev_exit;
1712 }
1713
1714 /*
1715 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1716 * be faster than pixel clock, infinitesimally faster, tested in
1717 * simulation. Otherwise, exact value is unimportant for HDMI
1718 * operation." This conflicts with bcm2835's vc4 documentation, which
1719 * states HSM's clock has to be at least 108% of the pixel clock.
1720 *
1721 * Real life tests reveal that vc4's firmware statement holds up, and
1722 * users are able to use pixel clocks closer to HSM's, namely for
1723 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1724 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1725 * 162MHz.
1726 *
1727 * Additionally, the AXI clock needs to be at least 25% of
1728 * pixel clock, but HSM ends up being the limiting factor.
1729 */
1730 hsm_rate = max_t(unsigned long,
1731 HSM_MIN_CLOCK_FREQ,
1732 (tmds_char_rate / 100) * 101);
1733 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1734 if (ret) {
1735 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1736 goto err_put_runtime_pm;
1737 }
1738
1739 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate);
1740 if (ret) {
1741 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1742 goto err_put_runtime_pm;
1743 }
1744
1745 ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1746 if (ret) {
1747 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1748 goto err_put_runtime_pm;
1749 }
1750
1751
1752 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1753
1754 if (tmds_char_rate > 297000000)
1755 bvb_rate = 300000000;
1756 else if (tmds_char_rate > 148500000)
1757 bvb_rate = 150000000;
1758 else
1759 bvb_rate = 75000000;
1760
1761 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1762 if (ret) {
1763 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1764 goto err_disable_pixel_clock;
1765 }
1766
1767 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1768 if (ret) {
1769 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1770 goto err_disable_pixel_clock;
1771 }
1772
1773 if (vc4_hdmi->variant->phy_init)
1774 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
1775
1776 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1777
1778 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1779 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1780 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1781 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1782
1783 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1784
1785 if (vc4_hdmi->variant->set_timings)
1786 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1787
1788 drm_dev_exit(idx);
1789
1790 mutex_unlock(&vc4_hdmi->mutex);
1791
1792 return;
1793
1794err_disable_pixel_clock:
1795 clk_disable_unprepare(vc4_hdmi->pixel_clock);
1796err_put_runtime_pm:
1797 pm_runtime_put(&vc4_hdmi->pdev->dev);
1798err_dev_exit:
1799 drm_dev_exit(idx);
1800out:
1801 mutex_unlock(&vc4_hdmi->mutex);
1802 return;
1803}
1804
1805static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1806 struct drm_atomic_state *state)
1807{
1808 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1809 struct drm_device *drm = vc4_hdmi->connector.dev;
1810 struct drm_connector *connector = &vc4_hdmi->connector;
1811 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1812 struct drm_connector_state *conn_state =
1813 drm_atomic_get_new_connector_state(state, connector);
1814 unsigned long flags;
1815 int idx;
1816
1817 mutex_lock(&vc4_hdmi->mutex);
1818
1819 if (!drm_dev_enter(drm, &idx))
1820 goto out;
1821
1822 if (vc4_hdmi->variant->csc_setup)
1823 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1824
1825 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1826 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1827 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1828
1829 drm_dev_exit(idx);
1830
1831out:
1832 mutex_unlock(&vc4_hdmi->mutex);
1833}
1834
1835static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1836 struct drm_atomic_state *state)
1837{
1838 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1839 struct drm_device *drm = vc4_hdmi->connector.dev;
1840 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1841 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1842 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1843 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1844 unsigned long flags;
1845 int ret;
1846 int idx;
1847
1848 mutex_lock(&vc4_hdmi->mutex);
1849
1850 if (!drm_dev_enter(drm, &idx))
1851 goto out;
1852
1853 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1854
1855 HDMI_WRITE(HDMI_VID_CTL,
1856 VC4_HD_VID_CTL_ENABLE |
1857 VC4_HD_VID_CTL_CLRRGB |
1858 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1859 VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1860 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1861 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1862
1863 HDMI_WRITE(HDMI_VID_CTL,
1864 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1865
1866 if (display->is_hdmi) {
1867 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1868 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1869 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1870
1871 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1872
1873 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1874 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1875 WARN_ONCE(ret, "Timeout waiting for "
1876 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1877 } else {
1878 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1879 HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1880 ~(VC4_HDMI_RAM_PACKET_ENABLE));
1881 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1882 HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1883 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1884
1885 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1886
1887 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1888 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1889 WARN_ONCE(ret, "Timeout waiting for "
1890 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1891 }
1892
1893 if (display->is_hdmi) {
1894 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1895
1896 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1897 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1898
1899 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1900 VC4_HDMI_RAM_PACKET_ENABLE);
1901
1902 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1903 vc4_hdmi->packet_ram_enabled = true;
1904
1905 vc4_hdmi_set_infoframes(encoder);
1906 }
1907
1908 vc4_hdmi_recenter_fifo(vc4_hdmi);
1909 vc4_hdmi_enable_scrambling(encoder);
1910
1911 drm_dev_exit(idx);
1912
1913out:
1914 mutex_unlock(&vc4_hdmi->mutex);
1915}
1916
1917static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1918 struct drm_crtc_state *crtc_state,
1919 struct drm_connector_state *conn_state)
1920{
1921 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1922 struct vc4_hdmi_connector_state *vc4_state =
1923 conn_state_to_vc4_hdmi_conn_state(conn_state);
1924
1925 mutex_lock(&vc4_hdmi->mutex);
1926 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode,
1927 &crtc_state->adjusted_mode);
1928 vc4_hdmi->output_bpc = vc4_state->output_bpc;
1929 vc4_hdmi->output_format = vc4_state->output_format;
1930 mutex_unlock(&vc4_hdmi->mutex);
1931}
1932
1933static bool
1934vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi,
1935 const struct drm_display_info *info,
1936 const struct drm_display_mode *mode,
1937 unsigned int format, unsigned int bpc)
1938{
1939 struct drm_device *dev = vc4_hdmi->connector.dev;
1940 u8 vic = drm_match_cea_mode(mode);
1941
1942 if (vic == 1 && bpc != 8) {
1943 drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc);
1944 return false;
1945 }
1946
1947 if (!info->is_hdmi &&
1948 (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) {
1949 drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n");
1950 return false;
1951 }
1952
1953 switch (format) {
1954 case VC4_HDMI_OUTPUT_RGB:
1955 drm_dbg(dev, "RGB Format, checking the constraints.\n");
1956
1957 if (!(info->color_formats & DRM_COLOR_FORMAT_RGB444))
1958 return false;
1959
1960 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1961 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1962 return false;
1963 }
1964
1965 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1966 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1967 return false;
1968 }
1969
1970 drm_dbg(dev, "RGB format supported in that configuration.\n");
1971
1972 return true;
1973
1974 case VC4_HDMI_OUTPUT_YUV422:
1975 drm_dbg(dev, "YUV422 format, checking the constraints.\n");
1976
1977 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) {
1978 drm_dbg(dev, "Sink doesn't support YUV422.\n");
1979 return false;
1980 }
1981
1982 if (bpc != 12) {
1983 drm_dbg(dev, "YUV422 only supports 12 bpc.\n");
1984 return false;
1985 }
1986
1987 drm_dbg(dev, "YUV422 format supported in that configuration.\n");
1988
1989 return true;
1990
1991 case VC4_HDMI_OUTPUT_YUV444:
1992 drm_dbg(dev, "YUV444 format, checking the constraints.\n");
1993
1994 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR444)) {
1995 drm_dbg(dev, "Sink doesn't support YUV444.\n");
1996 return false;
1997 }
1998
1999 if (bpc == 10 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_30)) {
2000 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
2001 return false;
2002 }
2003
2004 if (bpc == 12 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_36)) {
2005 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
2006 return false;
2007 }
2008
2009 drm_dbg(dev, "YUV444 format supported in that configuration.\n");
2010
2011 return true;
2012 }
2013
2014 return false;
2015}
2016
2017static enum drm_mode_status
2018vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi,
2019 const struct drm_display_mode *mode,
2020 unsigned long long clock)
2021{
2022 const struct drm_connector *connector = &vc4_hdmi->connector;
2023 const struct drm_display_info *info = &connector->display_info;
2024 struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
2025
2026 if (clock > vc4_hdmi->variant->max_pixel_clock)
2027 return MODE_CLOCK_HIGH;
2028
2029 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK)
2030 return MODE_CLOCK_HIGH;
2031
2032 /* 4096x2160@60 is not reliable without overclocking core */
2033 if (!vc4->hvs->vc5_hdmi_enable_4096by2160 &&
2034 mode->hdisplay > 3840 && mode->vdisplay >= 2160 &&
2035 drm_mode_vrefresh(mode) >= 50)
2036 return MODE_CLOCK_HIGH;
2037
2038 if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000))
2039 return MODE_CLOCK_HIGH;
2040
2041 return MODE_OK;
2042}
2043
2044static unsigned long long
2045vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
2046 unsigned int bpc,
2047 enum vc4_hdmi_output_format fmt)
2048{
2049 unsigned long long clock = mode->clock * 1000ULL;
2050
2051 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2052 clock = clock * 2;
2053
2054 if (fmt == VC4_HDMI_OUTPUT_YUV422)
2055 bpc = 8;
2056
2057 clock = clock * bpc;
2058 do_div(clock, 8);
2059
2060 return clock;
2061}
2062
2063static int
2064vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi,
2065 struct vc4_hdmi_connector_state *vc4_state,
2066 const struct drm_display_mode *mode,
2067 unsigned int bpc, unsigned int fmt)
2068{
2069 unsigned long long clock;
2070
2071 clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
2072 if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, clock) != MODE_OK)
2073 return -EINVAL;
2074
2075 vc4_state->tmds_char_rate = clock;
2076
2077 return 0;
2078}
2079
2080static int
2081vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi,
2082 struct vc4_hdmi_connector_state *vc4_state,
2083 const struct drm_display_mode *mode,
2084 unsigned int bpc)
2085{
2086 struct drm_device *dev = vc4_hdmi->connector.dev;
2087 const struct drm_connector *connector = &vc4_hdmi->connector;
2088 const struct drm_display_info *info = &connector->display_info;
2089 unsigned int format;
2090
2091 drm_dbg(dev, "Trying with an RGB output\n");
2092
2093 format = VC4_HDMI_OUTPUT_RGB;
2094 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
2095 int ret;
2096
2097 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
2098 mode, bpc, format);
2099 if (!ret) {
2100 vc4_state->output_format = format;
2101 return 0;
2102 }
2103 }
2104
2105 drm_dbg(dev, "Failed, Trying with an YUV422 output\n");
2106
2107 format = VC4_HDMI_OUTPUT_YUV422;
2108 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
2109 int ret;
2110
2111 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
2112 mode, bpc, format);
2113 if (!ret) {
2114 vc4_state->output_format = format;
2115 return 0;
2116 }
2117 }
2118
2119 drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n");
2120
2121 return -EINVAL;
2122}
2123
2124static int
2125vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi,
2126 struct vc4_hdmi_connector_state *vc4_state,
2127 const struct drm_display_mode *mode)
2128{
2129 struct drm_device *dev = vc4_hdmi->connector.dev;
2130 struct drm_connector_state *conn_state = &vc4_state->base;
2131 unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12);
2132 unsigned int bpc;
2133 int ret;
2134
2135 for (bpc = max_bpc; bpc >= 8; bpc -= 2) {
2136 drm_dbg(dev, "Trying with a %d bpc output\n", bpc);
2137
2138 ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state,
2139 mode, bpc);
2140 if (ret)
2141 continue;
2142
2143 vc4_state->output_bpc = bpc;
2144
2145 drm_dbg(dev,
2146 "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n",
2147 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
2148 vc4_state->output_bpc,
2149 vc4_hdmi_output_fmt_str(vc4_state->output_format),
2150 vc4_state->tmds_char_rate);
2151
2152 break;
2153 }
2154
2155 return ret;
2156}
2157
2158#define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
2159#define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
2160
2161static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
2162 struct drm_crtc_state *crtc_state,
2163 struct drm_connector_state *conn_state)
2164{
2165 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
2166 struct drm_connector *connector = &vc4_hdmi->connector;
2167 struct drm_connector_state *old_conn_state =
2168 drm_atomic_get_old_connector_state(conn_state->state, connector);
2169 struct vc4_hdmi_connector_state *old_vc4_state =
2170 conn_state_to_vc4_hdmi_conn_state(old_conn_state);
2171 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
2172 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
2173 unsigned long long tmds_char_rate = mode->clock * 1000;
2174 unsigned long long tmds_bit_rate;
2175 int ret;
2176
2177 if (vc4_hdmi->variant->unsupported_odd_h_timings) {
2178 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
2179 /* Only try to fixup DBLCLK modes to get 480i and 576i
2180 * working.
2181 * A generic solution for all modes with odd horizontal
2182 * timing values seems impossible based on trying to
2183 * solve it for 1366x768 monitors.
2184 */
2185 if ((mode->hsync_start - mode->hdisplay) & 1)
2186 mode->hsync_start--;
2187 if ((mode->hsync_end - mode->hsync_start) & 1)
2188 mode->hsync_end--;
2189 }
2190
2191 /* Now check whether we still have odd values remaining */
2192 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
2193 (mode->hsync_end % 2) || (mode->htotal % 2))
2194 return -EINVAL;
2195 }
2196
2197 /*
2198 * The 1440p@60 pixel rate is in the same range than the first
2199 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
2200 * bandwidth). Slightly lower the frequency to bring it out of
2201 * the WiFi range.
2202 */
2203 tmds_bit_rate = tmds_char_rate * 10;
2204 if (vc4_hdmi->disable_wifi_frequencies &&
2205 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
2206 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
2207 mode->clock = 238560;
2208 tmds_char_rate = mode->clock * 1000;
2209 }
2210
2211 ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode);
2212 if (ret)
2213 return ret;
2214
2215 /* vc4_hdmi_encoder_compute_config may have changed output_bpc and/or output_format */
2216 if (vc4_state->output_bpc != old_vc4_state->output_bpc ||
2217 vc4_state->output_format != old_vc4_state->output_format)
2218 crtc_state->mode_changed = true;
2219
2220 return 0;
2221}
2222
2223static enum drm_mode_status
2224vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
2225 const struct drm_display_mode *mode)
2226{
2227 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
2228
2229 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
2230 !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
2231 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
2232 (mode->hsync_end % 2) || (mode->htotal % 2)))
2233 return MODE_H_ILLEGAL;
2234
2235 return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, mode->clock * 1000);
2236}
2237
2238static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
2239 .atomic_check = vc4_hdmi_encoder_atomic_check,
2240 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
2241 .mode_valid = vc4_hdmi_encoder_mode_valid,
2242};
2243
2244static int vc4_hdmi_late_register(struct drm_encoder *encoder)
2245{
2246 struct drm_device *drm = encoder->dev;
2247 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
2248 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2249
2250 drm_debugfs_add_file(drm, variant->debugfs_name,
2251 vc4_hdmi_debugfs_regs, vc4_hdmi);
2252
2253 return 0;
2254}
2255
2256static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
2257 .late_register = vc4_hdmi_late_register,
2258};
2259
2260static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
2261{
2262 int i;
2263 u32 channel_map = 0;
2264
2265 for (i = 0; i < 8; i++) {
2266 if (channel_mask & BIT(i))
2267 channel_map |= i << (3 * i);
2268 }
2269 return channel_map;
2270}
2271
2272static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
2273{
2274 int i;
2275 u32 channel_map = 0;
2276
2277 for (i = 0; i < 8; i++) {
2278 if (channel_mask & BIT(i))
2279 channel_map |= i << (4 * i);
2280 }
2281 return channel_map;
2282}
2283
2284static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
2285{
2286 struct drm_device *drm = vc4_hdmi->connector.dev;
2287 unsigned long flags;
2288 u32 hotplug;
2289 int idx;
2290
2291 if (!drm_dev_enter(drm, &idx))
2292 return false;
2293
2294 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2295 hotplug = HDMI_READ(HDMI_HOTPLUG);
2296 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2297
2298 drm_dev_exit(idx);
2299
2300 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
2301}
2302
2303/* HDMI audio codec callbacks */
2304static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
2305 unsigned int samplerate)
2306{
2307 struct drm_device *drm = vc4_hdmi->connector.dev;
2308 u32 hsm_clock;
2309 unsigned long flags;
2310 unsigned long n, m;
2311 int idx;
2312
2313 if (!drm_dev_enter(drm, &idx))
2314 return;
2315
2316 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
2317 rational_best_approximation(hsm_clock, samplerate,
2318 VC4_HD_MAI_SMP_N_MASK >>
2319 VC4_HD_MAI_SMP_N_SHIFT,
2320 (VC4_HD_MAI_SMP_M_MASK >>
2321 VC4_HD_MAI_SMP_M_SHIFT) + 1,
2322 &n, &m);
2323
2324 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2325 HDMI_WRITE(HDMI_MAI_SMP,
2326 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
2327 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
2328 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2329
2330 drm_dev_exit(idx);
2331}
2332
2333static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
2334{
2335 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
2336 u32 n, cts;
2337 u64 tmp;
2338
2339 lockdep_assert_held(&vc4_hdmi->mutex);
2340 lockdep_assert_held(&vc4_hdmi->hw_lock);
2341
2342 n = 128 * samplerate / 1000;
2343 tmp = (u64)(mode->clock * 1000) * n;
2344 do_div(tmp, 128 * samplerate);
2345 cts = tmp;
2346
2347 HDMI_WRITE(HDMI_CRP_CFG,
2348 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
2349 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
2350
2351 /*
2352 * We could get slightly more accurate clocks in some cases by
2353 * providing a CTS_1 value. The two CTS values are alternated
2354 * between based on the period fields
2355 */
2356 HDMI_WRITE(HDMI_CTS_0, cts);
2357 HDMI_WRITE(HDMI_CTS_1, cts);
2358}
2359
2360static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
2361{
2362 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
2363
2364 return snd_soc_card_get_drvdata(card);
2365}
2366
2367static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
2368{
2369 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
2370
2371 lockdep_assert_held(&vc4_hdmi->mutex);
2372
2373 /*
2374 * If the encoder is currently in DVI mode, treat the codec DAI
2375 * as missing.
2376 */
2377 if (!display->is_hdmi)
2378 return false;
2379
2380 return true;
2381}
2382
2383static int vc4_hdmi_audio_startup(struct device *dev, void *data)
2384{
2385 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2386 struct drm_device *drm = vc4_hdmi->connector.dev;
2387 unsigned long flags;
2388 int ret = 0;
2389 int idx;
2390
2391 mutex_lock(&vc4_hdmi->mutex);
2392
2393 if (!drm_dev_enter(drm, &idx)) {
2394 ret = -ENODEV;
2395 goto out;
2396 }
2397
2398 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2399 ret = -ENODEV;
2400 goto out_dev_exit;
2401 }
2402
2403 vc4_hdmi->audio.streaming = true;
2404
2405 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2406 HDMI_WRITE(HDMI_MAI_CTL,
2407 VC4_HD_MAI_CTL_RESET |
2408 VC4_HD_MAI_CTL_FLUSH |
2409 VC4_HD_MAI_CTL_DLATE |
2410 VC4_HD_MAI_CTL_ERRORE |
2411 VC4_HD_MAI_CTL_ERRORF);
2412 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2413
2414 if (vc4_hdmi->variant->phy_rng_enable)
2415 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
2416
2417out_dev_exit:
2418 drm_dev_exit(idx);
2419out:
2420 mutex_unlock(&vc4_hdmi->mutex);
2421
2422 return ret;
2423}
2424
2425static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
2426{
2427 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2428 struct device *dev = &vc4_hdmi->pdev->dev;
2429 unsigned long flags;
2430 int ret;
2431
2432 lockdep_assert_held(&vc4_hdmi->mutex);
2433
2434 vc4_hdmi->audio.streaming = false;
2435 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
2436 if (ret)
2437 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
2438
2439 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2440
2441 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
2442 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
2443 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
2444
2445 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2446}
2447
2448static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
2449{
2450 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2451 struct drm_device *drm = vc4_hdmi->connector.dev;
2452 unsigned long flags;
2453 int idx;
2454
2455 mutex_lock(&vc4_hdmi->mutex);
2456
2457 if (!drm_dev_enter(drm, &idx))
2458 goto out;
2459
2460 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2461
2462 HDMI_WRITE(HDMI_MAI_CTL,
2463 VC4_HD_MAI_CTL_DLATE |
2464 VC4_HD_MAI_CTL_ERRORE |
2465 VC4_HD_MAI_CTL_ERRORF);
2466
2467 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2468
2469 if (vc4_hdmi->variant->phy_rng_disable)
2470 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
2471
2472 vc4_hdmi->audio.streaming = false;
2473 vc4_hdmi_audio_reset(vc4_hdmi);
2474
2475 drm_dev_exit(idx);
2476
2477out:
2478 mutex_unlock(&vc4_hdmi->mutex);
2479}
2480
2481static int sample_rate_to_mai_fmt(int samplerate)
2482{
2483 switch (samplerate) {
2484 case 8000:
2485 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
2486 case 11025:
2487 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
2488 case 12000:
2489 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
2490 case 16000:
2491 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
2492 case 22050:
2493 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
2494 case 24000:
2495 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
2496 case 32000:
2497 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
2498 case 44100:
2499 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
2500 case 48000:
2501 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
2502 case 64000:
2503 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
2504 case 88200:
2505 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
2506 case 96000:
2507 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
2508 case 128000:
2509 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
2510 case 176400:
2511 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
2512 case 192000:
2513 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
2514 default:
2515 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
2516 }
2517}
2518
2519/* HDMI audio codec callbacks */
2520static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
2521 struct hdmi_codec_daifmt *daifmt,
2522 struct hdmi_codec_params *params)
2523{
2524 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2525 struct drm_device *drm = vc4_hdmi->connector.dev;
2526 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2527 unsigned int sample_rate = params->sample_rate;
2528 unsigned int channels = params->channels;
2529 unsigned long flags;
2530 u32 audio_packet_config, channel_mask;
2531 u32 channel_map;
2532 u32 mai_audio_format;
2533 u32 mai_sample_rate;
2534 int ret = 0;
2535 int idx;
2536
2537 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
2538 sample_rate, params->sample_width, channels);
2539
2540 mutex_lock(&vc4_hdmi->mutex);
2541
2542 if (!drm_dev_enter(drm, &idx)) {
2543 ret = -ENODEV;
2544 goto out;
2545 }
2546
2547 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2548 ret = -EINVAL;
2549 goto out_dev_exit;
2550 }
2551
2552 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
2553
2554 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2555 HDMI_WRITE(HDMI_MAI_CTL,
2556 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
2557 VC4_HD_MAI_CTL_WHOLSMP |
2558 VC4_HD_MAI_CTL_CHALIGN |
2559 VC4_HD_MAI_CTL_ENABLE);
2560
2561 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
2562 if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
2563 params->channels == 8)
2564 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
2565 else
2566 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
2567 HDMI_WRITE(HDMI_MAI_FMT,
2568 VC4_SET_FIELD(mai_sample_rate,
2569 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
2570 VC4_SET_FIELD(mai_audio_format,
2571 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
2572
2573 /* The B frame identifier should match the value used by alsa-lib (8) */
2574 audio_packet_config =
2575 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
2576 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
2577 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
2578
2579 channel_mask = GENMASK(channels - 1, 0);
2580 audio_packet_config |= VC4_SET_FIELD(channel_mask,
2581 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
2582
2583 /* Set the MAI threshold */
2584 HDMI_WRITE(HDMI_MAI_THR,
2585 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) |
2586 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) |
2587 VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) |
2588 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW));
2589
2590 HDMI_WRITE(HDMI_MAI_CONFIG,
2591 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
2592 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
2593 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
2594
2595 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
2596 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
2597 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
2598
2599 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
2600
2601 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2602
2603 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea));
2604 vc4_hdmi_set_audio_infoframe(encoder);
2605
2606out_dev_exit:
2607 drm_dev_exit(idx);
2608out:
2609 mutex_unlock(&vc4_hdmi->mutex);
2610
2611 return ret;
2612}
2613
2614static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
2615 .name = "vc4-hdmi-cpu-dai-component",
2616 .legacy_dai_naming = 1,
2617};
2618
2619static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
2620{
2621 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
2622
2623 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
2624
2625 return 0;
2626}
2627
2628static const struct snd_soc_dai_ops vc4_snd_dai_ops = {
2629 .probe = vc4_hdmi_audio_cpu_dai_probe,
2630};
2631
2632static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
2633 .name = "vc4-hdmi-cpu-dai",
2634 .ops = &vc4_snd_dai_ops,
2635 .playback = {
2636 .stream_name = "Playback",
2637 .channels_min = 1,
2638 .channels_max = 8,
2639 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2640 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2641 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2642 SNDRV_PCM_RATE_192000,
2643 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
2644 },
2645};
2646
2647static const struct snd_dmaengine_pcm_config pcm_conf = {
2648 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
2649 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
2650};
2651
2652static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
2653 uint8_t *buf, size_t len)
2654{
2655 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2656 struct drm_connector *connector = &vc4_hdmi->connector;
2657
2658 mutex_lock(&vc4_hdmi->mutex);
2659 memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
2660 mutex_unlock(&vc4_hdmi->mutex);
2661
2662 return 0;
2663}
2664
2665static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
2666 .get_eld = vc4_hdmi_audio_get_eld,
2667 .prepare = vc4_hdmi_audio_prepare,
2668 .audio_shutdown = vc4_hdmi_audio_shutdown,
2669 .audio_startup = vc4_hdmi_audio_startup,
2670};
2671
2672static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
2673 .ops = &vc4_hdmi_codec_ops,
2674 .max_i2s_channels = 8,
2675 .i2s = 1,
2676};
2677
2678static void vc4_hdmi_audio_codec_release(void *ptr)
2679{
2680 struct vc4_hdmi *vc4_hdmi = ptr;
2681
2682 platform_device_unregister(vc4_hdmi->audio.codec_pdev);
2683 vc4_hdmi->audio.codec_pdev = NULL;
2684}
2685
2686static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
2687{
2688 const struct vc4_hdmi_register *mai_data =
2689 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
2690 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
2691 struct snd_soc_card *card = &vc4_hdmi->audio.card;
2692 struct device *dev = &vc4_hdmi->pdev->dev;
2693 struct platform_device *codec_pdev;
2694 const __be32 *addr;
2695 int index, len;
2696 int ret;
2697
2698 /*
2699 * ASoC makes it a bit hard to retrieve a pointer to the
2700 * vc4_hdmi structure. Registering the card will overwrite our
2701 * device drvdata with a pointer to the snd_soc_card structure,
2702 * which can then be used to retrieve whatever drvdata we want
2703 * to associate.
2704 *
2705 * However, that doesn't fly in the case where we wouldn't
2706 * register an ASoC card (because of an old DT that is missing
2707 * the dmas properties for example), then the card isn't
2708 * registered and the device drvdata wouldn't be set.
2709 *
2710 * We can deal with both cases by making sure a snd_soc_card
2711 * pointer and a vc4_hdmi structure are pointing to the same
2712 * memory address, so we can treat them indistinctly without any
2713 * issue.
2714 */
2715 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2716 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2717
2718 if (!of_find_property(dev->of_node, "dmas", &len) || !len) {
2719 dev_warn(dev,
2720 "'dmas' DT property is missing or empty, no HDMI audio\n");
2721 return 0;
2722 }
2723
2724 if (mai_data->reg != VC4_HD) {
2725 WARN_ONCE(true, "MAI isn't in the HD block\n");
2726 return -EINVAL;
2727 }
2728
2729 /*
2730 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
2731 * the bus address specified in the DT, because the physical address
2732 * (the one returned by platform_get_resource()) is not appropriate
2733 * for DMA transfers.
2734 * This VC/MMU should probably be exposed to avoid this kind of hacks.
2735 */
2736 index = of_property_match_string(dev->of_node, "reg-names", "hd");
2737 /* Before BCM2711, we don't have a named register range */
2738 if (index < 0)
2739 index = 1;
2740
2741 addr = of_get_address(dev->of_node, index, NULL, NULL);
2742
2743 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
2744 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2745 vc4_hdmi->audio.dma_data.maxburst = 2;
2746
2747 /*
2748 * NOTE: Strictly speaking, we should probably use a DRM-managed
2749 * registration there to avoid removing all the audio components
2750 * by the time the driver doesn't have any user anymore.
2751 *
2752 * However, the ASoC core uses a number of devm_kzalloc calls
2753 * when registering, even when using non-device-managed
2754 * functions (such as in snd_soc_register_component()).
2755 *
2756 * If we call snd_soc_unregister_component() in a DRM-managed
2757 * action, the device-managed actions have already been executed
2758 * and thus we would access memory that has been freed.
2759 *
2760 * Using device-managed hooks here probably leaves us open to a
2761 * bunch of issues if userspace still has a handle on the ALSA
2762 * device when the device is removed. However, this is mitigated
2763 * by the use of drm_dev_enter()/drm_dev_exit() in the audio
2764 * path to prevent the access to the device resources if it
2765 * isn't there anymore.
2766 *
2767 * Then, the vc4_hdmi structure is DRM-managed and thus only
2768 * freed whenever the last user has closed the DRM device file.
2769 * It should thus outlive ALSA in most situations.
2770 */
2771 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
2772 if (ret) {
2773 dev_err(dev, "Could not register PCM component: %d\n", ret);
2774 return ret;
2775 }
2776
2777 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
2778 &vc4_hdmi_audio_cpu_dai_drv, 1);
2779 if (ret) {
2780 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
2781 return ret;
2782 }
2783
2784 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
2785 PLATFORM_DEVID_AUTO,
2786 &vc4_hdmi_codec_pdata,
2787 sizeof(vc4_hdmi_codec_pdata));
2788 if (IS_ERR(codec_pdev)) {
2789 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
2790 return PTR_ERR(codec_pdev);
2791 }
2792 vc4_hdmi->audio.codec_pdev = codec_pdev;
2793
2794 ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi);
2795 if (ret)
2796 return ret;
2797
2798 dai_link->cpus = &vc4_hdmi->audio.cpu;
2799 dai_link->codecs = &vc4_hdmi->audio.codec;
2800 dai_link->platforms = &vc4_hdmi->audio.platform;
2801
2802 dai_link->num_cpus = 1;
2803 dai_link->num_codecs = 1;
2804 dai_link->num_platforms = 1;
2805
2806 dai_link->name = "MAI";
2807 dai_link->stream_name = "MAI PCM";
2808 dai_link->codecs->dai_name = "i2s-hifi";
2809 dai_link->cpus->dai_name = dev_name(dev);
2810 dai_link->codecs->name = dev_name(&codec_pdev->dev);
2811 dai_link->platforms->name = dev_name(dev);
2812
2813 card->dai_link = dai_link;
2814 card->num_links = 1;
2815 card->name = vc4_hdmi->variant->card_name;
2816 card->driver_name = "vc4-hdmi";
2817 card->dev = dev;
2818 card->owner = THIS_MODULE;
2819
2820 /*
2821 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
2822 * stores a pointer to the snd card object in dev->driver_data. This
2823 * means we cannot use it for something else. The hdmi back-pointer is
2824 * now stored in card->drvdata and should be retrieved with
2825 * snd_soc_card_get_drvdata() if needed.
2826 */
2827 snd_soc_card_set_drvdata(card, vc4_hdmi);
2828 ret = devm_snd_soc_register_card(dev, card);
2829 if (ret)
2830 dev_err_probe(dev, ret, "Could not register sound card\n");
2831
2832 return ret;
2833
2834}
2835
2836static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
2837{
2838 struct vc4_hdmi *vc4_hdmi = priv;
2839 struct drm_connector *connector = &vc4_hdmi->connector;
2840 struct drm_device *dev = connector->dev;
2841
2842 if (dev && dev->registered)
2843 drm_connector_helper_hpd_irq_event(connector);
2844
2845 return IRQ_HANDLED;
2846}
2847
2848static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
2849{
2850 struct drm_connector *connector = &vc4_hdmi->connector;
2851 struct platform_device *pdev = vc4_hdmi->pdev;
2852 int ret;
2853
2854 if (vc4_hdmi->variant->external_irq_controller) {
2855 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
2856 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
2857
2858 ret = devm_request_threaded_irq(&pdev->dev, hpd_con,
2859 NULL,
2860 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2861 "vc4 hdmi hpd connected", vc4_hdmi);
2862 if (ret)
2863 return ret;
2864
2865 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm,
2866 NULL,
2867 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2868 "vc4 hdmi hpd disconnected", vc4_hdmi);
2869 if (ret)
2870 return ret;
2871
2872 connector->polled = DRM_CONNECTOR_POLL_HPD;
2873 }
2874
2875 return 0;
2876}
2877
2878#ifdef CONFIG_DRM_VC4_HDMI_CEC
2879static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
2880{
2881 struct vc4_hdmi *vc4_hdmi = priv;
2882
2883 if (vc4_hdmi->cec_rx_msg.len)
2884 cec_received_msg(vc4_hdmi->cec_adap,
2885 &vc4_hdmi->cec_rx_msg);
2886
2887 return IRQ_HANDLED;
2888}
2889
2890static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
2891{
2892 struct vc4_hdmi *vc4_hdmi = priv;
2893
2894 if (vc4_hdmi->cec_tx_ok) {
2895 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
2896 0, 0, 0, 0);
2897 } else {
2898 /*
2899 * This CEC implementation makes 1 retry, so if we
2900 * get a NACK, then that means it made 2 attempts.
2901 */
2902 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
2903 0, 2, 0, 0);
2904 }
2905 return IRQ_HANDLED;
2906}
2907
2908static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
2909{
2910 struct vc4_hdmi *vc4_hdmi = priv;
2911 irqreturn_t ret;
2912
2913 if (vc4_hdmi->cec_irq_was_rx)
2914 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
2915 else
2916 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
2917
2918 return ret;
2919}
2920
2921static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
2922{
2923 struct drm_device *dev = vc4_hdmi->connector.dev;
2924 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
2925 unsigned int i;
2926
2927 lockdep_assert_held(&vc4_hdmi->hw_lock);
2928
2929 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
2930 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
2931
2932 if (msg->len > 16) {
2933 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
2934 return;
2935 }
2936
2937 for (i = 0; i < msg->len; i += 4) {
2938 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
2939
2940 msg->msg[i] = val & 0xff;
2941 msg->msg[i + 1] = (val >> 8) & 0xff;
2942 msg->msg[i + 2] = (val >> 16) & 0xff;
2943 msg->msg[i + 3] = (val >> 24) & 0xff;
2944 }
2945}
2946
2947static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2948{
2949 u32 cntrl1;
2950
2951 /*
2952 * We don't need to protect the register access using
2953 * drm_dev_enter() there because the interrupt handler lifetime
2954 * is tied to the device itself, and not to the DRM device.
2955 *
2956 * So when the device will be gone, one of the first thing we
2957 * will be doing will be to unregister the interrupt handler,
2958 * and then unregister the DRM device. drm_dev_enter() would
2959 * thus always succeed if we are here.
2960 */
2961
2962 lockdep_assert_held(&vc4_hdmi->hw_lock);
2963
2964 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2965 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
2966 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2967 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2968
2969 return IRQ_WAKE_THREAD;
2970}
2971
2972static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
2973{
2974 struct vc4_hdmi *vc4_hdmi = priv;
2975 irqreturn_t ret;
2976
2977 spin_lock(&vc4_hdmi->hw_lock);
2978 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2979 spin_unlock(&vc4_hdmi->hw_lock);
2980
2981 return ret;
2982}
2983
2984static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2985{
2986 u32 cntrl1;
2987
2988 lockdep_assert_held(&vc4_hdmi->hw_lock);
2989
2990 /*
2991 * We don't need to protect the register access using
2992 * drm_dev_enter() there because the interrupt handler lifetime
2993 * is tied to the device itself, and not to the DRM device.
2994 *
2995 * So when the device will be gone, one of the first thing we
2996 * will be doing will be to unregister the interrupt handler,
2997 * and then unregister the DRM device. drm_dev_enter() would
2998 * thus always succeed if we are here.
2999 */
3000
3001 vc4_hdmi->cec_rx_msg.len = 0;
3002 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
3003 vc4_cec_read_msg(vc4_hdmi, cntrl1);
3004 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
3005 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
3006 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
3007
3008 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
3009
3010 return IRQ_WAKE_THREAD;
3011}
3012
3013static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
3014{
3015 struct vc4_hdmi *vc4_hdmi = priv;
3016 irqreturn_t ret;
3017
3018 spin_lock(&vc4_hdmi->hw_lock);
3019 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
3020 spin_unlock(&vc4_hdmi->hw_lock);
3021
3022 return ret;
3023}
3024
3025static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
3026{
3027 struct vc4_hdmi *vc4_hdmi = priv;
3028 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
3029 irqreturn_t ret;
3030 u32 cntrl5;
3031
3032 /*
3033 * We don't need to protect the register access using
3034 * drm_dev_enter() there because the interrupt handler lifetime
3035 * is tied to the device itself, and not to the DRM device.
3036 *
3037 * So when the device will be gone, one of the first thing we
3038 * will be doing will be to unregister the interrupt handler,
3039 * and then unregister the DRM device. drm_dev_enter() would
3040 * thus always succeed if we are here.
3041 */
3042
3043 if (!(stat & VC4_HDMI_CPU_CEC))
3044 return IRQ_NONE;
3045
3046 spin_lock(&vc4_hdmi->hw_lock);
3047 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
3048 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
3049 if (vc4_hdmi->cec_irq_was_rx)
3050 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
3051 else
3052 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
3053
3054 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
3055 spin_unlock(&vc4_hdmi->hw_lock);
3056
3057 return ret;
3058}
3059
3060static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
3061{
3062 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
3063 struct drm_device *drm = vc4_hdmi->connector.dev;
3064 /* clock period in microseconds */
3065 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
3066 unsigned long flags;
3067 u32 val;
3068 int ret;
3069 int idx;
3070
3071 if (!drm_dev_enter(drm, &idx))
3072 /*
3073 * We can't return an error code, because the CEC
3074 * framework will emit WARN_ON messages at unbind
3075 * otherwise.
3076 */
3077 return 0;
3078
3079 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
3080 if (ret) {
3081 drm_dev_exit(idx);
3082 return ret;
3083 }
3084
3085 mutex_lock(&vc4_hdmi->mutex);
3086
3087 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3088
3089 val = HDMI_READ(HDMI_CEC_CNTRL_5);
3090 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
3091 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
3092 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
3093 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
3094 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
3095
3096 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
3097 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
3098 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
3099 HDMI_WRITE(HDMI_CEC_CNTRL_2,
3100 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
3101 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
3102 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
3103 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
3104 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
3105 HDMI_WRITE(HDMI_CEC_CNTRL_3,
3106 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
3107 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
3108 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
3109 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
3110 HDMI_WRITE(HDMI_CEC_CNTRL_4,
3111 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
3112 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
3113 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
3114 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
3115
3116 if (!vc4_hdmi->variant->external_irq_controller)
3117 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
3118
3119 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3120
3121 mutex_unlock(&vc4_hdmi->mutex);
3122 drm_dev_exit(idx);
3123
3124 return 0;
3125}
3126
3127static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
3128{
3129 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
3130 struct drm_device *drm = vc4_hdmi->connector.dev;
3131 unsigned long flags;
3132 int idx;
3133
3134 if (!drm_dev_enter(drm, &idx))
3135 /*
3136 * We can't return an error code, because the CEC
3137 * framework will emit WARN_ON messages at unbind
3138 * otherwise.
3139 */
3140 return 0;
3141
3142 mutex_lock(&vc4_hdmi->mutex);
3143
3144 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3145
3146 if (!vc4_hdmi->variant->external_irq_controller)
3147 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
3148
3149 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
3150 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
3151
3152 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3153
3154 mutex_unlock(&vc4_hdmi->mutex);
3155
3156 pm_runtime_put(&vc4_hdmi->pdev->dev);
3157
3158 drm_dev_exit(idx);
3159
3160 return 0;
3161}
3162
3163static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
3164{
3165 if (enable)
3166 return vc4_hdmi_cec_enable(adap);
3167 else
3168 return vc4_hdmi_cec_disable(adap);
3169}
3170
3171static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
3172{
3173 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
3174 struct drm_device *drm = vc4_hdmi->connector.dev;
3175 unsigned long flags;
3176 int idx;
3177
3178 if (!drm_dev_enter(drm, &idx))
3179 /*
3180 * We can't return an error code, because the CEC
3181 * framework will emit WARN_ON messages at unbind
3182 * otherwise.
3183 */
3184 return 0;
3185
3186 mutex_lock(&vc4_hdmi->mutex);
3187 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3188 HDMI_WRITE(HDMI_CEC_CNTRL_1,
3189 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
3190 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
3191 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3192 mutex_unlock(&vc4_hdmi->mutex);
3193
3194 drm_dev_exit(idx);
3195
3196 return 0;
3197}
3198
3199static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
3200 u32 signal_free_time, struct cec_msg *msg)
3201{
3202 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
3203 struct drm_device *dev = vc4_hdmi->connector.dev;
3204 unsigned long flags;
3205 u32 val;
3206 unsigned int i;
3207 int idx;
3208
3209 if (!drm_dev_enter(dev, &idx))
3210 return -ENODEV;
3211
3212 if (msg->len > 16) {
3213 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
3214 drm_dev_exit(idx);
3215 return -ENOMEM;
3216 }
3217
3218 mutex_lock(&vc4_hdmi->mutex);
3219
3220 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3221
3222 for (i = 0; i < msg->len; i += 4)
3223 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
3224 (msg->msg[i]) |
3225 (msg->msg[i + 1] << 8) |
3226 (msg->msg[i + 2] << 16) |
3227 (msg->msg[i + 3] << 24));
3228
3229 val = HDMI_READ(HDMI_CEC_CNTRL_1);
3230 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
3231 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
3232 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
3233 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
3234 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
3235
3236 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
3237
3238 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3239 mutex_unlock(&vc4_hdmi->mutex);
3240 drm_dev_exit(idx);
3241
3242 return 0;
3243}
3244
3245static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
3246 .adap_enable = vc4_hdmi_cec_adap_enable,
3247 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
3248 .adap_transmit = vc4_hdmi_cec_adap_transmit,
3249};
3250
3251static void vc4_hdmi_cec_release(void *ptr)
3252{
3253 struct vc4_hdmi *vc4_hdmi = ptr;
3254
3255 cec_unregister_adapter(vc4_hdmi->cec_adap);
3256 vc4_hdmi->cec_adap = NULL;
3257}
3258
3259static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
3260{
3261 struct cec_connector_info conn_info;
3262 struct platform_device *pdev = vc4_hdmi->pdev;
3263 struct device *dev = &pdev->dev;
3264 int ret;
3265
3266 if (!of_property_present(dev->of_node, "interrupts")) {
3267 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
3268 return 0;
3269 }
3270
3271 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
3272 vc4_hdmi,
3273 vc4_hdmi->variant->card_name,
3274 CEC_CAP_DEFAULTS |
3275 CEC_CAP_CONNECTOR_INFO, 1);
3276 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
3277 if (ret < 0)
3278 return ret;
3279
3280 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
3281 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
3282
3283 if (vc4_hdmi->variant->external_irq_controller) {
3284 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"),
3285 vc4_cec_irq_handler_rx_bare,
3286 vc4_cec_irq_handler_rx_thread, 0,
3287 "vc4 hdmi cec rx", vc4_hdmi);
3288 if (ret)
3289 goto err_delete_cec_adap;
3290
3291 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"),
3292 vc4_cec_irq_handler_tx_bare,
3293 vc4_cec_irq_handler_tx_thread, 0,
3294 "vc4 hdmi cec tx", vc4_hdmi);
3295 if (ret)
3296 goto err_delete_cec_adap;
3297 } else {
3298 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
3299 vc4_cec_irq_handler,
3300 vc4_cec_irq_handler_thread, 0,
3301 "vc4 hdmi cec", vc4_hdmi);
3302 if (ret)
3303 goto err_delete_cec_adap;
3304 }
3305
3306 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
3307 if (ret < 0)
3308 goto err_delete_cec_adap;
3309
3310 /*
3311 * NOTE: Strictly speaking, we should probably use a DRM-managed
3312 * registration there to avoid removing the CEC adapter by the
3313 * time the DRM driver doesn't have any user anymore.
3314 *
3315 * However, the CEC framework already cleans up the CEC adapter
3316 * only when the last user has closed its file descriptor, so we
3317 * don't need to handle it in DRM.
3318 *
3319 * By the time the device-managed hook is executed, we will give
3320 * up our reference to the CEC adapter and therefore don't
3321 * really care when it's actually freed.
3322 *
3323 * There's still a problematic sequence: if we unregister our
3324 * CEC adapter, but the userspace keeps a handle on the CEC
3325 * adapter but not the DRM device for some reason. In such a
3326 * case, our vc4_hdmi structure will be freed, but the
3327 * cec_adapter structure will have a dangling pointer to what
3328 * used to be our HDMI controller. If we get a CEC call at that
3329 * moment, we could end up with a use-after-free. Fortunately,
3330 * the CEC framework already handles this too, by calling
3331 * cec_is_registered() in cec_ioctl() and cec_poll().
3332 */
3333 ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi);
3334 if (ret)
3335 return ret;
3336
3337 return 0;
3338
3339err_delete_cec_adap:
3340 cec_delete_adapter(vc4_hdmi->cec_adap);
3341
3342 return ret;
3343}
3344#else
3345static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
3346{
3347 return 0;
3348}
3349#endif
3350
3351static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr)
3352{
3353 struct debugfs_reg32 *regs = ptr;
3354
3355 kfree(regs);
3356}
3357
3358static int vc4_hdmi_build_regset(struct drm_device *drm,
3359 struct vc4_hdmi *vc4_hdmi,
3360 struct debugfs_regset32 *regset,
3361 enum vc4_hdmi_regs reg)
3362{
3363 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
3364 struct debugfs_reg32 *regs, *new_regs;
3365 unsigned int count = 0;
3366 unsigned int i;
3367 int ret;
3368
3369 regs = kcalloc(variant->num_registers, sizeof(*regs),
3370 GFP_KERNEL);
3371 if (!regs)
3372 return -ENOMEM;
3373
3374 for (i = 0; i < variant->num_registers; i++) {
3375 const struct vc4_hdmi_register *field = &variant->registers[i];
3376
3377 if (field->reg != reg)
3378 continue;
3379
3380 regs[count].name = field->name;
3381 regs[count].offset = field->offset;
3382 count++;
3383 }
3384
3385 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
3386 if (!new_regs)
3387 return -ENOMEM;
3388
3389 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
3390 regset->regs = new_regs;
3391 regset->nregs = count;
3392
3393 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs);
3394 if (ret)
3395 return ret;
3396
3397 return 0;
3398}
3399
3400static int vc4_hdmi_init_resources(struct drm_device *drm,
3401 struct vc4_hdmi *vc4_hdmi)
3402{
3403 struct platform_device *pdev = vc4_hdmi->pdev;
3404 struct device *dev = &pdev->dev;
3405 int ret;
3406
3407 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
3408 if (IS_ERR(vc4_hdmi->hdmicore_regs))
3409 return PTR_ERR(vc4_hdmi->hdmicore_regs);
3410
3411 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
3412 if (IS_ERR(vc4_hdmi->hd_regs))
3413 return PTR_ERR(vc4_hdmi->hd_regs);
3414
3415 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3416 if (ret)
3417 return ret;
3418
3419 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3420 if (ret)
3421 return ret;
3422
3423 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
3424 if (IS_ERR(vc4_hdmi->pixel_clock)) {
3425 ret = PTR_ERR(vc4_hdmi->pixel_clock);
3426 if (ret != -EPROBE_DEFER)
3427 DRM_ERROR("Failed to get pixel clock\n");
3428 return ret;
3429 }
3430
3431 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3432 if (IS_ERR(vc4_hdmi->hsm_clock)) {
3433 DRM_ERROR("Failed to get HDMI state machine clock\n");
3434 return PTR_ERR(vc4_hdmi->hsm_clock);
3435 }
3436 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
3437 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
3438
3439 return 0;
3440}
3441
3442static int vc5_hdmi_init_resources(struct drm_device *drm,
3443 struct vc4_hdmi *vc4_hdmi)
3444{
3445 struct platform_device *pdev = vc4_hdmi->pdev;
3446 struct device *dev = &pdev->dev;
3447 struct resource *res;
3448 int ret;
3449
3450 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
3451 if (!res)
3452 return -ENODEV;
3453
3454 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
3455 resource_size(res));
3456 if (!vc4_hdmi->hdmicore_regs)
3457 return -ENOMEM;
3458
3459 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
3460 if (!res)
3461 return -ENODEV;
3462
3463 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
3464 if (!vc4_hdmi->hd_regs)
3465 return -ENOMEM;
3466
3467 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
3468 if (!res)
3469 return -ENODEV;
3470
3471 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
3472 if (!vc4_hdmi->cec_regs)
3473 return -ENOMEM;
3474
3475 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
3476 if (!res)
3477 return -ENODEV;
3478
3479 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
3480 if (!vc4_hdmi->csc_regs)
3481 return -ENOMEM;
3482
3483 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
3484 if (!res)
3485 return -ENODEV;
3486
3487 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
3488 if (!vc4_hdmi->dvp_regs)
3489 return -ENOMEM;
3490
3491 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
3492 if (!res)
3493 return -ENODEV;
3494
3495 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
3496 if (!vc4_hdmi->phy_regs)
3497 return -ENOMEM;
3498
3499 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
3500 if (!res)
3501 return -ENODEV;
3502
3503 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
3504 if (!vc4_hdmi->ram_regs)
3505 return -ENOMEM;
3506
3507 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
3508 if (!res)
3509 return -ENODEV;
3510
3511 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
3512 if (!vc4_hdmi->rm_regs)
3513 return -ENOMEM;
3514
3515 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3516 if (IS_ERR(vc4_hdmi->hsm_clock)) {
3517 DRM_ERROR("Failed to get HDMI state machine clock\n");
3518 return PTR_ERR(vc4_hdmi->hsm_clock);
3519 }
3520
3521 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
3522 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
3523 DRM_ERROR("Failed to get pixel bvb clock\n");
3524 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
3525 }
3526
3527 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
3528 if (IS_ERR(vc4_hdmi->audio_clock)) {
3529 DRM_ERROR("Failed to get audio clock\n");
3530 return PTR_ERR(vc4_hdmi->audio_clock);
3531 }
3532
3533 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
3534 if (IS_ERR(vc4_hdmi->cec_clock)) {
3535 DRM_ERROR("Failed to get CEC clock\n");
3536 return PTR_ERR(vc4_hdmi->cec_clock);
3537 }
3538
3539 vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
3540 if (IS_ERR(vc4_hdmi->reset)) {
3541 DRM_ERROR("Failed to get HDMI reset line\n");
3542 return PTR_ERR(vc4_hdmi->reset);
3543 }
3544
3545 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3546 if (ret)
3547 return ret;
3548
3549 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3550 if (ret)
3551 return ret;
3552
3553 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
3554 if (ret)
3555 return ret;
3556
3557 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
3558 if (ret)
3559 return ret;
3560
3561 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
3562 if (ret)
3563 return ret;
3564
3565 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
3566 if (ret)
3567 return ret;
3568
3569 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
3570 if (ret)
3571 return ret;
3572
3573 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
3574 if (ret)
3575 return ret;
3576
3577 return 0;
3578}
3579
3580static int vc4_hdmi_runtime_suspend(struct device *dev)
3581{
3582 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3583
3584 clk_disable_unprepare(vc4_hdmi->hsm_clock);
3585
3586 return 0;
3587}
3588
3589static int vc4_hdmi_runtime_resume(struct device *dev)
3590{
3591 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3592 unsigned long __maybe_unused flags;
3593 u32 __maybe_unused value;
3594 unsigned long rate;
3595 int ret;
3596
3597 ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
3598 if (ret)
3599 return ret;
3600
3601 /*
3602 * Whenever the RaspberryPi boots without an HDMI monitor
3603 * plugged in, the firmware won't have initialized the HSM clock
3604 * rate and it will be reported as 0.
3605 *
3606 * If we try to access a register of the controller in such a
3607 * case, it will lead to a silent CPU stall. Let's make sure we
3608 * prevent such a case.
3609 */
3610 rate = clk_get_rate(vc4_hdmi->hsm_clock);
3611 if (!rate) {
3612 ret = -EINVAL;
3613 goto err_disable_clk;
3614 }
3615
3616 if (vc4_hdmi->variant->reset)
3617 vc4_hdmi->variant->reset(vc4_hdmi);
3618
3619#ifdef CONFIG_DRM_VC4_HDMI_CEC
3620 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3621 value = HDMI_READ(HDMI_CEC_CNTRL_1);
3622 /* Set the logical address to Unregistered */
3623 value |= VC4_HDMI_CEC_ADDR_MASK;
3624 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
3625 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3626
3627 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
3628
3629 if (!vc4_hdmi->variant->external_irq_controller) {
3630 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3631 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
3632 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3633 }
3634#endif
3635
3636 return 0;
3637
3638err_disable_clk:
3639 clk_disable_unprepare(vc4_hdmi->hsm_clock);
3640 return ret;
3641}
3642
3643static void vc4_hdmi_put_ddc_device(void *ptr)
3644{
3645 struct vc4_hdmi *vc4_hdmi = ptr;
3646
3647 put_device(&vc4_hdmi->ddc->dev);
3648}
3649
3650static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
3651{
3652 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
3653 struct platform_device *pdev = to_platform_device(dev);
3654 struct drm_device *drm = dev_get_drvdata(master);
3655 struct vc4_hdmi *vc4_hdmi;
3656 struct drm_encoder *encoder;
3657 struct device_node *ddc_node;
3658 int ret;
3659
3660 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL);
3661 if (!vc4_hdmi)
3662 return -ENOMEM;
3663
3664 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex);
3665 if (ret)
3666 return ret;
3667
3668 spin_lock_init(&vc4_hdmi->hw_lock);
3669 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
3670
3671 dev_set_drvdata(dev, vc4_hdmi);
3672 encoder = &vc4_hdmi->encoder.base;
3673 vc4_hdmi->encoder.type = variant->encoder_type;
3674 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
3675 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
3676 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
3677 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
3678 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
3679 vc4_hdmi->pdev = pdev;
3680 vc4_hdmi->variant = variant;
3681
3682 /*
3683 * Since we don't know the state of the controller and its
3684 * display (if any), let's assume it's always enabled.
3685 * vc4_hdmi_disable_scrambling() will thus run at boot, make
3686 * sure it's disabled, and avoid any inconsistency.
3687 */
3688 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
3689 vc4_hdmi->scdc_enabled = true;
3690
3691 ret = variant->init_resources(drm, vc4_hdmi);
3692 if (ret)
3693 return ret;
3694
3695 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
3696 if (!ddc_node) {
3697 DRM_ERROR("Failed to find ddc node in device tree\n");
3698 return -ENODEV;
3699 }
3700
3701 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
3702 of_node_put(ddc_node);
3703 if (!vc4_hdmi->ddc) {
3704 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
3705 return -EPROBE_DEFER;
3706 }
3707
3708 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi);
3709 if (ret)
3710 return ret;
3711
3712 /* Only use the GPIO HPD pin if present in the DT, otherwise
3713 * we'll use the HDMI core's register.
3714 */
3715 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
3716 if (IS_ERR(vc4_hdmi->hpd_gpio)) {
3717 return PTR_ERR(vc4_hdmi->hpd_gpio);
3718 }
3719
3720 vc4_hdmi->disable_wifi_frequencies =
3721 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
3722
3723 ret = devm_pm_runtime_enable(dev);
3724 if (ret)
3725 return ret;
3726
3727 /*
3728 * We need to have the device powered up at this point to call
3729 * our reset hook and for the CEC init.
3730 */
3731 ret = pm_runtime_resume_and_get(dev);
3732 if (ret)
3733 return ret;
3734
3735 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
3736 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
3737 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
3738 clk_prepare_enable(vc4_hdmi->pixel_clock);
3739 clk_prepare_enable(vc4_hdmi->hsm_clock);
3740 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
3741 }
3742
3743 ret = drmm_encoder_init(drm, encoder,
3744 &vc4_hdmi_encoder_funcs,
3745 DRM_MODE_ENCODER_TMDS,
3746 NULL);
3747 if (ret)
3748 goto err_put_runtime_pm;
3749
3750 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
3751
3752 ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
3753 if (ret)
3754 goto err_put_runtime_pm;
3755
3756 ret = vc4_hdmi_hotplug_init(vc4_hdmi);
3757 if (ret)
3758 goto err_put_runtime_pm;
3759
3760 ret = vc4_hdmi_cec_init(vc4_hdmi);
3761 if (ret)
3762 goto err_put_runtime_pm;
3763
3764 ret = vc4_hdmi_audio_init(vc4_hdmi);
3765 if (ret)
3766 goto err_put_runtime_pm;
3767
3768 pm_runtime_put_sync(dev);
3769
3770 return 0;
3771
3772err_put_runtime_pm:
3773 pm_runtime_put_sync(dev);
3774
3775 return ret;
3776}
3777
3778static const struct component_ops vc4_hdmi_ops = {
3779 .bind = vc4_hdmi_bind,
3780};
3781
3782static int vc4_hdmi_dev_probe(struct platform_device *pdev)
3783{
3784 return component_add(&pdev->dev, &vc4_hdmi_ops);
3785}
3786
3787static void vc4_hdmi_dev_remove(struct platform_device *pdev)
3788{
3789 component_del(&pdev->dev, &vc4_hdmi_ops);
3790}
3791
3792static const struct vc4_hdmi_variant bcm2835_variant = {
3793 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3794 .debugfs_name = "hdmi_regs",
3795 .card_name = "vc4-hdmi",
3796 .max_pixel_clock = 162000000,
3797 .registers = vc4_hdmi_fields,
3798 .num_registers = ARRAY_SIZE(vc4_hdmi_fields),
3799
3800 .init_resources = vc4_hdmi_init_resources,
3801 .csc_setup = vc4_hdmi_csc_setup,
3802 .reset = vc4_hdmi_reset,
3803 .set_timings = vc4_hdmi_set_timings,
3804 .phy_init = vc4_hdmi_phy_init,
3805 .phy_disable = vc4_hdmi_phy_disable,
3806 .phy_rng_enable = vc4_hdmi_phy_rng_enable,
3807 .phy_rng_disable = vc4_hdmi_phy_rng_disable,
3808 .channel_map = vc4_hdmi_channel_map,
3809 .supports_hdr = false,
3810};
3811
3812static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
3813 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3814 .debugfs_name = "hdmi0_regs",
3815 .card_name = "vc4-hdmi-0",
3816 .max_pixel_clock = 600000000,
3817 .registers = vc5_hdmi_hdmi0_fields,
3818 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
3819 .phy_lane_mapping = {
3820 PHY_LANE_0,
3821 PHY_LANE_1,
3822 PHY_LANE_2,
3823 PHY_LANE_CK,
3824 },
3825 .unsupported_odd_h_timings = true,
3826 .external_irq_controller = true,
3827
3828 .init_resources = vc5_hdmi_init_resources,
3829 .csc_setup = vc5_hdmi_csc_setup,
3830 .reset = vc5_hdmi_reset,
3831 .set_timings = vc5_hdmi_set_timings,
3832 .phy_init = vc5_hdmi_phy_init,
3833 .phy_disable = vc5_hdmi_phy_disable,
3834 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3835 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3836 .channel_map = vc5_hdmi_channel_map,
3837 .supports_hdr = true,
3838 .hp_detect = vc5_hdmi_hp_detect,
3839};
3840
3841static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
3842 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
3843 .debugfs_name = "hdmi1_regs",
3844 .card_name = "vc4-hdmi-1",
3845 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
3846 .registers = vc5_hdmi_hdmi1_fields,
3847 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
3848 .phy_lane_mapping = {
3849 PHY_LANE_1,
3850 PHY_LANE_0,
3851 PHY_LANE_CK,
3852 PHY_LANE_2,
3853 },
3854 .unsupported_odd_h_timings = true,
3855 .external_irq_controller = true,
3856
3857 .init_resources = vc5_hdmi_init_resources,
3858 .csc_setup = vc5_hdmi_csc_setup,
3859 .reset = vc5_hdmi_reset,
3860 .set_timings = vc5_hdmi_set_timings,
3861 .phy_init = vc5_hdmi_phy_init,
3862 .phy_disable = vc5_hdmi_phy_disable,
3863 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3864 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3865 .channel_map = vc5_hdmi_channel_map,
3866 .supports_hdr = true,
3867 .hp_detect = vc5_hdmi_hp_detect,
3868};
3869
3870static const struct of_device_id vc4_hdmi_dt_match[] = {
3871 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
3872 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
3873 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
3874 {}
3875};
3876
3877static const struct dev_pm_ops vc4_hdmi_pm_ops = {
3878 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
3879 vc4_hdmi_runtime_resume,
3880 NULL)
3881};
3882
3883struct platform_driver vc4_hdmi_driver = {
3884 .probe = vc4_hdmi_dev_probe,
3885 .remove_new = vc4_hdmi_dev_remove,
3886 .driver = {
3887 .name = "vc4_hdmi",
3888 .of_match_table = vc4_hdmi_dt_match,
3889 .pm = &vc4_hdmi_pm_ops,
3890 },
3891};