Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
7 */
8
9/**
10 * DOC: VC4 Falcon HDMI module
11 *
12 * The HDMI core has a state machine and a PHY. On BCM2835, most of
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
15 *
16 * HDMI infoframes are kept within a small packet ram, where each
17 * packet can be individually enabled for including in a frame.
18 *
19 * HDMI audio is implemented entirely within the HDMI IP block. A
20 * register in the HDMI encoder takes SPDIF frames from the DMA engine
21 * and transfers them over an internal MAI (multi-channel audio
22 * interconnect) bus to the encoder side for insertion into the video
23 * blank regions.
24 *
25 * The driver's HDMI encoder does not yet support power management.
26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27 * continuously running, and only the HDMI logic and packet ram are
28 * powered off/on at disable/enable time.
29 *
30 * The driver does not yet support CEC control, though the HDMI
31 * encoder block has CEC support.
32 */
33
34#include <drm/display/drm_hdmi_helper.h>
35#include <drm/display/drm_scdc_helper.h>
36#include <drm/drm_atomic_helper.h>
37#include <drm/drm_drv.h>
38#include <drm/drm_probe_helper.h>
39#include <drm/drm_simple_kms_helper.h>
40#include <linux/clk.h>
41#include <linux/component.h>
42#include <linux/gpio/consumer.h>
43#include <linux/i2c.h>
44#include <linux/of_address.h>
45#include <linux/of_platform.h>
46#include <linux/pm_runtime.h>
47#include <linux/rational.h>
48#include <linux/reset.h>
49#include <sound/dmaengine_pcm.h>
50#include <sound/hdmi-codec.h>
51#include <sound/pcm_drm_eld.h>
52#include <sound/pcm_params.h>
53#include <sound/soc.h>
54#include "media/cec.h"
55#include "vc4_drv.h"
56#include "vc4_hdmi.h"
57#include "vc4_hdmi_regs.h"
58#include "vc4_regs.h"
59
60#define VC5_HDMI_HORZA_HFP_SHIFT 16
61#define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
62#define VC5_HDMI_HORZA_VPOS BIT(15)
63#define VC5_HDMI_HORZA_HPOS BIT(14)
64#define VC5_HDMI_HORZA_HAP_SHIFT 0
65#define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
66
67#define VC5_HDMI_HORZB_HBP_SHIFT 16
68#define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
69#define VC5_HDMI_HORZB_HSP_SHIFT 0
70#define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
71
72#define VC5_HDMI_VERTA_VSP_SHIFT 24
73#define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
74#define VC5_HDMI_VERTA_VFP_SHIFT 16
75#define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
76#define VC5_HDMI_VERTA_VAL_SHIFT 0
77#define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
78
79#define VC5_HDMI_VERTB_VSPO_SHIFT 16
80#define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
81
82#define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
83#define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
84#define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
85#define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
86
87#define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0)
88
89#define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8
90#define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8)
91
92#define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0
93#define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0)
94
95#define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31)
96
97#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8
98#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8)
99
100#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK VC4_MASK(7, 0)
101#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE BIT(0)
102#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE BIT(4)
103
104# define VC4_HD_M_SW_RST BIT(2)
105# define VC4_HD_M_ENABLE BIT(0)
106
107#define HSM_MIN_CLOCK_FREQ 120000000
108#define CEC_CLOCK_FREQ 40000
109
110#define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
111
112static const char * const output_format_str[] = {
113 [VC4_HDMI_OUTPUT_RGB] = "RGB",
114 [VC4_HDMI_OUTPUT_YUV420] = "YUV 4:2:0",
115 [VC4_HDMI_OUTPUT_YUV422] = "YUV 4:2:2",
116 [VC4_HDMI_OUTPUT_YUV444] = "YUV 4:4:4",
117};
118
119static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt)
120{
121 if (fmt >= ARRAY_SIZE(output_format_str))
122 return "invalid";
123
124 return output_format_str[fmt];
125}
126
127static unsigned long long
128vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
129 unsigned int bpc, enum vc4_hdmi_output_format fmt);
130
131static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi)
132{
133 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
134
135 lockdep_assert_held(&vc4_hdmi->mutex);
136
137 if (!display->is_hdmi)
138 return false;
139
140 if (!display->hdmi.scdc.supported ||
141 !display->hdmi.scdc.scrambling.supported)
142 return false;
143
144 return true;
145}
146
147static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
148 unsigned int bpc,
149 enum vc4_hdmi_output_format fmt)
150{
151 unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
152
153 return clock > HDMI_14_MAX_TMDS_CLK;
154}
155
156static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi,
157 const struct drm_display_mode *mode)
158{
159 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
160
161 return !display->is_hdmi ||
162 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL;
163}
164
165static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
166{
167 struct drm_info_node *node = (struct drm_info_node *)m->private;
168 struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
169 struct drm_device *drm = vc4_hdmi->connector.dev;
170 struct drm_printer p = drm_seq_file_printer(m);
171 int idx;
172
173 if (!drm_dev_enter(drm, &idx))
174 return -ENODEV;
175
176 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
177 drm_print_regset32(&p, &vc4_hdmi->hd_regset);
178 drm_print_regset32(&p, &vc4_hdmi->cec_regset);
179 drm_print_regset32(&p, &vc4_hdmi->csc_regset);
180 drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
181 drm_print_regset32(&p, &vc4_hdmi->phy_regset);
182 drm_print_regset32(&p, &vc4_hdmi->ram_regset);
183 drm_print_regset32(&p, &vc4_hdmi->rm_regset);
184
185 drm_dev_exit(idx);
186
187 return 0;
188}
189
190static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
191{
192 struct drm_device *drm = vc4_hdmi->connector.dev;
193 unsigned long flags;
194 int idx;
195
196 /*
197 * We can be called by our bind callback, when the
198 * connector->dev pointer might not be initialised yet.
199 */
200 if (drm && !drm_dev_enter(drm, &idx))
201 return;
202
203 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
204
205 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
206 udelay(1);
207 HDMI_WRITE(HDMI_M_CTL, 0);
208
209 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
210
211 HDMI_WRITE(HDMI_SW_RESET_CONTROL,
212 VC4_HDMI_SW_RESET_HDMI |
213 VC4_HDMI_SW_RESET_FORMAT_DETECT);
214
215 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
216
217 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
218
219 if (drm)
220 drm_dev_exit(idx);
221}
222
223static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
224{
225 struct drm_device *drm = vc4_hdmi->connector.dev;
226 unsigned long flags;
227 int idx;
228
229 /*
230 * We can be called by our bind callback, when the
231 * connector->dev pointer might not be initialised yet.
232 */
233 if (drm && !drm_dev_enter(drm, &idx))
234 return;
235
236 reset_control_reset(vc4_hdmi->reset);
237
238 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
239
240 HDMI_WRITE(HDMI_DVP_CTL, 0);
241
242 HDMI_WRITE(HDMI_CLOCK_STOP,
243 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
244
245 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
246
247 if (drm)
248 drm_dev_exit(idx);
249}
250
251#ifdef CONFIG_DRM_VC4_HDMI_CEC
252static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
253{
254 struct drm_device *drm = vc4_hdmi->connector.dev;
255 unsigned long cec_rate;
256 unsigned long flags;
257 u16 clk_cnt;
258 u32 value;
259 int idx;
260
261 /*
262 * This function is called by our runtime_resume implementation
263 * and thus at bind time, when we haven't registered our
264 * connector yet and thus don't have a pointer to the DRM
265 * device.
266 */
267 if (drm && !drm_dev_enter(drm, &idx))
268 return;
269
270 cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
271
272 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
273
274 value = HDMI_READ(HDMI_CEC_CNTRL_1);
275 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
276
277 /*
278 * Set the clock divider: the hsm_clock rate and this divider
279 * setting will give a 40 kHz CEC clock.
280 */
281 clk_cnt = cec_rate / CEC_CLOCK_FREQ;
282 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
283 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
284
285 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
286
287 if (drm)
288 drm_dev_exit(idx);
289}
290#else
291static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
292#endif
293
294static int reset_pipe(struct drm_crtc *crtc,
295 struct drm_modeset_acquire_ctx *ctx)
296{
297 struct drm_atomic_state *state;
298 struct drm_crtc_state *crtc_state;
299 int ret;
300
301 state = drm_atomic_state_alloc(crtc->dev);
302 if (!state)
303 return -ENOMEM;
304
305 state->acquire_ctx = ctx;
306
307 crtc_state = drm_atomic_get_crtc_state(state, crtc);
308 if (IS_ERR(crtc_state)) {
309 ret = PTR_ERR(crtc_state);
310 goto out;
311 }
312
313 crtc_state->connectors_changed = true;
314
315 ret = drm_atomic_commit(state);
316out:
317 drm_atomic_state_put(state);
318
319 return ret;
320}
321
322static int vc4_hdmi_reset_link(struct drm_connector *connector,
323 struct drm_modeset_acquire_ctx *ctx)
324{
325 struct drm_device *drm;
326 struct vc4_hdmi *vc4_hdmi;
327 struct drm_connector_state *conn_state;
328 struct drm_crtc_state *crtc_state;
329 struct drm_crtc *crtc;
330 bool scrambling_needed;
331 u8 config;
332 int ret;
333
334 if (!connector)
335 return 0;
336
337 drm = connector->dev;
338 ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx);
339 if (ret)
340 return ret;
341
342 conn_state = connector->state;
343 crtc = conn_state->crtc;
344 if (!crtc)
345 return 0;
346
347 ret = drm_modeset_lock(&crtc->mutex, ctx);
348 if (ret)
349 return ret;
350
351 crtc_state = crtc->state;
352 if (!crtc_state->active)
353 return 0;
354
355 vc4_hdmi = connector_to_vc4_hdmi(connector);
356 mutex_lock(&vc4_hdmi->mutex);
357
358 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) {
359 mutex_unlock(&vc4_hdmi->mutex);
360 return 0;
361 }
362
363 scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode,
364 vc4_hdmi->output_bpc,
365 vc4_hdmi->output_format);
366 if (!scrambling_needed) {
367 mutex_unlock(&vc4_hdmi->mutex);
368 return 0;
369 }
370
371 if (conn_state->commit &&
372 !try_wait_for_completion(&conn_state->commit->hw_done)) {
373 mutex_unlock(&vc4_hdmi->mutex);
374 return 0;
375 }
376
377 ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);
378 if (ret < 0) {
379 drm_err(drm, "Failed to read TMDS config: %d\n", ret);
380 mutex_unlock(&vc4_hdmi->mutex);
381 return 0;
382 }
383
384 if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) {
385 mutex_unlock(&vc4_hdmi->mutex);
386 return 0;
387 }
388
389 mutex_unlock(&vc4_hdmi->mutex);
390
391 /*
392 * HDMI 2.0 says that one should not send scrambled data
393 * prior to configuring the sink scrambling, and that
394 * TMDS clock/data transmission should be suspended when
395 * changing the TMDS clock rate in the sink. So let's
396 * just do a full modeset here, even though some sinks
397 * would be perfectly happy if were to just reconfigure
398 * the SCDC settings on the fly.
399 */
400 return reset_pipe(crtc, ctx);
401}
402
403static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi,
404 struct drm_modeset_acquire_ctx *ctx,
405 enum drm_connector_status status)
406{
407 struct drm_connector *connector = &vc4_hdmi->connector;
408 struct edid *edid;
409
410 /*
411 * NOTE: This function should really be called with
412 * vc4_hdmi->mutex held, but doing so results in reentrancy
413 * issues since cec_s_phys_addr_from_edid might call
414 * .adap_enable, which leads to that funtion being called with
415 * our mutex held.
416 *
417 * A similar situation occurs with vc4_hdmi_reset_link() that
418 * will call into our KMS hooks if the scrambling was enabled.
419 *
420 * Concurrency isn't an issue at the moment since we don't share
421 * any state with any of the other frameworks so we can ignore
422 * the lock for now.
423 */
424
425 if (status == connector_status_disconnected) {
426 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
427 return;
428 }
429
430 edid = drm_get_edid(connector, vc4_hdmi->ddc);
431 if (!edid)
432 return;
433
434 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
435 kfree(edid);
436
437 vc4_hdmi_reset_link(connector, ctx);
438}
439
440static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector,
441 struct drm_modeset_acquire_ctx *ctx,
442 bool force)
443{
444 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
445 enum drm_connector_status status = connector_status_disconnected;
446
447 /*
448 * NOTE: This function should really take vc4_hdmi->mutex, but
449 * doing so results in reentrancy issues since
450 * vc4_hdmi_handle_hotplug() can call into other functions that
451 * would take the mutex while it's held here.
452 *
453 * Concurrency isn't an issue at the moment since we don't share
454 * any state with any of the other frameworks so we can ignore
455 * the lock for now.
456 */
457
458 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
459
460 if (vc4_hdmi->hpd_gpio) {
461 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
462 status = connector_status_connected;
463 } else {
464 if (vc4_hdmi->variant->hp_detect &&
465 vc4_hdmi->variant->hp_detect(vc4_hdmi))
466 status = connector_status_connected;
467 }
468
469 vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status);
470 pm_runtime_put(&vc4_hdmi->pdev->dev);
471
472 return status;
473}
474
475static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
476{
477 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
478 struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
479 int ret = 0;
480 struct edid *edid;
481
482 /*
483 * NOTE: This function should really take vc4_hdmi->mutex, but
484 * doing so results in reentrancy issues since
485 * cec_s_phys_addr_from_edid might call .adap_enable, which
486 * leads to that funtion being called with our mutex held.
487 *
488 * Concurrency isn't an issue at the moment since we don't share
489 * any state with any of the other frameworks so we can ignore
490 * the lock for now.
491 */
492
493 edid = drm_get_edid(connector, vc4_hdmi->ddc);
494 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
495 if (!edid)
496 return -ENODEV;
497
498 drm_connector_update_edid_property(connector, edid);
499 ret = drm_add_edid_modes(connector, edid);
500 kfree(edid);
501
502 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) {
503 struct drm_device *drm = connector->dev;
504 const struct drm_display_mode *mode;
505
506 list_for_each_entry(mode, &connector->probed_modes, head) {
507 if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) {
508 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
509 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
510 }
511 }
512 }
513
514 return ret;
515}
516
517static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
518 struct drm_atomic_state *state)
519{
520 struct drm_connector_state *old_state =
521 drm_atomic_get_old_connector_state(state, connector);
522 struct drm_connector_state *new_state =
523 drm_atomic_get_new_connector_state(state, connector);
524 struct drm_crtc *crtc = new_state->crtc;
525
526 if (!crtc)
527 return 0;
528
529 if (old_state->colorspace != new_state->colorspace ||
530 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
531 struct drm_crtc_state *crtc_state;
532
533 crtc_state = drm_atomic_get_crtc_state(state, crtc);
534 if (IS_ERR(crtc_state))
535 return PTR_ERR(crtc_state);
536
537 crtc_state->mode_changed = true;
538 }
539
540 return 0;
541}
542
543static void vc4_hdmi_connector_reset(struct drm_connector *connector)
544{
545 struct vc4_hdmi_connector_state *old_state =
546 conn_state_to_vc4_hdmi_conn_state(connector->state);
547 struct vc4_hdmi_connector_state *new_state =
548 kzalloc(sizeof(*new_state), GFP_KERNEL);
549
550 if (connector->state)
551 __drm_atomic_helper_connector_destroy_state(connector->state);
552
553 kfree(old_state);
554 __drm_atomic_helper_connector_reset(connector, &new_state->base);
555
556 if (!new_state)
557 return;
558
559 new_state->base.max_bpc = 8;
560 new_state->base.max_requested_bpc = 8;
561 new_state->output_format = VC4_HDMI_OUTPUT_RGB;
562 drm_atomic_helper_connector_tv_margins_reset(connector);
563}
564
565static struct drm_connector_state *
566vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
567{
568 struct drm_connector_state *conn_state = connector->state;
569 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
570 struct vc4_hdmi_connector_state *new_state;
571
572 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
573 if (!new_state)
574 return NULL;
575
576 new_state->tmds_char_rate = vc4_state->tmds_char_rate;
577 new_state->output_bpc = vc4_state->output_bpc;
578 new_state->output_format = vc4_state->output_format;
579 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
580
581 return &new_state->base;
582}
583
584static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
585 .fill_modes = drm_helper_probe_single_connector_modes,
586 .reset = vc4_hdmi_connector_reset,
587 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
588 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
589};
590
591static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
592 .detect_ctx = vc4_hdmi_connector_detect_ctx,
593 .get_modes = vc4_hdmi_connector_get_modes,
594 .atomic_check = vc4_hdmi_connector_atomic_check,
595};
596
597static int vc4_hdmi_connector_init(struct drm_device *dev,
598 struct vc4_hdmi *vc4_hdmi)
599{
600 struct drm_connector *connector = &vc4_hdmi->connector;
601 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
602 int ret;
603
604 ret = drmm_connector_init(dev, connector,
605 &vc4_hdmi_connector_funcs,
606 DRM_MODE_CONNECTOR_HDMIA,
607 vc4_hdmi->ddc);
608 if (ret)
609 return ret;
610
611 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
612
613 /*
614 * Some of the properties below require access to state, like bpc.
615 * Allocate some default initial connector state with our reset helper.
616 */
617 if (connector->funcs->reset)
618 connector->funcs->reset(connector);
619
620 /* Create and attach TV margin props to this connector. */
621 ret = drm_mode_create_tv_margin_properties(dev);
622 if (ret)
623 return ret;
624
625 ret = drm_mode_create_hdmi_colorspace_property(connector);
626 if (ret)
627 return ret;
628
629 drm_connector_attach_colorspace_property(connector);
630 drm_connector_attach_tv_margin_properties(connector);
631 drm_connector_attach_max_bpc_property(connector, 8, 12);
632
633 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
634 DRM_CONNECTOR_POLL_DISCONNECT);
635
636 connector->interlace_allowed = 1;
637 connector->doublescan_allowed = 0;
638 connector->stereo_allowed = 1;
639
640 if (vc4_hdmi->variant->supports_hdr)
641 drm_connector_attach_hdr_output_metadata_property(connector);
642
643 drm_connector_attach_encoder(connector, encoder);
644
645 return 0;
646}
647
648static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
649 enum hdmi_infoframe_type type,
650 bool poll)
651{
652 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
653 struct drm_device *drm = vc4_hdmi->connector.dev;
654 u32 packet_id = type - 0x80;
655 unsigned long flags;
656 int ret = 0;
657 int idx;
658
659 if (!drm_dev_enter(drm, &idx))
660 return -ENODEV;
661
662 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
663 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
664 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
665 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
666
667 if (poll) {
668 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
669 BIT(packet_id)), 100);
670 }
671
672 drm_dev_exit(idx);
673 return ret;
674}
675
676static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
677 union hdmi_infoframe *frame)
678{
679 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
680 struct drm_device *drm = vc4_hdmi->connector.dev;
681 u32 packet_id = frame->any.type - 0x80;
682 const struct vc4_hdmi_register *ram_packet_start =
683 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
684 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
685 u32 packet_reg_next = ram_packet_start->offset +
686 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
687 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
688 ram_packet_start->reg);
689 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
690 unsigned long flags;
691 ssize_t len, i;
692 int ret;
693 int idx;
694
695 if (!drm_dev_enter(drm, &idx))
696 return;
697
698 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
699 VC4_HDMI_RAM_PACKET_ENABLE),
700 "Packet RAM has to be on to store the packet.");
701
702 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
703 if (len < 0)
704 goto out;
705
706 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
707 if (ret) {
708 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
709 goto out;
710 }
711
712 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
713
714 for (i = 0; i < len; i += 7) {
715 writel(buffer[i + 0] << 0 |
716 buffer[i + 1] << 8 |
717 buffer[i + 2] << 16,
718 base + packet_reg);
719 packet_reg += 4;
720
721 writel(buffer[i + 3] << 0 |
722 buffer[i + 4] << 8 |
723 buffer[i + 5] << 16 |
724 buffer[i + 6] << 24,
725 base + packet_reg);
726 packet_reg += 4;
727 }
728
729 /*
730 * clear remainder of packet ram as it's included in the
731 * infoframe and triggers a checksum error on hdmi analyser
732 */
733 for (; packet_reg < packet_reg_next; packet_reg += 4)
734 writel(0, base + packet_reg);
735
736 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
737 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
738
739 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
740
741 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
742 BIT(packet_id)), 100);
743 if (ret)
744 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
745
746out:
747 drm_dev_exit(idx);
748}
749
750static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
751 enum vc4_hdmi_output_format fmt)
752{
753 switch (fmt) {
754 case VC4_HDMI_OUTPUT_RGB:
755 frame->colorspace = HDMI_COLORSPACE_RGB;
756 break;
757
758 case VC4_HDMI_OUTPUT_YUV420:
759 frame->colorspace = HDMI_COLORSPACE_YUV420;
760 break;
761
762 case VC4_HDMI_OUTPUT_YUV422:
763 frame->colorspace = HDMI_COLORSPACE_YUV422;
764 break;
765
766 case VC4_HDMI_OUTPUT_YUV444:
767 frame->colorspace = HDMI_COLORSPACE_YUV444;
768 break;
769
770 default:
771 break;
772 }
773}
774
775static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
776{
777 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
778 struct drm_connector *connector = &vc4_hdmi->connector;
779 struct drm_connector_state *cstate = connector->state;
780 struct vc4_hdmi_connector_state *vc4_state =
781 conn_state_to_vc4_hdmi_conn_state(cstate);
782 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
783 union hdmi_infoframe frame;
784 int ret;
785
786 lockdep_assert_held(&vc4_hdmi->mutex);
787
788 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
789 connector, mode);
790 if (ret < 0) {
791 DRM_ERROR("couldn't fill AVI infoframe\n");
792 return;
793 }
794
795 drm_hdmi_avi_infoframe_quant_range(&frame.avi,
796 connector, mode,
797 vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ?
798 HDMI_QUANTIZATION_RANGE_FULL :
799 HDMI_QUANTIZATION_RANGE_LIMITED);
800 drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate);
801 vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format);
802 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
803
804 vc4_hdmi_write_infoframe(encoder, &frame);
805}
806
807static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
808{
809 union hdmi_infoframe frame;
810 int ret;
811
812 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
813 if (ret < 0) {
814 DRM_ERROR("couldn't fill SPD infoframe\n");
815 return;
816 }
817
818 frame.spd.sdi = HDMI_SPD_SDI_PC;
819
820 vc4_hdmi_write_infoframe(encoder, &frame);
821}
822
823static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
824{
825 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
826 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
827 union hdmi_infoframe frame;
828
829 memcpy(&frame.audio, audio, sizeof(*audio));
830
831 if (vc4_hdmi->packet_ram_enabled)
832 vc4_hdmi_write_infoframe(encoder, &frame);
833}
834
835static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
836{
837 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
838 struct drm_connector *connector = &vc4_hdmi->connector;
839 struct drm_connector_state *conn_state = connector->state;
840 union hdmi_infoframe frame;
841
842 lockdep_assert_held(&vc4_hdmi->mutex);
843
844 if (!vc4_hdmi->variant->supports_hdr)
845 return;
846
847 if (!conn_state->hdr_output_metadata)
848 return;
849
850 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
851 return;
852
853 vc4_hdmi_write_infoframe(encoder, &frame);
854}
855
856static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
857{
858 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
859
860 lockdep_assert_held(&vc4_hdmi->mutex);
861
862 vc4_hdmi_set_avi_infoframe(encoder);
863 vc4_hdmi_set_spd_infoframe(encoder);
864 /*
865 * If audio was streaming, then we need to reenabled the audio
866 * infoframe here during encoder_enable.
867 */
868 if (vc4_hdmi->audio.streaming)
869 vc4_hdmi_set_audio_infoframe(encoder);
870
871 vc4_hdmi_set_hdr_infoframe(encoder);
872}
873
874#define SCRAMBLING_POLLING_DELAY_MS 1000
875
876static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
877{
878 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
879 struct drm_device *drm = vc4_hdmi->connector.dev;
880 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
881 unsigned long flags;
882 int idx;
883
884 lockdep_assert_held(&vc4_hdmi->mutex);
885
886 if (!vc4_hdmi_supports_scrambling(vc4_hdmi))
887 return;
888
889 if (!vc4_hdmi_mode_needs_scrambling(mode,
890 vc4_hdmi->output_bpc,
891 vc4_hdmi->output_format))
892 return;
893
894 if (!drm_dev_enter(drm, &idx))
895 return;
896
897 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
898 drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
899
900 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
901 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
902 VC5_HDMI_SCRAMBLER_CTL_ENABLE);
903 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
904
905 drm_dev_exit(idx);
906
907 vc4_hdmi->scdc_enabled = true;
908
909 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
910 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
911}
912
913static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
914{
915 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
916 struct drm_device *drm = vc4_hdmi->connector.dev;
917 unsigned long flags;
918 int idx;
919
920 lockdep_assert_held(&vc4_hdmi->mutex);
921
922 if (!vc4_hdmi->scdc_enabled)
923 return;
924
925 vc4_hdmi->scdc_enabled = false;
926
927 if (delayed_work_pending(&vc4_hdmi->scrambling_work))
928 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
929
930 if (!drm_dev_enter(drm, &idx))
931 return;
932
933 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
934 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
935 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
936 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
937
938 drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
939 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
940
941 drm_dev_exit(idx);
942}
943
944static void vc4_hdmi_scrambling_wq(struct work_struct *work)
945{
946 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
947 struct vc4_hdmi,
948 scrambling_work);
949
950 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
951 return;
952
953 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
954 drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
955
956 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
957 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
958}
959
960static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
961 struct drm_atomic_state *state)
962{
963 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
964 struct drm_device *drm = vc4_hdmi->connector.dev;
965 unsigned long flags;
966 int idx;
967
968 mutex_lock(&vc4_hdmi->mutex);
969
970 vc4_hdmi->packet_ram_enabled = false;
971
972 if (!drm_dev_enter(drm, &idx))
973 goto out;
974
975 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
976
977 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
978
979 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
980
981 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
982
983 mdelay(1);
984
985 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
986 HDMI_WRITE(HDMI_VID_CTL,
987 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
988 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
989
990 vc4_hdmi_disable_scrambling(encoder);
991
992 drm_dev_exit(idx);
993
994out:
995 mutex_unlock(&vc4_hdmi->mutex);
996}
997
998static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
999 struct drm_atomic_state *state)
1000{
1001 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1002 struct drm_device *drm = vc4_hdmi->connector.dev;
1003 unsigned long flags;
1004 int ret;
1005 int idx;
1006
1007 mutex_lock(&vc4_hdmi->mutex);
1008
1009 if (!drm_dev_enter(drm, &idx))
1010 goto out;
1011
1012 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1013 HDMI_WRITE(HDMI_VID_CTL,
1014 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
1015 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1016
1017 if (vc4_hdmi->variant->phy_disable)
1018 vc4_hdmi->variant->phy_disable(vc4_hdmi);
1019
1020 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
1021 clk_disable_unprepare(vc4_hdmi->pixel_clock);
1022
1023 ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
1024 if (ret < 0)
1025 DRM_ERROR("Failed to release power domain: %d\n", ret);
1026
1027 drm_dev_exit(idx);
1028
1029out:
1030 mutex_unlock(&vc4_hdmi->mutex);
1031}
1032
1033static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1034 struct drm_connector_state *state,
1035 const struct drm_display_mode *mode)
1036{
1037 struct drm_device *drm = vc4_hdmi->connector.dev;
1038 unsigned long flags;
1039 u32 csc_ctl;
1040 int idx;
1041
1042 if (!drm_dev_enter(drm, &idx))
1043 return;
1044
1045 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1046
1047 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
1048 VC4_HD_CSC_CTL_ORDER);
1049
1050 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) {
1051 /* CEA VICs other than #1 requre limited range RGB
1052 * output unless overridden by an AVI infoframe.
1053 * Apply a colorspace conversion to squash 0-255 down
1054 * to 16-235. The matrix here is:
1055 *
1056 * [ 0 0 0.8594 16]
1057 * [ 0 0.8594 0 16]
1058 * [ 0.8594 0 0 16]
1059 * [ 0 0 0 1]
1060 */
1061 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
1062 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
1063 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1064 VC4_HD_CSC_CTL_MODE);
1065
1066 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
1067 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
1068 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
1069 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
1070 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
1071 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
1072 }
1073
1074 /* The RGB order applies even when CSC is disabled. */
1075 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1076
1077 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1078
1079 drm_dev_exit(idx);
1080}
1081
1082/*
1083 * If we need to output Full Range RGB, then use the unity matrix
1084 *
1085 * [ 1 0 0 0]
1086 * [ 0 1 0 0]
1087 * [ 0 0 1 0]
1088 *
1089 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1090 */
1091static const u16 vc5_hdmi_csc_full_rgb_unity[3][4] = {
1092 { 0x2000, 0x0000, 0x0000, 0x0000 },
1093 { 0x0000, 0x2000, 0x0000, 0x0000 },
1094 { 0x0000, 0x0000, 0x2000, 0x0000 },
1095};
1096
1097/*
1098 * CEA VICs other than #1 require limited range RGB output unless
1099 * overridden by an AVI infoframe. Apply a colorspace conversion to
1100 * squash 0-255 down to 16-235. The matrix here is:
1101 *
1102 * [ 0.8594 0 0 16]
1103 * [ 0 0.8594 0 16]
1104 * [ 0 0 0.8594 16]
1105 *
1106 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1107 */
1108static const u16 vc5_hdmi_csc_full_rgb_to_limited_rgb[3][4] = {
1109 { 0x1b80, 0x0000, 0x0000, 0x0400 },
1110 { 0x0000, 0x1b80, 0x0000, 0x0400 },
1111 { 0x0000, 0x0000, 0x1b80, 0x0400 },
1112};
1113
1114/*
1115 * Conversion between Full Range RGB and Full Range YUV422 using the
1116 * BT.709 Colorspace
1117 *
1118 *
1119 * [ 0.181906 0.611804 0.061758 16 ]
1120 * [ -0.100268 -0.337232 0.437500 128 ]
1121 * [ 0.437500 -0.397386 -0.040114 128 ]
1122 *
1123 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1124 */
1125static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709[3][4] = {
1126 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1127 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1128 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1129};
1130
1131/*
1132 * Conversion between Full Range RGB and Full Range YUV444 using the
1133 * BT.709 Colorspace
1134 *
1135 * [ -0.100268 -0.337232 0.437500 128 ]
1136 * [ 0.437500 -0.397386 -0.040114 128 ]
1137 * [ 0.181906 0.611804 0.061758 16 ]
1138 *
1139 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1140 */
1141static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709[3][4] = {
1142 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1143 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1144 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1145};
1146
1147static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
1148 const u16 coeffs[3][4])
1149{
1150 lockdep_assert_held(&vc4_hdmi->hw_lock);
1151
1152 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
1153 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
1154 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
1155 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
1156 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
1157 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
1158}
1159
1160static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1161 struct drm_connector_state *state,
1162 const struct drm_display_mode *mode)
1163{
1164 struct drm_device *drm = vc4_hdmi->connector.dev;
1165 struct vc4_hdmi_connector_state *vc4_state =
1166 conn_state_to_vc4_hdmi_conn_state(state);
1167 unsigned long flags;
1168 u32 if_cfg = 0;
1169 u32 if_xbar = 0x543210;
1170 u32 csc_chan_ctl = 0;
1171 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1172 VC5_MT_CP_CSC_CTL_MODE);
1173 int idx;
1174
1175 if (!drm_dev_enter(drm, &idx))
1176 return;
1177
1178 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1179
1180 switch (vc4_state->output_format) {
1181 case VC4_HDMI_OUTPUT_YUV444:
1182 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709);
1183 break;
1184
1185 case VC4_HDMI_OUTPUT_YUV422:
1186 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
1187 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) |
1188 VC5_MT_CP_CSC_CTL_USE_444_TO_422 |
1189 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION;
1190
1191 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
1192 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP);
1193
1194 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
1195 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422);
1196
1197 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709);
1198 break;
1199
1200 case VC4_HDMI_OUTPUT_RGB:
1201 if_xbar = 0x354021;
1202
1203 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode))
1204 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb);
1205 else
1206 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity);
1207 break;
1208
1209 default:
1210 break;
1211 }
1212
1213 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg);
1214 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar);
1215 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl);
1216 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1217
1218 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1219
1220 drm_dev_exit(idx);
1221}
1222
1223static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1224 struct drm_connector_state *state,
1225 const struct drm_display_mode *mode)
1226{
1227 struct drm_device *drm = vc4_hdmi->connector.dev;
1228 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1229 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1230 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1231 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1232 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1233 VC4_HDMI_VERTA_VSP) |
1234 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1235 VC4_HDMI_VERTA_VFP) |
1236 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
1237 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1238 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1239 interlaced,
1240 VC4_HDMI_VERTB_VBP));
1241 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1242 VC4_SET_FIELD(mode->crtc_vtotal -
1243 mode->crtc_vsync_end,
1244 VC4_HDMI_VERTB_VBP));
1245 unsigned long flags;
1246 u32 reg;
1247 int idx;
1248
1249 if (!drm_dev_enter(drm, &idx))
1250 return;
1251
1252 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1253
1254 HDMI_WRITE(HDMI_HORZA,
1255 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
1256 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
1257 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1258 VC4_HDMI_HORZA_HAP));
1259
1260 HDMI_WRITE(HDMI_HORZB,
1261 VC4_SET_FIELD((mode->htotal -
1262 mode->hsync_end) * pixel_rep,
1263 VC4_HDMI_HORZB_HBP) |
1264 VC4_SET_FIELD((mode->hsync_end -
1265 mode->hsync_start) * pixel_rep,
1266 VC4_HDMI_HORZB_HSP) |
1267 VC4_SET_FIELD((mode->hsync_start -
1268 mode->hdisplay) * pixel_rep,
1269 VC4_HDMI_HORZB_HFP));
1270
1271 HDMI_WRITE(HDMI_VERTA0, verta);
1272 HDMI_WRITE(HDMI_VERTA1, verta);
1273
1274 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1275 HDMI_WRITE(HDMI_VERTB1, vertb);
1276
1277 reg = HDMI_READ(HDMI_MISC_CONTROL);
1278 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1279 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP);
1280 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1281
1282 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1283
1284 drm_dev_exit(idx);
1285}
1286
1287static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1288 struct drm_connector_state *state,
1289 const struct drm_display_mode *mode)
1290{
1291 struct drm_device *drm = vc4_hdmi->connector.dev;
1292 const struct vc4_hdmi_connector_state *vc4_state =
1293 conn_state_to_vc4_hdmi_conn_state(state);
1294 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1295 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1296 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1297 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1298 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1299 VC5_HDMI_VERTA_VSP) |
1300 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1301 VC5_HDMI_VERTA_VFP) |
1302 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
1303 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
1304 VC5_HDMI_VERTB_VSPO) |
1305 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
1306 VC4_HDMI_VERTB_VBP));
1307 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
1308 VC4_SET_FIELD(mode->crtc_vtotal -
1309 mode->crtc_vsync_end - interlaced,
1310 VC4_HDMI_VERTB_VBP));
1311 unsigned long flags;
1312 unsigned char gcp;
1313 u32 reg;
1314 int idx;
1315
1316 if (!drm_dev_enter(drm, &idx))
1317 return;
1318
1319 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1320
1321 HDMI_WRITE(HDMI_HORZA,
1322 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
1323 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
1324 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1325 VC5_HDMI_HORZA_HAP) |
1326 VC4_SET_FIELD((mode->hsync_start -
1327 mode->hdisplay) * pixel_rep,
1328 VC5_HDMI_HORZA_HFP));
1329
1330 HDMI_WRITE(HDMI_HORZB,
1331 VC4_SET_FIELD((mode->htotal -
1332 mode->hsync_end) * pixel_rep,
1333 VC5_HDMI_HORZB_HBP) |
1334 VC4_SET_FIELD((mode->hsync_end -
1335 mode->hsync_start) * pixel_rep,
1336 VC5_HDMI_HORZB_HSP));
1337
1338 HDMI_WRITE(HDMI_VERTA0, verta);
1339 HDMI_WRITE(HDMI_VERTA1, verta);
1340
1341 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1342 HDMI_WRITE(HDMI_VERTB1, vertb);
1343
1344 switch (vc4_state->output_bpc) {
1345 case 12:
1346 gcp = 6;
1347 break;
1348 case 10:
1349 gcp = 5;
1350 break;
1351 case 8:
1352 default:
1353 gcp = 0;
1354 break;
1355 }
1356
1357 /*
1358 * YCC422 is always 36-bit and not considered deep colour so
1359 * doesn't signal in GCP.
1360 */
1361 if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) {
1362 gcp = 0;
1363 }
1364
1365 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
1366 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
1367 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
1368 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
1369 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
1370 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
1371
1372 reg = HDMI_READ(HDMI_GCP_WORD_1);
1373 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
1374 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
1375 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK;
1376 reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE;
1377 HDMI_WRITE(HDMI_GCP_WORD_1, reg);
1378
1379 reg = HDMI_READ(HDMI_GCP_CONFIG);
1380 reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
1381 HDMI_WRITE(HDMI_GCP_CONFIG, reg);
1382
1383 reg = HDMI_READ(HDMI_MISC_CONTROL);
1384 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1385 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
1386 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1387
1388 HDMI_WRITE(HDMI_CLOCK_STOP, 0);
1389
1390 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1391
1392 drm_dev_exit(idx);
1393}
1394
1395static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
1396{
1397 struct drm_device *drm = vc4_hdmi->connector.dev;
1398 unsigned long flags;
1399 u32 drift;
1400 int ret;
1401 int idx;
1402
1403 if (!drm_dev_enter(drm, &idx))
1404 return;
1405
1406 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1407
1408 drift = HDMI_READ(HDMI_FIFO_CTL);
1409 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1410
1411 HDMI_WRITE(HDMI_FIFO_CTL,
1412 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1413 HDMI_WRITE(HDMI_FIFO_CTL,
1414 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1415
1416 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1417
1418 usleep_range(1000, 1100);
1419
1420 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1421
1422 HDMI_WRITE(HDMI_FIFO_CTL,
1423 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1424 HDMI_WRITE(HDMI_FIFO_CTL,
1425 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1426
1427 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1428
1429 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1430 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1431 WARN_ONCE(ret, "Timeout waiting for "
1432 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1433
1434 drm_dev_exit(idx);
1435}
1436
1437static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1438 struct drm_atomic_state *state)
1439{
1440 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1441 struct drm_device *drm = vc4_hdmi->connector.dev;
1442 struct drm_connector *connector = &vc4_hdmi->connector;
1443 struct drm_connector_state *conn_state =
1444 drm_atomic_get_new_connector_state(state, connector);
1445 struct vc4_hdmi_connector_state *vc4_conn_state =
1446 conn_state_to_vc4_hdmi_conn_state(conn_state);
1447 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1448 unsigned long tmds_char_rate = vc4_conn_state->tmds_char_rate;
1449 unsigned long bvb_rate, hsm_rate;
1450 unsigned long flags;
1451 int ret;
1452 int idx;
1453
1454 mutex_lock(&vc4_hdmi->mutex);
1455
1456 if (!drm_dev_enter(drm, &idx))
1457 goto out;
1458
1459 /*
1460 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1461 * be faster than pixel clock, infinitesimally faster, tested in
1462 * simulation. Otherwise, exact value is unimportant for HDMI
1463 * operation." This conflicts with bcm2835's vc4 documentation, which
1464 * states HSM's clock has to be at least 108% of the pixel clock.
1465 *
1466 * Real life tests reveal that vc4's firmware statement holds up, and
1467 * users are able to use pixel clocks closer to HSM's, namely for
1468 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1469 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1470 * 162MHz.
1471 *
1472 * Additionally, the AXI clock needs to be at least 25% of
1473 * pixel clock, but HSM ends up being the limiting factor.
1474 */
1475 hsm_rate = max_t(unsigned long, 120000000, (tmds_char_rate / 100) * 101);
1476 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1477 if (ret) {
1478 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1479 goto err_dev_exit;
1480 }
1481
1482 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1483 if (ret < 0) {
1484 DRM_ERROR("Failed to retain power domain: %d\n", ret);
1485 goto err_dev_exit;
1486 }
1487
1488 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate);
1489 if (ret) {
1490 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1491 goto err_put_runtime_pm;
1492 }
1493
1494 ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1495 if (ret) {
1496 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1497 goto err_put_runtime_pm;
1498 }
1499
1500
1501 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1502
1503 if (tmds_char_rate > 297000000)
1504 bvb_rate = 300000000;
1505 else if (tmds_char_rate > 148500000)
1506 bvb_rate = 150000000;
1507 else
1508 bvb_rate = 75000000;
1509
1510 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1511 if (ret) {
1512 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1513 goto err_disable_pixel_clock;
1514 }
1515
1516 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1517 if (ret) {
1518 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1519 goto err_disable_pixel_clock;
1520 }
1521
1522 if (vc4_hdmi->variant->phy_init)
1523 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
1524
1525 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1526
1527 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1528 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1529 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1530 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1531
1532 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1533
1534 if (vc4_hdmi->variant->set_timings)
1535 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1536
1537 drm_dev_exit(idx);
1538
1539 mutex_unlock(&vc4_hdmi->mutex);
1540
1541 return;
1542
1543err_disable_pixel_clock:
1544 clk_disable_unprepare(vc4_hdmi->pixel_clock);
1545err_put_runtime_pm:
1546 pm_runtime_put(&vc4_hdmi->pdev->dev);
1547err_dev_exit:
1548 drm_dev_exit(idx);
1549out:
1550 mutex_unlock(&vc4_hdmi->mutex);
1551 return;
1552}
1553
1554static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1555 struct drm_atomic_state *state)
1556{
1557 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1558 struct drm_device *drm = vc4_hdmi->connector.dev;
1559 struct drm_connector *connector = &vc4_hdmi->connector;
1560 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1561 struct drm_connector_state *conn_state =
1562 drm_atomic_get_new_connector_state(state, connector);
1563 unsigned long flags;
1564 int idx;
1565
1566 mutex_lock(&vc4_hdmi->mutex);
1567
1568 if (!drm_dev_enter(drm, &idx))
1569 goto out;
1570
1571 if (vc4_hdmi->variant->csc_setup)
1572 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1573
1574 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1575 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1576 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1577
1578 drm_dev_exit(idx);
1579
1580out:
1581 mutex_unlock(&vc4_hdmi->mutex);
1582}
1583
1584static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1585 struct drm_atomic_state *state)
1586{
1587 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1588 struct drm_device *drm = vc4_hdmi->connector.dev;
1589 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1590 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1591 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1592 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1593 unsigned long flags;
1594 int ret;
1595 int idx;
1596
1597 mutex_lock(&vc4_hdmi->mutex);
1598
1599 if (!drm_dev_enter(drm, &idx))
1600 goto out;
1601
1602 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1603
1604 HDMI_WRITE(HDMI_VID_CTL,
1605 VC4_HD_VID_CTL_ENABLE |
1606 VC4_HD_VID_CTL_CLRRGB |
1607 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1608 VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1609 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1610 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1611
1612 HDMI_WRITE(HDMI_VID_CTL,
1613 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1614
1615 if (display->is_hdmi) {
1616 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1617 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1618 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1619
1620 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1621
1622 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1623 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1624 WARN_ONCE(ret, "Timeout waiting for "
1625 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1626 } else {
1627 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1628 HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1629 ~(VC4_HDMI_RAM_PACKET_ENABLE));
1630 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1631 HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1632 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1633
1634 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1635
1636 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1637 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1638 WARN_ONCE(ret, "Timeout waiting for "
1639 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1640 }
1641
1642 if (display->is_hdmi) {
1643 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1644
1645 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1646 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1647
1648 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1649 VC4_HDMI_RAM_PACKET_ENABLE);
1650
1651 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1652 vc4_hdmi->packet_ram_enabled = true;
1653
1654 vc4_hdmi_set_infoframes(encoder);
1655 }
1656
1657 vc4_hdmi_recenter_fifo(vc4_hdmi);
1658 vc4_hdmi_enable_scrambling(encoder);
1659
1660 drm_dev_exit(idx);
1661
1662out:
1663 mutex_unlock(&vc4_hdmi->mutex);
1664}
1665
1666static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1667 struct drm_crtc_state *crtc_state,
1668 struct drm_connector_state *conn_state)
1669{
1670 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1671 struct vc4_hdmi_connector_state *vc4_state =
1672 conn_state_to_vc4_hdmi_conn_state(conn_state);
1673
1674 mutex_lock(&vc4_hdmi->mutex);
1675 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode,
1676 &crtc_state->adjusted_mode);
1677 vc4_hdmi->output_bpc = vc4_state->output_bpc;
1678 vc4_hdmi->output_format = vc4_state->output_format;
1679 mutex_unlock(&vc4_hdmi->mutex);
1680}
1681
1682static bool
1683vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi,
1684 const struct drm_display_info *info,
1685 const struct drm_display_mode *mode,
1686 unsigned int format, unsigned int bpc)
1687{
1688 struct drm_device *dev = vc4_hdmi->connector.dev;
1689 u8 vic = drm_match_cea_mode(mode);
1690
1691 if (vic == 1 && bpc != 8) {
1692 drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc);
1693 return false;
1694 }
1695
1696 if (!info->is_hdmi &&
1697 (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) {
1698 drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n");
1699 return false;
1700 }
1701
1702 switch (format) {
1703 case VC4_HDMI_OUTPUT_RGB:
1704 drm_dbg(dev, "RGB Format, checking the constraints.\n");
1705
1706 if (!(info->color_formats & DRM_COLOR_FORMAT_RGB444))
1707 return false;
1708
1709 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1710 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1711 return false;
1712 }
1713
1714 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1715 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1716 return false;
1717 }
1718
1719 drm_dbg(dev, "RGB format supported in that configuration.\n");
1720
1721 return true;
1722
1723 case VC4_HDMI_OUTPUT_YUV422:
1724 drm_dbg(dev, "YUV422 format, checking the constraints.\n");
1725
1726 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) {
1727 drm_dbg(dev, "Sink doesn't support YUV422.\n");
1728 return false;
1729 }
1730
1731 if (bpc != 12) {
1732 drm_dbg(dev, "YUV422 only supports 12 bpc.\n");
1733 return false;
1734 }
1735
1736 drm_dbg(dev, "YUV422 format supported in that configuration.\n");
1737
1738 return true;
1739
1740 case VC4_HDMI_OUTPUT_YUV444:
1741 drm_dbg(dev, "YUV444 format, checking the constraints.\n");
1742
1743 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR444)) {
1744 drm_dbg(dev, "Sink doesn't support YUV444.\n");
1745 return false;
1746 }
1747
1748 if (bpc == 10 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1749 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1750 return false;
1751 }
1752
1753 if (bpc == 12 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1754 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1755 return false;
1756 }
1757
1758 drm_dbg(dev, "YUV444 format supported in that configuration.\n");
1759
1760 return true;
1761 }
1762
1763 return false;
1764}
1765
1766static enum drm_mode_status
1767vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi,
1768 const struct drm_display_mode *mode,
1769 unsigned long long clock)
1770{
1771 const struct drm_connector *connector = &vc4_hdmi->connector;
1772 const struct drm_display_info *info = &connector->display_info;
1773 struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
1774
1775 if (clock > vc4_hdmi->variant->max_pixel_clock)
1776 return MODE_CLOCK_HIGH;
1777
1778 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK)
1779 return MODE_CLOCK_HIGH;
1780
1781 /* 4096x2160@60 is not reliable without overclocking core */
1782 if (!vc4->hvs->vc5_hdmi_enable_4096by2160 &&
1783 mode->hdisplay > 3840 && mode->vdisplay >= 2160 &&
1784 drm_mode_vrefresh(mode) >= 50)
1785 return MODE_CLOCK_HIGH;
1786
1787 if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000))
1788 return MODE_CLOCK_HIGH;
1789
1790 return MODE_OK;
1791}
1792
1793static unsigned long long
1794vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
1795 unsigned int bpc,
1796 enum vc4_hdmi_output_format fmt)
1797{
1798 unsigned long long clock = mode->clock * 1000ULL;
1799
1800 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1801 clock = clock * 2;
1802
1803 if (fmt == VC4_HDMI_OUTPUT_YUV422)
1804 bpc = 8;
1805
1806 clock = clock * bpc;
1807 do_div(clock, 8);
1808
1809 return clock;
1810}
1811
1812static int
1813vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi,
1814 struct vc4_hdmi_connector_state *vc4_state,
1815 const struct drm_display_mode *mode,
1816 unsigned int bpc, unsigned int fmt)
1817{
1818 unsigned long long clock;
1819
1820 clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
1821 if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, clock) != MODE_OK)
1822 return -EINVAL;
1823
1824 vc4_state->tmds_char_rate = clock;
1825
1826 return 0;
1827}
1828
1829static int
1830vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi,
1831 struct vc4_hdmi_connector_state *vc4_state,
1832 const struct drm_display_mode *mode,
1833 unsigned int bpc)
1834{
1835 struct drm_device *dev = vc4_hdmi->connector.dev;
1836 const struct drm_connector *connector = &vc4_hdmi->connector;
1837 const struct drm_display_info *info = &connector->display_info;
1838 unsigned int format;
1839
1840 drm_dbg(dev, "Trying with an RGB output\n");
1841
1842 format = VC4_HDMI_OUTPUT_RGB;
1843 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
1844 int ret;
1845
1846 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
1847 mode, bpc, format);
1848 if (!ret) {
1849 vc4_state->output_format = format;
1850 return 0;
1851 }
1852 }
1853
1854 drm_dbg(dev, "Failed, Trying with an YUV422 output\n");
1855
1856 format = VC4_HDMI_OUTPUT_YUV422;
1857 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
1858 int ret;
1859
1860 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
1861 mode, bpc, format);
1862 if (!ret) {
1863 vc4_state->output_format = format;
1864 return 0;
1865 }
1866 }
1867
1868 drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n");
1869
1870 return -EINVAL;
1871}
1872
1873static int
1874vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi,
1875 struct vc4_hdmi_connector_state *vc4_state,
1876 const struct drm_display_mode *mode)
1877{
1878 struct drm_device *dev = vc4_hdmi->connector.dev;
1879 struct drm_connector_state *conn_state = &vc4_state->base;
1880 unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12);
1881 unsigned int bpc;
1882 int ret;
1883
1884 for (bpc = max_bpc; bpc >= 8; bpc -= 2) {
1885 drm_dbg(dev, "Trying with a %d bpc output\n", bpc);
1886
1887 ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state,
1888 mode, bpc);
1889 if (ret)
1890 continue;
1891
1892 vc4_state->output_bpc = bpc;
1893
1894 drm_dbg(dev,
1895 "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n",
1896 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
1897 vc4_state->output_bpc,
1898 vc4_hdmi_output_fmt_str(vc4_state->output_format),
1899 vc4_state->tmds_char_rate);
1900
1901 break;
1902 }
1903
1904 return ret;
1905}
1906
1907#define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
1908#define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
1909
1910static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1911 struct drm_crtc_state *crtc_state,
1912 struct drm_connector_state *conn_state)
1913{
1914 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1915 struct drm_connector *connector = &vc4_hdmi->connector;
1916 struct drm_connector_state *old_conn_state =
1917 drm_atomic_get_old_connector_state(conn_state->state, connector);
1918 struct vc4_hdmi_connector_state *old_vc4_state =
1919 conn_state_to_vc4_hdmi_conn_state(old_conn_state);
1920 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1921 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1922 unsigned long long tmds_char_rate = mode->clock * 1000;
1923 unsigned long long tmds_bit_rate;
1924 int ret;
1925
1926 if (vc4_hdmi->variant->unsupported_odd_h_timings) {
1927 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1928 /* Only try to fixup DBLCLK modes to get 480i and 576i
1929 * working.
1930 * A generic solution for all modes with odd horizontal
1931 * timing values seems impossible based on trying to
1932 * solve it for 1366x768 monitors.
1933 */
1934 if ((mode->hsync_start - mode->hdisplay) & 1)
1935 mode->hsync_start--;
1936 if ((mode->hsync_end - mode->hsync_start) & 1)
1937 mode->hsync_end--;
1938 }
1939
1940 /* Now check whether we still have odd values remaining */
1941 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1942 (mode->hsync_end % 2) || (mode->htotal % 2))
1943 return -EINVAL;
1944 }
1945
1946 /*
1947 * The 1440p@60 pixel rate is in the same range than the first
1948 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1949 * bandwidth). Slightly lower the frequency to bring it out of
1950 * the WiFi range.
1951 */
1952 tmds_bit_rate = tmds_char_rate * 10;
1953 if (vc4_hdmi->disable_wifi_frequencies &&
1954 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1955 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1956 mode->clock = 238560;
1957 tmds_char_rate = mode->clock * 1000;
1958 }
1959
1960 ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode);
1961 if (ret)
1962 return ret;
1963
1964 /* vc4_hdmi_encoder_compute_config may have changed output_bpc and/or output_format */
1965 if (vc4_state->output_bpc != old_vc4_state->output_bpc ||
1966 vc4_state->output_format != old_vc4_state->output_format)
1967 crtc_state->mode_changed = true;
1968
1969 return 0;
1970}
1971
1972static enum drm_mode_status
1973vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1974 const struct drm_display_mode *mode)
1975{
1976 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1977
1978 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1979 !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1980 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1981 (mode->hsync_end % 2) || (mode->htotal % 2)))
1982 return MODE_H_ILLEGAL;
1983
1984 return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, mode->clock * 1000);
1985}
1986
1987static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1988 .atomic_check = vc4_hdmi_encoder_atomic_check,
1989 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
1990 .mode_valid = vc4_hdmi_encoder_mode_valid,
1991};
1992
1993static int vc4_hdmi_late_register(struct drm_encoder *encoder)
1994{
1995 struct drm_device *drm = encoder->dev;
1996 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1997 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1998 int ret;
1999
2000 ret = vc4_debugfs_add_file(drm->primary, variant->debugfs_name,
2001 vc4_hdmi_debugfs_regs,
2002 vc4_hdmi);
2003 if (ret)
2004 return ret;
2005
2006 return 0;
2007}
2008
2009static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
2010 .late_register = vc4_hdmi_late_register,
2011};
2012
2013static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
2014{
2015 int i;
2016 u32 channel_map = 0;
2017
2018 for (i = 0; i < 8; i++) {
2019 if (channel_mask & BIT(i))
2020 channel_map |= i << (3 * i);
2021 }
2022 return channel_map;
2023}
2024
2025static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
2026{
2027 int i;
2028 u32 channel_map = 0;
2029
2030 for (i = 0; i < 8; i++) {
2031 if (channel_mask & BIT(i))
2032 channel_map |= i << (4 * i);
2033 }
2034 return channel_map;
2035}
2036
2037static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
2038{
2039 struct drm_device *drm = vc4_hdmi->connector.dev;
2040 unsigned long flags;
2041 u32 hotplug;
2042 int idx;
2043
2044 if (!drm_dev_enter(drm, &idx))
2045 return false;
2046
2047 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2048 hotplug = HDMI_READ(HDMI_HOTPLUG);
2049 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2050
2051 drm_dev_exit(idx);
2052
2053 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
2054}
2055
2056/* HDMI audio codec callbacks */
2057static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
2058 unsigned int samplerate)
2059{
2060 struct drm_device *drm = vc4_hdmi->connector.dev;
2061 u32 hsm_clock;
2062 unsigned long flags;
2063 unsigned long n, m;
2064 int idx;
2065
2066 if (!drm_dev_enter(drm, &idx))
2067 return;
2068
2069 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
2070 rational_best_approximation(hsm_clock, samplerate,
2071 VC4_HD_MAI_SMP_N_MASK >>
2072 VC4_HD_MAI_SMP_N_SHIFT,
2073 (VC4_HD_MAI_SMP_M_MASK >>
2074 VC4_HD_MAI_SMP_M_SHIFT) + 1,
2075 &n, &m);
2076
2077 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2078 HDMI_WRITE(HDMI_MAI_SMP,
2079 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
2080 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
2081 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2082
2083 drm_dev_exit(idx);
2084}
2085
2086static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
2087{
2088 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
2089 u32 n, cts;
2090 u64 tmp;
2091
2092 lockdep_assert_held(&vc4_hdmi->mutex);
2093 lockdep_assert_held(&vc4_hdmi->hw_lock);
2094
2095 n = 128 * samplerate / 1000;
2096 tmp = (u64)(mode->clock * 1000) * n;
2097 do_div(tmp, 128 * samplerate);
2098 cts = tmp;
2099
2100 HDMI_WRITE(HDMI_CRP_CFG,
2101 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
2102 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
2103
2104 /*
2105 * We could get slightly more accurate clocks in some cases by
2106 * providing a CTS_1 value. The two CTS values are alternated
2107 * between based on the period fields
2108 */
2109 HDMI_WRITE(HDMI_CTS_0, cts);
2110 HDMI_WRITE(HDMI_CTS_1, cts);
2111}
2112
2113static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
2114{
2115 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
2116
2117 return snd_soc_card_get_drvdata(card);
2118}
2119
2120static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
2121{
2122 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
2123
2124 lockdep_assert_held(&vc4_hdmi->mutex);
2125
2126 /*
2127 * If the encoder is currently in DVI mode, treat the codec DAI
2128 * as missing.
2129 */
2130 if (!display->is_hdmi)
2131 return false;
2132
2133 return true;
2134}
2135
2136static int vc4_hdmi_audio_startup(struct device *dev, void *data)
2137{
2138 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2139 struct drm_device *drm = vc4_hdmi->connector.dev;
2140 unsigned long flags;
2141 int ret = 0;
2142 int idx;
2143
2144 mutex_lock(&vc4_hdmi->mutex);
2145
2146 if (!drm_dev_enter(drm, &idx)) {
2147 ret = -ENODEV;
2148 goto out;
2149 }
2150
2151 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2152 ret = -ENODEV;
2153 goto out_dev_exit;
2154 }
2155
2156 vc4_hdmi->audio.streaming = true;
2157
2158 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2159 HDMI_WRITE(HDMI_MAI_CTL,
2160 VC4_HD_MAI_CTL_RESET |
2161 VC4_HD_MAI_CTL_FLUSH |
2162 VC4_HD_MAI_CTL_DLATE |
2163 VC4_HD_MAI_CTL_ERRORE |
2164 VC4_HD_MAI_CTL_ERRORF);
2165 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2166
2167 if (vc4_hdmi->variant->phy_rng_enable)
2168 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
2169
2170out_dev_exit:
2171 drm_dev_exit(idx);
2172out:
2173 mutex_unlock(&vc4_hdmi->mutex);
2174
2175 return ret;
2176}
2177
2178static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
2179{
2180 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2181 struct device *dev = &vc4_hdmi->pdev->dev;
2182 unsigned long flags;
2183 int ret;
2184
2185 lockdep_assert_held(&vc4_hdmi->mutex);
2186
2187 vc4_hdmi->audio.streaming = false;
2188 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
2189 if (ret)
2190 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
2191
2192 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2193
2194 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
2195 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
2196 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
2197
2198 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2199}
2200
2201static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
2202{
2203 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2204 struct drm_device *drm = vc4_hdmi->connector.dev;
2205 unsigned long flags;
2206 int idx;
2207
2208 mutex_lock(&vc4_hdmi->mutex);
2209
2210 if (!drm_dev_enter(drm, &idx))
2211 goto out;
2212
2213 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2214
2215 HDMI_WRITE(HDMI_MAI_CTL,
2216 VC4_HD_MAI_CTL_DLATE |
2217 VC4_HD_MAI_CTL_ERRORE |
2218 VC4_HD_MAI_CTL_ERRORF);
2219
2220 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2221
2222 if (vc4_hdmi->variant->phy_rng_disable)
2223 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
2224
2225 vc4_hdmi->audio.streaming = false;
2226 vc4_hdmi_audio_reset(vc4_hdmi);
2227
2228 drm_dev_exit(idx);
2229
2230out:
2231 mutex_unlock(&vc4_hdmi->mutex);
2232}
2233
2234static int sample_rate_to_mai_fmt(int samplerate)
2235{
2236 switch (samplerate) {
2237 case 8000:
2238 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
2239 case 11025:
2240 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
2241 case 12000:
2242 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
2243 case 16000:
2244 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
2245 case 22050:
2246 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
2247 case 24000:
2248 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
2249 case 32000:
2250 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
2251 case 44100:
2252 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
2253 case 48000:
2254 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
2255 case 64000:
2256 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
2257 case 88200:
2258 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
2259 case 96000:
2260 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
2261 case 128000:
2262 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
2263 case 176400:
2264 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
2265 case 192000:
2266 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
2267 default:
2268 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
2269 }
2270}
2271
2272/* HDMI audio codec callbacks */
2273static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
2274 struct hdmi_codec_daifmt *daifmt,
2275 struct hdmi_codec_params *params)
2276{
2277 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2278 struct drm_device *drm = vc4_hdmi->connector.dev;
2279 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2280 unsigned int sample_rate = params->sample_rate;
2281 unsigned int channels = params->channels;
2282 unsigned long flags;
2283 u32 audio_packet_config, channel_mask;
2284 u32 channel_map;
2285 u32 mai_audio_format;
2286 u32 mai_sample_rate;
2287 int ret = 0;
2288 int idx;
2289
2290 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
2291 sample_rate, params->sample_width, channels);
2292
2293 mutex_lock(&vc4_hdmi->mutex);
2294
2295 if (!drm_dev_enter(drm, &idx)) {
2296 ret = -ENODEV;
2297 goto out;
2298 }
2299
2300 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2301 ret = -EINVAL;
2302 goto out_dev_exit;
2303 }
2304
2305 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
2306
2307 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2308 HDMI_WRITE(HDMI_MAI_CTL,
2309 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
2310 VC4_HD_MAI_CTL_WHOLSMP |
2311 VC4_HD_MAI_CTL_CHALIGN |
2312 VC4_HD_MAI_CTL_ENABLE);
2313
2314 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
2315 if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
2316 params->channels == 8)
2317 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
2318 else
2319 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
2320 HDMI_WRITE(HDMI_MAI_FMT,
2321 VC4_SET_FIELD(mai_sample_rate,
2322 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
2323 VC4_SET_FIELD(mai_audio_format,
2324 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
2325
2326 /* The B frame identifier should match the value used by alsa-lib (8) */
2327 audio_packet_config =
2328 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
2329 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
2330 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
2331
2332 channel_mask = GENMASK(channels - 1, 0);
2333 audio_packet_config |= VC4_SET_FIELD(channel_mask,
2334 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
2335
2336 /* Set the MAI threshold */
2337 HDMI_WRITE(HDMI_MAI_THR,
2338 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) |
2339 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) |
2340 VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) |
2341 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW));
2342
2343 HDMI_WRITE(HDMI_MAI_CONFIG,
2344 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
2345 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
2346 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
2347
2348 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
2349 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
2350 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
2351
2352 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
2353
2354 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2355
2356 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea));
2357 vc4_hdmi_set_audio_infoframe(encoder);
2358
2359out_dev_exit:
2360 drm_dev_exit(idx);
2361out:
2362 mutex_unlock(&vc4_hdmi->mutex);
2363
2364 return ret;
2365}
2366
2367static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
2368 .name = "vc4-hdmi-cpu-dai-component",
2369 .legacy_dai_naming = 1,
2370};
2371
2372static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
2373{
2374 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
2375
2376 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
2377
2378 return 0;
2379}
2380
2381static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
2382 .name = "vc4-hdmi-cpu-dai",
2383 .probe = vc4_hdmi_audio_cpu_dai_probe,
2384 .playback = {
2385 .stream_name = "Playback",
2386 .channels_min = 1,
2387 .channels_max = 8,
2388 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2389 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2390 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2391 SNDRV_PCM_RATE_192000,
2392 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
2393 },
2394};
2395
2396static const struct snd_dmaengine_pcm_config pcm_conf = {
2397 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
2398 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
2399};
2400
2401static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
2402 uint8_t *buf, size_t len)
2403{
2404 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2405 struct drm_connector *connector = &vc4_hdmi->connector;
2406
2407 mutex_lock(&vc4_hdmi->mutex);
2408 memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
2409 mutex_unlock(&vc4_hdmi->mutex);
2410
2411 return 0;
2412}
2413
2414static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
2415 .get_eld = vc4_hdmi_audio_get_eld,
2416 .prepare = vc4_hdmi_audio_prepare,
2417 .audio_shutdown = vc4_hdmi_audio_shutdown,
2418 .audio_startup = vc4_hdmi_audio_startup,
2419};
2420
2421static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
2422 .ops = &vc4_hdmi_codec_ops,
2423 .max_i2s_channels = 8,
2424 .i2s = 1,
2425};
2426
2427static void vc4_hdmi_audio_codec_release(void *ptr)
2428{
2429 struct vc4_hdmi *vc4_hdmi = ptr;
2430
2431 platform_device_unregister(vc4_hdmi->audio.codec_pdev);
2432 vc4_hdmi->audio.codec_pdev = NULL;
2433}
2434
2435static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
2436{
2437 const struct vc4_hdmi_register *mai_data =
2438 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
2439 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
2440 struct snd_soc_card *card = &vc4_hdmi->audio.card;
2441 struct device *dev = &vc4_hdmi->pdev->dev;
2442 struct platform_device *codec_pdev;
2443 const __be32 *addr;
2444 int index, len;
2445 int ret;
2446
2447 /*
2448 * ASoC makes it a bit hard to retrieve a pointer to the
2449 * vc4_hdmi structure. Registering the card will overwrite our
2450 * device drvdata with a pointer to the snd_soc_card structure,
2451 * which can then be used to retrieve whatever drvdata we want
2452 * to associate.
2453 *
2454 * However, that doesn't fly in the case where we wouldn't
2455 * register an ASoC card (because of an old DT that is missing
2456 * the dmas properties for example), then the card isn't
2457 * registered and the device drvdata wouldn't be set.
2458 *
2459 * We can deal with both cases by making sure a snd_soc_card
2460 * pointer and a vc4_hdmi structure are pointing to the same
2461 * memory address, so we can treat them indistinctly without any
2462 * issue.
2463 */
2464 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2465 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2466
2467 if (!of_find_property(dev->of_node, "dmas", &len) || !len) {
2468 dev_warn(dev,
2469 "'dmas' DT property is missing or empty, no HDMI audio\n");
2470 return 0;
2471 }
2472
2473 if (mai_data->reg != VC4_HD) {
2474 WARN_ONCE(true, "MAI isn't in the HD block\n");
2475 return -EINVAL;
2476 }
2477
2478 /*
2479 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
2480 * the bus address specified in the DT, because the physical address
2481 * (the one returned by platform_get_resource()) is not appropriate
2482 * for DMA transfers.
2483 * This VC/MMU should probably be exposed to avoid this kind of hacks.
2484 */
2485 index = of_property_match_string(dev->of_node, "reg-names", "hd");
2486 /* Before BCM2711, we don't have a named register range */
2487 if (index < 0)
2488 index = 1;
2489
2490 addr = of_get_address(dev->of_node, index, NULL, NULL);
2491
2492 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
2493 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2494 vc4_hdmi->audio.dma_data.maxburst = 2;
2495
2496 /*
2497 * NOTE: Strictly speaking, we should probably use a DRM-managed
2498 * registration there to avoid removing all the audio components
2499 * by the time the driver doesn't have any user anymore.
2500 *
2501 * However, the ASoC core uses a number of devm_kzalloc calls
2502 * when registering, even when using non-device-managed
2503 * functions (such as in snd_soc_register_component()).
2504 *
2505 * If we call snd_soc_unregister_component() in a DRM-managed
2506 * action, the device-managed actions have already been executed
2507 * and thus we would access memory that has been freed.
2508 *
2509 * Using device-managed hooks here probably leaves us open to a
2510 * bunch of issues if userspace still has a handle on the ALSA
2511 * device when the device is removed. However, this is mitigated
2512 * by the use of drm_dev_enter()/drm_dev_exit() in the audio
2513 * path to prevent the access to the device resources if it
2514 * isn't there anymore.
2515 *
2516 * Then, the vc4_hdmi structure is DRM-managed and thus only
2517 * freed whenever the last user has closed the DRM device file.
2518 * It should thus outlive ALSA in most situations.
2519 */
2520 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
2521 if (ret) {
2522 dev_err(dev, "Could not register PCM component: %d\n", ret);
2523 return ret;
2524 }
2525
2526 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
2527 &vc4_hdmi_audio_cpu_dai_drv, 1);
2528 if (ret) {
2529 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
2530 return ret;
2531 }
2532
2533 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
2534 PLATFORM_DEVID_AUTO,
2535 &vc4_hdmi_codec_pdata,
2536 sizeof(vc4_hdmi_codec_pdata));
2537 if (IS_ERR(codec_pdev)) {
2538 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
2539 return PTR_ERR(codec_pdev);
2540 }
2541 vc4_hdmi->audio.codec_pdev = codec_pdev;
2542
2543 ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi);
2544 if (ret)
2545 return ret;
2546
2547 dai_link->cpus = &vc4_hdmi->audio.cpu;
2548 dai_link->codecs = &vc4_hdmi->audio.codec;
2549 dai_link->platforms = &vc4_hdmi->audio.platform;
2550
2551 dai_link->num_cpus = 1;
2552 dai_link->num_codecs = 1;
2553 dai_link->num_platforms = 1;
2554
2555 dai_link->name = "MAI";
2556 dai_link->stream_name = "MAI PCM";
2557 dai_link->codecs->dai_name = "i2s-hifi";
2558 dai_link->cpus->dai_name = dev_name(dev);
2559 dai_link->codecs->name = dev_name(&codec_pdev->dev);
2560 dai_link->platforms->name = dev_name(dev);
2561
2562 card->dai_link = dai_link;
2563 card->num_links = 1;
2564 card->name = vc4_hdmi->variant->card_name;
2565 card->driver_name = "vc4-hdmi";
2566 card->dev = dev;
2567 card->owner = THIS_MODULE;
2568
2569 /*
2570 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
2571 * stores a pointer to the snd card object in dev->driver_data. This
2572 * means we cannot use it for something else. The hdmi back-pointer is
2573 * now stored in card->drvdata and should be retrieved with
2574 * snd_soc_card_get_drvdata() if needed.
2575 */
2576 snd_soc_card_set_drvdata(card, vc4_hdmi);
2577 ret = devm_snd_soc_register_card(dev, card);
2578 if (ret)
2579 dev_err_probe(dev, ret, "Could not register sound card\n");
2580
2581 return ret;
2582
2583}
2584
2585static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
2586{
2587 struct vc4_hdmi *vc4_hdmi = priv;
2588 struct drm_connector *connector = &vc4_hdmi->connector;
2589 struct drm_device *dev = connector->dev;
2590
2591 if (dev && dev->registered)
2592 drm_connector_helper_hpd_irq_event(connector);
2593
2594 return IRQ_HANDLED;
2595}
2596
2597static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
2598{
2599 struct drm_connector *connector = &vc4_hdmi->connector;
2600 struct platform_device *pdev = vc4_hdmi->pdev;
2601 int ret;
2602
2603 if (vc4_hdmi->variant->external_irq_controller) {
2604 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
2605 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
2606
2607 ret = devm_request_threaded_irq(&pdev->dev, hpd_con,
2608 NULL,
2609 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2610 "vc4 hdmi hpd connected", vc4_hdmi);
2611 if (ret)
2612 return ret;
2613
2614 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm,
2615 NULL,
2616 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2617 "vc4 hdmi hpd disconnected", vc4_hdmi);
2618 if (ret)
2619 return ret;
2620
2621 connector->polled = DRM_CONNECTOR_POLL_HPD;
2622 }
2623
2624 return 0;
2625}
2626
2627#ifdef CONFIG_DRM_VC4_HDMI_CEC
2628static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
2629{
2630 struct vc4_hdmi *vc4_hdmi = priv;
2631
2632 if (vc4_hdmi->cec_rx_msg.len)
2633 cec_received_msg(vc4_hdmi->cec_adap,
2634 &vc4_hdmi->cec_rx_msg);
2635
2636 return IRQ_HANDLED;
2637}
2638
2639static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
2640{
2641 struct vc4_hdmi *vc4_hdmi = priv;
2642
2643 if (vc4_hdmi->cec_tx_ok) {
2644 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
2645 0, 0, 0, 0);
2646 } else {
2647 /*
2648 * This CEC implementation makes 1 retry, so if we
2649 * get a NACK, then that means it made 2 attempts.
2650 */
2651 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
2652 0, 2, 0, 0);
2653 }
2654 return IRQ_HANDLED;
2655}
2656
2657static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
2658{
2659 struct vc4_hdmi *vc4_hdmi = priv;
2660 irqreturn_t ret;
2661
2662 if (vc4_hdmi->cec_irq_was_rx)
2663 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
2664 else
2665 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
2666
2667 return ret;
2668}
2669
2670static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
2671{
2672 struct drm_device *dev = vc4_hdmi->connector.dev;
2673 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
2674 unsigned int i;
2675
2676 lockdep_assert_held(&vc4_hdmi->hw_lock);
2677
2678 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
2679 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
2680
2681 if (msg->len > 16) {
2682 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
2683 return;
2684 }
2685
2686 for (i = 0; i < msg->len; i += 4) {
2687 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
2688
2689 msg->msg[i] = val & 0xff;
2690 msg->msg[i + 1] = (val >> 8) & 0xff;
2691 msg->msg[i + 2] = (val >> 16) & 0xff;
2692 msg->msg[i + 3] = (val >> 24) & 0xff;
2693 }
2694}
2695
2696static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2697{
2698 u32 cntrl1;
2699
2700 /*
2701 * We don't need to protect the register access using
2702 * drm_dev_enter() there because the interrupt handler lifetime
2703 * is tied to the device itself, and not to the DRM device.
2704 *
2705 * So when the device will be gone, one of the first thing we
2706 * will be doing will be to unregister the interrupt handler,
2707 * and then unregister the DRM device. drm_dev_enter() would
2708 * thus always succeed if we are here.
2709 */
2710
2711 lockdep_assert_held(&vc4_hdmi->hw_lock);
2712
2713 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2714 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
2715 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2716 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2717
2718 return IRQ_WAKE_THREAD;
2719}
2720
2721static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
2722{
2723 struct vc4_hdmi *vc4_hdmi = priv;
2724 irqreturn_t ret;
2725
2726 spin_lock(&vc4_hdmi->hw_lock);
2727 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2728 spin_unlock(&vc4_hdmi->hw_lock);
2729
2730 return ret;
2731}
2732
2733static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2734{
2735 u32 cntrl1;
2736
2737 lockdep_assert_held(&vc4_hdmi->hw_lock);
2738
2739 /*
2740 * We don't need to protect the register access using
2741 * drm_dev_enter() there because the interrupt handler lifetime
2742 * is tied to the device itself, and not to the DRM device.
2743 *
2744 * So when the device will be gone, one of the first thing we
2745 * will be doing will be to unregister the interrupt handler,
2746 * and then unregister the DRM device. drm_dev_enter() would
2747 * thus always succeed if we are here.
2748 */
2749
2750 vc4_hdmi->cec_rx_msg.len = 0;
2751 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2752 vc4_cec_read_msg(vc4_hdmi, cntrl1);
2753 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2754 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2755 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2756
2757 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2758
2759 return IRQ_WAKE_THREAD;
2760}
2761
2762static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
2763{
2764 struct vc4_hdmi *vc4_hdmi = priv;
2765 irqreturn_t ret;
2766
2767 spin_lock(&vc4_hdmi->hw_lock);
2768 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2769 spin_unlock(&vc4_hdmi->hw_lock);
2770
2771 return ret;
2772}
2773
2774static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
2775{
2776 struct vc4_hdmi *vc4_hdmi = priv;
2777 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
2778 irqreturn_t ret;
2779 u32 cntrl5;
2780
2781 /*
2782 * We don't need to protect the register access using
2783 * drm_dev_enter() there because the interrupt handler lifetime
2784 * is tied to the device itself, and not to the DRM device.
2785 *
2786 * So when the device will be gone, one of the first thing we
2787 * will be doing will be to unregister the interrupt handler,
2788 * and then unregister the DRM device. drm_dev_enter() would
2789 * thus always succeed if we are here.
2790 */
2791
2792 if (!(stat & VC4_HDMI_CPU_CEC))
2793 return IRQ_NONE;
2794
2795 spin_lock(&vc4_hdmi->hw_lock);
2796 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
2797 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
2798 if (vc4_hdmi->cec_irq_was_rx)
2799 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2800 else
2801 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2802
2803 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
2804 spin_unlock(&vc4_hdmi->hw_lock);
2805
2806 return ret;
2807}
2808
2809static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
2810{
2811 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2812 struct drm_device *drm = vc4_hdmi->connector.dev;
2813 /* clock period in microseconds */
2814 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
2815 unsigned long flags;
2816 u32 val;
2817 int ret;
2818 int idx;
2819
2820 if (!drm_dev_enter(drm, &idx))
2821 /*
2822 * We can't return an error code, because the CEC
2823 * framework will emit WARN_ON messages at unbind
2824 * otherwise.
2825 */
2826 return 0;
2827
2828 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
2829 if (ret) {
2830 drm_dev_exit(idx);
2831 return ret;
2832 }
2833
2834 mutex_lock(&vc4_hdmi->mutex);
2835
2836 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2837
2838 val = HDMI_READ(HDMI_CEC_CNTRL_5);
2839 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
2840 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2841 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2842 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2843 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2844
2845 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2846 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2847 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2848 HDMI_WRITE(HDMI_CEC_CNTRL_2,
2849 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2850 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2851 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2852 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2853 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2854 HDMI_WRITE(HDMI_CEC_CNTRL_3,
2855 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2856 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2857 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2858 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2859 HDMI_WRITE(HDMI_CEC_CNTRL_4,
2860 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2861 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2862 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2863 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2864
2865 if (!vc4_hdmi->variant->external_irq_controller)
2866 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2867
2868 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2869
2870 mutex_unlock(&vc4_hdmi->mutex);
2871 drm_dev_exit(idx);
2872
2873 return 0;
2874}
2875
2876static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2877{
2878 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2879 struct drm_device *drm = vc4_hdmi->connector.dev;
2880 unsigned long flags;
2881 int idx;
2882
2883 if (!drm_dev_enter(drm, &idx))
2884 /*
2885 * We can't return an error code, because the CEC
2886 * framework will emit WARN_ON messages at unbind
2887 * otherwise.
2888 */
2889 return 0;
2890
2891 mutex_lock(&vc4_hdmi->mutex);
2892
2893 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2894
2895 if (!vc4_hdmi->variant->external_irq_controller)
2896 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2897
2898 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2899 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2900
2901 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2902
2903 mutex_unlock(&vc4_hdmi->mutex);
2904
2905 pm_runtime_put(&vc4_hdmi->pdev->dev);
2906
2907 drm_dev_exit(idx);
2908
2909 return 0;
2910}
2911
2912static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2913{
2914 if (enable)
2915 return vc4_hdmi_cec_enable(adap);
2916 else
2917 return vc4_hdmi_cec_disable(adap);
2918}
2919
2920static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2921{
2922 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2923 struct drm_device *drm = vc4_hdmi->connector.dev;
2924 unsigned long flags;
2925 int idx;
2926
2927 if (!drm_dev_enter(drm, &idx))
2928 /*
2929 * We can't return an error code, because the CEC
2930 * framework will emit WARN_ON messages at unbind
2931 * otherwise.
2932 */
2933 return 0;
2934
2935 mutex_lock(&vc4_hdmi->mutex);
2936 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2937 HDMI_WRITE(HDMI_CEC_CNTRL_1,
2938 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2939 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2940 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2941 mutex_unlock(&vc4_hdmi->mutex);
2942
2943 drm_dev_exit(idx);
2944
2945 return 0;
2946}
2947
2948static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2949 u32 signal_free_time, struct cec_msg *msg)
2950{
2951 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2952 struct drm_device *dev = vc4_hdmi->connector.dev;
2953 unsigned long flags;
2954 u32 val;
2955 unsigned int i;
2956 int idx;
2957
2958 if (!drm_dev_enter(dev, &idx))
2959 return -ENODEV;
2960
2961 if (msg->len > 16) {
2962 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2963 drm_dev_exit(idx);
2964 return -ENOMEM;
2965 }
2966
2967 mutex_lock(&vc4_hdmi->mutex);
2968
2969 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2970
2971 for (i = 0; i < msg->len; i += 4)
2972 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2973 (msg->msg[i]) |
2974 (msg->msg[i + 1] << 8) |
2975 (msg->msg[i + 2] << 16) |
2976 (msg->msg[i + 3] << 24));
2977
2978 val = HDMI_READ(HDMI_CEC_CNTRL_1);
2979 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2980 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2981 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2982 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2983 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2984
2985 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2986
2987 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2988 mutex_unlock(&vc4_hdmi->mutex);
2989 drm_dev_exit(idx);
2990
2991 return 0;
2992}
2993
2994static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
2995 .adap_enable = vc4_hdmi_cec_adap_enable,
2996 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
2997 .adap_transmit = vc4_hdmi_cec_adap_transmit,
2998};
2999
3000static void vc4_hdmi_cec_release(void *ptr)
3001{
3002 struct vc4_hdmi *vc4_hdmi = ptr;
3003
3004 cec_unregister_adapter(vc4_hdmi->cec_adap);
3005 vc4_hdmi->cec_adap = NULL;
3006}
3007
3008static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
3009{
3010 struct cec_connector_info conn_info;
3011 struct platform_device *pdev = vc4_hdmi->pdev;
3012 struct device *dev = &pdev->dev;
3013 int ret;
3014
3015 if (!of_find_property(dev->of_node, "interrupts", NULL)) {
3016 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
3017 return 0;
3018 }
3019
3020 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
3021 vc4_hdmi,
3022 vc4_hdmi->variant->card_name,
3023 CEC_CAP_DEFAULTS |
3024 CEC_CAP_CONNECTOR_INFO, 1);
3025 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
3026 if (ret < 0)
3027 return ret;
3028
3029 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
3030 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
3031
3032 if (vc4_hdmi->variant->external_irq_controller) {
3033 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"),
3034 vc4_cec_irq_handler_rx_bare,
3035 vc4_cec_irq_handler_rx_thread, 0,
3036 "vc4 hdmi cec rx", vc4_hdmi);
3037 if (ret)
3038 goto err_delete_cec_adap;
3039
3040 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"),
3041 vc4_cec_irq_handler_tx_bare,
3042 vc4_cec_irq_handler_tx_thread, 0,
3043 "vc4 hdmi cec tx", vc4_hdmi);
3044 if (ret)
3045 goto err_delete_cec_adap;
3046 } else {
3047 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
3048 vc4_cec_irq_handler,
3049 vc4_cec_irq_handler_thread, 0,
3050 "vc4 hdmi cec", vc4_hdmi);
3051 if (ret)
3052 goto err_delete_cec_adap;
3053 }
3054
3055 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
3056 if (ret < 0)
3057 goto err_delete_cec_adap;
3058
3059 /*
3060 * NOTE: Strictly speaking, we should probably use a DRM-managed
3061 * registration there to avoid removing the CEC adapter by the
3062 * time the DRM driver doesn't have any user anymore.
3063 *
3064 * However, the CEC framework already cleans up the CEC adapter
3065 * only when the last user has closed its file descriptor, so we
3066 * don't need to handle it in DRM.
3067 *
3068 * By the time the device-managed hook is executed, we will give
3069 * up our reference to the CEC adapter and therefore don't
3070 * really care when it's actually freed.
3071 *
3072 * There's still a problematic sequence: if we unregister our
3073 * CEC adapter, but the userspace keeps a handle on the CEC
3074 * adapter but not the DRM device for some reason. In such a
3075 * case, our vc4_hdmi structure will be freed, but the
3076 * cec_adapter structure will have a dangling pointer to what
3077 * used to be our HDMI controller. If we get a CEC call at that
3078 * moment, we could end up with a use-after-free. Fortunately,
3079 * the CEC framework already handles this too, by calling
3080 * cec_is_registered() in cec_ioctl() and cec_poll().
3081 */
3082 ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi);
3083 if (ret)
3084 return ret;
3085
3086 return 0;
3087
3088err_delete_cec_adap:
3089 cec_delete_adapter(vc4_hdmi->cec_adap);
3090
3091 return ret;
3092}
3093#else
3094static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
3095{
3096 return 0;
3097}
3098#endif
3099
3100static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr)
3101{
3102 struct debugfs_reg32 *regs = ptr;
3103
3104 kfree(regs);
3105}
3106
3107static int vc4_hdmi_build_regset(struct drm_device *drm,
3108 struct vc4_hdmi *vc4_hdmi,
3109 struct debugfs_regset32 *regset,
3110 enum vc4_hdmi_regs reg)
3111{
3112 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
3113 struct debugfs_reg32 *regs, *new_regs;
3114 unsigned int count = 0;
3115 unsigned int i;
3116 int ret;
3117
3118 regs = kcalloc(variant->num_registers, sizeof(*regs),
3119 GFP_KERNEL);
3120 if (!regs)
3121 return -ENOMEM;
3122
3123 for (i = 0; i < variant->num_registers; i++) {
3124 const struct vc4_hdmi_register *field = &variant->registers[i];
3125
3126 if (field->reg != reg)
3127 continue;
3128
3129 regs[count].name = field->name;
3130 regs[count].offset = field->offset;
3131 count++;
3132 }
3133
3134 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
3135 if (!new_regs)
3136 return -ENOMEM;
3137
3138 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
3139 regset->regs = new_regs;
3140 regset->nregs = count;
3141
3142 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs);
3143 if (ret)
3144 return ret;
3145
3146 return 0;
3147}
3148
3149static int vc4_hdmi_init_resources(struct drm_device *drm,
3150 struct vc4_hdmi *vc4_hdmi)
3151{
3152 struct platform_device *pdev = vc4_hdmi->pdev;
3153 struct device *dev = &pdev->dev;
3154 int ret;
3155
3156 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
3157 if (IS_ERR(vc4_hdmi->hdmicore_regs))
3158 return PTR_ERR(vc4_hdmi->hdmicore_regs);
3159
3160 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
3161 if (IS_ERR(vc4_hdmi->hd_regs))
3162 return PTR_ERR(vc4_hdmi->hd_regs);
3163
3164 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3165 if (ret)
3166 return ret;
3167
3168 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3169 if (ret)
3170 return ret;
3171
3172 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
3173 if (IS_ERR(vc4_hdmi->pixel_clock)) {
3174 ret = PTR_ERR(vc4_hdmi->pixel_clock);
3175 if (ret != -EPROBE_DEFER)
3176 DRM_ERROR("Failed to get pixel clock\n");
3177 return ret;
3178 }
3179
3180 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3181 if (IS_ERR(vc4_hdmi->hsm_clock)) {
3182 DRM_ERROR("Failed to get HDMI state machine clock\n");
3183 return PTR_ERR(vc4_hdmi->hsm_clock);
3184 }
3185
3186 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
3187 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
3188
3189 vc4_hdmi->hsm_rpm_clock = devm_clk_get(dev, "hdmi");
3190 if (IS_ERR(vc4_hdmi->hsm_rpm_clock)) {
3191 DRM_ERROR("Failed to get HDMI state machine clock\n");
3192 return PTR_ERR(vc4_hdmi->hsm_rpm_clock);
3193 }
3194
3195 return 0;
3196}
3197
3198static int vc5_hdmi_init_resources(struct drm_device *drm,
3199 struct vc4_hdmi *vc4_hdmi)
3200{
3201 struct platform_device *pdev = vc4_hdmi->pdev;
3202 struct device *dev = &pdev->dev;
3203 struct resource *res;
3204 int ret;
3205
3206 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
3207 if (!res)
3208 return -ENODEV;
3209
3210 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
3211 resource_size(res));
3212 if (!vc4_hdmi->hdmicore_regs)
3213 return -ENOMEM;
3214
3215 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
3216 if (!res)
3217 return -ENODEV;
3218
3219 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
3220 if (!vc4_hdmi->hd_regs)
3221 return -ENOMEM;
3222
3223 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
3224 if (!res)
3225 return -ENODEV;
3226
3227 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
3228 if (!vc4_hdmi->cec_regs)
3229 return -ENOMEM;
3230
3231 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
3232 if (!res)
3233 return -ENODEV;
3234
3235 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
3236 if (!vc4_hdmi->csc_regs)
3237 return -ENOMEM;
3238
3239 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
3240 if (!res)
3241 return -ENODEV;
3242
3243 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
3244 if (!vc4_hdmi->dvp_regs)
3245 return -ENOMEM;
3246
3247 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
3248 if (!res)
3249 return -ENODEV;
3250
3251 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
3252 if (!vc4_hdmi->phy_regs)
3253 return -ENOMEM;
3254
3255 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
3256 if (!res)
3257 return -ENODEV;
3258
3259 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
3260 if (!vc4_hdmi->ram_regs)
3261 return -ENOMEM;
3262
3263 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
3264 if (!res)
3265 return -ENODEV;
3266
3267 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
3268 if (!vc4_hdmi->rm_regs)
3269 return -ENOMEM;
3270
3271 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3272 if (IS_ERR(vc4_hdmi->hsm_clock)) {
3273 DRM_ERROR("Failed to get HDMI state machine clock\n");
3274 return PTR_ERR(vc4_hdmi->hsm_clock);
3275 }
3276
3277 vc4_hdmi->hsm_rpm_clock = devm_clk_get(dev, "hdmi");
3278 if (IS_ERR(vc4_hdmi->hsm_rpm_clock)) {
3279 DRM_ERROR("Failed to get HDMI state machine clock\n");
3280 return PTR_ERR(vc4_hdmi->hsm_rpm_clock);
3281 }
3282
3283 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
3284 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
3285 DRM_ERROR("Failed to get pixel bvb clock\n");
3286 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
3287 }
3288
3289 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
3290 if (IS_ERR(vc4_hdmi->audio_clock)) {
3291 DRM_ERROR("Failed to get audio clock\n");
3292 return PTR_ERR(vc4_hdmi->audio_clock);
3293 }
3294
3295 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
3296 if (IS_ERR(vc4_hdmi->cec_clock)) {
3297 DRM_ERROR("Failed to get CEC clock\n");
3298 return PTR_ERR(vc4_hdmi->cec_clock);
3299 }
3300
3301 vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
3302 if (IS_ERR(vc4_hdmi->reset)) {
3303 DRM_ERROR("Failed to get HDMI reset line\n");
3304 return PTR_ERR(vc4_hdmi->reset);
3305 }
3306
3307 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3308 if (ret)
3309 return ret;
3310
3311 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3312 if (ret)
3313 return ret;
3314
3315 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
3316 if (ret)
3317 return ret;
3318
3319 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
3320 if (ret)
3321 return ret;
3322
3323 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
3324 if (ret)
3325 return ret;
3326
3327 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
3328 if (ret)
3329 return ret;
3330
3331 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
3332 if (ret)
3333 return ret;
3334
3335 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
3336 if (ret)
3337 return ret;
3338
3339 return 0;
3340}
3341
3342static int vc4_hdmi_runtime_suspend(struct device *dev)
3343{
3344 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3345
3346 clk_disable_unprepare(vc4_hdmi->hsm_rpm_clock);
3347
3348 return 0;
3349}
3350
3351static int vc4_hdmi_runtime_resume(struct device *dev)
3352{
3353 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3354 unsigned long __maybe_unused flags;
3355 u32 __maybe_unused value;
3356 unsigned long rate;
3357 int ret;
3358
3359 /*
3360 * The HSM clock is in the HDMI power domain, so we need to set
3361 * its frequency while the power domain is active so that it
3362 * keeps its rate.
3363 */
3364 ret = clk_set_min_rate(vc4_hdmi->hsm_rpm_clock, HSM_MIN_CLOCK_FREQ);
3365 if (ret)
3366 return ret;
3367
3368 ret = clk_prepare_enable(vc4_hdmi->hsm_rpm_clock);
3369 if (ret)
3370 return ret;
3371
3372 /*
3373 * Whenever the RaspberryPi boots without an HDMI monitor
3374 * plugged in, the firmware won't have initialized the HSM clock
3375 * rate and it will be reported as 0.
3376 *
3377 * If we try to access a register of the controller in such a
3378 * case, it will lead to a silent CPU stall. Let's make sure we
3379 * prevent such a case.
3380 */
3381 rate = clk_get_rate(vc4_hdmi->hsm_rpm_clock);
3382 if (!rate) {
3383 ret = -EINVAL;
3384 goto err_disable_clk;
3385 }
3386
3387 if (vc4_hdmi->variant->reset)
3388 vc4_hdmi->variant->reset(vc4_hdmi);
3389
3390#ifdef CONFIG_DRM_VC4_HDMI_CEC
3391 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3392 value = HDMI_READ(HDMI_CEC_CNTRL_1);
3393 /* Set the logical address to Unregistered */
3394 value |= VC4_HDMI_CEC_ADDR_MASK;
3395 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
3396 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3397
3398 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
3399
3400 if (!vc4_hdmi->variant->external_irq_controller) {
3401 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3402 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
3403 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3404 }
3405#endif
3406
3407 return 0;
3408
3409err_disable_clk:
3410 clk_disable_unprepare(vc4_hdmi->hsm_clock);
3411 return ret;
3412}
3413
3414static void vc4_hdmi_put_ddc_device(void *ptr)
3415{
3416 struct vc4_hdmi *vc4_hdmi = ptr;
3417
3418 put_device(&vc4_hdmi->ddc->dev);
3419}
3420
3421static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
3422{
3423 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
3424 struct platform_device *pdev = to_platform_device(dev);
3425 struct drm_device *drm = dev_get_drvdata(master);
3426 struct vc4_hdmi *vc4_hdmi;
3427 struct drm_encoder *encoder;
3428 struct device_node *ddc_node;
3429 int ret;
3430
3431 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL);
3432 if (!vc4_hdmi)
3433 return -ENOMEM;
3434
3435 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex);
3436 if (ret)
3437 return ret;
3438
3439 spin_lock_init(&vc4_hdmi->hw_lock);
3440 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
3441
3442 dev_set_drvdata(dev, vc4_hdmi);
3443 encoder = &vc4_hdmi->encoder.base;
3444 vc4_hdmi->encoder.type = variant->encoder_type;
3445 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
3446 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
3447 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
3448 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
3449 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
3450 vc4_hdmi->pdev = pdev;
3451 vc4_hdmi->variant = variant;
3452
3453 /*
3454 * Since we don't know the state of the controller and its
3455 * display (if any), let's assume it's always enabled.
3456 * vc4_hdmi_disable_scrambling() will thus run at boot, make
3457 * sure it's disabled, and avoid any inconsistency.
3458 */
3459 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
3460 vc4_hdmi->scdc_enabled = true;
3461
3462 ret = variant->init_resources(drm, vc4_hdmi);
3463 if (ret)
3464 return ret;
3465
3466 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
3467 if (!ddc_node) {
3468 DRM_ERROR("Failed to find ddc node in device tree\n");
3469 return -ENODEV;
3470 }
3471
3472 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
3473 of_node_put(ddc_node);
3474 if (!vc4_hdmi->ddc) {
3475 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
3476 return -EPROBE_DEFER;
3477 }
3478
3479 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi);
3480 if (ret)
3481 return ret;
3482
3483 /* Only use the GPIO HPD pin if present in the DT, otherwise
3484 * we'll use the HDMI core's register.
3485 */
3486 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
3487 if (IS_ERR(vc4_hdmi->hpd_gpio)) {
3488 return PTR_ERR(vc4_hdmi->hpd_gpio);
3489 }
3490
3491 vc4_hdmi->disable_wifi_frequencies =
3492 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
3493
3494 ret = devm_pm_runtime_enable(dev);
3495 if (ret)
3496 return ret;
3497
3498 /*
3499 * We need to have the device powered up at this point to call
3500 * our reset hook and for the CEC init.
3501 */
3502 ret = pm_runtime_resume_and_get(dev);
3503 if (ret)
3504 return ret;
3505
3506 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
3507 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
3508 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
3509 clk_prepare_enable(vc4_hdmi->pixel_clock);
3510 clk_prepare_enable(vc4_hdmi->hsm_clock);
3511 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
3512 }
3513
3514 ret = drmm_encoder_init(drm, encoder,
3515 &vc4_hdmi_encoder_funcs,
3516 DRM_MODE_ENCODER_TMDS,
3517 NULL);
3518 if (ret)
3519 goto err_put_runtime_pm;
3520
3521 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
3522
3523 ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
3524 if (ret)
3525 goto err_put_runtime_pm;
3526
3527 ret = vc4_hdmi_hotplug_init(vc4_hdmi);
3528 if (ret)
3529 goto err_put_runtime_pm;
3530
3531 ret = vc4_hdmi_cec_init(vc4_hdmi);
3532 if (ret)
3533 goto err_put_runtime_pm;
3534
3535 ret = vc4_hdmi_audio_init(vc4_hdmi);
3536 if (ret)
3537 goto err_put_runtime_pm;
3538
3539 pm_runtime_put_sync(dev);
3540
3541 return 0;
3542
3543err_put_runtime_pm:
3544 pm_runtime_put_sync(dev);
3545
3546 return ret;
3547}
3548
3549static const struct component_ops vc4_hdmi_ops = {
3550 .bind = vc4_hdmi_bind,
3551};
3552
3553static int vc4_hdmi_dev_probe(struct platform_device *pdev)
3554{
3555 return component_add(&pdev->dev, &vc4_hdmi_ops);
3556}
3557
3558static int vc4_hdmi_dev_remove(struct platform_device *pdev)
3559{
3560 component_del(&pdev->dev, &vc4_hdmi_ops);
3561 return 0;
3562}
3563
3564static const struct vc4_hdmi_variant bcm2835_variant = {
3565 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3566 .debugfs_name = "hdmi_regs",
3567 .card_name = "vc4-hdmi",
3568 .max_pixel_clock = 162000000,
3569 .registers = vc4_hdmi_fields,
3570 .num_registers = ARRAY_SIZE(vc4_hdmi_fields),
3571
3572 .init_resources = vc4_hdmi_init_resources,
3573 .csc_setup = vc4_hdmi_csc_setup,
3574 .reset = vc4_hdmi_reset,
3575 .set_timings = vc4_hdmi_set_timings,
3576 .phy_init = vc4_hdmi_phy_init,
3577 .phy_disable = vc4_hdmi_phy_disable,
3578 .phy_rng_enable = vc4_hdmi_phy_rng_enable,
3579 .phy_rng_disable = vc4_hdmi_phy_rng_disable,
3580 .channel_map = vc4_hdmi_channel_map,
3581 .supports_hdr = false,
3582};
3583
3584static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
3585 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3586 .debugfs_name = "hdmi0_regs",
3587 .card_name = "vc4-hdmi-0",
3588 .max_pixel_clock = 600000000,
3589 .registers = vc5_hdmi_hdmi0_fields,
3590 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
3591 .phy_lane_mapping = {
3592 PHY_LANE_0,
3593 PHY_LANE_1,
3594 PHY_LANE_2,
3595 PHY_LANE_CK,
3596 },
3597 .unsupported_odd_h_timings = true,
3598 .external_irq_controller = true,
3599
3600 .init_resources = vc5_hdmi_init_resources,
3601 .csc_setup = vc5_hdmi_csc_setup,
3602 .reset = vc5_hdmi_reset,
3603 .set_timings = vc5_hdmi_set_timings,
3604 .phy_init = vc5_hdmi_phy_init,
3605 .phy_disable = vc5_hdmi_phy_disable,
3606 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3607 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3608 .channel_map = vc5_hdmi_channel_map,
3609 .supports_hdr = true,
3610 .hp_detect = vc5_hdmi_hp_detect,
3611};
3612
3613static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
3614 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
3615 .debugfs_name = "hdmi1_regs",
3616 .card_name = "vc4-hdmi-1",
3617 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
3618 .registers = vc5_hdmi_hdmi1_fields,
3619 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
3620 .phy_lane_mapping = {
3621 PHY_LANE_1,
3622 PHY_LANE_0,
3623 PHY_LANE_CK,
3624 PHY_LANE_2,
3625 },
3626 .unsupported_odd_h_timings = true,
3627 .external_irq_controller = true,
3628
3629 .init_resources = vc5_hdmi_init_resources,
3630 .csc_setup = vc5_hdmi_csc_setup,
3631 .reset = vc5_hdmi_reset,
3632 .set_timings = vc5_hdmi_set_timings,
3633 .phy_init = vc5_hdmi_phy_init,
3634 .phy_disable = vc5_hdmi_phy_disable,
3635 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3636 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3637 .channel_map = vc5_hdmi_channel_map,
3638 .supports_hdr = true,
3639 .hp_detect = vc5_hdmi_hp_detect,
3640};
3641
3642static const struct of_device_id vc4_hdmi_dt_match[] = {
3643 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
3644 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
3645 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
3646 {}
3647};
3648
3649static const struct dev_pm_ops vc4_hdmi_pm_ops = {
3650 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
3651 vc4_hdmi_runtime_resume,
3652 NULL)
3653};
3654
3655struct platform_driver vc4_hdmi_driver = {
3656 .probe = vc4_hdmi_dev_probe,
3657 .remove = vc4_hdmi_dev_remove,
3658 .driver = {
3659 .name = "vc4_hdmi",
3660 .of_match_table = vc4_hdmi_dt_match,
3661 .pm = &vc4_hdmi_pm_ops,
3662 },
3663};