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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/clk.h>
7#include <linux/delay.h>
8#include <linux/dma-mapping.h>
9#include <linux/err.h>
10#include <linux/gpio/consumer.h>
11#include <linux/interrupt.h>
12#include <linux/mfd/syscon.h>
13#include <linux/of.h>
14#include <linux/of_graph.h>
15#include <linux/of_irq.h>
16#include <linux/pinctrl/consumer.h>
17#include <linux/pm_opp.h>
18#include <linux/regmap.h>
19#include <linux/regulator/consumer.h>
20#include <linux/spinlock.h>
21
22#include <video/mipi_display.h>
23
24#include <drm/display/drm_dsc_helper.h>
25#include <drm/drm_of.h>
26
27#include "dsi.h"
28#include "dsi.xml.h"
29#include "sfpb.xml.h"
30#include "dsi_cfg.h"
31#include "msm_dsc_helper.h"
32#include "msm_kms.h"
33#include "msm_gem.h"
34#include "phy/dsi_phy.h"
35
36#define DSI_RESET_TOGGLE_DELAY_MS 20
37
38static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc);
39
40static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
41{
42 u32 ver;
43
44 if (!major || !minor)
45 return -EINVAL;
46
47 /*
48 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0
49 * makes all other registers 4-byte shifted down.
50 *
51 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and
52 * older, we read the DSI_VERSION register without any shift(offset
53 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In
54 * the case of DSI6G, this has to be zero (the offset points to a
55 * scratch register which we never touch)
56 */
57
58 ver = msm_readl(base + REG_DSI_VERSION);
59 if (ver) {
60 /* older dsi host, there is no register shift */
61 ver = FIELD(ver, DSI_VERSION_MAJOR);
62 if (ver <= MSM_DSI_VER_MAJOR_V2) {
63 /* old versions */
64 *major = ver;
65 *minor = 0;
66 return 0;
67 } else {
68 return -EINVAL;
69 }
70 } else {
71 /*
72 * newer host, offset 0 has 6G_HW_VERSION, the rest of the
73 * registers are shifted down, read DSI_VERSION again with
74 * the shifted offset
75 */
76 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
77 ver = FIELD(ver, DSI_VERSION_MAJOR);
78 if (ver == MSM_DSI_VER_MAJOR_6G) {
79 /* 6G version */
80 *major = ver;
81 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION);
82 return 0;
83 } else {
84 return -EINVAL;
85 }
86 }
87}
88
89#define DSI_ERR_STATE_ACK 0x0000
90#define DSI_ERR_STATE_TIMEOUT 0x0001
91#define DSI_ERR_STATE_DLN0_PHY 0x0002
92#define DSI_ERR_STATE_FIFO 0x0004
93#define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008
94#define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010
95#define DSI_ERR_STATE_PLL_UNLOCKED 0x0020
96
97#define DSI_CLK_CTRL_ENABLE_CLKS \
98 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \
99 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \
100 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \
101 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK)
102
103struct msm_dsi_host {
104 struct mipi_dsi_host base;
105
106 struct platform_device *pdev;
107 struct drm_device *dev;
108
109 int id;
110
111 void __iomem *ctrl_base;
112 phys_addr_t ctrl_size;
113 struct regulator_bulk_data *supplies;
114
115 int num_bus_clks;
116 struct clk_bulk_data bus_clks[DSI_BUS_CLK_MAX];
117
118 struct clk *byte_clk;
119 struct clk *esc_clk;
120 struct clk *pixel_clk;
121 struct clk *byte_intf_clk;
122
123 unsigned long byte_clk_rate;
124 unsigned long byte_intf_clk_rate;
125 unsigned long pixel_clk_rate;
126 unsigned long esc_clk_rate;
127
128 /* DSI v2 specific clocks */
129 struct clk *src_clk;
130
131 unsigned long src_clk_rate;
132
133 struct gpio_desc *disp_en_gpio;
134 struct gpio_desc *te_gpio;
135
136 const struct msm_dsi_cfg_handler *cfg_hnd;
137
138 struct completion dma_comp;
139 struct completion video_comp;
140 struct mutex dev_mutex;
141 struct mutex cmd_mutex;
142 spinlock_t intr_lock; /* Protect interrupt ctrl register */
143
144 u32 err_work_state;
145 struct work_struct err_work;
146 struct workqueue_struct *workqueue;
147
148 /* DSI 6G TX buffer*/
149 struct drm_gem_object *tx_gem_obj;
150 struct msm_gem_address_space *aspace;
151
152 /* DSI v2 TX buffer */
153 void *tx_buf;
154 dma_addr_t tx_buf_paddr;
155
156 int tx_size;
157
158 u8 *rx_buf;
159
160 struct regmap *sfpb;
161
162 struct drm_display_mode *mode;
163 struct drm_dsc_config *dsc;
164
165 /* connected device info */
166 unsigned int channel;
167 unsigned int lanes;
168 enum mipi_dsi_pixel_format format;
169 unsigned long mode_flags;
170
171 /* lane data parsed via DT */
172 int dlane_swap;
173 int num_data_lanes;
174
175 /* from phy DT */
176 bool cphy_mode;
177
178 u32 dma_cmd_ctrl_restore;
179
180 bool registered;
181 bool power_on;
182 bool enabled;
183 int irq;
184};
185
186static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt)
187{
188 switch (fmt) {
189 case MIPI_DSI_FMT_RGB565: return 16;
190 case MIPI_DSI_FMT_RGB666_PACKED: return 18;
191 case MIPI_DSI_FMT_RGB666:
192 case MIPI_DSI_FMT_RGB888:
193 default: return 24;
194 }
195}
196
197static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
198{
199 return msm_readl(msm_host->ctrl_base + reg);
200}
201static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
202{
203 msm_writel(data, msm_host->ctrl_base + reg);
204}
205
206static const struct msm_dsi_cfg_handler *dsi_get_config(
207 struct msm_dsi_host *msm_host)
208{
209 const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
210 struct device *dev = &msm_host->pdev->dev;
211 struct clk *ahb_clk;
212 int ret;
213 u32 major = 0, minor = 0;
214
215 ahb_clk = msm_clk_get(msm_host->pdev, "iface");
216 if (IS_ERR(ahb_clk)) {
217 pr_err("%s: cannot get interface clock\n", __func__);
218 goto exit;
219 }
220
221 pm_runtime_get_sync(dev);
222
223 ret = clk_prepare_enable(ahb_clk);
224 if (ret) {
225 pr_err("%s: unable to enable ahb_clk\n", __func__);
226 goto runtime_put;
227 }
228
229 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor);
230 if (ret) {
231 pr_err("%s: Invalid version\n", __func__);
232 goto disable_clks;
233 }
234
235 cfg_hnd = msm_dsi_cfg_get(major, minor);
236
237 DBG("%s: Version %x:%x\n", __func__, major, minor);
238
239disable_clks:
240 clk_disable_unprepare(ahb_clk);
241runtime_put:
242 pm_runtime_put_sync(dev);
243exit:
244 return cfg_hnd;
245}
246
247static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host)
248{
249 return container_of(host, struct msm_dsi_host, base);
250}
251
252int dsi_clk_init_v2(struct msm_dsi_host *msm_host)
253{
254 struct platform_device *pdev = msm_host->pdev;
255 int ret = 0;
256
257 msm_host->src_clk = msm_clk_get(pdev, "src");
258
259 if (IS_ERR(msm_host->src_clk)) {
260 ret = PTR_ERR(msm_host->src_clk);
261 pr_err("%s: can't find src clock. ret=%d\n",
262 __func__, ret);
263 msm_host->src_clk = NULL;
264 return ret;
265 }
266
267 return ret;
268}
269
270int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host)
271{
272 struct platform_device *pdev = msm_host->pdev;
273 int ret = 0;
274
275 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf");
276 if (IS_ERR(msm_host->byte_intf_clk)) {
277 ret = PTR_ERR(msm_host->byte_intf_clk);
278 pr_err("%s: can't find byte_intf clock. ret=%d\n",
279 __func__, ret);
280 }
281
282 return ret;
283}
284
285static int dsi_clk_init(struct msm_dsi_host *msm_host)
286{
287 struct platform_device *pdev = msm_host->pdev;
288 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
289 const struct msm_dsi_config *cfg = cfg_hnd->cfg;
290 int i, ret = 0;
291
292 /* get bus clocks */
293 for (i = 0; i < cfg->num_bus_clks; i++)
294 msm_host->bus_clks[i].id = cfg->bus_clk_names[i];
295 msm_host->num_bus_clks = cfg->num_bus_clks;
296
297 ret = devm_clk_bulk_get(&pdev->dev, msm_host->num_bus_clks, msm_host->bus_clks);
298 if (ret < 0) {
299 dev_err(&pdev->dev, "Unable to get clocks, ret = %d\n", ret);
300 goto exit;
301 }
302
303 /* get link and source clocks */
304 msm_host->byte_clk = msm_clk_get(pdev, "byte");
305 if (IS_ERR(msm_host->byte_clk)) {
306 ret = PTR_ERR(msm_host->byte_clk);
307 pr_err("%s: can't find dsi_byte clock. ret=%d\n",
308 __func__, ret);
309 msm_host->byte_clk = NULL;
310 goto exit;
311 }
312
313 msm_host->pixel_clk = msm_clk_get(pdev, "pixel");
314 if (IS_ERR(msm_host->pixel_clk)) {
315 ret = PTR_ERR(msm_host->pixel_clk);
316 pr_err("%s: can't find dsi_pixel clock. ret=%d\n",
317 __func__, ret);
318 msm_host->pixel_clk = NULL;
319 goto exit;
320 }
321
322 msm_host->esc_clk = msm_clk_get(pdev, "core");
323 if (IS_ERR(msm_host->esc_clk)) {
324 ret = PTR_ERR(msm_host->esc_clk);
325 pr_err("%s: can't find dsi_esc clock. ret=%d\n",
326 __func__, ret);
327 msm_host->esc_clk = NULL;
328 goto exit;
329 }
330
331 if (cfg_hnd->ops->clk_init_ver)
332 ret = cfg_hnd->ops->clk_init_ver(msm_host);
333exit:
334 return ret;
335}
336
337int msm_dsi_runtime_suspend(struct device *dev)
338{
339 struct platform_device *pdev = to_platform_device(dev);
340 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev);
341 struct mipi_dsi_host *host = msm_dsi->host;
342 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
343
344 if (!msm_host->cfg_hnd)
345 return 0;
346
347 clk_bulk_disable_unprepare(msm_host->num_bus_clks, msm_host->bus_clks);
348
349 return 0;
350}
351
352int msm_dsi_runtime_resume(struct device *dev)
353{
354 struct platform_device *pdev = to_platform_device(dev);
355 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev);
356 struct mipi_dsi_host *host = msm_dsi->host;
357 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
358
359 if (!msm_host->cfg_hnd)
360 return 0;
361
362 return clk_bulk_prepare_enable(msm_host->num_bus_clks, msm_host->bus_clks);
363}
364
365int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host)
366{
367 int ret;
368
369 DBG("Set clk rates: pclk=%d, byteclk=%lu",
370 msm_host->mode->clock, msm_host->byte_clk_rate);
371
372 ret = dev_pm_opp_set_rate(&msm_host->pdev->dev,
373 msm_host->byte_clk_rate);
374 if (ret) {
375 pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret);
376 return ret;
377 }
378
379 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
380 if (ret) {
381 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
382 return ret;
383 }
384
385 if (msm_host->byte_intf_clk) {
386 ret = clk_set_rate(msm_host->byte_intf_clk, msm_host->byte_intf_clk_rate);
387 if (ret) {
388 pr_err("%s: Failed to set rate byte intf clk, %d\n",
389 __func__, ret);
390 return ret;
391 }
392 }
393
394 return 0;
395}
396
397
398int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
399{
400 int ret;
401
402 ret = clk_prepare_enable(msm_host->esc_clk);
403 if (ret) {
404 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
405 goto error;
406 }
407
408 ret = clk_prepare_enable(msm_host->byte_clk);
409 if (ret) {
410 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
411 goto byte_clk_err;
412 }
413
414 ret = clk_prepare_enable(msm_host->pixel_clk);
415 if (ret) {
416 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
417 goto pixel_clk_err;
418 }
419
420 ret = clk_prepare_enable(msm_host->byte_intf_clk);
421 if (ret) {
422 pr_err("%s: Failed to enable byte intf clk\n",
423 __func__);
424 goto byte_intf_clk_err;
425 }
426
427 return 0;
428
429byte_intf_clk_err:
430 clk_disable_unprepare(msm_host->pixel_clk);
431pixel_clk_err:
432 clk_disable_unprepare(msm_host->byte_clk);
433byte_clk_err:
434 clk_disable_unprepare(msm_host->esc_clk);
435error:
436 return ret;
437}
438
439int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host)
440{
441 int ret;
442
443 DBG("Set clk rates: pclk=%d, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu",
444 msm_host->mode->clock, msm_host->byte_clk_rate,
445 msm_host->esc_clk_rate, msm_host->src_clk_rate);
446
447 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
448 if (ret) {
449 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
450 return ret;
451 }
452
453 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate);
454 if (ret) {
455 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret);
456 return ret;
457 }
458
459 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate);
460 if (ret) {
461 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret);
462 return ret;
463 }
464
465 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
466 if (ret) {
467 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
468 return ret;
469 }
470
471 return 0;
472}
473
474int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
475{
476 int ret;
477
478 ret = clk_prepare_enable(msm_host->byte_clk);
479 if (ret) {
480 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
481 goto error;
482 }
483
484 ret = clk_prepare_enable(msm_host->esc_clk);
485 if (ret) {
486 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
487 goto esc_clk_err;
488 }
489
490 ret = clk_prepare_enable(msm_host->src_clk);
491 if (ret) {
492 pr_err("%s: Failed to enable dsi src clk\n", __func__);
493 goto src_clk_err;
494 }
495
496 ret = clk_prepare_enable(msm_host->pixel_clk);
497 if (ret) {
498 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
499 goto pixel_clk_err;
500 }
501
502 return 0;
503
504pixel_clk_err:
505 clk_disable_unprepare(msm_host->src_clk);
506src_clk_err:
507 clk_disable_unprepare(msm_host->esc_clk);
508esc_clk_err:
509 clk_disable_unprepare(msm_host->byte_clk);
510error:
511 return ret;
512}
513
514void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host)
515{
516 /* Drop the performance state vote */
517 dev_pm_opp_set_rate(&msm_host->pdev->dev, 0);
518 clk_disable_unprepare(msm_host->esc_clk);
519 clk_disable_unprepare(msm_host->pixel_clk);
520 clk_disable_unprepare(msm_host->byte_intf_clk);
521 clk_disable_unprepare(msm_host->byte_clk);
522}
523
524void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host)
525{
526 clk_disable_unprepare(msm_host->pixel_clk);
527 clk_disable_unprepare(msm_host->src_clk);
528 clk_disable_unprepare(msm_host->esc_clk);
529 clk_disable_unprepare(msm_host->byte_clk);
530}
531
532static unsigned long dsi_adjust_pclk_for_compression(const struct drm_display_mode *mode,
533 const struct drm_dsc_config *dsc)
534{
535 int new_hdisplay = DIV_ROUND_UP(mode->hdisplay * drm_dsc_get_bpp_int(dsc),
536 dsc->bits_per_component * 3);
537
538 int new_htotal = mode->htotal - mode->hdisplay + new_hdisplay;
539
540 return new_htotal * mode->vtotal * drm_mode_vrefresh(mode);
541}
542
543static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode,
544 const struct drm_dsc_config *dsc, bool is_bonded_dsi)
545{
546 unsigned long pclk_rate;
547
548 pclk_rate = mode->clock * 1000;
549
550 if (dsc)
551 pclk_rate = dsi_adjust_pclk_for_compression(mode, dsc);
552
553 /*
554 * For bonded DSI mode, the current DRM mode has the complete width of the
555 * panel. Since, the complete panel is driven by two DSI controllers,
556 * the clock rates have to be split between the two dsi controllers.
557 * Adjust the byte and pixel clock rates for each dsi host accordingly.
558 */
559 if (is_bonded_dsi)
560 pclk_rate /= 2;
561
562 return pclk_rate;
563}
564
565unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_dsi,
566 const struct drm_display_mode *mode)
567{
568 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
569 u8 lanes = msm_host->lanes;
570 u32 bpp = dsi_get_bpp(msm_host->format);
571 unsigned long pclk_rate = dsi_get_pclk_rate(mode, msm_host->dsc, is_bonded_dsi);
572 unsigned long pclk_bpp;
573
574 if (lanes == 0) {
575 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
576 lanes = 1;
577 }
578
579 /* CPHY "byte_clk" is in units of 16 bits */
580 if (msm_host->cphy_mode)
581 pclk_bpp = mult_frac(pclk_rate, bpp, 16 * lanes);
582 else
583 pclk_bpp = mult_frac(pclk_rate, bpp, 8 * lanes);
584
585 return pclk_bpp;
586}
587
588static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
589{
590 msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode, msm_host->dsc, is_bonded_dsi);
591 msm_host->byte_clk_rate = dsi_byte_clk_get_rate(&msm_host->base, is_bonded_dsi,
592 msm_host->mode);
593
594 DBG("pclk=%lu, bclk=%lu", msm_host->pixel_clk_rate,
595 msm_host->byte_clk_rate);
596
597}
598
599int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
600{
601 if (!msm_host->mode) {
602 pr_err("%s: mode not set\n", __func__);
603 return -EINVAL;
604 }
605
606 dsi_calc_pclk(msm_host, is_bonded_dsi);
607 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
608 return 0;
609}
610
611int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
612{
613 u32 bpp = dsi_get_bpp(msm_host->format);
614 unsigned int esc_mhz, esc_div;
615 unsigned long byte_mhz;
616
617 dsi_calc_pclk(msm_host, is_bonded_dsi);
618
619 msm_host->src_clk_rate = mult_frac(msm_host->pixel_clk_rate, bpp, 8);
620
621 /*
622 * esc clock is byte clock followed by a 4 bit divider,
623 * we need to find an escape clock frequency within the
624 * mipi DSI spec range within the maximum divider limit
625 * We iterate here between an escape clock frequencey
626 * between 20 Mhz to 5 Mhz and pick up the first one
627 * that can be supported by our divider
628 */
629
630 byte_mhz = msm_host->byte_clk_rate / 1000000;
631
632 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) {
633 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz);
634
635 /*
636 * TODO: Ideally, we shouldn't know what sort of divider
637 * is available in mmss_cc, we're just assuming that
638 * it'll always be a 4 bit divider. Need to come up with
639 * a better way here.
640 */
641 if (esc_div >= 1 && esc_div <= 16)
642 break;
643 }
644
645 if (esc_mhz < 5)
646 return -EINVAL;
647
648 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div;
649
650 DBG("esc=%lu, src=%lu", msm_host->esc_clk_rate,
651 msm_host->src_clk_rate);
652
653 return 0;
654}
655
656static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable)
657{
658 u32 intr;
659 unsigned long flags;
660
661 spin_lock_irqsave(&msm_host->intr_lock, flags);
662 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
663
664 if (enable)
665 intr |= mask;
666 else
667 intr &= ~mask;
668
669 DBG("intr=%x enable=%d", intr, enable);
670
671 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);
672 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
673}
674
675static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags)
676{
677 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
678 return BURST_MODE;
679 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
680 return NON_BURST_SYNCH_PULSE;
681
682 return NON_BURST_SYNCH_EVENT;
683}
684
685static inline enum dsi_vid_dst_format dsi_get_vid_fmt(
686 const enum mipi_dsi_pixel_format mipi_fmt)
687{
688 switch (mipi_fmt) {
689 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888;
690 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE;
691 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666;
692 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565;
693 default: return VID_DST_FORMAT_RGB888;
694 }
695}
696
697static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(
698 const enum mipi_dsi_pixel_format mipi_fmt)
699{
700 switch (mipi_fmt) {
701 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888;
702 case MIPI_DSI_FMT_RGB666_PACKED:
703 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666;
704 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565;
705 default: return CMD_DST_FORMAT_RGB888;
706 }
707}
708
709static void dsi_ctrl_disable(struct msm_dsi_host *msm_host)
710{
711 dsi_write(msm_host, REG_DSI_CTRL, 0);
712}
713
714bool msm_dsi_host_is_wide_bus_enabled(struct mipi_dsi_host *host)
715{
716 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
717
718 return msm_host->dsc &&
719 (msm_host->cfg_hnd->major == MSM_DSI_VER_MAJOR_6G &&
720 msm_host->cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V2_5_0);
721}
722
723static void dsi_ctrl_enable(struct msm_dsi_host *msm_host,
724 struct msm_dsi_phy_shared_timings *phy_shared_timings, struct msm_dsi_phy *phy)
725{
726 u32 flags = msm_host->mode_flags;
727 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
728 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
729 u32 data = 0, lane_ctrl = 0;
730
731 if (flags & MIPI_DSI_MODE_VIDEO) {
732 if (flags & MIPI_DSI_MODE_VIDEO_HSE)
733 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE;
734 if (flags & MIPI_DSI_MODE_VIDEO_NO_HFP)
735 data |= DSI_VID_CFG0_HFP_POWER_STOP;
736 if (flags & MIPI_DSI_MODE_VIDEO_NO_HBP)
737 data |= DSI_VID_CFG0_HBP_POWER_STOP;
738 if (flags & MIPI_DSI_MODE_VIDEO_NO_HSA)
739 data |= DSI_VID_CFG0_HSA_POWER_STOP;
740 /* Always set low power stop mode for BLLP
741 * to let command engine send packets
742 */
743 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP |
744 DSI_VID_CFG0_BLLP_POWER_STOP;
745 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
746 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
747 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
748 dsi_write(msm_host, REG_DSI_VID_CFG0, data);
749
750 /* Do not swap RGB colors */
751 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB);
752 dsi_write(msm_host, REG_DSI_VID_CFG1, 0);
753 } else {
754 /* Do not swap RGB colors */
755 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB);
756 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt));
757 dsi_write(msm_host, REG_DSI_CMD_CFG0, data);
758
759 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) |
760 DSI_CMD_CFG1_WR_MEM_CONTINUE(
761 MIPI_DCS_WRITE_MEMORY_CONTINUE);
762 /* Always insert DCS command */
763 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND;
764 dsi_write(msm_host, REG_DSI_CMD_CFG1, data);
765
766 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
767 data = dsi_read(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2);
768
769 if (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_3)
770 data |= DSI_CMD_MODE_MDP_CTRL2_BURST_MODE;
771
772 /* TODO: Allow for video-mode support once tested/fixed */
773 if (msm_dsi_host_is_wide_bus_enabled(&msm_host->base))
774 data |= DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN;
775
776 dsi_write(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2, data);
777 }
778 }
779
780 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,
781 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER |
782 DSI_CMD_DMA_CTRL_LOW_POWER);
783
784 data = 0;
785 /* Always assume dedicated TE pin */
786 data |= DSI_TRIG_CTRL_TE;
787 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE);
788 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW);
789 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel);
790 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
791 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2))
792 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME;
793 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);
794
795 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) |
796 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre);
797 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);
798
799 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
800 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) &&
801 phy_shared_timings->clk_pre_inc_by_2)
802 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND,
803 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK);
804
805 data = 0;
806 if (!(flags & MIPI_DSI_MODE_NO_EOT_PACKET))
807 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND;
808 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);
809
810 /* allow only ack-err-status to generate interrupt */
811 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);
812
813 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
814
815 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
816
817 data = DSI_CTRL_CLK_EN;
818
819 DBG("lane number=%d", msm_host->lanes);
820 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0);
821
822 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
823 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap));
824
825 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) {
826 lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL);
827
828 if (msm_dsi_phy_set_continuous_clock(phy, true))
829 lane_ctrl &= ~DSI_LANE_CTRL_HS_REQ_SEL_PHY;
830
831 dsi_write(msm_host, REG_DSI_LANE_CTRL,
832 lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
833 }
834
835 data |= DSI_CTRL_ENABLE;
836
837 dsi_write(msm_host, REG_DSI_CTRL, data);
838
839 if (msm_host->cphy_mode)
840 dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0));
841}
842
843static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode, u32 hdisplay)
844{
845 struct drm_dsc_config *dsc = msm_host->dsc;
846 u32 reg, reg_ctrl, reg_ctrl2;
847 u32 slice_per_intf, total_bytes_per_intf;
848 u32 pkt_per_line;
849 u32 eol_byte_num;
850
851 /* first calculate dsc parameters and then program
852 * compress mode registers
853 */
854 slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay);
855
856 total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
857
858 eol_byte_num = total_bytes_per_intf % 3;
859
860 /*
861 * Typically, pkt_per_line = slice_per_intf * slice_per_pkt.
862 *
863 * Since the current driver only supports slice_per_pkt = 1,
864 * pkt_per_line will be equal to slice per intf for now.
865 */
866 pkt_per_line = slice_per_intf;
867
868 if (is_cmd_mode) /* packet data type */
869 reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE);
870 else
871 reg = DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(MIPI_DSI_COMPRESSED_PIXEL_STREAM);
872
873 /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE
874 * registers have similar offsets, so for below common code use
875 * DSI_VIDEO_COMPRESSION_MODE_XXXX for setting bits
876 */
877 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1);
878 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num);
879 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EN;
880
881 if (is_cmd_mode) {
882 reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL);
883 reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2);
884
885 reg_ctrl &= ~0xffff;
886 reg_ctrl |= reg;
887
888 reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK;
889 reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size);
890
891 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl);
892 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2);
893 } else {
894 dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);
895 }
896}
897
898static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
899{
900 struct drm_display_mode *mode = msm_host->mode;
901 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */
902 u32 h_total = mode->htotal;
903 u32 v_total = mode->vtotal;
904 u32 hs_end = mode->hsync_end - mode->hsync_start;
905 u32 vs_end = mode->vsync_end - mode->vsync_start;
906 u32 ha_start = h_total - mode->hsync_start;
907 u32 ha_end = ha_start + mode->hdisplay;
908 u32 va_start = v_total - mode->vsync_start;
909 u32 va_end = va_start + mode->vdisplay;
910 u32 hdisplay = mode->hdisplay;
911 u32 wc;
912 int ret;
913 bool wide_bus_enabled = msm_dsi_host_is_wide_bus_enabled(&msm_host->base);
914
915 DBG("");
916
917 /*
918 * For bonded DSI mode, the current DRM mode has
919 * the complete width of the panel. Since, the complete
920 * panel is driven by two DSI controllers, the horizontal
921 * timings have to be split between the two dsi controllers.
922 * Adjust the DSI host timing values accordingly.
923 */
924 if (is_bonded_dsi) {
925 h_total /= 2;
926 hs_end /= 2;
927 ha_start /= 2;
928 ha_end /= 2;
929 hdisplay /= 2;
930 }
931
932 if (msm_host->dsc) {
933 struct drm_dsc_config *dsc = msm_host->dsc;
934 u32 bytes_per_pclk;
935
936 /* update dsc params with timing params */
937 if (!dsc || !mode->hdisplay || !mode->vdisplay) {
938 pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n",
939 mode->hdisplay, mode->vdisplay);
940 return;
941 }
942
943 dsc->pic_width = mode->hdisplay;
944 dsc->pic_height = mode->vdisplay;
945 DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height);
946
947 /* we do the calculations for dsc parameters here so that
948 * panel can use these parameters
949 */
950 ret = dsi_populate_dsc_params(msm_host, dsc);
951 if (ret)
952 return;
953
954 /* Divide the display by 3 but keep back/font porch and
955 * pulse width same
956 */
957 h_total -= hdisplay;
958 if (wide_bus_enabled && !(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
959 bytes_per_pclk = 6;
960 else
961 bytes_per_pclk = 3;
962
963 hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), bytes_per_pclk);
964
965 h_total += hdisplay;
966 ha_end = ha_start + hdisplay;
967 }
968
969 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
970 if (msm_host->dsc)
971 dsi_update_dsc_timing(msm_host, false, mode->hdisplay);
972
973 dsi_write(msm_host, REG_DSI_ACTIVE_H,
974 DSI_ACTIVE_H_START(ha_start) |
975 DSI_ACTIVE_H_END(ha_end));
976 dsi_write(msm_host, REG_DSI_ACTIVE_V,
977 DSI_ACTIVE_V_START(va_start) |
978 DSI_ACTIVE_V_END(va_end));
979 dsi_write(msm_host, REG_DSI_TOTAL,
980 DSI_TOTAL_H_TOTAL(h_total - 1) |
981 DSI_TOTAL_V_TOTAL(v_total - 1));
982
983 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,
984 DSI_ACTIVE_HSYNC_START(hs_start) |
985 DSI_ACTIVE_HSYNC_END(hs_end));
986 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);
987 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,
988 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
989 DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
990 } else { /* command mode */
991 if (msm_host->dsc)
992 dsi_update_dsc_timing(msm_host, true, mode->hdisplay);
993
994 /* image data and 1 byte write_memory_start cmd */
995 if (!msm_host->dsc)
996 wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
997 else
998 /*
999 * When DSC is enabled, WC = slice_chunk_size * slice_per_pkt + 1.
1000 * Currently, the driver only supports default value of slice_per_pkt = 1
1001 *
1002 * TODO: Expand mipi_dsi_device struct to hold slice_per_pkt info
1003 * and adjust DSC math to account for slice_per_pkt.
1004 */
1005 wc = msm_host->dsc->slice_chunk_size + 1;
1006
1007 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,
1008 DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) |
1009 DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(
1010 msm_host->channel) |
1011 DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(
1012 MIPI_DSI_DCS_LONG_WRITE));
1013
1014 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL,
1015 DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) |
1016 DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay));
1017 }
1018}
1019
1020static void dsi_sw_reset(struct msm_dsi_host *msm_host)
1021{
1022 u32 ctrl;
1023
1024 ctrl = dsi_read(msm_host, REG_DSI_CTRL);
1025
1026 if (ctrl & DSI_CTRL_ENABLE) {
1027 dsi_write(msm_host, REG_DSI_CTRL, ctrl & ~DSI_CTRL_ENABLE);
1028 /*
1029 * dsi controller need to be disabled before
1030 * clocks turned on
1031 */
1032 wmb();
1033 }
1034
1035 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
1036 wmb(); /* clocks need to be enabled before reset */
1037
1038 /* dsi controller can only be reset while clocks are running */
1039 dsi_write(msm_host, REG_DSI_RESET, 1);
1040 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */
1041 dsi_write(msm_host, REG_DSI_RESET, 0);
1042 wmb(); /* controller out of reset */
1043
1044 if (ctrl & DSI_CTRL_ENABLE) {
1045 dsi_write(msm_host, REG_DSI_CTRL, ctrl);
1046 wmb(); /* make sure dsi controller enabled again */
1047 }
1048}
1049
1050static void dsi_op_mode_config(struct msm_dsi_host *msm_host,
1051 bool video_mode, bool enable)
1052{
1053 u32 dsi_ctrl;
1054
1055 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL);
1056
1057 if (!enable) {
1058 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN |
1059 DSI_CTRL_CMD_MODE_EN);
1060 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE |
1061 DSI_IRQ_MASK_VIDEO_DONE, 0);
1062 } else {
1063 if (video_mode) {
1064 dsi_ctrl |= DSI_CTRL_VID_MODE_EN;
1065 } else { /* command mode */
1066 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN;
1067 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1);
1068 }
1069 dsi_ctrl |= DSI_CTRL_ENABLE;
1070 }
1071
1072 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);
1073}
1074
1075static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host)
1076{
1077 u32 data;
1078
1079 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL);
1080
1081 if (mode == 0)
1082 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER;
1083 else
1084 data |= DSI_CMD_DMA_CTRL_LOW_POWER;
1085
1086 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);
1087}
1088
1089static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
1090{
1091 u32 ret = 0;
1092 struct device *dev = &msm_host->pdev->dev;
1093
1094 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1);
1095
1096 reinit_completion(&msm_host->video_comp);
1097
1098 ret = wait_for_completion_timeout(&msm_host->video_comp,
1099 msecs_to_jiffies(70));
1100
1101 if (ret == 0)
1102 DRM_DEV_ERROR(dev, "wait for video done timed out\n");
1103
1104 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0);
1105}
1106
1107static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
1108{
1109 u32 data;
1110
1111 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
1112 return;
1113
1114 data = dsi_read(msm_host, REG_DSI_STATUS0);
1115
1116 /* if video mode engine is not busy, its because
1117 * either timing engine was not turned on or the
1118 * DSI controller has finished transmitting the video
1119 * data already, so no need to wait in those cases
1120 */
1121 if (!(data & DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY))
1122 return;
1123
1124 if (msm_host->power_on && msm_host->enabled) {
1125 dsi_wait4video_done(msm_host);
1126 /* delay 4 ms to skip BLLP */
1127 usleep_range(2000, 4000);
1128 }
1129}
1130
1131int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size)
1132{
1133 struct drm_device *dev = msm_host->dev;
1134 struct msm_drm_private *priv = dev->dev_private;
1135 uint64_t iova;
1136 u8 *data;
1137
1138 msm_host->aspace = msm_gem_address_space_get(priv->kms->aspace);
1139
1140 data = msm_gem_kernel_new(dev, size, MSM_BO_WC,
1141 msm_host->aspace,
1142 &msm_host->tx_gem_obj, &iova);
1143
1144 if (IS_ERR(data)) {
1145 msm_host->tx_gem_obj = NULL;
1146 return PTR_ERR(data);
1147 }
1148
1149 msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem");
1150
1151 msm_host->tx_size = msm_host->tx_gem_obj->size;
1152
1153 return 0;
1154}
1155
1156int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size)
1157{
1158 struct drm_device *dev = msm_host->dev;
1159
1160 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size,
1161 &msm_host->tx_buf_paddr, GFP_KERNEL);
1162 if (!msm_host->tx_buf)
1163 return -ENOMEM;
1164
1165 msm_host->tx_size = size;
1166
1167 return 0;
1168}
1169
1170void msm_dsi_tx_buf_free(struct mipi_dsi_host *host)
1171{
1172 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1173 struct drm_device *dev = msm_host->dev;
1174
1175 /*
1176 * This is possible if we're tearing down before we've had a chance to
1177 * fully initialize. A very real possibility if our probe is deferred,
1178 * in which case we'll hit msm_dsi_host_destroy() without having run
1179 * through the dsi_tx_buf_alloc().
1180 */
1181 if (!dev)
1182 return;
1183
1184 if (msm_host->tx_gem_obj) {
1185 msm_gem_kernel_put(msm_host->tx_gem_obj, msm_host->aspace);
1186 msm_gem_address_space_put(msm_host->aspace);
1187 msm_host->tx_gem_obj = NULL;
1188 msm_host->aspace = NULL;
1189 }
1190
1191 if (msm_host->tx_buf)
1192 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf,
1193 msm_host->tx_buf_paddr);
1194}
1195
1196void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host)
1197{
1198 return msm_gem_get_vaddr(msm_host->tx_gem_obj);
1199}
1200
1201void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host)
1202{
1203 return msm_host->tx_buf;
1204}
1205
1206void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host)
1207{
1208 msm_gem_put_vaddr(msm_host->tx_gem_obj);
1209}
1210
1211/*
1212 * prepare cmd buffer to be txed
1213 */
1214static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host,
1215 const struct mipi_dsi_msg *msg)
1216{
1217 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1218 struct mipi_dsi_packet packet;
1219 int len;
1220 int ret;
1221 u8 *data;
1222
1223 ret = mipi_dsi_create_packet(&packet, msg);
1224 if (ret) {
1225 pr_err("%s: create packet failed, %d\n", __func__, ret);
1226 return ret;
1227 }
1228 len = (packet.size + 3) & (~0x3);
1229
1230 if (len > msm_host->tx_size) {
1231 pr_err("%s: packet size is too big\n", __func__);
1232 return -EINVAL;
1233 }
1234
1235 data = cfg_hnd->ops->tx_buf_get(msm_host);
1236 if (IS_ERR(data)) {
1237 ret = PTR_ERR(data);
1238 pr_err("%s: get vaddr failed, %d\n", __func__, ret);
1239 return ret;
1240 }
1241
1242 /* MSM specific command format in memory */
1243 data[0] = packet.header[1];
1244 data[1] = packet.header[2];
1245 data[2] = packet.header[0];
1246 data[3] = BIT(7); /* Last packet */
1247 if (mipi_dsi_packet_format_is_long(msg->type))
1248 data[3] |= BIT(6);
1249 if (msg->rx_buf && msg->rx_len)
1250 data[3] |= BIT(5);
1251
1252 /* Long packet */
1253 if (packet.payload && packet.payload_length)
1254 memcpy(data + 4, packet.payload, packet.payload_length);
1255
1256 /* Append 0xff to the end */
1257 if (packet.size < len)
1258 memset(data + packet.size, 0xff, len - packet.size);
1259
1260 if (cfg_hnd->ops->tx_buf_put)
1261 cfg_hnd->ops->tx_buf_put(msm_host);
1262
1263 return len;
1264}
1265
1266/*
1267 * dsi_short_read1_resp: 1 parameter
1268 */
1269static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1270{
1271 u8 *data = msg->rx_buf;
1272 if (data && (msg->rx_len >= 1)) {
1273 *data = buf[1]; /* strip out dcs type */
1274 return 1;
1275 } else {
1276 pr_err("%s: read data does not match with rx_buf len %zu\n",
1277 __func__, msg->rx_len);
1278 return -EINVAL;
1279 }
1280}
1281
1282/*
1283 * dsi_short_read2_resp: 2 parameter
1284 */
1285static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1286{
1287 u8 *data = msg->rx_buf;
1288 if (data && (msg->rx_len >= 2)) {
1289 data[0] = buf[1]; /* strip out dcs type */
1290 data[1] = buf[2];
1291 return 2;
1292 } else {
1293 pr_err("%s: read data does not match with rx_buf len %zu\n",
1294 __func__, msg->rx_len);
1295 return -EINVAL;
1296 }
1297}
1298
1299static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1300{
1301 /* strip out 4 byte dcs header */
1302 if (msg->rx_buf && msg->rx_len)
1303 memcpy(msg->rx_buf, buf + 4, msg->rx_len);
1304
1305 return msg->rx_len;
1306}
1307
1308int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base)
1309{
1310 struct drm_device *dev = msm_host->dev;
1311 struct msm_drm_private *priv = dev->dev_private;
1312
1313 if (!dma_base)
1314 return -EINVAL;
1315
1316 return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj,
1317 priv->kms->aspace, dma_base);
1318}
1319
1320int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base)
1321{
1322 if (!dma_base)
1323 return -EINVAL;
1324
1325 *dma_base = msm_host->tx_buf_paddr;
1326 return 0;
1327}
1328
1329static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len)
1330{
1331 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1332 int ret;
1333 uint64_t dma_base;
1334 bool triggered;
1335
1336 ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base);
1337 if (ret) {
1338 pr_err("%s: failed to get iova: %d\n", __func__, ret);
1339 return ret;
1340 }
1341
1342 reinit_completion(&msm_host->dma_comp);
1343
1344 dsi_wait4video_eng_busy(msm_host);
1345
1346 triggered = msm_dsi_manager_cmd_xfer_trigger(
1347 msm_host->id, dma_base, len);
1348 if (triggered) {
1349 ret = wait_for_completion_timeout(&msm_host->dma_comp,
1350 msecs_to_jiffies(200));
1351 DBG("ret=%d", ret);
1352 if (ret == 0)
1353 ret = -ETIMEDOUT;
1354 else
1355 ret = len;
1356 } else
1357 ret = len;
1358
1359 return ret;
1360}
1361
1362static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host,
1363 u8 *buf, int rx_byte, int pkt_size)
1364{
1365 u32 *temp, data;
1366 int i, j = 0, cnt;
1367 u32 read_cnt;
1368 u8 reg[16];
1369 int repeated_bytes = 0;
1370 int buf_offset = buf - msm_host->rx_buf;
1371
1372 temp = (u32 *)reg;
1373 cnt = (rx_byte + 3) >> 2;
1374 if (cnt > 4)
1375 cnt = 4; /* 4 x 32 bits registers only */
1376
1377 if (rx_byte == 4)
1378 read_cnt = 4;
1379 else
1380 read_cnt = pkt_size + 6;
1381
1382 /*
1383 * In case of multiple reads from the panel, after the first read, there
1384 * is possibility that there are some bytes in the payload repeating in
1385 * the RDBK_DATA registers. Since we read all the parameters from the
1386 * panel right from the first byte for every pass. We need to skip the
1387 * repeating bytes and then append the new parameters to the rx buffer.
1388 */
1389 if (read_cnt > 16) {
1390 int bytes_shifted;
1391 /* Any data more than 16 bytes will be shifted out.
1392 * The temp read buffer should already contain these bytes.
1393 * The remaining bytes in read buffer are the repeated bytes.
1394 */
1395 bytes_shifted = read_cnt - 16;
1396 repeated_bytes = buf_offset - bytes_shifted;
1397 }
1398
1399 for (i = cnt - 1; i >= 0; i--) {
1400 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i));
1401 *temp++ = ntohl(data); /* to host byte order */
1402 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data));
1403 }
1404
1405 for (i = repeated_bytes; i < 16; i++)
1406 buf[j++] = reg[i];
1407
1408 return j;
1409}
1410
1411static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host,
1412 const struct mipi_dsi_msg *msg)
1413{
1414 int len, ret;
1415 int bllp_len = msm_host->mode->hdisplay *
1416 dsi_get_bpp(msm_host->format) / 8;
1417
1418 len = dsi_cmd_dma_add(msm_host, msg);
1419 if (len < 0) {
1420 pr_err("%s: failed to add cmd type = 0x%x\n",
1421 __func__, msg->type);
1422 return len;
1423 }
1424
1425 /* for video mode, do not send cmds more than
1426 * one pixel line, since it only transmit it
1427 * during BLLP.
1428 */
1429 /* TODO: if the command is sent in LP mode, the bit rate is only
1430 * half of esc clk rate. In this case, if the video is already
1431 * actively streaming, we need to check more carefully if the
1432 * command can be fit into one BLLP.
1433 */
1434 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) {
1435 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n",
1436 __func__, len);
1437 return -EINVAL;
1438 }
1439
1440 ret = dsi_cmd_dma_tx(msm_host, len);
1441 if (ret < 0) {
1442 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d, ret=%d\n",
1443 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len, ret);
1444 return ret;
1445 } else if (ret < len) {
1446 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, ret=%d len=%d\n",
1447 __func__, msg->type, (*(u8 *)(msg->tx_buf)), ret, len);
1448 return -EIO;
1449 }
1450
1451 return len;
1452}
1453
1454static void dsi_err_worker(struct work_struct *work)
1455{
1456 struct msm_dsi_host *msm_host =
1457 container_of(work, struct msm_dsi_host, err_work);
1458 u32 status = msm_host->err_work_state;
1459
1460 pr_err_ratelimited("%s: status=%x\n", __func__, status);
1461 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW)
1462 dsi_sw_reset(msm_host);
1463
1464 /* It is safe to clear here because error irq is disabled. */
1465 msm_host->err_work_state = 0;
1466
1467 /* enable dsi error interrupt */
1468 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
1469}
1470
1471static void dsi_ack_err_status(struct msm_dsi_host *msm_host)
1472{
1473 u32 status;
1474
1475 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS);
1476
1477 if (status) {
1478 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);
1479 /* Writing of an extra 0 needed to clear error bits */
1480 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);
1481 msm_host->err_work_state |= DSI_ERR_STATE_ACK;
1482 }
1483}
1484
1485static void dsi_timeout_status(struct msm_dsi_host *msm_host)
1486{
1487 u32 status;
1488
1489 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS);
1490
1491 if (status) {
1492 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);
1493 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT;
1494 }
1495}
1496
1497static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host)
1498{
1499 u32 status;
1500
1501 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR);
1502
1503 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC |
1504 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC |
1505 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL |
1506 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 |
1507 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) {
1508 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);
1509 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY;
1510 }
1511}
1512
1513static void dsi_fifo_status(struct msm_dsi_host *msm_host)
1514{
1515 u32 status;
1516
1517 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS);
1518
1519 /* fifo underflow, overflow */
1520 if (status) {
1521 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);
1522 msm_host->err_work_state |= DSI_ERR_STATE_FIFO;
1523 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW)
1524 msm_host->err_work_state |=
1525 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW;
1526 }
1527}
1528
1529static void dsi_status(struct msm_dsi_host *msm_host)
1530{
1531 u32 status;
1532
1533 status = dsi_read(msm_host, REG_DSI_STATUS0);
1534
1535 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) {
1536 dsi_write(msm_host, REG_DSI_STATUS0, status);
1537 msm_host->err_work_state |=
1538 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION;
1539 }
1540}
1541
1542static void dsi_clk_status(struct msm_dsi_host *msm_host)
1543{
1544 u32 status;
1545
1546 status = dsi_read(msm_host, REG_DSI_CLK_STATUS);
1547
1548 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) {
1549 dsi_write(msm_host, REG_DSI_CLK_STATUS, status);
1550 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED;
1551 }
1552}
1553
1554static void dsi_error(struct msm_dsi_host *msm_host)
1555{
1556 /* disable dsi error interrupt */
1557 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0);
1558
1559 dsi_clk_status(msm_host);
1560 dsi_fifo_status(msm_host);
1561 dsi_ack_err_status(msm_host);
1562 dsi_timeout_status(msm_host);
1563 dsi_status(msm_host);
1564 dsi_dln0_phy_err(msm_host);
1565
1566 queue_work(msm_host->workqueue, &msm_host->err_work);
1567}
1568
1569static irqreturn_t dsi_host_irq(int irq, void *ptr)
1570{
1571 struct msm_dsi_host *msm_host = ptr;
1572 u32 isr;
1573 unsigned long flags;
1574
1575 if (!msm_host->ctrl_base)
1576 return IRQ_HANDLED;
1577
1578 spin_lock_irqsave(&msm_host->intr_lock, flags);
1579 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
1580 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);
1581 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
1582
1583 DBG("isr=0x%x, id=%d", isr, msm_host->id);
1584
1585 if (isr & DSI_IRQ_ERROR)
1586 dsi_error(msm_host);
1587
1588 if (isr & DSI_IRQ_VIDEO_DONE)
1589 complete(&msm_host->video_comp);
1590
1591 if (isr & DSI_IRQ_CMD_DMA_DONE)
1592 complete(&msm_host->dma_comp);
1593
1594 return IRQ_HANDLED;
1595}
1596
1597static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host,
1598 struct device *panel_device)
1599{
1600 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device,
1601 "disp-enable",
1602 GPIOD_OUT_LOW);
1603 if (IS_ERR(msm_host->disp_en_gpio)) {
1604 DBG("cannot get disp-enable-gpios %ld",
1605 PTR_ERR(msm_host->disp_en_gpio));
1606 return PTR_ERR(msm_host->disp_en_gpio);
1607 }
1608
1609 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te",
1610 GPIOD_IN);
1611 if (IS_ERR(msm_host->te_gpio)) {
1612 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio));
1613 return PTR_ERR(msm_host->te_gpio);
1614 }
1615
1616 return 0;
1617}
1618
1619static int dsi_host_attach(struct mipi_dsi_host *host,
1620 struct mipi_dsi_device *dsi)
1621{
1622 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1623 int ret;
1624
1625 if (dsi->lanes > msm_host->num_data_lanes)
1626 return -EINVAL;
1627
1628 msm_host->channel = dsi->channel;
1629 msm_host->lanes = dsi->lanes;
1630 msm_host->format = dsi->format;
1631 msm_host->mode_flags = dsi->mode_flags;
1632 if (dsi->dsc)
1633 msm_host->dsc = dsi->dsc;
1634
1635 /* Some gpios defined in panel DT need to be controlled by host */
1636 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev);
1637 if (ret)
1638 return ret;
1639
1640 ret = dsi_dev_attach(msm_host->pdev);
1641 if (ret)
1642 return ret;
1643
1644 DBG("id=%d", msm_host->id);
1645
1646 return 0;
1647}
1648
1649static int dsi_host_detach(struct mipi_dsi_host *host,
1650 struct mipi_dsi_device *dsi)
1651{
1652 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1653
1654 dsi_dev_detach(msm_host->pdev);
1655
1656 DBG("id=%d", msm_host->id);
1657
1658 return 0;
1659}
1660
1661static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
1662 const struct mipi_dsi_msg *msg)
1663{
1664 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1665 int ret;
1666
1667 if (!msg || !msm_host->power_on)
1668 return -EINVAL;
1669
1670 mutex_lock(&msm_host->cmd_mutex);
1671 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg);
1672 mutex_unlock(&msm_host->cmd_mutex);
1673
1674 return ret;
1675}
1676
1677static const struct mipi_dsi_host_ops dsi_host_ops = {
1678 .attach = dsi_host_attach,
1679 .detach = dsi_host_detach,
1680 .transfer = dsi_host_transfer,
1681};
1682
1683/*
1684 * List of supported physical to logical lane mappings.
1685 * For example, the 2nd entry represents the following mapping:
1686 *
1687 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
1688 */
1689static const int supported_data_lane_swaps[][4] = {
1690 { 0, 1, 2, 3 },
1691 { 3, 0, 1, 2 },
1692 { 2, 3, 0, 1 },
1693 { 1, 2, 3, 0 },
1694 { 0, 3, 2, 1 },
1695 { 1, 0, 3, 2 },
1696 { 2, 1, 0, 3 },
1697 { 3, 2, 1, 0 },
1698};
1699
1700static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
1701 struct device_node *ep)
1702{
1703 struct device *dev = &msm_host->pdev->dev;
1704 struct property *prop;
1705 u32 lane_map[4];
1706 int ret, i, len, num_lanes;
1707
1708 prop = of_find_property(ep, "data-lanes", &len);
1709 if (!prop) {
1710 DRM_DEV_DEBUG(dev,
1711 "failed to find data lane mapping, using default\n");
1712 /* Set the number of date lanes to 4 by default. */
1713 msm_host->num_data_lanes = 4;
1714 return 0;
1715 }
1716
1717 num_lanes = drm_of_get_data_lanes_count(ep, 1, 4);
1718 if (num_lanes < 0) {
1719 DRM_DEV_ERROR(dev, "bad number of data lanes\n");
1720 return num_lanes;
1721 }
1722
1723 msm_host->num_data_lanes = num_lanes;
1724
1725 ret = of_property_read_u32_array(ep, "data-lanes", lane_map,
1726 num_lanes);
1727 if (ret) {
1728 DRM_DEV_ERROR(dev, "failed to read lane data\n");
1729 return ret;
1730 }
1731
1732 /*
1733 * compare DT specified physical-logical lane mappings with the ones
1734 * supported by hardware
1735 */
1736 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) {
1737 const int *swap = supported_data_lane_swaps[i];
1738 int j;
1739
1740 /*
1741 * the data-lanes array we get from DT has a logical->physical
1742 * mapping. The "data lane swap" register field represents
1743 * supported configurations in a physical->logical mapping.
1744 * Translate the DT mapping to what we understand and find a
1745 * configuration that works.
1746 */
1747 for (j = 0; j < num_lanes; j++) {
1748 if (lane_map[j] < 0 || lane_map[j] > 3)
1749 DRM_DEV_ERROR(dev, "bad physical lane entry %u\n",
1750 lane_map[j]);
1751
1752 if (swap[lane_map[j]] != j)
1753 break;
1754 }
1755
1756 if (j == num_lanes) {
1757 msm_host->dlane_swap = i;
1758 return 0;
1759 }
1760 }
1761
1762 return -EINVAL;
1763}
1764
1765static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc)
1766{
1767 int ret;
1768
1769 if (dsc->bits_per_pixel & 0xf) {
1770 DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n");
1771 return -EINVAL;
1772 }
1773
1774 if (dsc->bits_per_component != 8) {
1775 DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support bits_per_component != 8 yet\n");
1776 return -EOPNOTSUPP;
1777 }
1778
1779 dsc->simple_422 = 0;
1780 dsc->convert_rgb = 1;
1781 dsc->vbr_enable = 0;
1782
1783 drm_dsc_set_const_params(dsc);
1784 drm_dsc_set_rc_buf_thresh(dsc);
1785
1786 /* handle only bpp = bpc = 8, pre-SCR panels */
1787 ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR);
1788 if (ret) {
1789 DRM_DEV_ERROR(&msm_host->pdev->dev, "could not find DSC RC parameters\n");
1790 return ret;
1791 }
1792
1793 dsc->initial_scale_value = drm_dsc_initial_scale_value(dsc);
1794 dsc->line_buf_depth = dsc->bits_per_component + 1;
1795
1796 return drm_dsc_compute_rc_parameters(dsc);
1797}
1798
1799static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
1800{
1801 struct device *dev = &msm_host->pdev->dev;
1802 struct device_node *np = dev->of_node;
1803 struct device_node *endpoint;
1804 int ret = 0;
1805
1806 /*
1807 * Get the endpoint of the output port of the DSI host. In our case,
1808 * this is mapped to port number with reg = 1. Don't return an error if
1809 * the remote endpoint isn't defined. It's possible that there is
1810 * nothing connected to the dsi output.
1811 */
1812 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1813 if (!endpoint) {
1814 DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__);
1815 return 0;
1816 }
1817
1818 ret = dsi_host_parse_lane_data(msm_host, endpoint);
1819 if (ret) {
1820 DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n",
1821 __func__, ret);
1822 ret = -EINVAL;
1823 goto err;
1824 }
1825
1826 if (of_property_read_bool(np, "syscon-sfpb")) {
1827 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np,
1828 "syscon-sfpb");
1829 if (IS_ERR(msm_host->sfpb)) {
1830 DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n",
1831 __func__);
1832 ret = PTR_ERR(msm_host->sfpb);
1833 }
1834 }
1835
1836err:
1837 of_node_put(endpoint);
1838
1839 return ret;
1840}
1841
1842static int dsi_host_get_id(struct msm_dsi_host *msm_host)
1843{
1844 struct platform_device *pdev = msm_host->pdev;
1845 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
1846 struct resource *res;
1847 int i, j;
1848
1849 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl");
1850 if (!res)
1851 return -EINVAL;
1852
1853 for (i = 0; i < VARIANTS_MAX; i++)
1854 for (j = 0; j < DSI_MAX; j++)
1855 if (cfg->io_start[i][j] == res->start)
1856 return j;
1857
1858 return -EINVAL;
1859}
1860
1861int msm_dsi_host_init(struct msm_dsi *msm_dsi)
1862{
1863 struct msm_dsi_host *msm_host = NULL;
1864 struct platform_device *pdev = msm_dsi->pdev;
1865 const struct msm_dsi_config *cfg;
1866 int ret;
1867
1868 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
1869 if (!msm_host) {
1870 return -ENOMEM;
1871 }
1872
1873 msm_host->pdev = pdev;
1874 msm_dsi->host = &msm_host->base;
1875
1876 ret = dsi_host_parse_dt(msm_host);
1877 if (ret) {
1878 pr_err("%s: failed to parse dt\n", __func__);
1879 return ret;
1880 }
1881
1882 msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", &msm_host->ctrl_size);
1883 if (IS_ERR(msm_host->ctrl_base)) {
1884 pr_err("%s: unable to map Dsi ctrl base\n", __func__);
1885 return PTR_ERR(msm_host->ctrl_base);
1886 }
1887
1888 pm_runtime_enable(&pdev->dev);
1889
1890 msm_host->cfg_hnd = dsi_get_config(msm_host);
1891 if (!msm_host->cfg_hnd) {
1892 pr_err("%s: get config failed\n", __func__);
1893 return -EINVAL;
1894 }
1895 cfg = msm_host->cfg_hnd->cfg;
1896
1897 msm_host->id = dsi_host_get_id(msm_host);
1898 if (msm_host->id < 0) {
1899 pr_err("%s: unable to identify DSI host index\n", __func__);
1900 return msm_host->id;
1901 }
1902
1903 /* fixup base address by io offset */
1904 msm_host->ctrl_base += cfg->io_offset;
1905
1906 ret = devm_regulator_bulk_get_const(&pdev->dev, cfg->num_regulators,
1907 cfg->regulator_data,
1908 &msm_host->supplies);
1909 if (ret)
1910 return ret;
1911
1912 ret = dsi_clk_init(msm_host);
1913 if (ret) {
1914 pr_err("%s: unable to initialize dsi clks\n", __func__);
1915 return ret;
1916 }
1917
1918 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL);
1919 if (!msm_host->rx_buf) {
1920 pr_err("%s: alloc rx temp buf failed\n", __func__);
1921 return -ENOMEM;
1922 }
1923
1924 ret = devm_pm_opp_set_clkname(&pdev->dev, "byte");
1925 if (ret)
1926 return ret;
1927 /* OPP table is optional */
1928 ret = devm_pm_opp_of_add_table(&pdev->dev);
1929 if (ret && ret != -ENODEV) {
1930 dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1931 return ret;
1932 }
1933
1934 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1935 if (!msm_host->irq) {
1936 dev_err(&pdev->dev, "failed to get irq\n");
1937 return -EINVAL;
1938 }
1939
1940 /* do not autoenable, will be enabled later */
1941 ret = devm_request_irq(&pdev->dev, msm_host->irq, dsi_host_irq,
1942 IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN,
1943 "dsi_isr", msm_host);
1944 if (ret < 0) {
1945 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n",
1946 msm_host->irq, ret);
1947 return ret;
1948 }
1949
1950 init_completion(&msm_host->dma_comp);
1951 init_completion(&msm_host->video_comp);
1952 mutex_init(&msm_host->dev_mutex);
1953 mutex_init(&msm_host->cmd_mutex);
1954 spin_lock_init(&msm_host->intr_lock);
1955
1956 /* setup workqueue */
1957 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0);
1958 if (!msm_host->workqueue)
1959 return -ENOMEM;
1960
1961 INIT_WORK(&msm_host->err_work, dsi_err_worker);
1962
1963 msm_dsi->id = msm_host->id;
1964
1965 DBG("Dsi Host %d initialized", msm_host->id);
1966 return 0;
1967}
1968
1969void msm_dsi_host_destroy(struct mipi_dsi_host *host)
1970{
1971 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1972
1973 DBG("");
1974 if (msm_host->workqueue) {
1975 destroy_workqueue(msm_host->workqueue);
1976 msm_host->workqueue = NULL;
1977 }
1978
1979 mutex_destroy(&msm_host->cmd_mutex);
1980 mutex_destroy(&msm_host->dev_mutex);
1981
1982 pm_runtime_disable(&msm_host->pdev->dev);
1983}
1984
1985int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
1986 struct drm_device *dev)
1987{
1988 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1989 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1990 int ret;
1991
1992 msm_host->dev = dev;
1993
1994 ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K);
1995 if (ret) {
1996 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
1997 return ret;
1998 }
1999
2000 return 0;
2001}
2002
2003int msm_dsi_host_register(struct mipi_dsi_host *host)
2004{
2005 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2006 int ret;
2007
2008 /* Register mipi dsi host */
2009 if (!msm_host->registered) {
2010 host->dev = &msm_host->pdev->dev;
2011 host->ops = &dsi_host_ops;
2012 ret = mipi_dsi_host_register(host);
2013 if (ret)
2014 return ret;
2015
2016 msm_host->registered = true;
2017 }
2018
2019 return 0;
2020}
2021
2022void msm_dsi_host_unregister(struct mipi_dsi_host *host)
2023{
2024 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2025
2026 if (msm_host->registered) {
2027 mipi_dsi_host_unregister(host);
2028 host->dev = NULL;
2029 host->ops = NULL;
2030 msm_host->registered = false;
2031 }
2032}
2033
2034int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
2035 const struct mipi_dsi_msg *msg)
2036{
2037 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2038 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2039
2040 /* TODO: make sure dsi_cmd_mdp is idle.
2041 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME
2042 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed.
2043 * How to handle the old versions? Wait for mdp cmd done?
2044 */
2045
2046 /*
2047 * mdss interrupt is generated in mdp core clock domain
2048 * mdp clock need to be enabled to receive dsi interrupt
2049 */
2050 pm_runtime_get_sync(&msm_host->pdev->dev);
2051 cfg_hnd->ops->link_clk_set_rate(msm_host);
2052 cfg_hnd->ops->link_clk_enable(msm_host);
2053
2054 /* TODO: vote for bus bandwidth */
2055
2056 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
2057 dsi_set_tx_power_mode(0, msm_host);
2058
2059 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL);
2060 dsi_write(msm_host, REG_DSI_CTRL,
2061 msm_host->dma_cmd_ctrl_restore |
2062 DSI_CTRL_CMD_MODE_EN |
2063 DSI_CTRL_ENABLE);
2064 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1);
2065
2066 return 0;
2067}
2068
2069void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
2070 const struct mipi_dsi_msg *msg)
2071{
2072 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2073 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2074
2075 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0);
2076 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);
2077
2078 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
2079 dsi_set_tx_power_mode(1, msm_host);
2080
2081 /* TODO: unvote for bus bandwidth */
2082
2083 cfg_hnd->ops->link_clk_disable(msm_host);
2084 pm_runtime_put(&msm_host->pdev->dev);
2085}
2086
2087int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host,
2088 const struct mipi_dsi_msg *msg)
2089{
2090 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2091
2092 return dsi_cmds2buf_tx(msm_host, msg);
2093}
2094
2095int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host,
2096 const struct mipi_dsi_msg *msg)
2097{
2098 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2099 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2100 int data_byte, rx_byte, dlen, end;
2101 int short_response, diff, pkt_size, ret = 0;
2102 char cmd;
2103 int rlen = msg->rx_len;
2104 u8 *buf;
2105
2106 if (rlen <= 2) {
2107 short_response = 1;
2108 pkt_size = rlen;
2109 rx_byte = 4;
2110 } else {
2111 short_response = 0;
2112 data_byte = 10; /* first read */
2113 if (rlen < data_byte)
2114 pkt_size = rlen;
2115 else
2116 pkt_size = data_byte;
2117 rx_byte = data_byte + 6; /* 4 header + 2 crc */
2118 }
2119
2120 buf = msm_host->rx_buf;
2121 end = 0;
2122 while (!end) {
2123 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8};
2124 struct mipi_dsi_msg max_pkt_size_msg = {
2125 .channel = msg->channel,
2126 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
2127 .tx_len = 2,
2128 .tx_buf = tx,
2129 };
2130
2131 DBG("rlen=%d pkt_size=%d rx_byte=%d",
2132 rlen, pkt_size, rx_byte);
2133
2134 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg);
2135 if (ret < 2) {
2136 pr_err("%s: Set max pkt size failed, %d\n",
2137 __func__, ret);
2138 return -EINVAL;
2139 }
2140
2141 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
2142 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) {
2143 /* Clear the RDBK_DATA registers */
2144 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,
2145 DSI_RDBK_DATA_CTRL_CLR);
2146 wmb(); /* make sure the RDBK registers are cleared */
2147 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);
2148 wmb(); /* release cleared status before transfer */
2149 }
2150
2151 ret = dsi_cmds2buf_tx(msm_host, msg);
2152 if (ret < 0) {
2153 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret);
2154 return ret;
2155 } else if (ret < msg->tx_len) {
2156 pr_err("%s: Read cmd Tx failed, too short: %d\n", __func__, ret);
2157 return -ECOMM;
2158 }
2159
2160 /*
2161 * once cmd_dma_done interrupt received,
2162 * return data from client is ready and stored
2163 * at RDBK_DATA register already
2164 * since rx fifo is 16 bytes, dcs header is kept at first loop,
2165 * after that dcs header lost during shift into registers
2166 */
2167 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size);
2168
2169 if (dlen <= 0)
2170 return 0;
2171
2172 if (short_response)
2173 break;
2174
2175 if (rlen <= data_byte) {
2176 diff = data_byte - rlen;
2177 end = 1;
2178 } else {
2179 diff = 0;
2180 rlen -= data_byte;
2181 }
2182
2183 if (!end) {
2184 dlen -= 2; /* 2 crc */
2185 dlen -= diff;
2186 buf += dlen; /* next start position */
2187 data_byte = 14; /* NOT first read */
2188 if (rlen < data_byte)
2189 pkt_size += rlen;
2190 else
2191 pkt_size += data_byte;
2192 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff);
2193 }
2194 }
2195
2196 /*
2197 * For single Long read, if the requested rlen < 10,
2198 * we need to shift the start position of rx
2199 * data buffer to skip the bytes which are not
2200 * updated.
2201 */
2202 if (pkt_size < 10 && !short_response)
2203 buf = msm_host->rx_buf + (10 - rlen);
2204 else
2205 buf = msm_host->rx_buf;
2206
2207 cmd = buf[0];
2208 switch (cmd) {
2209 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
2210 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__);
2211 ret = 0;
2212 break;
2213 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
2214 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
2215 ret = dsi_short_read1_resp(buf, msg);
2216 break;
2217 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
2218 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
2219 ret = dsi_short_read2_resp(buf, msg);
2220 break;
2221 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
2222 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
2223 ret = dsi_long_read_resp(buf, msg);
2224 break;
2225 default:
2226 pr_warn("%s:Invalid response cmd\n", __func__);
2227 ret = 0;
2228 }
2229
2230 return ret;
2231}
2232
2233void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base,
2234 u32 len)
2235{
2236 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2237
2238 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base);
2239 dsi_write(msm_host, REG_DSI_DMA_LEN, len);
2240 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);
2241
2242 /* Make sure trigger happens */
2243 wmb();
2244}
2245
2246void msm_dsi_host_set_phy_mode(struct mipi_dsi_host *host,
2247 struct msm_dsi_phy *src_phy)
2248{
2249 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2250
2251 msm_host->cphy_mode = src_phy->cphy_mode;
2252}
2253
2254void msm_dsi_host_reset_phy(struct mipi_dsi_host *host)
2255{
2256 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2257
2258 DBG("");
2259 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);
2260 /* Make sure fully reset */
2261 wmb();
2262 udelay(1000);
2263 dsi_write(msm_host, REG_DSI_PHY_RESET, 0);
2264 udelay(100);
2265}
2266
2267void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
2268 struct msm_dsi_phy_clk_request *clk_req,
2269 bool is_bonded_dsi)
2270{
2271 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2272 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2273 int ret;
2274
2275 ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_bonded_dsi);
2276 if (ret) {
2277 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
2278 return;
2279 }
2280
2281 /* CPHY transmits 16 bits over 7 clock cycles
2282 * "byte_clk" is in units of 16-bits (see dsi_calc_pclk),
2283 * so multiply by 7 to get the "bitclk rate"
2284 */
2285 if (msm_host->cphy_mode)
2286 clk_req->bitclk_rate = msm_host->byte_clk_rate * 7;
2287 else
2288 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8;
2289 clk_req->escclk_rate = msm_host->esc_clk_rate;
2290}
2291
2292void msm_dsi_host_enable_irq(struct mipi_dsi_host *host)
2293{
2294 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2295
2296 enable_irq(msm_host->irq);
2297}
2298
2299void msm_dsi_host_disable_irq(struct mipi_dsi_host *host)
2300{
2301 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2302
2303 disable_irq(msm_host->irq);
2304}
2305
2306int msm_dsi_host_enable(struct mipi_dsi_host *host)
2307{
2308 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2309
2310 dsi_op_mode_config(msm_host,
2311 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true);
2312
2313 /* TODO: clock should be turned off for command mode,
2314 * and only turned on before MDP START.
2315 * This part of code should be enabled once mdp driver support it.
2316 */
2317 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) {
2318 * dsi_link_clk_disable(msm_host);
2319 * pm_runtime_put(&msm_host->pdev->dev);
2320 * }
2321 */
2322 msm_host->enabled = true;
2323 return 0;
2324}
2325
2326int msm_dsi_host_disable(struct mipi_dsi_host *host)
2327{
2328 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2329
2330 msm_host->enabled = false;
2331 dsi_op_mode_config(msm_host,
2332 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false);
2333
2334 /* Since we have disabled INTF, the video engine won't stop so that
2335 * the cmd engine will be blocked.
2336 * Reset to disable video engine so that we can send off cmd.
2337 */
2338 dsi_sw_reset(msm_host);
2339
2340 return 0;
2341}
2342
2343static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable)
2344{
2345 enum sfpb_ahb_arb_master_port_en en;
2346
2347 if (!msm_host->sfpb)
2348 return;
2349
2350 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE;
2351
2352 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG,
2353 SFPB_GPREG_MASTER_PORT_EN__MASK,
2354 SFPB_GPREG_MASTER_PORT_EN(en));
2355}
2356
2357int msm_dsi_host_power_on(struct mipi_dsi_host *host,
2358 struct msm_dsi_phy_shared_timings *phy_shared_timings,
2359 bool is_bonded_dsi, struct msm_dsi_phy *phy)
2360{
2361 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2362 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2363 int ret = 0;
2364
2365 mutex_lock(&msm_host->dev_mutex);
2366 if (msm_host->power_on) {
2367 DBG("dsi host already on");
2368 goto unlock_ret;
2369 }
2370
2371 msm_host->byte_intf_clk_rate = msm_host->byte_clk_rate;
2372 if (phy_shared_timings->byte_intf_clk_div_2)
2373 msm_host->byte_intf_clk_rate /= 2;
2374
2375 msm_dsi_sfpb_config(msm_host, true);
2376
2377 ret = regulator_bulk_enable(msm_host->cfg_hnd->cfg->num_regulators,
2378 msm_host->supplies);
2379 if (ret) {
2380 pr_err("%s:Failed to enable vregs.ret=%d\n",
2381 __func__, ret);
2382 goto unlock_ret;
2383 }
2384
2385 pm_runtime_get_sync(&msm_host->pdev->dev);
2386 ret = cfg_hnd->ops->link_clk_set_rate(msm_host);
2387 if (!ret)
2388 ret = cfg_hnd->ops->link_clk_enable(msm_host);
2389 if (ret) {
2390 pr_err("%s: failed to enable link clocks. ret=%d\n",
2391 __func__, ret);
2392 goto fail_disable_reg;
2393 }
2394
2395 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev);
2396 if (ret) {
2397 pr_err("%s: failed to set pinctrl default state, %d\n",
2398 __func__, ret);
2399 goto fail_disable_clk;
2400 }
2401
2402 dsi_timing_setup(msm_host, is_bonded_dsi);
2403 dsi_sw_reset(msm_host);
2404 dsi_ctrl_enable(msm_host, phy_shared_timings, phy);
2405
2406 if (msm_host->disp_en_gpio)
2407 gpiod_set_value(msm_host->disp_en_gpio, 1);
2408
2409 msm_host->power_on = true;
2410 mutex_unlock(&msm_host->dev_mutex);
2411
2412 return 0;
2413
2414fail_disable_clk:
2415 cfg_hnd->ops->link_clk_disable(msm_host);
2416 pm_runtime_put(&msm_host->pdev->dev);
2417fail_disable_reg:
2418 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators,
2419 msm_host->supplies);
2420unlock_ret:
2421 mutex_unlock(&msm_host->dev_mutex);
2422 return ret;
2423}
2424
2425int msm_dsi_host_power_off(struct mipi_dsi_host *host)
2426{
2427 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2428 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2429
2430 mutex_lock(&msm_host->dev_mutex);
2431 if (!msm_host->power_on) {
2432 DBG("dsi host already off");
2433 goto unlock_ret;
2434 }
2435
2436 dsi_ctrl_disable(msm_host);
2437
2438 if (msm_host->disp_en_gpio)
2439 gpiod_set_value(msm_host->disp_en_gpio, 0);
2440
2441 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev);
2442
2443 cfg_hnd->ops->link_clk_disable(msm_host);
2444 pm_runtime_put(&msm_host->pdev->dev);
2445
2446 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators,
2447 msm_host->supplies);
2448
2449 msm_dsi_sfpb_config(msm_host, false);
2450
2451 DBG("-");
2452
2453 msm_host->power_on = false;
2454
2455unlock_ret:
2456 mutex_unlock(&msm_host->dev_mutex);
2457 return 0;
2458}
2459
2460int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
2461 const struct drm_display_mode *mode)
2462{
2463 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2464
2465 if (msm_host->mode) {
2466 drm_mode_destroy(msm_host->dev, msm_host->mode);
2467 msm_host->mode = NULL;
2468 }
2469
2470 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode);
2471 if (!msm_host->mode) {
2472 pr_err("%s: cannot duplicate mode\n", __func__);
2473 return -ENOMEM;
2474 }
2475
2476 return 0;
2477}
2478
2479enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host,
2480 const struct drm_display_mode *mode)
2481{
2482 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2483 struct drm_dsc_config *dsc = msm_host->dsc;
2484 int pic_width = mode->hdisplay;
2485 int pic_height = mode->vdisplay;
2486
2487 if (!msm_host->dsc)
2488 return MODE_OK;
2489
2490 if (pic_width % dsc->slice_width) {
2491 pr_err("DSI: pic_width %d has to be multiple of slice %d\n",
2492 pic_width, dsc->slice_width);
2493 return MODE_H_ILLEGAL;
2494 }
2495
2496 if (pic_height % dsc->slice_height) {
2497 pr_err("DSI: pic_height %d has to be multiple of slice %d\n",
2498 pic_height, dsc->slice_height);
2499 return MODE_V_ILLEGAL;
2500 }
2501
2502 return MODE_OK;
2503}
2504
2505unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host)
2506{
2507 return to_msm_dsi_host(host)->mode_flags;
2508}
2509
2510void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host)
2511{
2512 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2513
2514 pm_runtime_get_sync(&msm_host->pdev->dev);
2515
2516 msm_disp_snapshot_add_block(disp_state, msm_host->ctrl_size,
2517 msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id);
2518
2519 pm_runtime_put_sync(&msm_host->pdev->dev);
2520}
2521
2522static void msm_dsi_host_video_test_pattern_setup(struct msm_dsi_host *msm_host)
2523{
2524 u32 reg;
2525
2526 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);
2527
2528 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, 0xff);
2529 /* draw checkered rectangle pattern */
2530 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL,
2531 DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN);
2532 /* use 24-bit RGB test pttern */
2533 dsi_write(msm_host, REG_DSI_TPG_VIDEO_CONFIG,
2534 DSI_TPG_VIDEO_CONFIG_BPP(VIDEO_CONFIG_24BPP) |
2535 DSI_TPG_VIDEO_CONFIG_RGB);
2536
2537 reg |= DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(VID_MDSS_GENERAL_PATTERN);
2538 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg);
2539
2540 DBG("Video test pattern setup done\n");
2541}
2542
2543static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host)
2544{
2545 u32 reg;
2546
2547 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);
2548
2549 /* initial value for test pattern */
2550 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff);
2551
2552 reg |= DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(CMD_MDP_MDSS_GENERAL_PATTERN);
2553
2554 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg);
2555 /* draw checkered rectangle pattern */
2556 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2,
2557 DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN);
2558
2559 DBG("Cmd test pattern setup done\n");
2560}
2561
2562void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host)
2563{
2564 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2565 bool is_video_mode = !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO);
2566 u32 reg;
2567
2568 if (is_video_mode)
2569 msm_dsi_host_video_test_pattern_setup(msm_host);
2570 else
2571 msm_dsi_host_cmd_test_pattern_setup(msm_host);
2572
2573 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);
2574 /* enable the test pattern generator */
2575 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, (reg | DSI_TEST_PATTERN_GEN_CTRL_EN));
2576
2577 /* for command mode need to trigger one frame from tpg */
2578 if (!is_video_mode)
2579 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER,
2580 DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER);
2581}
2582
2583struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host)
2584{
2585 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2586
2587 return msm_host->dsc;
2588}