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1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/gpio.h>
18#include <linux/gpio/consumer.h>
19#include <linux/interrupt.h>
20#include <linux/of_device.h>
21#include <linux/of_gpio.h>
22#include <linux/of_irq.h>
23#include <linux/pinctrl/consumer.h>
24#include <linux/of_graph.h>
25#include <linux/regulator/consumer.h>
26#include <linux/spinlock.h>
27#include <linux/mfd/syscon.h>
28#include <linux/regmap.h>
29#include <video/mipi_display.h>
30
31#include "dsi.h"
32#include "dsi.xml.h"
33#include "sfpb.xml.h"
34#include "dsi_cfg.h"
35#include "msm_kms.h"
36
37static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
38{
39 u32 ver;
40
41 if (!major || !minor)
42 return -EINVAL;
43
44 /*
45 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0
46 * makes all other registers 4-byte shifted down.
47 *
48 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and
49 * older, we read the DSI_VERSION register without any shift(offset
50 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In
51 * the case of DSI6G, this has to be zero (the offset points to a
52 * scratch register which we never touch)
53 */
54
55 ver = msm_readl(base + REG_DSI_VERSION);
56 if (ver) {
57 /* older dsi host, there is no register shift */
58 ver = FIELD(ver, DSI_VERSION_MAJOR);
59 if (ver <= MSM_DSI_VER_MAJOR_V2) {
60 /* old versions */
61 *major = ver;
62 *minor = 0;
63 return 0;
64 } else {
65 return -EINVAL;
66 }
67 } else {
68 /*
69 * newer host, offset 0 has 6G_HW_VERSION, the rest of the
70 * registers are shifted down, read DSI_VERSION again with
71 * the shifted offset
72 */
73 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
74 ver = FIELD(ver, DSI_VERSION_MAJOR);
75 if (ver == MSM_DSI_VER_MAJOR_6G) {
76 /* 6G version */
77 *major = ver;
78 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION);
79 return 0;
80 } else {
81 return -EINVAL;
82 }
83 }
84}
85
86#define DSI_ERR_STATE_ACK 0x0000
87#define DSI_ERR_STATE_TIMEOUT 0x0001
88#define DSI_ERR_STATE_DLN0_PHY 0x0002
89#define DSI_ERR_STATE_FIFO 0x0004
90#define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008
91#define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010
92#define DSI_ERR_STATE_PLL_UNLOCKED 0x0020
93
94#define DSI_CLK_CTRL_ENABLE_CLKS \
95 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \
96 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \
97 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \
98 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK)
99
100struct msm_dsi_host {
101 struct mipi_dsi_host base;
102
103 struct platform_device *pdev;
104 struct drm_device *dev;
105
106 int id;
107
108 void __iomem *ctrl_base;
109 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
110
111 struct clk *bus_clks[DSI_BUS_CLK_MAX];
112
113 struct clk *byte_clk;
114 struct clk *esc_clk;
115 struct clk *pixel_clk;
116 struct clk *byte_clk_src;
117 struct clk *pixel_clk_src;
118 struct clk *byte_intf_clk;
119
120 u32 byte_clk_rate;
121 u32 esc_clk_rate;
122
123 /* DSI v2 specific clocks */
124 struct clk *src_clk;
125 struct clk *esc_clk_src;
126 struct clk *dsi_clk_src;
127
128 u32 src_clk_rate;
129
130 struct gpio_desc *disp_en_gpio;
131 struct gpio_desc *te_gpio;
132
133 const struct msm_dsi_cfg_handler *cfg_hnd;
134
135 struct completion dma_comp;
136 struct completion video_comp;
137 struct mutex dev_mutex;
138 struct mutex cmd_mutex;
139 spinlock_t intr_lock; /* Protect interrupt ctrl register */
140
141 u32 err_work_state;
142 struct work_struct err_work;
143 struct work_struct hpd_work;
144 struct workqueue_struct *workqueue;
145
146 /* DSI 6G TX buffer*/
147 struct drm_gem_object *tx_gem_obj;
148
149 /* DSI v2 TX buffer */
150 void *tx_buf;
151 dma_addr_t tx_buf_paddr;
152
153 int tx_size;
154
155 u8 *rx_buf;
156
157 struct regmap *sfpb;
158
159 struct drm_display_mode *mode;
160
161 /* connected device info */
162 struct device_node *device_node;
163 unsigned int channel;
164 unsigned int lanes;
165 enum mipi_dsi_pixel_format format;
166 unsigned long mode_flags;
167
168 /* lane data parsed via DT */
169 int dlane_swap;
170 int num_data_lanes;
171
172 u32 dma_cmd_ctrl_restore;
173
174 bool registered;
175 bool power_on;
176 bool enabled;
177 int irq;
178};
179
180static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt)
181{
182 switch (fmt) {
183 case MIPI_DSI_FMT_RGB565: return 16;
184 case MIPI_DSI_FMT_RGB666_PACKED: return 18;
185 case MIPI_DSI_FMT_RGB666:
186 case MIPI_DSI_FMT_RGB888:
187 default: return 24;
188 }
189}
190
191static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
192{
193 return msm_readl(msm_host->ctrl_base + reg);
194}
195static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
196{
197 msm_writel(data, msm_host->ctrl_base + reg);
198}
199
200static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host);
201static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host);
202
203static const struct msm_dsi_cfg_handler *dsi_get_config(
204 struct msm_dsi_host *msm_host)
205{
206 const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
207 struct device *dev = &msm_host->pdev->dev;
208 struct regulator *gdsc_reg;
209 struct clk *ahb_clk;
210 int ret;
211 u32 major = 0, minor = 0;
212
213 gdsc_reg = regulator_get(dev, "gdsc");
214 if (IS_ERR(gdsc_reg)) {
215 pr_err("%s: cannot get gdsc\n", __func__);
216 goto exit;
217 }
218
219 ahb_clk = msm_clk_get(msm_host->pdev, "iface");
220 if (IS_ERR(ahb_clk)) {
221 pr_err("%s: cannot get interface clock\n", __func__);
222 goto put_gdsc;
223 }
224
225 pm_runtime_get_sync(dev);
226
227 ret = regulator_enable(gdsc_reg);
228 if (ret) {
229 pr_err("%s: unable to enable gdsc\n", __func__);
230 goto put_gdsc;
231 }
232
233 ret = clk_prepare_enable(ahb_clk);
234 if (ret) {
235 pr_err("%s: unable to enable ahb_clk\n", __func__);
236 goto disable_gdsc;
237 }
238
239 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor);
240 if (ret) {
241 pr_err("%s: Invalid version\n", __func__);
242 goto disable_clks;
243 }
244
245 cfg_hnd = msm_dsi_cfg_get(major, minor);
246
247 DBG("%s: Version %x:%x\n", __func__, major, minor);
248
249disable_clks:
250 clk_disable_unprepare(ahb_clk);
251disable_gdsc:
252 regulator_disable(gdsc_reg);
253 pm_runtime_put_sync(dev);
254put_gdsc:
255 regulator_put(gdsc_reg);
256exit:
257 return cfg_hnd;
258}
259
260static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host)
261{
262 return container_of(host, struct msm_dsi_host, base);
263}
264
265static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host)
266{
267 struct regulator_bulk_data *s = msm_host->supplies;
268 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
269 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
270 int i;
271
272 DBG("");
273 for (i = num - 1; i >= 0; i--)
274 if (regs[i].disable_load >= 0)
275 regulator_set_load(s[i].consumer,
276 regs[i].disable_load);
277
278 regulator_bulk_disable(num, s);
279}
280
281static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host)
282{
283 struct regulator_bulk_data *s = msm_host->supplies;
284 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
285 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
286 int ret, i;
287
288 DBG("");
289 for (i = 0; i < num; i++) {
290 if (regs[i].enable_load >= 0) {
291 ret = regulator_set_load(s[i].consumer,
292 regs[i].enable_load);
293 if (ret < 0) {
294 pr_err("regulator %d set op mode failed, %d\n",
295 i, ret);
296 goto fail;
297 }
298 }
299 }
300
301 ret = regulator_bulk_enable(num, s);
302 if (ret < 0) {
303 pr_err("regulator enable failed, %d\n", ret);
304 goto fail;
305 }
306
307 return 0;
308
309fail:
310 for (i--; i >= 0; i--)
311 regulator_set_load(s[i].consumer, regs[i].disable_load);
312 return ret;
313}
314
315static int dsi_regulator_init(struct msm_dsi_host *msm_host)
316{
317 struct regulator_bulk_data *s = msm_host->supplies;
318 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
319 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
320 int i, ret;
321
322 for (i = 0; i < num; i++)
323 s[i].supply = regs[i].name;
324
325 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s);
326 if (ret < 0) {
327 pr_err("%s: failed to init regulator, ret=%d\n",
328 __func__, ret);
329 return ret;
330 }
331
332 return 0;
333}
334
335static int dsi_clk_init(struct msm_dsi_host *msm_host)
336{
337 struct platform_device *pdev = msm_host->pdev;
338 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
339 const struct msm_dsi_config *cfg = cfg_hnd->cfg;
340 int i, ret = 0;
341
342 /* get bus clocks */
343 for (i = 0; i < cfg->num_bus_clks; i++) {
344 msm_host->bus_clks[i] = msm_clk_get(pdev,
345 cfg->bus_clk_names[i]);
346 if (IS_ERR(msm_host->bus_clks[i])) {
347 ret = PTR_ERR(msm_host->bus_clks[i]);
348 pr_err("%s: Unable to get %s clock, ret = %d\n",
349 __func__, cfg->bus_clk_names[i], ret);
350 goto exit;
351 }
352 }
353
354 /* get link and source clocks */
355 msm_host->byte_clk = msm_clk_get(pdev, "byte");
356 if (IS_ERR(msm_host->byte_clk)) {
357 ret = PTR_ERR(msm_host->byte_clk);
358 pr_err("%s: can't find dsi_byte clock. ret=%d\n",
359 __func__, ret);
360 msm_host->byte_clk = NULL;
361 goto exit;
362 }
363
364 msm_host->pixel_clk = msm_clk_get(pdev, "pixel");
365 if (IS_ERR(msm_host->pixel_clk)) {
366 ret = PTR_ERR(msm_host->pixel_clk);
367 pr_err("%s: can't find dsi_pixel clock. ret=%d\n",
368 __func__, ret);
369 msm_host->pixel_clk = NULL;
370 goto exit;
371 }
372
373 msm_host->esc_clk = msm_clk_get(pdev, "core");
374 if (IS_ERR(msm_host->esc_clk)) {
375 ret = PTR_ERR(msm_host->esc_clk);
376 pr_err("%s: can't find dsi_esc clock. ret=%d\n",
377 __func__, ret);
378 msm_host->esc_clk = NULL;
379 goto exit;
380 }
381
382 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G &&
383 cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V2_2_1) {
384 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf");
385 if (IS_ERR(msm_host->byte_intf_clk)) {
386 ret = PTR_ERR(msm_host->byte_intf_clk);
387 pr_err("%s: can't find byte_intf clock. ret=%d\n",
388 __func__, ret);
389 goto exit;
390 }
391 } else {
392 msm_host->byte_intf_clk = NULL;
393 }
394
395 msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk);
396 if (!msm_host->byte_clk_src) {
397 ret = -ENODEV;
398 pr_err("%s: can't find byte_clk clock. ret=%d\n", __func__, ret);
399 goto exit;
400 }
401
402 msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk);
403 if (!msm_host->pixel_clk_src) {
404 ret = -ENODEV;
405 pr_err("%s: can't find pixel_clk clock. ret=%d\n", __func__, ret);
406 goto exit;
407 }
408
409 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
410 msm_host->src_clk = msm_clk_get(pdev, "src");
411 if (IS_ERR(msm_host->src_clk)) {
412 ret = PTR_ERR(msm_host->src_clk);
413 pr_err("%s: can't find src clock. ret=%d\n",
414 __func__, ret);
415 msm_host->src_clk = NULL;
416 goto exit;
417 }
418
419 msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk);
420 if (!msm_host->esc_clk_src) {
421 ret = -ENODEV;
422 pr_err("%s: can't get esc clock parent. ret=%d\n",
423 __func__, ret);
424 goto exit;
425 }
426
427 msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk);
428 if (!msm_host->dsi_clk_src) {
429 ret = -ENODEV;
430 pr_err("%s: can't get src clock parent. ret=%d\n",
431 __func__, ret);
432 }
433 }
434exit:
435 return ret;
436}
437
438static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host)
439{
440 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
441 int i, ret;
442
443 DBG("id=%d", msm_host->id);
444
445 for (i = 0; i < cfg->num_bus_clks; i++) {
446 ret = clk_prepare_enable(msm_host->bus_clks[i]);
447 if (ret) {
448 pr_err("%s: failed to enable bus clock %d ret %d\n",
449 __func__, i, ret);
450 goto err;
451 }
452 }
453
454 return 0;
455err:
456 for (; i > 0; i--)
457 clk_disable_unprepare(msm_host->bus_clks[i]);
458
459 return ret;
460}
461
462static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host)
463{
464 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
465 int i;
466
467 DBG("");
468
469 for (i = cfg->num_bus_clks - 1; i >= 0; i--)
470 clk_disable_unprepare(msm_host->bus_clks[i]);
471}
472
473int msm_dsi_runtime_suspend(struct device *dev)
474{
475 struct platform_device *pdev = to_platform_device(dev);
476 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev);
477 struct mipi_dsi_host *host = msm_dsi->host;
478 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
479
480 if (!msm_host->cfg_hnd)
481 return 0;
482
483 dsi_bus_clk_disable(msm_host);
484
485 return 0;
486}
487
488int msm_dsi_runtime_resume(struct device *dev)
489{
490 struct platform_device *pdev = to_platform_device(dev);
491 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev);
492 struct mipi_dsi_host *host = msm_dsi->host;
493 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
494
495 if (!msm_host->cfg_hnd)
496 return 0;
497
498 return dsi_bus_clk_enable(msm_host);
499}
500
501static int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
502{
503 int ret;
504
505 DBG("Set clk rates: pclk=%d, byteclk=%d",
506 msm_host->mode->clock, msm_host->byte_clk_rate);
507
508 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
509 if (ret) {
510 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
511 goto error;
512 }
513
514 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
515 if (ret) {
516 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
517 goto error;
518 }
519
520 if (msm_host->byte_intf_clk) {
521 ret = clk_set_rate(msm_host->byte_intf_clk,
522 msm_host->byte_clk_rate / 2);
523 if (ret) {
524 pr_err("%s: Failed to set rate byte intf clk, %d\n",
525 __func__, ret);
526 goto error;
527 }
528 }
529
530 ret = clk_prepare_enable(msm_host->esc_clk);
531 if (ret) {
532 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
533 goto error;
534 }
535
536 ret = clk_prepare_enable(msm_host->byte_clk);
537 if (ret) {
538 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
539 goto byte_clk_err;
540 }
541
542 ret = clk_prepare_enable(msm_host->pixel_clk);
543 if (ret) {
544 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
545 goto pixel_clk_err;
546 }
547
548 if (msm_host->byte_intf_clk) {
549 ret = clk_prepare_enable(msm_host->byte_intf_clk);
550 if (ret) {
551 pr_err("%s: Failed to enable byte intf clk\n",
552 __func__);
553 goto byte_intf_clk_err;
554 }
555 }
556
557 return 0;
558
559byte_intf_clk_err:
560 clk_disable_unprepare(msm_host->pixel_clk);
561pixel_clk_err:
562 clk_disable_unprepare(msm_host->byte_clk);
563byte_clk_err:
564 clk_disable_unprepare(msm_host->esc_clk);
565error:
566 return ret;
567}
568
569static int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
570{
571 int ret;
572
573 DBG("Set clk rates: pclk=%d, byteclk=%d, esc_clk=%d, dsi_src_clk=%d",
574 msm_host->mode->clock, msm_host->byte_clk_rate,
575 msm_host->esc_clk_rate, msm_host->src_clk_rate);
576
577 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
578 if (ret) {
579 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
580 goto error;
581 }
582
583 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate);
584 if (ret) {
585 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret);
586 goto error;
587 }
588
589 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate);
590 if (ret) {
591 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret);
592 goto error;
593 }
594
595 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
596 if (ret) {
597 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
598 goto error;
599 }
600
601 ret = clk_prepare_enable(msm_host->byte_clk);
602 if (ret) {
603 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
604 goto error;
605 }
606
607 ret = clk_prepare_enable(msm_host->esc_clk);
608 if (ret) {
609 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
610 goto esc_clk_err;
611 }
612
613 ret = clk_prepare_enable(msm_host->src_clk);
614 if (ret) {
615 pr_err("%s: Failed to enable dsi src clk\n", __func__);
616 goto src_clk_err;
617 }
618
619 ret = clk_prepare_enable(msm_host->pixel_clk);
620 if (ret) {
621 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
622 goto pixel_clk_err;
623 }
624
625 return 0;
626
627pixel_clk_err:
628 clk_disable_unprepare(msm_host->src_clk);
629src_clk_err:
630 clk_disable_unprepare(msm_host->esc_clk);
631esc_clk_err:
632 clk_disable_unprepare(msm_host->byte_clk);
633error:
634 return ret;
635}
636
637static int dsi_link_clk_enable(struct msm_dsi_host *msm_host)
638{
639 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
640
641 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G)
642 return dsi_link_clk_enable_6g(msm_host);
643 else
644 return dsi_link_clk_enable_v2(msm_host);
645}
646
647static void dsi_link_clk_disable(struct msm_dsi_host *msm_host)
648{
649 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
650
651 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
652 clk_disable_unprepare(msm_host->esc_clk);
653 clk_disable_unprepare(msm_host->pixel_clk);
654 if (msm_host->byte_intf_clk)
655 clk_disable_unprepare(msm_host->byte_intf_clk);
656 clk_disable_unprepare(msm_host->byte_clk);
657 } else {
658 clk_disable_unprepare(msm_host->pixel_clk);
659 clk_disable_unprepare(msm_host->src_clk);
660 clk_disable_unprepare(msm_host->esc_clk);
661 clk_disable_unprepare(msm_host->byte_clk);
662 }
663}
664
665static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)
666{
667 struct drm_display_mode *mode = msm_host->mode;
668 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
669 u8 lanes = msm_host->lanes;
670 u32 bpp = dsi_get_bpp(msm_host->format);
671 u32 pclk_rate;
672
673 if (!mode) {
674 pr_err("%s: mode not set\n", __func__);
675 return -EINVAL;
676 }
677
678 pclk_rate = mode->clock * 1000;
679 if (lanes > 0) {
680 msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
681 } else {
682 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
683 msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
684 }
685
686 DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
687
688 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
689
690 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
691 unsigned int esc_mhz, esc_div;
692 unsigned long byte_mhz;
693
694 msm_host->src_clk_rate = (pclk_rate * bpp) / 8;
695
696 /*
697 * esc clock is byte clock followed by a 4 bit divider,
698 * we need to find an escape clock frequency within the
699 * mipi DSI spec range within the maximum divider limit
700 * We iterate here between an escape clock frequencey
701 * between 20 Mhz to 5 Mhz and pick up the first one
702 * that can be supported by our divider
703 */
704
705 byte_mhz = msm_host->byte_clk_rate / 1000000;
706
707 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) {
708 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz);
709
710 /*
711 * TODO: Ideally, we shouldn't know what sort of divider
712 * is available in mmss_cc, we're just assuming that
713 * it'll always be a 4 bit divider. Need to come up with
714 * a better way here.
715 */
716 if (esc_div >= 1 && esc_div <= 16)
717 break;
718 }
719
720 if (esc_mhz < 5)
721 return -EINVAL;
722
723 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div;
724
725 DBG("esc=%d, src=%d", msm_host->esc_clk_rate,
726 msm_host->src_clk_rate);
727 }
728
729 return 0;
730}
731
732static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable)
733{
734 u32 intr;
735 unsigned long flags;
736
737 spin_lock_irqsave(&msm_host->intr_lock, flags);
738 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
739
740 if (enable)
741 intr |= mask;
742 else
743 intr &= ~mask;
744
745 DBG("intr=%x enable=%d", intr, enable);
746
747 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);
748 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
749}
750
751static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags)
752{
753 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
754 return BURST_MODE;
755 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
756 return NON_BURST_SYNCH_PULSE;
757
758 return NON_BURST_SYNCH_EVENT;
759}
760
761static inline enum dsi_vid_dst_format dsi_get_vid_fmt(
762 const enum mipi_dsi_pixel_format mipi_fmt)
763{
764 switch (mipi_fmt) {
765 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888;
766 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE;
767 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666;
768 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565;
769 default: return VID_DST_FORMAT_RGB888;
770 }
771}
772
773static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(
774 const enum mipi_dsi_pixel_format mipi_fmt)
775{
776 switch (mipi_fmt) {
777 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888;
778 case MIPI_DSI_FMT_RGB666_PACKED:
779 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666;
780 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565;
781 default: return CMD_DST_FORMAT_RGB888;
782 }
783}
784
785static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
786 struct msm_dsi_phy_shared_timings *phy_shared_timings)
787{
788 u32 flags = msm_host->mode_flags;
789 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
790 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
791 u32 data = 0;
792
793 if (!enable) {
794 dsi_write(msm_host, REG_DSI_CTRL, 0);
795 return;
796 }
797
798 if (flags & MIPI_DSI_MODE_VIDEO) {
799 if (flags & MIPI_DSI_MODE_VIDEO_HSE)
800 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE;
801 if (flags & MIPI_DSI_MODE_VIDEO_HFP)
802 data |= DSI_VID_CFG0_HFP_POWER_STOP;
803 if (flags & MIPI_DSI_MODE_VIDEO_HBP)
804 data |= DSI_VID_CFG0_HBP_POWER_STOP;
805 if (flags & MIPI_DSI_MODE_VIDEO_HSA)
806 data |= DSI_VID_CFG0_HSA_POWER_STOP;
807 /* Always set low power stop mode for BLLP
808 * to let command engine send packets
809 */
810 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP |
811 DSI_VID_CFG0_BLLP_POWER_STOP;
812 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
813 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
814 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
815 dsi_write(msm_host, REG_DSI_VID_CFG0, data);
816
817 /* Do not swap RGB colors */
818 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB);
819 dsi_write(msm_host, REG_DSI_VID_CFG1, 0);
820 } else {
821 /* Do not swap RGB colors */
822 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB);
823 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt));
824 dsi_write(msm_host, REG_DSI_CMD_CFG0, data);
825
826 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) |
827 DSI_CMD_CFG1_WR_MEM_CONTINUE(
828 MIPI_DCS_WRITE_MEMORY_CONTINUE);
829 /* Always insert DCS command */
830 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND;
831 dsi_write(msm_host, REG_DSI_CMD_CFG1, data);
832 }
833
834 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,
835 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER |
836 DSI_CMD_DMA_CTRL_LOW_POWER);
837
838 data = 0;
839 /* Always assume dedicated TE pin */
840 data |= DSI_TRIG_CTRL_TE;
841 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE);
842 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW);
843 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel);
844 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
845 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2))
846 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME;
847 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);
848
849 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) |
850 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre);
851 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);
852
853 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
854 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) &&
855 phy_shared_timings->clk_pre_inc_by_2)
856 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND,
857 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK);
858
859 data = 0;
860 if (!(flags & MIPI_DSI_MODE_EOT_PACKET))
861 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND;
862 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);
863
864 /* allow only ack-err-status to generate interrupt */
865 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);
866
867 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
868
869 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
870
871 data = DSI_CTRL_CLK_EN;
872
873 DBG("lane number=%d", msm_host->lanes);
874 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0);
875
876 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
877 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap));
878
879 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
880 dsi_write(msm_host, REG_DSI_LANE_CTRL,
881 DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
882
883 data |= DSI_CTRL_ENABLE;
884
885 dsi_write(msm_host, REG_DSI_CTRL, data);
886}
887
888static void dsi_timing_setup(struct msm_dsi_host *msm_host)
889{
890 struct drm_display_mode *mode = msm_host->mode;
891 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */
892 u32 h_total = mode->htotal;
893 u32 v_total = mode->vtotal;
894 u32 hs_end = mode->hsync_end - mode->hsync_start;
895 u32 vs_end = mode->vsync_end - mode->vsync_start;
896 u32 ha_start = h_total - mode->hsync_start;
897 u32 ha_end = ha_start + mode->hdisplay;
898 u32 va_start = v_total - mode->vsync_start;
899 u32 va_end = va_start + mode->vdisplay;
900 u32 wc;
901
902 DBG("");
903
904 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
905 dsi_write(msm_host, REG_DSI_ACTIVE_H,
906 DSI_ACTIVE_H_START(ha_start) |
907 DSI_ACTIVE_H_END(ha_end));
908 dsi_write(msm_host, REG_DSI_ACTIVE_V,
909 DSI_ACTIVE_V_START(va_start) |
910 DSI_ACTIVE_V_END(va_end));
911 dsi_write(msm_host, REG_DSI_TOTAL,
912 DSI_TOTAL_H_TOTAL(h_total - 1) |
913 DSI_TOTAL_V_TOTAL(v_total - 1));
914
915 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,
916 DSI_ACTIVE_HSYNC_START(hs_start) |
917 DSI_ACTIVE_HSYNC_END(hs_end));
918 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);
919 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,
920 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
921 DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
922 } else { /* command mode */
923 /* image data and 1 byte write_memory_start cmd */
924 wc = mode->hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
925
926 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL,
927 DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) |
928 DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(
929 msm_host->channel) |
930 DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(
931 MIPI_DSI_DCS_LONG_WRITE));
932
933 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL,
934 DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(mode->hdisplay) |
935 DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay));
936 }
937}
938
939static void dsi_sw_reset(struct msm_dsi_host *msm_host)
940{
941 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
942 wmb(); /* clocks need to be enabled before reset */
943
944 dsi_write(msm_host, REG_DSI_RESET, 1);
945 wmb(); /* make sure reset happen */
946 dsi_write(msm_host, REG_DSI_RESET, 0);
947}
948
949static void dsi_op_mode_config(struct msm_dsi_host *msm_host,
950 bool video_mode, bool enable)
951{
952 u32 dsi_ctrl;
953
954 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL);
955
956 if (!enable) {
957 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN |
958 DSI_CTRL_CMD_MODE_EN);
959 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE |
960 DSI_IRQ_MASK_VIDEO_DONE, 0);
961 } else {
962 if (video_mode) {
963 dsi_ctrl |= DSI_CTRL_VID_MODE_EN;
964 } else { /* command mode */
965 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN;
966 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1);
967 }
968 dsi_ctrl |= DSI_CTRL_ENABLE;
969 }
970
971 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);
972}
973
974static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host)
975{
976 u32 data;
977
978 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL);
979
980 if (mode == 0)
981 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER;
982 else
983 data |= DSI_CMD_DMA_CTRL_LOW_POWER;
984
985 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);
986}
987
988static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
989{
990 u32 ret = 0;
991 struct device *dev = &msm_host->pdev->dev;
992
993 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1);
994
995 reinit_completion(&msm_host->video_comp);
996
997 ret = wait_for_completion_timeout(&msm_host->video_comp,
998 msecs_to_jiffies(70));
999
1000 if (ret <= 0)
1001 dev_err(dev, "wait for video done timed out\n");
1002
1003 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0);
1004}
1005
1006static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
1007{
1008 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
1009 return;
1010
1011 if (msm_host->power_on && msm_host->enabled) {
1012 dsi_wait4video_done(msm_host);
1013 /* delay 4 ms to skip BLLP */
1014 usleep_range(2000, 4000);
1015 }
1016}
1017
1018/* dsi_cmd */
1019static int dsi_tx_buf_alloc(struct msm_dsi_host *msm_host, int size)
1020{
1021 struct drm_device *dev = msm_host->dev;
1022 struct msm_drm_private *priv = dev->dev_private;
1023 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1024 int ret;
1025 uint64_t iova;
1026
1027 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
1028 msm_host->tx_gem_obj = msm_gem_new(dev, size, MSM_BO_UNCACHED);
1029 if (IS_ERR(msm_host->tx_gem_obj)) {
1030 ret = PTR_ERR(msm_host->tx_gem_obj);
1031 pr_err("%s: failed to allocate gem, %d\n",
1032 __func__, ret);
1033 msm_host->tx_gem_obj = NULL;
1034 return ret;
1035 }
1036
1037 ret = msm_gem_get_iova(msm_host->tx_gem_obj,
1038 priv->kms->aspace, &iova);
1039 mutex_unlock(&dev->struct_mutex);
1040 if (ret) {
1041 pr_err("%s: failed to get iova, %d\n", __func__, ret);
1042 return ret;
1043 }
1044
1045 if (iova & 0x07) {
1046 pr_err("%s: buf NOT 8 bytes aligned\n", __func__);
1047 return -EINVAL;
1048 }
1049
1050 msm_host->tx_size = msm_host->tx_gem_obj->size;
1051 } else {
1052 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size,
1053 &msm_host->tx_buf_paddr, GFP_KERNEL);
1054 if (!msm_host->tx_buf) {
1055 ret = -ENOMEM;
1056 pr_err("%s: failed to allocate tx buf, %d\n",
1057 __func__, ret);
1058 return ret;
1059 }
1060
1061 msm_host->tx_size = size;
1062 }
1063
1064 return 0;
1065}
1066
1067static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
1068{
1069 struct drm_device *dev = msm_host->dev;
1070
1071 if (msm_host->tx_gem_obj) {
1072 msm_gem_put_iova(msm_host->tx_gem_obj, 0);
1073 drm_gem_object_put_unlocked(msm_host->tx_gem_obj);
1074 msm_host->tx_gem_obj = NULL;
1075 }
1076
1077 if (msm_host->tx_buf)
1078 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf,
1079 msm_host->tx_buf_paddr);
1080}
1081
1082/*
1083 * prepare cmd buffer to be txed
1084 */
1085static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host,
1086 const struct mipi_dsi_msg *msg)
1087{
1088 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1089 struct mipi_dsi_packet packet;
1090 int len;
1091 int ret;
1092 u8 *data;
1093
1094 ret = mipi_dsi_create_packet(&packet, msg);
1095 if (ret) {
1096 pr_err("%s: create packet failed, %d\n", __func__, ret);
1097 return ret;
1098 }
1099 len = (packet.size + 3) & (~0x3);
1100
1101 if (len > msm_host->tx_size) {
1102 pr_err("%s: packet size is too big\n", __func__);
1103 return -EINVAL;
1104 }
1105
1106 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
1107 data = msm_gem_get_vaddr(msm_host->tx_gem_obj);
1108 if (IS_ERR(data)) {
1109 ret = PTR_ERR(data);
1110 pr_err("%s: get vaddr failed, %d\n", __func__, ret);
1111 return ret;
1112 }
1113 } else {
1114 data = msm_host->tx_buf;
1115 }
1116
1117 /* MSM specific command format in memory */
1118 data[0] = packet.header[1];
1119 data[1] = packet.header[2];
1120 data[2] = packet.header[0];
1121 data[3] = BIT(7); /* Last packet */
1122 if (mipi_dsi_packet_format_is_long(msg->type))
1123 data[3] |= BIT(6);
1124 if (msg->rx_buf && msg->rx_len)
1125 data[3] |= BIT(5);
1126
1127 /* Long packet */
1128 if (packet.payload && packet.payload_length)
1129 memcpy(data + 4, packet.payload, packet.payload_length);
1130
1131 /* Append 0xff to the end */
1132 if (packet.size < len)
1133 memset(data + packet.size, 0xff, len - packet.size);
1134
1135 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G)
1136 msm_gem_put_vaddr(msm_host->tx_gem_obj);
1137
1138 return len;
1139}
1140
1141/*
1142 * dsi_short_read1_resp: 1 parameter
1143 */
1144static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1145{
1146 u8 *data = msg->rx_buf;
1147 if (data && (msg->rx_len >= 1)) {
1148 *data = buf[1]; /* strip out dcs type */
1149 return 1;
1150 } else {
1151 pr_err("%s: read data does not match with rx_buf len %zu\n",
1152 __func__, msg->rx_len);
1153 return -EINVAL;
1154 }
1155}
1156
1157/*
1158 * dsi_short_read2_resp: 2 parameter
1159 */
1160static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1161{
1162 u8 *data = msg->rx_buf;
1163 if (data && (msg->rx_len >= 2)) {
1164 data[0] = buf[1]; /* strip out dcs type */
1165 data[1] = buf[2];
1166 return 2;
1167 } else {
1168 pr_err("%s: read data does not match with rx_buf len %zu\n",
1169 __func__, msg->rx_len);
1170 return -EINVAL;
1171 }
1172}
1173
1174static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1175{
1176 /* strip out 4 byte dcs header */
1177 if (msg->rx_buf && msg->rx_len)
1178 memcpy(msg->rx_buf, buf + 4, msg->rx_len);
1179
1180 return msg->rx_len;
1181}
1182
1183static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len)
1184{
1185 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1186 struct drm_device *dev = msm_host->dev;
1187 struct msm_drm_private *priv = dev->dev_private;
1188 int ret;
1189 uint64_t dma_base;
1190 bool triggered;
1191
1192 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
1193 ret = msm_gem_get_iova(msm_host->tx_gem_obj,
1194 priv->kms->aspace, &dma_base);
1195 if (ret) {
1196 pr_err("%s: failed to get iova: %d\n", __func__, ret);
1197 return ret;
1198 }
1199 } else {
1200 dma_base = msm_host->tx_buf_paddr;
1201 }
1202
1203 reinit_completion(&msm_host->dma_comp);
1204
1205 dsi_wait4video_eng_busy(msm_host);
1206
1207 triggered = msm_dsi_manager_cmd_xfer_trigger(
1208 msm_host->id, dma_base, len);
1209 if (triggered) {
1210 ret = wait_for_completion_timeout(&msm_host->dma_comp,
1211 msecs_to_jiffies(200));
1212 DBG("ret=%d", ret);
1213 if (ret == 0)
1214 ret = -ETIMEDOUT;
1215 else
1216 ret = len;
1217 } else
1218 ret = len;
1219
1220 return ret;
1221}
1222
1223static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host,
1224 u8 *buf, int rx_byte, int pkt_size)
1225{
1226 u32 *lp, *temp, data;
1227 int i, j = 0, cnt;
1228 u32 read_cnt;
1229 u8 reg[16];
1230 int repeated_bytes = 0;
1231 int buf_offset = buf - msm_host->rx_buf;
1232
1233 lp = (u32 *)buf;
1234 temp = (u32 *)reg;
1235 cnt = (rx_byte + 3) >> 2;
1236 if (cnt > 4)
1237 cnt = 4; /* 4 x 32 bits registers only */
1238
1239 if (rx_byte == 4)
1240 read_cnt = 4;
1241 else
1242 read_cnt = pkt_size + 6;
1243
1244 /*
1245 * In case of multiple reads from the panel, after the first read, there
1246 * is possibility that there are some bytes in the payload repeating in
1247 * the RDBK_DATA registers. Since we read all the parameters from the
1248 * panel right from the first byte for every pass. We need to skip the
1249 * repeating bytes and then append the new parameters to the rx buffer.
1250 */
1251 if (read_cnt > 16) {
1252 int bytes_shifted;
1253 /* Any data more than 16 bytes will be shifted out.
1254 * The temp read buffer should already contain these bytes.
1255 * The remaining bytes in read buffer are the repeated bytes.
1256 */
1257 bytes_shifted = read_cnt - 16;
1258 repeated_bytes = buf_offset - bytes_shifted;
1259 }
1260
1261 for (i = cnt - 1; i >= 0; i--) {
1262 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i));
1263 *temp++ = ntohl(data); /* to host byte order */
1264 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data));
1265 }
1266
1267 for (i = repeated_bytes; i < 16; i++)
1268 buf[j++] = reg[i];
1269
1270 return j;
1271}
1272
1273static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host,
1274 const struct mipi_dsi_msg *msg)
1275{
1276 int len, ret;
1277 int bllp_len = msm_host->mode->hdisplay *
1278 dsi_get_bpp(msm_host->format) / 8;
1279
1280 len = dsi_cmd_dma_add(msm_host, msg);
1281 if (!len) {
1282 pr_err("%s: failed to add cmd type = 0x%x\n",
1283 __func__, msg->type);
1284 return -EINVAL;
1285 }
1286
1287 /* for video mode, do not send cmds more than
1288 * one pixel line, since it only transmit it
1289 * during BLLP.
1290 */
1291 /* TODO: if the command is sent in LP mode, the bit rate is only
1292 * half of esc clk rate. In this case, if the video is already
1293 * actively streaming, we need to check more carefully if the
1294 * command can be fit into one BLLP.
1295 */
1296 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) {
1297 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n",
1298 __func__, len);
1299 return -EINVAL;
1300 }
1301
1302 ret = dsi_cmd_dma_tx(msm_host, len);
1303 if (ret < len) {
1304 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n",
1305 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len);
1306 return -ECOMM;
1307 }
1308
1309 return len;
1310}
1311
1312static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host)
1313{
1314 u32 data0, data1;
1315
1316 data0 = dsi_read(msm_host, REG_DSI_CTRL);
1317 data1 = data0;
1318 data1 &= ~DSI_CTRL_ENABLE;
1319 dsi_write(msm_host, REG_DSI_CTRL, data1);
1320 /*
1321 * dsi controller need to be disabled before
1322 * clocks turned on
1323 */
1324 wmb();
1325
1326 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
1327 wmb(); /* make sure clocks enabled */
1328
1329 /* dsi controller can only be reset while clocks are running */
1330 dsi_write(msm_host, REG_DSI_RESET, 1);
1331 wmb(); /* make sure reset happen */
1332 dsi_write(msm_host, REG_DSI_RESET, 0);
1333 wmb(); /* controller out of reset */
1334 dsi_write(msm_host, REG_DSI_CTRL, data0);
1335 wmb(); /* make sure dsi controller enabled again */
1336}
1337
1338static void dsi_hpd_worker(struct work_struct *work)
1339{
1340 struct msm_dsi_host *msm_host =
1341 container_of(work, struct msm_dsi_host, hpd_work);
1342
1343 drm_helper_hpd_irq_event(msm_host->dev);
1344}
1345
1346static void dsi_err_worker(struct work_struct *work)
1347{
1348 struct msm_dsi_host *msm_host =
1349 container_of(work, struct msm_dsi_host, err_work);
1350 u32 status = msm_host->err_work_state;
1351
1352 pr_err_ratelimited("%s: status=%x\n", __func__, status);
1353 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW)
1354 dsi_sw_reset_restore(msm_host);
1355
1356 /* It is safe to clear here because error irq is disabled. */
1357 msm_host->err_work_state = 0;
1358
1359 /* enable dsi error interrupt */
1360 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
1361}
1362
1363static void dsi_ack_err_status(struct msm_dsi_host *msm_host)
1364{
1365 u32 status;
1366
1367 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS);
1368
1369 if (status) {
1370 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);
1371 /* Writing of an extra 0 needed to clear error bits */
1372 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);
1373 msm_host->err_work_state |= DSI_ERR_STATE_ACK;
1374 }
1375}
1376
1377static void dsi_timeout_status(struct msm_dsi_host *msm_host)
1378{
1379 u32 status;
1380
1381 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS);
1382
1383 if (status) {
1384 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);
1385 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT;
1386 }
1387}
1388
1389static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host)
1390{
1391 u32 status;
1392
1393 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR);
1394
1395 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC |
1396 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC |
1397 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL |
1398 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 |
1399 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) {
1400 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);
1401 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY;
1402 }
1403}
1404
1405static void dsi_fifo_status(struct msm_dsi_host *msm_host)
1406{
1407 u32 status;
1408
1409 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS);
1410
1411 /* fifo underflow, overflow */
1412 if (status) {
1413 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);
1414 msm_host->err_work_state |= DSI_ERR_STATE_FIFO;
1415 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW)
1416 msm_host->err_work_state |=
1417 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW;
1418 }
1419}
1420
1421static void dsi_status(struct msm_dsi_host *msm_host)
1422{
1423 u32 status;
1424
1425 status = dsi_read(msm_host, REG_DSI_STATUS0);
1426
1427 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) {
1428 dsi_write(msm_host, REG_DSI_STATUS0, status);
1429 msm_host->err_work_state |=
1430 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION;
1431 }
1432}
1433
1434static void dsi_clk_status(struct msm_dsi_host *msm_host)
1435{
1436 u32 status;
1437
1438 status = dsi_read(msm_host, REG_DSI_CLK_STATUS);
1439
1440 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) {
1441 dsi_write(msm_host, REG_DSI_CLK_STATUS, status);
1442 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED;
1443 }
1444}
1445
1446static void dsi_error(struct msm_dsi_host *msm_host)
1447{
1448 /* disable dsi error interrupt */
1449 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0);
1450
1451 dsi_clk_status(msm_host);
1452 dsi_fifo_status(msm_host);
1453 dsi_ack_err_status(msm_host);
1454 dsi_timeout_status(msm_host);
1455 dsi_status(msm_host);
1456 dsi_dln0_phy_err(msm_host);
1457
1458 queue_work(msm_host->workqueue, &msm_host->err_work);
1459}
1460
1461static irqreturn_t dsi_host_irq(int irq, void *ptr)
1462{
1463 struct msm_dsi_host *msm_host = ptr;
1464 u32 isr;
1465 unsigned long flags;
1466
1467 if (!msm_host->ctrl_base)
1468 return IRQ_HANDLED;
1469
1470 spin_lock_irqsave(&msm_host->intr_lock, flags);
1471 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
1472 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);
1473 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
1474
1475 DBG("isr=0x%x, id=%d", isr, msm_host->id);
1476
1477 if (isr & DSI_IRQ_ERROR)
1478 dsi_error(msm_host);
1479
1480 if (isr & DSI_IRQ_VIDEO_DONE)
1481 complete(&msm_host->video_comp);
1482
1483 if (isr & DSI_IRQ_CMD_DMA_DONE)
1484 complete(&msm_host->dma_comp);
1485
1486 return IRQ_HANDLED;
1487}
1488
1489static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host,
1490 struct device *panel_device)
1491{
1492 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device,
1493 "disp-enable",
1494 GPIOD_OUT_LOW);
1495 if (IS_ERR(msm_host->disp_en_gpio)) {
1496 DBG("cannot get disp-enable-gpios %ld",
1497 PTR_ERR(msm_host->disp_en_gpio));
1498 return PTR_ERR(msm_host->disp_en_gpio);
1499 }
1500
1501 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te",
1502 GPIOD_IN);
1503 if (IS_ERR(msm_host->te_gpio)) {
1504 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio));
1505 return PTR_ERR(msm_host->te_gpio);
1506 }
1507
1508 return 0;
1509}
1510
1511static int dsi_host_attach(struct mipi_dsi_host *host,
1512 struct mipi_dsi_device *dsi)
1513{
1514 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1515 int ret;
1516
1517 if (dsi->lanes > msm_host->num_data_lanes)
1518 return -EINVAL;
1519
1520 msm_host->channel = dsi->channel;
1521 msm_host->lanes = dsi->lanes;
1522 msm_host->format = dsi->format;
1523 msm_host->mode_flags = dsi->mode_flags;
1524
1525 msm_dsi_manager_attach_dsi_device(msm_host->id, dsi->mode_flags);
1526
1527 /* Some gpios defined in panel DT need to be controlled by host */
1528 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev);
1529 if (ret)
1530 return ret;
1531
1532 DBG("id=%d", msm_host->id);
1533 if (msm_host->dev)
1534 queue_work(msm_host->workqueue, &msm_host->hpd_work);
1535
1536 return 0;
1537}
1538
1539static int dsi_host_detach(struct mipi_dsi_host *host,
1540 struct mipi_dsi_device *dsi)
1541{
1542 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1543
1544 msm_host->device_node = NULL;
1545
1546 DBG("id=%d", msm_host->id);
1547 if (msm_host->dev)
1548 queue_work(msm_host->workqueue, &msm_host->hpd_work);
1549
1550 return 0;
1551}
1552
1553static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
1554 const struct mipi_dsi_msg *msg)
1555{
1556 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1557 int ret;
1558
1559 if (!msg || !msm_host->power_on)
1560 return -EINVAL;
1561
1562 mutex_lock(&msm_host->cmd_mutex);
1563 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg);
1564 mutex_unlock(&msm_host->cmd_mutex);
1565
1566 return ret;
1567}
1568
1569static struct mipi_dsi_host_ops dsi_host_ops = {
1570 .attach = dsi_host_attach,
1571 .detach = dsi_host_detach,
1572 .transfer = dsi_host_transfer,
1573};
1574
1575/*
1576 * List of supported physical to logical lane mappings.
1577 * For example, the 2nd entry represents the following mapping:
1578 *
1579 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
1580 */
1581static const int supported_data_lane_swaps[][4] = {
1582 { 0, 1, 2, 3 },
1583 { 3, 0, 1, 2 },
1584 { 2, 3, 0, 1 },
1585 { 1, 2, 3, 0 },
1586 { 0, 3, 2, 1 },
1587 { 1, 0, 3, 2 },
1588 { 2, 1, 0, 3 },
1589 { 3, 2, 1, 0 },
1590};
1591
1592static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
1593 struct device_node *ep)
1594{
1595 struct device *dev = &msm_host->pdev->dev;
1596 struct property *prop;
1597 u32 lane_map[4];
1598 int ret, i, len, num_lanes;
1599
1600 prop = of_find_property(ep, "data-lanes", &len);
1601 if (!prop) {
1602 dev_dbg(dev,
1603 "failed to find data lane mapping, using default\n");
1604 return 0;
1605 }
1606
1607 num_lanes = len / sizeof(u32);
1608
1609 if (num_lanes < 1 || num_lanes > 4) {
1610 dev_err(dev, "bad number of data lanes\n");
1611 return -EINVAL;
1612 }
1613
1614 msm_host->num_data_lanes = num_lanes;
1615
1616 ret = of_property_read_u32_array(ep, "data-lanes", lane_map,
1617 num_lanes);
1618 if (ret) {
1619 dev_err(dev, "failed to read lane data\n");
1620 return ret;
1621 }
1622
1623 /*
1624 * compare DT specified physical-logical lane mappings with the ones
1625 * supported by hardware
1626 */
1627 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) {
1628 const int *swap = supported_data_lane_swaps[i];
1629 int j;
1630
1631 /*
1632 * the data-lanes array we get from DT has a logical->physical
1633 * mapping. The "data lane swap" register field represents
1634 * supported configurations in a physical->logical mapping.
1635 * Translate the DT mapping to what we understand and find a
1636 * configuration that works.
1637 */
1638 for (j = 0; j < num_lanes; j++) {
1639 if (lane_map[j] < 0 || lane_map[j] > 3)
1640 dev_err(dev, "bad physical lane entry %u\n",
1641 lane_map[j]);
1642
1643 if (swap[lane_map[j]] != j)
1644 break;
1645 }
1646
1647 if (j == num_lanes) {
1648 msm_host->dlane_swap = i;
1649 return 0;
1650 }
1651 }
1652
1653 return -EINVAL;
1654}
1655
1656static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
1657{
1658 struct device *dev = &msm_host->pdev->dev;
1659 struct device_node *np = dev->of_node;
1660 struct device_node *endpoint, *device_node;
1661 int ret = 0;
1662
1663 /*
1664 * Get the endpoint of the output port of the DSI host. In our case,
1665 * this is mapped to port number with reg = 1. Don't return an error if
1666 * the remote endpoint isn't defined. It's possible that there is
1667 * nothing connected to the dsi output.
1668 */
1669 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1670 if (!endpoint) {
1671 dev_dbg(dev, "%s: no endpoint\n", __func__);
1672 return 0;
1673 }
1674
1675 ret = dsi_host_parse_lane_data(msm_host, endpoint);
1676 if (ret) {
1677 dev_err(dev, "%s: invalid lane configuration %d\n",
1678 __func__, ret);
1679 goto err;
1680 }
1681
1682 /* Get panel node from the output port's endpoint data */
1683 device_node = of_graph_get_remote_node(np, 1, 0);
1684 if (!device_node) {
1685 dev_dbg(dev, "%s: no valid device\n", __func__);
1686 goto err;
1687 }
1688
1689 msm_host->device_node = device_node;
1690
1691 if (of_property_read_bool(np, "syscon-sfpb")) {
1692 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np,
1693 "syscon-sfpb");
1694 if (IS_ERR(msm_host->sfpb)) {
1695 dev_err(dev, "%s: failed to get sfpb regmap\n",
1696 __func__);
1697 ret = PTR_ERR(msm_host->sfpb);
1698 }
1699 }
1700
1701 of_node_put(device_node);
1702
1703err:
1704 of_node_put(endpoint);
1705
1706 return ret;
1707}
1708
1709static int dsi_host_get_id(struct msm_dsi_host *msm_host)
1710{
1711 struct platform_device *pdev = msm_host->pdev;
1712 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
1713 struct resource *res;
1714 int i;
1715
1716 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl");
1717 if (!res)
1718 return -EINVAL;
1719
1720 for (i = 0; i < cfg->num_dsi; i++) {
1721 if (cfg->io_start[i] == res->start)
1722 return i;
1723 }
1724
1725 return -EINVAL;
1726}
1727
1728int msm_dsi_host_init(struct msm_dsi *msm_dsi)
1729{
1730 struct msm_dsi_host *msm_host = NULL;
1731 struct platform_device *pdev = msm_dsi->pdev;
1732 int ret;
1733
1734 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
1735 if (!msm_host) {
1736 pr_err("%s: FAILED: cannot alloc dsi host\n",
1737 __func__);
1738 ret = -ENOMEM;
1739 goto fail;
1740 }
1741
1742 msm_host->pdev = pdev;
1743 msm_dsi->host = &msm_host->base;
1744
1745 ret = dsi_host_parse_dt(msm_host);
1746 if (ret) {
1747 pr_err("%s: failed to parse dt\n", __func__);
1748 goto fail;
1749 }
1750
1751 msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL");
1752 if (IS_ERR(msm_host->ctrl_base)) {
1753 pr_err("%s: unable to map Dsi ctrl base\n", __func__);
1754 ret = PTR_ERR(msm_host->ctrl_base);
1755 goto fail;
1756 }
1757
1758 pm_runtime_enable(&pdev->dev);
1759
1760 msm_host->cfg_hnd = dsi_get_config(msm_host);
1761 if (!msm_host->cfg_hnd) {
1762 ret = -EINVAL;
1763 pr_err("%s: get config failed\n", __func__);
1764 goto fail;
1765 }
1766
1767 msm_host->id = dsi_host_get_id(msm_host);
1768 if (msm_host->id < 0) {
1769 ret = msm_host->id;
1770 pr_err("%s: unable to identify DSI host index\n", __func__);
1771 goto fail;
1772 }
1773
1774 /* fixup base address by io offset */
1775 msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset;
1776
1777 ret = dsi_regulator_init(msm_host);
1778 if (ret) {
1779 pr_err("%s: regulator init failed\n", __func__);
1780 goto fail;
1781 }
1782
1783 ret = dsi_clk_init(msm_host);
1784 if (ret) {
1785 pr_err("%s: unable to initialize dsi clks\n", __func__);
1786 goto fail;
1787 }
1788
1789 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL);
1790 if (!msm_host->rx_buf) {
1791 ret = -ENOMEM;
1792 pr_err("%s: alloc rx temp buf failed\n", __func__);
1793 goto fail;
1794 }
1795
1796 init_completion(&msm_host->dma_comp);
1797 init_completion(&msm_host->video_comp);
1798 mutex_init(&msm_host->dev_mutex);
1799 mutex_init(&msm_host->cmd_mutex);
1800 spin_lock_init(&msm_host->intr_lock);
1801
1802 /* setup workqueue */
1803 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0);
1804 INIT_WORK(&msm_host->err_work, dsi_err_worker);
1805 INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker);
1806
1807 msm_dsi->id = msm_host->id;
1808
1809 DBG("Dsi Host %d initialized", msm_host->id);
1810 return 0;
1811
1812fail:
1813 return ret;
1814}
1815
1816void msm_dsi_host_destroy(struct mipi_dsi_host *host)
1817{
1818 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1819
1820 DBG("");
1821 dsi_tx_buf_free(msm_host);
1822 if (msm_host->workqueue) {
1823 flush_workqueue(msm_host->workqueue);
1824 destroy_workqueue(msm_host->workqueue);
1825 msm_host->workqueue = NULL;
1826 }
1827
1828 mutex_destroy(&msm_host->cmd_mutex);
1829 mutex_destroy(&msm_host->dev_mutex);
1830
1831 pm_runtime_disable(&msm_host->pdev->dev);
1832}
1833
1834int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
1835 struct drm_device *dev)
1836{
1837 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1838 struct platform_device *pdev = msm_host->pdev;
1839 int ret;
1840
1841 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1842 if (msm_host->irq < 0) {
1843 ret = msm_host->irq;
1844 dev_err(dev->dev, "failed to get irq: %d\n", ret);
1845 return ret;
1846 }
1847
1848 ret = devm_request_irq(&pdev->dev, msm_host->irq,
1849 dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1850 "dsi_isr", msm_host);
1851 if (ret < 0) {
1852 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n",
1853 msm_host->irq, ret);
1854 return ret;
1855 }
1856
1857 msm_host->dev = dev;
1858 ret = dsi_tx_buf_alloc(msm_host, SZ_4K);
1859 if (ret) {
1860 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
1861 return ret;
1862 }
1863
1864 return 0;
1865}
1866
1867int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer)
1868{
1869 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1870 int ret;
1871
1872 /* Register mipi dsi host */
1873 if (!msm_host->registered) {
1874 host->dev = &msm_host->pdev->dev;
1875 host->ops = &dsi_host_ops;
1876 ret = mipi_dsi_host_register(host);
1877 if (ret)
1878 return ret;
1879
1880 msm_host->registered = true;
1881
1882 /* If the panel driver has not been probed after host register,
1883 * we should defer the host's probe.
1884 * It makes sure panel is connected when fbcon detects
1885 * connector status and gets the proper display mode to
1886 * create framebuffer.
1887 * Don't try to defer if there is nothing connected to the dsi
1888 * output
1889 */
1890 if (check_defer && msm_host->device_node) {
1891 if (!of_drm_find_panel(msm_host->device_node))
1892 if (!of_drm_find_bridge(msm_host->device_node))
1893 return -EPROBE_DEFER;
1894 }
1895 }
1896
1897 return 0;
1898}
1899
1900void msm_dsi_host_unregister(struct mipi_dsi_host *host)
1901{
1902 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1903
1904 if (msm_host->registered) {
1905 mipi_dsi_host_unregister(host);
1906 host->dev = NULL;
1907 host->ops = NULL;
1908 msm_host->registered = false;
1909 }
1910}
1911
1912int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
1913 const struct mipi_dsi_msg *msg)
1914{
1915 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1916
1917 /* TODO: make sure dsi_cmd_mdp is idle.
1918 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME
1919 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed.
1920 * How to handle the old versions? Wait for mdp cmd done?
1921 */
1922
1923 /*
1924 * mdss interrupt is generated in mdp core clock domain
1925 * mdp clock need to be enabled to receive dsi interrupt
1926 */
1927 pm_runtime_get_sync(&msm_host->pdev->dev);
1928 dsi_link_clk_enable(msm_host);
1929
1930 /* TODO: vote for bus bandwidth */
1931
1932 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
1933 dsi_set_tx_power_mode(0, msm_host);
1934
1935 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL);
1936 dsi_write(msm_host, REG_DSI_CTRL,
1937 msm_host->dma_cmd_ctrl_restore |
1938 DSI_CTRL_CMD_MODE_EN |
1939 DSI_CTRL_ENABLE);
1940 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1);
1941
1942 return 0;
1943}
1944
1945void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
1946 const struct mipi_dsi_msg *msg)
1947{
1948 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1949
1950 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0);
1951 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);
1952
1953 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
1954 dsi_set_tx_power_mode(1, msm_host);
1955
1956 /* TODO: unvote for bus bandwidth */
1957
1958 dsi_link_clk_disable(msm_host);
1959 pm_runtime_put_autosuspend(&msm_host->pdev->dev);
1960}
1961
1962int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host,
1963 const struct mipi_dsi_msg *msg)
1964{
1965 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1966
1967 return dsi_cmds2buf_tx(msm_host, msg);
1968}
1969
1970int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host,
1971 const struct mipi_dsi_msg *msg)
1972{
1973 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1974 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1975 int data_byte, rx_byte, dlen, end;
1976 int short_response, diff, pkt_size, ret = 0;
1977 char cmd;
1978 int rlen = msg->rx_len;
1979 u8 *buf;
1980
1981 if (rlen <= 2) {
1982 short_response = 1;
1983 pkt_size = rlen;
1984 rx_byte = 4;
1985 } else {
1986 short_response = 0;
1987 data_byte = 10; /* first read */
1988 if (rlen < data_byte)
1989 pkt_size = rlen;
1990 else
1991 pkt_size = data_byte;
1992 rx_byte = data_byte + 6; /* 4 header + 2 crc */
1993 }
1994
1995 buf = msm_host->rx_buf;
1996 end = 0;
1997 while (!end) {
1998 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8};
1999 struct mipi_dsi_msg max_pkt_size_msg = {
2000 .channel = msg->channel,
2001 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
2002 .tx_len = 2,
2003 .tx_buf = tx,
2004 };
2005
2006 DBG("rlen=%d pkt_size=%d rx_byte=%d",
2007 rlen, pkt_size, rx_byte);
2008
2009 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg);
2010 if (ret < 2) {
2011 pr_err("%s: Set max pkt size failed, %d\n",
2012 __func__, ret);
2013 return -EINVAL;
2014 }
2015
2016 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
2017 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) {
2018 /* Clear the RDBK_DATA registers */
2019 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,
2020 DSI_RDBK_DATA_CTRL_CLR);
2021 wmb(); /* make sure the RDBK registers are cleared */
2022 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);
2023 wmb(); /* release cleared status before transfer */
2024 }
2025
2026 ret = dsi_cmds2buf_tx(msm_host, msg);
2027 if (ret < msg->tx_len) {
2028 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret);
2029 return ret;
2030 }
2031
2032 /*
2033 * once cmd_dma_done interrupt received,
2034 * return data from client is ready and stored
2035 * at RDBK_DATA register already
2036 * since rx fifo is 16 bytes, dcs header is kept at first loop,
2037 * after that dcs header lost during shift into registers
2038 */
2039 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size);
2040
2041 if (dlen <= 0)
2042 return 0;
2043
2044 if (short_response)
2045 break;
2046
2047 if (rlen <= data_byte) {
2048 diff = data_byte - rlen;
2049 end = 1;
2050 } else {
2051 diff = 0;
2052 rlen -= data_byte;
2053 }
2054
2055 if (!end) {
2056 dlen -= 2; /* 2 crc */
2057 dlen -= diff;
2058 buf += dlen; /* next start position */
2059 data_byte = 14; /* NOT first read */
2060 if (rlen < data_byte)
2061 pkt_size += rlen;
2062 else
2063 pkt_size += data_byte;
2064 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff);
2065 }
2066 }
2067
2068 /*
2069 * For single Long read, if the requested rlen < 10,
2070 * we need to shift the start position of rx
2071 * data buffer to skip the bytes which are not
2072 * updated.
2073 */
2074 if (pkt_size < 10 && !short_response)
2075 buf = msm_host->rx_buf + (10 - rlen);
2076 else
2077 buf = msm_host->rx_buf;
2078
2079 cmd = buf[0];
2080 switch (cmd) {
2081 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
2082 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__);
2083 ret = 0;
2084 break;
2085 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
2086 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
2087 ret = dsi_short_read1_resp(buf, msg);
2088 break;
2089 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
2090 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
2091 ret = dsi_short_read2_resp(buf, msg);
2092 break;
2093 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
2094 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
2095 ret = dsi_long_read_resp(buf, msg);
2096 break;
2097 default:
2098 pr_warn("%s:Invalid response cmd\n", __func__);
2099 ret = 0;
2100 }
2101
2102 return ret;
2103}
2104
2105void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base,
2106 u32 len)
2107{
2108 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2109
2110 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base);
2111 dsi_write(msm_host, REG_DSI_DMA_LEN, len);
2112 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);
2113
2114 /* Make sure trigger happens */
2115 wmb();
2116}
2117
2118int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
2119 struct msm_dsi_pll *src_pll)
2120{
2121 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2122 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2123 struct clk *byte_clk_provider, *pixel_clk_provider;
2124 int ret;
2125
2126 ret = msm_dsi_pll_get_clk_provider(src_pll,
2127 &byte_clk_provider, &pixel_clk_provider);
2128 if (ret) {
2129 pr_info("%s: can't get provider from pll, don't set parent\n",
2130 __func__);
2131 return 0;
2132 }
2133
2134 ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider);
2135 if (ret) {
2136 pr_err("%s: can't set parent to byte_clk_src. ret=%d\n",
2137 __func__, ret);
2138 goto exit;
2139 }
2140
2141 ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider);
2142 if (ret) {
2143 pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n",
2144 __func__, ret);
2145 goto exit;
2146 }
2147
2148 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
2149 ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider);
2150 if (ret) {
2151 pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n",
2152 __func__, ret);
2153 goto exit;
2154 }
2155
2156 ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider);
2157 if (ret) {
2158 pr_err("%s: can't set parent to esc_clk_src. ret=%d\n",
2159 __func__, ret);
2160 goto exit;
2161 }
2162 }
2163
2164exit:
2165 return ret;
2166}
2167
2168void msm_dsi_host_reset_phy(struct mipi_dsi_host *host)
2169{
2170 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2171
2172 DBG("");
2173 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);
2174 /* Make sure fully reset */
2175 wmb();
2176 udelay(1000);
2177 dsi_write(msm_host, REG_DSI_PHY_RESET, 0);
2178 udelay(100);
2179}
2180
2181void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
2182 struct msm_dsi_phy_clk_request *clk_req)
2183{
2184 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2185 int ret;
2186
2187 ret = dsi_calc_clk_rate(msm_host);
2188 if (ret) {
2189 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
2190 return;
2191 }
2192
2193 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8;
2194 clk_req->escclk_rate = msm_host->esc_clk_rate;
2195}
2196
2197int msm_dsi_host_enable(struct mipi_dsi_host *host)
2198{
2199 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2200
2201 dsi_op_mode_config(msm_host,
2202 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true);
2203
2204 /* TODO: clock should be turned off for command mode,
2205 * and only turned on before MDP START.
2206 * This part of code should be enabled once mdp driver support it.
2207 */
2208 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) {
2209 * dsi_link_clk_disable(msm_host);
2210 * pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2211 * }
2212 */
2213 msm_host->enabled = true;
2214 return 0;
2215}
2216
2217int msm_dsi_host_disable(struct mipi_dsi_host *host)
2218{
2219 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2220
2221 msm_host->enabled = false;
2222 dsi_op_mode_config(msm_host,
2223 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false);
2224
2225 /* Since we have disabled INTF, the video engine won't stop so that
2226 * the cmd engine will be blocked.
2227 * Reset to disable video engine so that we can send off cmd.
2228 */
2229 dsi_sw_reset(msm_host);
2230
2231 return 0;
2232}
2233
2234static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable)
2235{
2236 enum sfpb_ahb_arb_master_port_en en;
2237
2238 if (!msm_host->sfpb)
2239 return;
2240
2241 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE;
2242
2243 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG,
2244 SFPB_GPREG_MASTER_PORT_EN__MASK,
2245 SFPB_GPREG_MASTER_PORT_EN(en));
2246}
2247
2248int msm_dsi_host_power_on(struct mipi_dsi_host *host,
2249 struct msm_dsi_phy_shared_timings *phy_shared_timings)
2250{
2251 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2252 int ret = 0;
2253
2254 mutex_lock(&msm_host->dev_mutex);
2255 if (msm_host->power_on) {
2256 DBG("dsi host already on");
2257 goto unlock_ret;
2258 }
2259
2260 msm_dsi_sfpb_config(msm_host, true);
2261
2262 ret = dsi_host_regulator_enable(msm_host);
2263 if (ret) {
2264 pr_err("%s:Failed to enable vregs.ret=%d\n",
2265 __func__, ret);
2266 goto unlock_ret;
2267 }
2268
2269 pm_runtime_get_sync(&msm_host->pdev->dev);
2270 ret = dsi_link_clk_enable(msm_host);
2271 if (ret) {
2272 pr_err("%s: failed to enable link clocks. ret=%d\n",
2273 __func__, ret);
2274 goto fail_disable_reg;
2275 }
2276
2277 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev);
2278 if (ret) {
2279 pr_err("%s: failed to set pinctrl default state, %d\n",
2280 __func__, ret);
2281 goto fail_disable_clk;
2282 }
2283
2284 dsi_timing_setup(msm_host);
2285 dsi_sw_reset(msm_host);
2286 dsi_ctrl_config(msm_host, true, phy_shared_timings);
2287
2288 if (msm_host->disp_en_gpio)
2289 gpiod_set_value(msm_host->disp_en_gpio, 1);
2290
2291 msm_host->power_on = true;
2292 mutex_unlock(&msm_host->dev_mutex);
2293
2294 return 0;
2295
2296fail_disable_clk:
2297 dsi_link_clk_disable(msm_host);
2298 pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2299fail_disable_reg:
2300 dsi_host_regulator_disable(msm_host);
2301unlock_ret:
2302 mutex_unlock(&msm_host->dev_mutex);
2303 return ret;
2304}
2305
2306int msm_dsi_host_power_off(struct mipi_dsi_host *host)
2307{
2308 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2309
2310 mutex_lock(&msm_host->dev_mutex);
2311 if (!msm_host->power_on) {
2312 DBG("dsi host already off");
2313 goto unlock_ret;
2314 }
2315
2316 dsi_ctrl_config(msm_host, false, NULL);
2317
2318 if (msm_host->disp_en_gpio)
2319 gpiod_set_value(msm_host->disp_en_gpio, 0);
2320
2321 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev);
2322
2323 dsi_link_clk_disable(msm_host);
2324 pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2325
2326 dsi_host_regulator_disable(msm_host);
2327
2328 msm_dsi_sfpb_config(msm_host, false);
2329
2330 DBG("-");
2331
2332 msm_host->power_on = false;
2333
2334unlock_ret:
2335 mutex_unlock(&msm_host->dev_mutex);
2336 return 0;
2337}
2338
2339int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
2340 struct drm_display_mode *mode)
2341{
2342 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2343
2344 if (msm_host->mode) {
2345 drm_mode_destroy(msm_host->dev, msm_host->mode);
2346 msm_host->mode = NULL;
2347 }
2348
2349 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode);
2350 if (!msm_host->mode) {
2351 pr_err("%s: cannot duplicate mode\n", __func__);
2352 return -ENOMEM;
2353 }
2354
2355 return 0;
2356}
2357
2358struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host,
2359 unsigned long *panel_flags)
2360{
2361 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2362 struct drm_panel *panel;
2363
2364 panel = of_drm_find_panel(msm_host->device_node);
2365 if (panel_flags)
2366 *panel_flags = msm_host->mode_flags;
2367
2368 return panel;
2369}
2370
2371struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host)
2372{
2373 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2374
2375 return of_drm_find_bridge(msm_host->device_node);
2376}