1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
  2/*
  3 * This file is provided under a dual BSD/GPLv2 license.  When using or
  4 * redistributing this file, you may do so under either license.
  5 *
  6 * Copyright(c) 2018 Intel Corporation. All rights reserved.
  7 */
  8
  9#ifndef __INCLUDE_SOUND_SOF_TOPOLOGY_H__
 10#define __INCLUDE_SOUND_SOF_TOPOLOGY_H__
 11
 12#include <sound/sof/header.h>
 13
 14/*
 15 * Component
 16 */
 17
 18/* types of component */
 19enum sof_comp_type {
 20	SOF_COMP_NONE = 0,
 21	SOF_COMP_HOST,
 22	SOF_COMP_DAI,
 23	SOF_COMP_SG_HOST,	/**< scatter gather variant */
 24	SOF_COMP_SG_DAI,	/**< scatter gather variant */
 25	SOF_COMP_VOLUME,
 26	SOF_COMP_MIXER,
 27	SOF_COMP_MUX,
 28	SOF_COMP_SRC,
 29	SOF_COMP_SPLITTER,
 30	SOF_COMP_TONE,
 31	SOF_COMP_SWITCH,
 32	SOF_COMP_BUFFER,
 33	SOF_COMP_EQ_IIR,
 34	SOF_COMP_EQ_FIR,
 35	SOF_COMP_KEYWORD_DETECT,
 36	SOF_COMP_KPB,			/* A key phrase buffer component */
 37	SOF_COMP_SELECTOR,		/**< channel selector component */
 38	SOF_COMP_DEMUX,
 39	SOF_COMP_ASRC,		/**< Asynchronous sample rate converter */
 40	SOF_COMP_DCBLOCK,
 41	SOF_COMP_SMART_AMP,             /**< smart amplifier component */
 42	/* keep FILEREAD/FILEWRITE as the last ones */
 43	SOF_COMP_FILEREAD = 10000,	/**< host test based file IO */
 44	SOF_COMP_FILEWRITE = 10001,	/**< host test based file IO */
 45};
 46
 47/* XRUN action for component */
 48#define SOF_XRUN_STOP		1	/**< stop stream */
 49#define SOF_XRUN_UNDER_ZERO	2	/**< send 0s to sink */
 50#define SOF_XRUN_OVER_NULL	4	/**< send data to NULL */
 51
 52/* create new generic component - SOF_IPC_TPLG_COMP_NEW */
 53struct sof_ipc_comp {
 54	struct sof_ipc_cmd_hdr hdr;
 55	uint32_t id;
 56	enum sof_comp_type type;
 57	uint32_t pipeline_id;
 58	uint32_t core;
 59
 60	/* extended data length, 0 if no extended data */
 61	uint32_t ext_data_length;
 62} __packed;
 63
 64/*
 65 * Component Buffers
 66 */
 67
 68/*
 69 * SOF memory capabilities, add new ones at the end
 70 */
 71#define SOF_MEM_CAPS_RAM			(1 << 0)
 72#define SOF_MEM_CAPS_ROM			(1 << 1)
 73#define SOF_MEM_CAPS_EXT			(1 << 2) /**< external */
 74#define SOF_MEM_CAPS_LP			(1 << 3) /**< low power */
 75#define SOF_MEM_CAPS_HP			(1 << 4) /**< high performance */
 76#define SOF_MEM_CAPS_DMA			(1 << 5) /**< DMA'able */
 77#define SOF_MEM_CAPS_CACHE			(1 << 6) /**< cacheable */
 78#define SOF_MEM_CAPS_EXEC			(1 << 7) /**< executable */
 79
 80/*
 81 * overrun will cause ring buffer overwrite, instead of XRUN.
 82 */
 83#define SOF_BUF_OVERRUN_PERMITTED	BIT(0)
 84
 85/*
 86 * underrun will cause readback of 0s, instead of XRUN.
 87 */
 88#define SOF_BUF_UNDERRUN_PERMITTED	BIT(1)
 89
 90/* create new component buffer - SOF_IPC_TPLG_BUFFER_NEW */
 91struct sof_ipc_buffer {
 92	struct sof_ipc_comp comp;
 93	uint32_t size;		/**< buffer size in bytes */
 94	uint32_t caps;		/**< SOF_MEM_CAPS_ */
 95	uint32_t flags;		/**< SOF_BUF_ flags defined above */
 96	uint32_t reserved;	/**< reserved for future use */
 97} __packed;
 98
 99/* generic component config data - must always be after struct sof_ipc_comp */
100struct sof_ipc_comp_config {
101	struct sof_ipc_cmd_hdr hdr;
102	uint32_t periods_sink;	/**< 0 means variable */
103	uint32_t periods_source;/**< 0 means variable */
104	uint32_t reserved1;	/**< reserved */
105	uint32_t frame_fmt;	/**< SOF_IPC_FRAME_ */
106	uint32_t xrun_action;
107
108	/* reserved for future use */
109	uint32_t reserved[2];
110} __packed;
111
112/* generic host component */
113struct sof_ipc_comp_host {
114	struct sof_ipc_comp comp;
115	struct sof_ipc_comp_config config;
116	uint32_t direction;	/**< SOF_IPC_STREAM_ */
117	uint32_t no_irq;	/**< don't send periodic IRQ to host/DSP */
118	uint32_t dmac_config; /**< DMA engine specific */
119}  __packed;
120
121/* generic DAI component */
122struct sof_ipc_comp_dai {
123	struct sof_ipc_comp comp;
124	struct sof_ipc_comp_config config;
125	uint32_t direction;	/**< SOF_IPC_STREAM_ */
126	uint32_t dai_index;	/**< index of this type dai */
127	uint32_t type;		/**< DAI type - SOF_DAI_ */
128	uint32_t reserved;	/**< reserved */
129}  __packed;
130
131/* generic mixer component */
132struct sof_ipc_comp_mixer {
133	struct sof_ipc_comp comp;
134	struct sof_ipc_comp_config config;
135}  __packed;
136
137/* volume ramping types */
138enum sof_volume_ramp {
139	SOF_VOLUME_LINEAR	= 0,
140	SOF_VOLUME_LOG,
141	SOF_VOLUME_LINEAR_ZC,
142	SOF_VOLUME_LOG_ZC,
143};
144
145/* generic volume component */
146struct sof_ipc_comp_volume {
147	struct sof_ipc_comp comp;
148	struct sof_ipc_comp_config config;
149	uint32_t channels;
150	uint32_t min_value;
151	uint32_t max_value;
152	uint32_t ramp;		/**< SOF_VOLUME_ */
153	uint32_t initial_ramp;	/**< ramp space in ms */
154}  __packed;
155
156/* generic SRC component */
157struct sof_ipc_comp_src {
158	struct sof_ipc_comp comp;
159	struct sof_ipc_comp_config config;
160	/* either source or sink rate must be non zero */
161	uint32_t source_rate;	/**< source rate or 0 for variable */
162	uint32_t sink_rate;	/**< sink rate or 0 for variable */
163	uint32_t rate_mask;	/**< SOF_RATE_ supported rates */
164} __packed;
165
166/* generic ASRC component */
167struct sof_ipc_comp_asrc {
168	struct sof_ipc_comp comp;
169	struct sof_ipc_comp_config config;
170	/* either source or sink rate must be non zero */
171	uint32_t source_rate;		/**< Define fixed source rate or */
172					/**< use 0 to indicate need to get */
173					/**< the rate from stream */
174	uint32_t sink_rate;		/**< Define fixed sink rate or */
175					/**< use 0 to indicate need to get */
176					/**< the rate from stream */
177	uint32_t asynchronous_mode;	/**< synchronous 0, asynchronous 1 */
178					/**< When 1 the ASRC tracks and */
179					/**< compensates for drift. */
180	uint32_t operation_mode;	/**< push 0, pull 1, In push mode the */
181					/**< ASRC consumes a defined number */
182					/**< of frames at input, with varying */
183					/**< number of frames at output. */
184					/**< In pull mode the ASRC outputs */
185					/**< a defined number of frames while */
186					/**< number of input frames varies. */
187
188	/* reserved for future use */
189	uint32_t reserved[4];
190} __attribute__((packed));
191
192/* generic MUX component */
193struct sof_ipc_comp_mux {
194	struct sof_ipc_comp comp;
195	struct sof_ipc_comp_config config;
196} __packed;
197
198/* generic tone generator component */
199struct sof_ipc_comp_tone {
200	struct sof_ipc_comp comp;
201	struct sof_ipc_comp_config config;
202	int32_t sample_rate;
203	int32_t frequency;
204	int32_t amplitude;
205	int32_t freq_mult;
206	int32_t ampl_mult;
207	int32_t length;
208	int32_t period;
209	int32_t repeats;
210	int32_t ramp_step;
211} __packed;
212
213/** \brief Types of processing components */
214enum sof_ipc_process_type {
215	SOF_PROCESS_NONE = 0,		/**< None */
216	SOF_PROCESS_EQFIR,		/**< Intel FIR */
217	SOF_PROCESS_EQIIR,		/**< Intel IIR */
218	SOF_PROCESS_KEYWORD_DETECT,	/**< Keyword Detection */
219	SOF_PROCESS_KPB,		/**< KeyPhrase Buffer Manager */
220	SOF_PROCESS_CHAN_SELECTOR,	/**< Channel Selector */
221	SOF_PROCESS_MUX,
222	SOF_PROCESS_DEMUX,
223	SOF_PROCESS_DCBLOCK,
224	SOF_PROCESS_SMART_AMP,	/**< Smart Amplifier */
225};
226
227/* generic "effect", "codec" or proprietary processing component */
228struct sof_ipc_comp_process {
229	struct sof_ipc_comp comp;
230	struct sof_ipc_comp_config config;
231	uint32_t size;	/**< size of bespoke data section in bytes */
232	uint32_t type;	/**< sof_ipc_process_type */
233
234	/* reserved for future use */
235	uint32_t reserved[7];
236
237	uint8_t data[];
238} __packed;
239
240/* frees components, buffers and pipelines
241 * SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_FREE, SOF_IPC_TPLG_BUFFER_FREE
242 */
243struct sof_ipc_free {
244	struct sof_ipc_cmd_hdr hdr;
245	uint32_t id;
246} __packed;
247
248struct sof_ipc_comp_reply {
249	struct sof_ipc_reply rhdr;
250	uint32_t id;
251	uint32_t offset;
252} __packed;
253
254/*
255 * Pipeline
256 */
257
258/** \brief Types of pipeline scheduling time domains */
259enum sof_ipc_pipe_sched_time_domain {
260	SOF_TIME_DOMAIN_DMA = 0,	/**< DMA interrupt */
261	SOF_TIME_DOMAIN_TIMER,		/**< Timer interrupt */
262};
263
264/* new pipeline - SOF_IPC_TPLG_PIPE_NEW */
265struct sof_ipc_pipe_new {
266	struct sof_ipc_cmd_hdr hdr;
267	uint32_t comp_id;	/**< component id for pipeline */
268	uint32_t pipeline_id;	/**< pipeline id */
269	uint32_t sched_id;	/**< Scheduling component id */
270	uint32_t core;		/**< core we run on */
271	uint32_t period;	/**< execution period in us*/
272	uint32_t priority;	/**< priority level 0 (low) to 10 (max) */
273	uint32_t period_mips;	/**< worst case instruction count per period */
274	uint32_t frames_per_sched;/**< output frames of pipeline, 0 is variable */
275	uint32_t xrun_limit_usecs; /**< report xruns greater than limit */
276	uint32_t time_domain;	/**< scheduling time domain */
277}  __packed;
278
279/* pipeline construction complete - SOF_IPC_TPLG_PIPE_COMPLETE */
280struct sof_ipc_pipe_ready {
281	struct sof_ipc_cmd_hdr hdr;
282	uint32_t comp_id;
283}  __packed;
284
285struct sof_ipc_pipe_free {
286	struct sof_ipc_cmd_hdr hdr;
287	uint32_t comp_id;
288}  __packed;
289
290/* connect two components in pipeline - SOF_IPC_TPLG_COMP_CONNECT */
291struct sof_ipc_pipe_comp_connect {
292	struct sof_ipc_cmd_hdr hdr;
293	uint32_t source_id;
294	uint32_t sink_id;
295}  __packed;
296
297/* external events */
298enum sof_event_types {
299	SOF_EVENT_NONE = 0,
300	SOF_KEYWORD_DETECT_DAPM_EVENT,
301};
302
303#endif