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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * drivers/soc/tegra/pmc.c
4 *
5 * Copyright (c) 2010 Google, Inc
6 * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
7 *
8 * Author:
9 * Colin Cross <ccross@google.com>
10 */
11
12#define pr_fmt(fmt) "tegra-pmc: " fmt
13
14#include <linux/arm-smccc.h>
15#include <linux/clk.h>
16#include <linux/clk-provider.h>
17#include <linux/clkdev.h>
18#include <linux/clk/clk-conf.h>
19#include <linux/clk/tegra.h>
20#include <linux/debugfs.h>
21#include <linux/delay.h>
22#include <linux/device.h>
23#include <linux/err.h>
24#include <linux/export.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/iopoll.h>
29#include <linux/irqdomain.h>
30#include <linux/irq.h>
31#include <linux/kernel.h>
32#include <linux/of_address.h>
33#include <linux/of_clk.h>
34#include <linux/of.h>
35#include <linux/of_irq.h>
36#include <linux/of_platform.h>
37#include <linux/pinctrl/pinconf-generic.h>
38#include <linux/pinctrl/pinconf.h>
39#include <linux/pinctrl/pinctrl.h>
40#include <linux/platform_device.h>
41#include <linux/pm_domain.h>
42#include <linux/pm_opp.h>
43#include <linux/power_supply.h>
44#include <linux/reboot.h>
45#include <linux/regmap.h>
46#include <linux/reset.h>
47#include <linux/seq_file.h>
48#include <linux/slab.h>
49#include <linux/spinlock.h>
50#include <linux/syscore_ops.h>
51
52#include <soc/tegra/common.h>
53#include <soc/tegra/fuse.h>
54#include <soc/tegra/pmc.h>
55
56#include <dt-bindings/interrupt-controller/arm-gic.h>
57#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
58#include <dt-bindings/gpio/tegra186-gpio.h>
59#include <dt-bindings/gpio/tegra194-gpio.h>
60#include <dt-bindings/gpio/tegra234-gpio.h>
61#include <dt-bindings/soc/tegra-pmc.h>
62
63#define PMC_CNTRL 0x0
64#define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
65#define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
66#define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
67#define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
68#define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
69#define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
70#define PMC_CNTRL_PWRREQ_POLARITY BIT(8)
71#define PMC_CNTRL_BLINK_EN 7
72#define PMC_CNTRL_MAIN_RST BIT(4)
73
74#define PMC_WAKE_MASK 0x0c
75#define PMC_WAKE_LEVEL 0x10
76#define PMC_WAKE_STATUS 0x14
77#define PMC_SW_WAKE_STATUS 0x18
78#define PMC_DPD_PADS_ORIDE 0x1c
79#define PMC_DPD_PADS_ORIDE_BLINK 20
80
81#define DPD_SAMPLE 0x020
82#define DPD_SAMPLE_ENABLE BIT(0)
83#define DPD_SAMPLE_DISABLE (0 << 0)
84
85#define PWRGATE_TOGGLE 0x30
86#define PWRGATE_TOGGLE_START BIT(8)
87
88#define REMOVE_CLAMPING 0x34
89
90#define PWRGATE_STATUS 0x38
91
92#define PMC_BLINK_TIMER 0x40
93#define PMC_IMPL_E_33V_PWR 0x40
94
95#define PMC_PWR_DET 0x48
96
97#define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
98#define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
99#define PMC_SCRATCH0_MODE_RCM BIT(1)
100#define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
101 PMC_SCRATCH0_MODE_BOOTLOADER | \
102 PMC_SCRATCH0_MODE_RCM)
103
104#define PMC_CPUPWRGOOD_TIMER 0xc8
105#define PMC_CPUPWROFF_TIMER 0xcc
106#define PMC_COREPWRGOOD_TIMER 0x3c
107#define PMC_COREPWROFF_TIMER 0xe0
108
109#define PMC_PWR_DET_VALUE 0xe4
110
111#define PMC_USB_DEBOUNCE_DEL 0xec
112#define PMC_USB_AO 0xf0
113
114#define PMC_SCRATCH37 0x130
115#define PMC_SCRATCH41 0x140
116
117#define PMC_WAKE2_MASK 0x160
118#define PMC_WAKE2_LEVEL 0x164
119#define PMC_WAKE2_STATUS 0x168
120#define PMC_SW_WAKE2_STATUS 0x16c
121
122#define PMC_CLK_OUT_CNTRL 0x1a8
123#define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0)
124#define PMC_SENSOR_CTRL 0x1b0
125#define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
126#define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
127
128#define PMC_RST_STATUS_POR 0
129#define PMC_RST_STATUS_WATCHDOG 1
130#define PMC_RST_STATUS_SENSOR 2
131#define PMC_RST_STATUS_SW_MAIN 3
132#define PMC_RST_STATUS_LP0 4
133#define PMC_RST_STATUS_AOTAG 5
134
135#define IO_DPD_REQ 0x1b8
136#define IO_DPD_REQ_CODE_IDLE (0U << 30)
137#define IO_DPD_REQ_CODE_OFF (1U << 30)
138#define IO_DPD_REQ_CODE_ON (2U << 30)
139#define IO_DPD_REQ_CODE_MASK (3U << 30)
140
141#define IO_DPD_STATUS 0x1bc
142#define IO_DPD2_REQ 0x1c0
143#define IO_DPD2_STATUS 0x1c4
144#define SEL_DPD_TIM 0x1c8
145
146#define PMC_UTMIP_UHSIC_TRIGGERS 0x1ec
147#define PMC_UTMIP_UHSIC_SAVED_STATE 0x1f0
148
149#define PMC_UTMIP_TERM_PAD_CFG 0x1f8
150#define PMC_UTMIP_UHSIC_SLEEP_CFG 0x1fc
151#define PMC_UTMIP_UHSIC_FAKE 0x218
152
153#define PMC_SCRATCH54 0x258
154#define PMC_SCRATCH54_DATA_SHIFT 8
155#define PMC_SCRATCH54_ADDR_SHIFT 0
156
157#define PMC_SCRATCH55 0x25c
158#define PMC_SCRATCH55_RESET_TEGRA BIT(31)
159#define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
160#define PMC_SCRATCH55_PINMUX_SHIFT 24
161#define PMC_SCRATCH55_16BITOP BIT(15)
162#define PMC_SCRATCH55_CHECKSUM_SHIFT 16
163#define PMC_SCRATCH55_I2CSLV1_SHIFT 0
164
165#define PMC_UTMIP_UHSIC_LINE_WAKEUP 0x26c
166
167#define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270
168#define PMC_UTMIP_MASTER_CONFIG 0x274
169#define PMC_UTMIP_UHSIC2_TRIGGERS 0x27c
170#define PMC_UTMIP_MASTER2_CONFIG 0x29c
171
172#define GPU_RG_CNTRL 0x2d4
173
174#define PMC_UTMIP_PAD_CFG0 0x4c0
175#define PMC_UTMIP_UHSIC_SLEEP_CFG1 0x4d0
176#define PMC_UTMIP_SLEEPWALK_P3 0x4e0
177/* Tegra186 and later */
178#define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))
179#define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3)
180#define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2))
181#define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2))
182#define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2))
183#define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2))
184#define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2))
185#define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2))
186#define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))
187#define WAKE_AOWAKE_SW_STATUS_W_0 0x49c
188#define WAKE_AOWAKE_SW_STATUS(x) (0x4a0 + ((x) << 2))
189#define WAKE_LATCH_SW 0x498
190
191#define WAKE_AOWAKE_CTRL 0x4f4
192#define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
193
194/* for secure PMC */
195#define TEGRA_SMC_PMC 0xc2fffe00
196#define TEGRA_SMC_PMC_READ 0xaa
197#define TEGRA_SMC_PMC_WRITE 0xbb
198
199struct pmc_clk {
200 struct clk_hw hw;
201 unsigned long offs;
202 u32 mux_shift;
203 u32 force_en_shift;
204};
205
206#define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
207
208struct pmc_clk_gate {
209 struct clk_hw hw;
210 unsigned long offs;
211 u32 shift;
212};
213
214#define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)
215
216struct pmc_clk_init_data {
217 char *name;
218 const char *const *parents;
219 int num_parents;
220 int clk_id;
221 u8 mux_shift;
222 u8 force_en_shift;
223};
224
225static const char * const clk_out1_parents[] = { "osc", "osc_div2",
226 "osc_div4", "extern1",
227};
228
229static const char * const clk_out2_parents[] = { "osc", "osc_div2",
230 "osc_div4", "extern2",
231};
232
233static const char * const clk_out3_parents[] = { "osc", "osc_div2",
234 "osc_div4", "extern3",
235};
236
237static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
238 {
239 .name = "pmc_clk_out_1",
240 .parents = clk_out1_parents,
241 .num_parents = ARRAY_SIZE(clk_out1_parents),
242 .clk_id = TEGRA_PMC_CLK_OUT_1,
243 .mux_shift = 6,
244 .force_en_shift = 2,
245 },
246 {
247 .name = "pmc_clk_out_2",
248 .parents = clk_out2_parents,
249 .num_parents = ARRAY_SIZE(clk_out2_parents),
250 .clk_id = TEGRA_PMC_CLK_OUT_2,
251 .mux_shift = 14,
252 .force_en_shift = 10,
253 },
254 {
255 .name = "pmc_clk_out_3",
256 .parents = clk_out3_parents,
257 .num_parents = ARRAY_SIZE(clk_out3_parents),
258 .clk_id = TEGRA_PMC_CLK_OUT_3,
259 .mux_shift = 22,
260 .force_en_shift = 18,
261 },
262};
263
264struct tegra_powergate {
265 struct generic_pm_domain genpd;
266 struct tegra_pmc *pmc;
267 unsigned int id;
268 struct clk **clks;
269 unsigned int num_clks;
270 unsigned long *clk_rates;
271 struct reset_control *reset;
272};
273
274struct tegra_io_pad_soc {
275 enum tegra_io_pad id;
276 unsigned int dpd;
277 unsigned int request;
278 unsigned int status;
279 unsigned int voltage;
280 const char *name;
281};
282
283struct tegra_pmc_regs {
284 unsigned int scratch0;
285 unsigned int rst_status;
286 unsigned int rst_source_shift;
287 unsigned int rst_source_mask;
288 unsigned int rst_level_shift;
289 unsigned int rst_level_mask;
290};
291
292struct tegra_wake_event {
293 const char *name;
294 unsigned int id;
295 unsigned int irq;
296 struct {
297 unsigned int instance;
298 unsigned int pin;
299 } gpio;
300};
301
302#define TEGRA_WAKE_SIMPLE(_name, _id) \
303 { \
304 .name = _name, \
305 .id = _id, \
306 .irq = 0, \
307 .gpio = { \
308 .instance = UINT_MAX, \
309 .pin = UINT_MAX, \
310 }, \
311 }
312
313#define TEGRA_WAKE_IRQ(_name, _id, _irq) \
314 { \
315 .name = _name, \
316 .id = _id, \
317 .irq = _irq, \
318 .gpio = { \
319 .instance = UINT_MAX, \
320 .pin = UINT_MAX, \
321 }, \
322 }
323
324#define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \
325 { \
326 .name = _name, \
327 .id = _id, \
328 .irq = 0, \
329 .gpio = { \
330 .instance = _instance, \
331 .pin = _pin, \
332 }, \
333 }
334
335struct tegra_pmc_soc {
336 unsigned int num_powergates;
337 const char *const *powergates;
338 unsigned int num_cpu_powergates;
339 const u8 *cpu_powergates;
340
341 bool has_tsense_reset;
342 bool has_gpu_clamps;
343 bool needs_mbist_war;
344 bool has_impl_33v_pwr;
345 bool maybe_tz_only;
346
347 const struct tegra_io_pad_soc *io_pads;
348 unsigned int num_io_pads;
349
350 const struct pinctrl_pin_desc *pin_descs;
351 unsigned int num_pin_descs;
352
353 const struct tegra_pmc_regs *regs;
354 void (*init)(struct tegra_pmc *pmc);
355 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
356 struct device_node *np,
357 bool invert);
358 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
359 int (*irq_set_type)(struct irq_data *data, unsigned int type);
360 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id,
361 bool new_state);
362
363 const char * const *reset_sources;
364 unsigned int num_reset_sources;
365 const char * const *reset_levels;
366 unsigned int num_reset_levels;
367
368 /*
369 * These describe events that can wake the system from sleep (i.e.
370 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2)
371 * are dealt with in the LIC.
372 */
373 const struct tegra_wake_event *wake_events;
374 unsigned int num_wake_events;
375 unsigned int max_wake_events;
376 unsigned int max_wake_vectors;
377
378 const struct pmc_clk_init_data *pmc_clks_data;
379 unsigned int num_pmc_clks;
380 bool has_blink_output;
381 bool has_usb_sleepwalk;
382 bool supports_core_domain;
383};
384
385/**
386 * struct tegra_pmc - NVIDIA Tegra PMC
387 * @dev: pointer to PMC device structure
388 * @base: pointer to I/O remapped register region
389 * @wake: pointer to I/O remapped region for WAKE registers
390 * @aotag: pointer to I/O remapped region for AOTAG registers
391 * @scratch: pointer to I/O remapped region for scratch registers
392 * @clk: pointer to pclk clock
393 * @soc: pointer to SoC data structure
394 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone
395 * @debugfs: pointer to debugfs entry
396 * @rate: currently configured rate of pclk
397 * @suspend_mode: lowest suspend mode available
398 * @cpu_good_time: CPU power good time (in microseconds)
399 * @cpu_off_time: CPU power off time (in microsecends)
400 * @core_osc_time: core power good OSC time (in microseconds)
401 * @core_pmu_time: core power good PMU time (in microseconds)
402 * @core_off_time: core power off time (in microseconds)
403 * @corereq_high: core power request is active-high
404 * @sysclkreq_high: system clock request is active-high
405 * @combined_req: combined power request for CPU & core
406 * @cpu_pwr_good_en: CPU power good signal is enabled
407 * @lp0_vec_phys: physical base address of the LP0 warm boot code
408 * @lp0_vec_size: size of the LP0 warm boot code
409 * @powergates_available: Bitmap of available power gates
410 * @powergates_lock: mutex for power gate register access
411 * @pctl_dev: pin controller exposed by the PMC
412 * @domain: IRQ domain provided by the PMC
413 * @irq: chip implementation for the IRQ domain
414 * @clk_nb: pclk clock changes handler
415 * @core_domain_state_synced: flag marking the core domain's state as synced
416 * @core_domain_registered: flag marking the core domain as registered
417 * @wake_type_level_map: Bitmap indicating level type for non-dual edge wakes
418 * @wake_type_dual_edge_map: Bitmap indicating if a wake is dual-edge or not
419 * @wake_sw_status_map: Bitmap to hold raw status of wakes without mask
420 * @wake_cntrl_level_map: Bitmap to hold wake levels to be programmed in
421 * cntrl register associated with each wake during system suspend.
422 */
423struct tegra_pmc {
424 struct device *dev;
425 void __iomem *base;
426 void __iomem *wake;
427 void __iomem *aotag;
428 void __iomem *scratch;
429 struct clk *clk;
430 struct dentry *debugfs;
431
432 const struct tegra_pmc_soc *soc;
433 bool tz_only;
434
435 unsigned long rate;
436
437 enum tegra_suspend_mode suspend_mode;
438 u32 cpu_good_time;
439 u32 cpu_off_time;
440 u32 core_osc_time;
441 u32 core_pmu_time;
442 u32 core_off_time;
443 bool corereq_high;
444 bool sysclkreq_high;
445 bool combined_req;
446 bool cpu_pwr_good_en;
447 u32 lp0_vec_phys;
448 u32 lp0_vec_size;
449 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
450
451 struct mutex powergates_lock;
452
453 struct pinctrl_dev *pctl_dev;
454
455 struct irq_domain *domain;
456 struct irq_chip irq;
457
458 struct notifier_block clk_nb;
459
460 bool core_domain_state_synced;
461 bool core_domain_registered;
462
463 unsigned long *wake_type_level_map;
464 unsigned long *wake_type_dual_edge_map;
465 unsigned long *wake_sw_status_map;
466 unsigned long *wake_cntrl_level_map;
467 struct syscore_ops syscore;
468};
469
470static struct tegra_pmc *pmc = &(struct tegra_pmc) {
471 .base = NULL,
472 .suspend_mode = TEGRA_SUSPEND_NOT_READY,
473};
474
475static inline struct tegra_powergate *
476to_powergate(struct generic_pm_domain *domain)
477{
478 return container_of(domain, struct tegra_powergate, genpd);
479}
480
481static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)
482{
483 struct arm_smccc_res res;
484
485 if (pmc->tz_only) {
486 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
487 0, 0, 0, &res);
488 if (res.a0) {
489 if (pmc->dev)
490 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
491 __func__, res.a0);
492 else
493 pr_warn("%s(): SMC failed: %lu\n", __func__,
494 res.a0);
495 }
496
497 return res.a1;
498 }
499
500 return readl(pmc->base + offset);
501}
502
503static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,
504 unsigned long offset)
505{
506 struct arm_smccc_res res;
507
508 if (pmc->tz_only) {
509 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
510 value, 0, 0, 0, 0, &res);
511 if (res.a0) {
512 if (pmc->dev)
513 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
514 __func__, res.a0);
515 else
516 pr_warn("%s(): SMC failed: %lu\n", __func__,
517 res.a0);
518 }
519 } else {
520 writel(value, pmc->base + offset);
521 }
522}
523
524static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset)
525{
526 if (pmc->tz_only)
527 return tegra_pmc_readl(pmc, offset);
528
529 return readl(pmc->scratch + offset);
530}
531
532static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value,
533 unsigned long offset)
534{
535 if (pmc->tz_only)
536 tegra_pmc_writel(pmc, value, offset);
537 else
538 writel(value, pmc->scratch + offset);
539}
540
541/*
542 * TODO Figure out a way to call this with the struct tegra_pmc * passed in.
543 * This currently doesn't work because readx_poll_timeout() can only operate
544 * on functions that take a single argument.
545 */
546static inline bool tegra_powergate_state(int id)
547{
548 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
549 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0;
550 else
551 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0;
552}
553
554static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id)
555{
556 return (pmc->soc && pmc->soc->powergates[id]);
557}
558
559static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id)
560{
561 return test_bit(id, pmc->powergates_available);
562}
563
564static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
565{
566 unsigned int i;
567
568 if (!pmc || !pmc->soc || !name)
569 return -EINVAL;
570
571 for (i = 0; i < pmc->soc->num_powergates; i++) {
572 if (!tegra_powergate_is_valid(pmc, i))
573 continue;
574
575 if (!strcmp(name, pmc->soc->powergates[i]))
576 return i;
577 }
578
579 return -ENODEV;
580}
581
582static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id,
583 bool new_state)
584{
585 unsigned int retries = 100;
586 bool status;
587 int ret;
588
589 /*
590 * As per TRM documentation, the toggle command will be dropped by PMC
591 * if there is contention with a HW-initiated toggling (i.e. CPU core
592 * power-gated), the command should be retried in that case.
593 */
594 do {
595 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
596
597 /* wait for PMC to execute the command */
598 ret = readx_poll_timeout(tegra_powergate_state, id, status,
599 status == new_state, 1, 10);
600 } while (ret == -ETIMEDOUT && retries--);
601
602 return ret;
603}
604
605static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc)
606{
607 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START);
608}
609
610static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id,
611 bool new_state)
612{
613 bool status;
614 int err;
615
616 /* wait while PMC power gating is contended */
617 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
618 status == true, 1, 100);
619 if (err)
620 return err;
621
622 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
623
624 /* wait for PMC to accept the command */
625 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
626 status == true, 1, 100);
627 if (err)
628 return err;
629
630 /* wait for PMC to execute the command */
631 err = readx_poll_timeout(tegra_powergate_state, id, status,
632 status == new_state, 10, 100000);
633 if (err)
634 return err;
635
636 return 0;
637}
638
639/**
640 * tegra_powergate_set() - set the state of a partition
641 * @pmc: power management controller
642 * @id: partition ID
643 * @new_state: new state of the partition
644 */
645static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id,
646 bool new_state)
647{
648 int err;
649
650 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
651 return -EINVAL;
652
653 mutex_lock(&pmc->powergates_lock);
654
655 if (tegra_powergate_state(id) == new_state) {
656 mutex_unlock(&pmc->powergates_lock);
657 return 0;
658 }
659
660 err = pmc->soc->powergate_set(pmc, id, new_state);
661
662 mutex_unlock(&pmc->powergates_lock);
663
664 return err;
665}
666
667static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
668 unsigned int id)
669{
670 u32 mask;
671
672 mutex_lock(&pmc->powergates_lock);
673
674 /*
675 * On Tegra124 and later, the clamps for the GPU are controlled by a
676 * separate register (with different semantics).
677 */
678 if (id == TEGRA_POWERGATE_3D) {
679 if (pmc->soc->has_gpu_clamps) {
680 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);
681 goto out;
682 }
683 }
684
685 /*
686 * Tegra 2 has a bug where PCIE and VDE clamping masks are
687 * swapped relatively to the partition ids
688 */
689 if (id == TEGRA_POWERGATE_VDEC)
690 mask = (1 << TEGRA_POWERGATE_PCIE);
691 else if (id == TEGRA_POWERGATE_PCIE)
692 mask = (1 << TEGRA_POWERGATE_VDEC);
693 else
694 mask = (1 << id);
695
696 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);
697
698out:
699 mutex_unlock(&pmc->powergates_lock);
700
701 return 0;
702}
703
704static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg)
705{
706 unsigned long safe_rate = 100 * 1000 * 1000;
707 unsigned int i;
708 int err;
709
710 for (i = 0; i < pg->num_clks; i++) {
711 pg->clk_rates[i] = clk_get_rate(pg->clks[i]);
712
713 if (!pg->clk_rates[i]) {
714 err = -EINVAL;
715 goto out;
716 }
717
718 if (pg->clk_rates[i] <= safe_rate)
719 continue;
720
721 /*
722 * We don't know whether voltage state is okay for the
723 * current clock rate, hence it's better to temporally
724 * switch clock to a safe rate which is suitable for
725 * all voltages, before enabling the clock.
726 */
727 err = clk_set_rate(pg->clks[i], safe_rate);
728 if (err)
729 goto out;
730 }
731
732 return 0;
733
734out:
735 while (i--)
736 clk_set_rate(pg->clks[i], pg->clk_rates[i]);
737
738 return err;
739}
740
741static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg)
742{
743 unsigned int i;
744 int err;
745
746 for (i = 0; i < pg->num_clks; i++) {
747 err = clk_set_rate(pg->clks[i], pg->clk_rates[i]);
748 if (err)
749 return err;
750 }
751
752 return 0;
753}
754
755static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
756{
757 unsigned int i;
758
759 for (i = 0; i < pg->num_clks; i++)
760 clk_disable_unprepare(pg->clks[i]);
761}
762
763static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
764{
765 unsigned int i;
766 int err;
767
768 for (i = 0; i < pg->num_clks; i++) {
769 err = clk_prepare_enable(pg->clks[i]);
770 if (err)
771 goto out;
772 }
773
774 return 0;
775
776out:
777 while (i--)
778 clk_disable_unprepare(pg->clks[i]);
779
780 return err;
781}
782
783static int tegra_powergate_power_up(struct tegra_powergate *pg,
784 bool disable_clocks)
785{
786 int err;
787
788 err = reset_control_assert(pg->reset);
789 if (err)
790 return err;
791
792 usleep_range(10, 20);
793
794 err = tegra_powergate_set(pg->pmc, pg->id, true);
795 if (err < 0)
796 return err;
797
798 usleep_range(10, 20);
799
800 err = tegra_powergate_prepare_clocks(pg);
801 if (err)
802 goto powergate_off;
803
804 err = tegra_powergate_enable_clocks(pg);
805 if (err)
806 goto unprepare_clks;
807
808 usleep_range(10, 20);
809
810 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);
811 if (err)
812 goto disable_clks;
813
814 usleep_range(10, 20);
815
816 err = reset_control_deassert(pg->reset);
817 if (err)
818 goto disable_clks;
819
820 usleep_range(10, 20);
821
822 if (pg->pmc->soc->needs_mbist_war)
823 err = tegra210_clk_handle_mbist_war(pg->id);
824 if (err)
825 goto disable_clks;
826
827 if (disable_clocks)
828 tegra_powergate_disable_clocks(pg);
829
830 err = tegra_powergate_unprepare_clocks(pg);
831 if (err)
832 return err;
833
834 return 0;
835
836disable_clks:
837 tegra_powergate_disable_clocks(pg);
838 usleep_range(10, 20);
839
840unprepare_clks:
841 tegra_powergate_unprepare_clocks(pg);
842
843powergate_off:
844 tegra_powergate_set(pg->pmc, pg->id, false);
845
846 return err;
847}
848
849static int tegra_powergate_power_down(struct tegra_powergate *pg)
850{
851 int err;
852
853 err = tegra_powergate_prepare_clocks(pg);
854 if (err)
855 return err;
856
857 err = tegra_powergate_enable_clocks(pg);
858 if (err)
859 goto unprepare_clks;
860
861 usleep_range(10, 20);
862
863 err = reset_control_assert(pg->reset);
864 if (err)
865 goto disable_clks;
866
867 usleep_range(10, 20);
868
869 tegra_powergate_disable_clocks(pg);
870
871 usleep_range(10, 20);
872
873 err = tegra_powergate_set(pg->pmc, pg->id, false);
874 if (err)
875 goto assert_resets;
876
877 err = tegra_powergate_unprepare_clocks(pg);
878 if (err)
879 return err;
880
881 return 0;
882
883assert_resets:
884 tegra_powergate_enable_clocks(pg);
885 usleep_range(10, 20);
886 reset_control_deassert(pg->reset);
887 usleep_range(10, 20);
888
889disable_clks:
890 tegra_powergate_disable_clocks(pg);
891
892unprepare_clks:
893 tegra_powergate_unprepare_clocks(pg);
894
895 return err;
896}
897
898static int tegra_genpd_power_on(struct generic_pm_domain *domain)
899{
900 struct tegra_powergate *pg = to_powergate(domain);
901 struct device *dev = pg->pmc->dev;
902 int err;
903
904 err = tegra_powergate_power_up(pg, true);
905 if (err) {
906 dev_err(dev, "failed to turn on PM domain %s: %d\n",
907 pg->genpd.name, err);
908 goto out;
909 }
910
911 reset_control_release(pg->reset);
912
913out:
914 return err;
915}
916
917static int tegra_genpd_power_off(struct generic_pm_domain *domain)
918{
919 struct tegra_powergate *pg = to_powergate(domain);
920 struct device *dev = pg->pmc->dev;
921 int err;
922
923 err = reset_control_acquire(pg->reset);
924 if (err < 0) {
925 dev_err(dev, "failed to acquire resets for PM domain %s: %d\n",
926 pg->genpd.name, err);
927 return err;
928 }
929
930 err = tegra_powergate_power_down(pg);
931 if (err) {
932 dev_err(dev, "failed to turn off PM domain %s: %d\n",
933 pg->genpd.name, err);
934 reset_control_release(pg->reset);
935 }
936
937 return err;
938}
939
940/**
941 * tegra_powergate_power_on() - power on partition
942 * @id: partition ID
943 */
944int tegra_powergate_power_on(unsigned int id)
945{
946 if (!tegra_powergate_is_available(pmc, id))
947 return -EINVAL;
948
949 return tegra_powergate_set(pmc, id, true);
950}
951EXPORT_SYMBOL(tegra_powergate_power_on);
952
953/**
954 * tegra_powergate_power_off() - power off partition
955 * @id: partition ID
956 */
957int tegra_powergate_power_off(unsigned int id)
958{
959 if (!tegra_powergate_is_available(pmc, id))
960 return -EINVAL;
961
962 return tegra_powergate_set(pmc, id, false);
963}
964EXPORT_SYMBOL(tegra_powergate_power_off);
965
966/**
967 * tegra_powergate_is_powered() - check if partition is powered
968 * @pmc: power management controller
969 * @id: partition ID
970 */
971static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id)
972{
973 if (!tegra_powergate_is_valid(pmc, id))
974 return -EINVAL;
975
976 return tegra_powergate_state(id);
977}
978
979/**
980 * tegra_powergate_remove_clamping() - remove power clamps for partition
981 * @id: partition ID
982 */
983int tegra_powergate_remove_clamping(unsigned int id)
984{
985 if (!tegra_powergate_is_available(pmc, id))
986 return -EINVAL;
987
988 return __tegra_powergate_remove_clamping(pmc, id);
989}
990EXPORT_SYMBOL(tegra_powergate_remove_clamping);
991
992/**
993 * tegra_powergate_sequence_power_up() - power up partition
994 * @id: partition ID
995 * @clk: clock for partition
996 * @rst: reset for partition
997 *
998 * Must be called with clk disabled, and returns with clk enabled.
999 */
1000int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
1001 struct reset_control *rst)
1002{
1003 struct tegra_powergate *pg;
1004 int err;
1005
1006 if (!tegra_powergate_is_available(pmc, id))
1007 return -EINVAL;
1008
1009 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
1010 if (!pg)
1011 return -ENOMEM;
1012
1013 pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL);
1014 if (!pg->clk_rates) {
1015 kfree(pg->clks);
1016 return -ENOMEM;
1017 }
1018
1019 pg->id = id;
1020 pg->clks = &clk;
1021 pg->num_clks = 1;
1022 pg->reset = rst;
1023 pg->pmc = pmc;
1024
1025 err = tegra_powergate_power_up(pg, false);
1026 if (err)
1027 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,
1028 err);
1029
1030 kfree(pg->clk_rates);
1031 kfree(pg);
1032
1033 return err;
1034}
1035EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
1036
1037/**
1038 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
1039 * @pmc: power management controller
1040 * @cpuid: CPU partition ID
1041 *
1042 * Returns the partition ID corresponding to the CPU partition ID or a
1043 * negative error code on failure.
1044 */
1045static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc,
1046 unsigned int cpuid)
1047{
1048 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
1049 return pmc->soc->cpu_powergates[cpuid];
1050
1051 return -EINVAL;
1052}
1053
1054/**
1055 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
1056 * @cpuid: CPU partition ID
1057 */
1058bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
1059{
1060 int id;
1061
1062 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1063 if (id < 0)
1064 return false;
1065
1066 return tegra_powergate_is_powered(pmc, id);
1067}
1068
1069/**
1070 * tegra_pmc_cpu_power_on() - power on CPU partition
1071 * @cpuid: CPU partition ID
1072 */
1073int tegra_pmc_cpu_power_on(unsigned int cpuid)
1074{
1075 int id;
1076
1077 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1078 if (id < 0)
1079 return id;
1080
1081 return tegra_powergate_set(pmc, id, true);
1082}
1083
1084/**
1085 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
1086 * @cpuid: CPU partition ID
1087 */
1088int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
1089{
1090 int id;
1091
1092 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1093 if (id < 0)
1094 return id;
1095
1096 return tegra_powergate_remove_clamping(id);
1097}
1098
1099static void tegra_pmc_program_reboot_reason(const char *cmd)
1100{
1101 u32 value;
1102
1103 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0);
1104 value &= ~PMC_SCRATCH0_MODE_MASK;
1105
1106 if (cmd) {
1107 if (strcmp(cmd, "recovery") == 0)
1108 value |= PMC_SCRATCH0_MODE_RECOVERY;
1109
1110 if (strcmp(cmd, "bootloader") == 0)
1111 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
1112
1113 if (strcmp(cmd, "forced-recovery") == 0)
1114 value |= PMC_SCRATCH0_MODE_RCM;
1115 }
1116
1117 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);
1118}
1119
1120static int tegra_pmc_reboot_notify(struct notifier_block *this,
1121 unsigned long action, void *data)
1122{
1123 if (action == SYS_RESTART)
1124 tegra_pmc_program_reboot_reason(data);
1125
1126 return NOTIFY_DONE;
1127}
1128
1129static struct notifier_block tegra_pmc_reboot_notifier = {
1130 .notifier_call = tegra_pmc_reboot_notify,
1131};
1132
1133static void tegra_pmc_restart(void)
1134{
1135 u32 value;
1136
1137 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
1138 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1139 value |= PMC_CNTRL_MAIN_RST;
1140 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1141}
1142
1143static int tegra_pmc_restart_handler(struct sys_off_data *data)
1144{
1145 tegra_pmc_restart();
1146
1147 return NOTIFY_DONE;
1148}
1149
1150static int tegra_pmc_power_off_handler(struct sys_off_data *data)
1151{
1152 /*
1153 * Reboot Nexus 7 into special bootloader mode if USB cable is
1154 * connected in order to display battery status and power off.
1155 */
1156 if (of_machine_is_compatible("asus,grouper") &&
1157 power_supply_is_system_supplied()) {
1158 const u32 go_to_charger_mode = 0xa5a55a5a;
1159
1160 tegra_pmc_writel(pmc, go_to_charger_mode, PMC_SCRATCH37);
1161 tegra_pmc_restart();
1162 }
1163
1164 return NOTIFY_DONE;
1165}
1166
1167static int powergate_show(struct seq_file *s, void *data)
1168{
1169 unsigned int i;
1170 int status;
1171
1172 seq_printf(s, " powergate powered\n");
1173 seq_printf(s, "------------------\n");
1174
1175 for (i = 0; i < pmc->soc->num_powergates; i++) {
1176 status = tegra_powergate_is_powered(pmc, i);
1177 if (status < 0)
1178 continue;
1179
1180 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
1181 status ? "yes" : "no");
1182 }
1183
1184 return 0;
1185}
1186
1187DEFINE_SHOW_ATTRIBUTE(powergate);
1188
1189static int tegra_powergate_debugfs_init(void)
1190{
1191 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
1192 &powergate_fops);
1193 if (!pmc->debugfs)
1194 return -ENOMEM;
1195
1196 return 0;
1197}
1198
1199static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
1200 struct device_node *np)
1201{
1202 struct clk *clk;
1203 unsigned int i, count;
1204 int err;
1205
1206 count = of_clk_get_parent_count(np);
1207 if (count == 0)
1208 return -ENODEV;
1209
1210 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
1211 if (!pg->clks)
1212 return -ENOMEM;
1213
1214 pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL);
1215 if (!pg->clk_rates) {
1216 kfree(pg->clks);
1217 return -ENOMEM;
1218 }
1219
1220 for (i = 0; i < count; i++) {
1221 pg->clks[i] = of_clk_get(np, i);
1222 if (IS_ERR(pg->clks[i])) {
1223 err = PTR_ERR(pg->clks[i]);
1224 goto err;
1225 }
1226 }
1227
1228 pg->num_clks = count;
1229
1230 return 0;
1231
1232err:
1233 while (i--)
1234 clk_put(pg->clks[i]);
1235
1236 kfree(pg->clk_rates);
1237 kfree(pg->clks);
1238
1239 return err;
1240}
1241
1242static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
1243 struct device_node *np, bool off)
1244{
1245 struct device *dev = pg->pmc->dev;
1246 int err;
1247
1248 pg->reset = of_reset_control_array_get_exclusive_released(np);
1249 if (IS_ERR(pg->reset)) {
1250 err = PTR_ERR(pg->reset);
1251 dev_err(dev, "failed to get device resets: %d\n", err);
1252 return err;
1253 }
1254
1255 err = reset_control_acquire(pg->reset);
1256 if (err < 0) {
1257 pr_err("failed to acquire resets: %d\n", err);
1258 goto out;
1259 }
1260
1261 if (off) {
1262 err = reset_control_assert(pg->reset);
1263 } else {
1264 err = reset_control_deassert(pg->reset);
1265 if (err < 0)
1266 goto out;
1267
1268 reset_control_release(pg->reset);
1269 }
1270
1271out:
1272 if (err) {
1273 reset_control_release(pg->reset);
1274 reset_control_put(pg->reset);
1275 }
1276
1277 return err;
1278}
1279
1280static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
1281{
1282 struct device *dev = pmc->dev;
1283 struct tegra_powergate *pg;
1284 int id, err = 0;
1285 bool off;
1286
1287 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
1288 if (!pg)
1289 return -ENOMEM;
1290
1291 id = tegra_powergate_lookup(pmc, np->name);
1292 if (id < 0) {
1293 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id);
1294 err = -ENODEV;
1295 goto free_mem;
1296 }
1297
1298 /*
1299 * Clear the bit for this powergate so it cannot be managed
1300 * directly via the legacy APIs for controlling powergates.
1301 */
1302 clear_bit(id, pmc->powergates_available);
1303
1304 pg->id = id;
1305 pg->genpd.name = np->name;
1306 pg->genpd.power_off = tegra_genpd_power_off;
1307 pg->genpd.power_on = tegra_genpd_power_on;
1308 pg->pmc = pmc;
1309
1310 off = !tegra_powergate_is_powered(pmc, pg->id);
1311
1312 err = tegra_powergate_of_get_clks(pg, np);
1313 if (err < 0) {
1314 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err);
1315 goto set_available;
1316 }
1317
1318 err = tegra_powergate_of_get_resets(pg, np, off);
1319 if (err < 0) {
1320 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err);
1321 goto remove_clks;
1322 }
1323
1324 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
1325 if (off)
1326 WARN_ON(tegra_powergate_power_up(pg, true));
1327
1328 goto remove_resets;
1329 }
1330
1331 err = pm_genpd_init(&pg->genpd, NULL, off);
1332 if (err < 0) {
1333 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np,
1334 err);
1335 goto remove_resets;
1336 }
1337
1338 err = of_genpd_add_provider_simple(np, &pg->genpd);
1339 if (err < 0) {
1340 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n",
1341 np, err);
1342 goto remove_genpd;
1343 }
1344
1345 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name);
1346
1347 return 0;
1348
1349remove_genpd:
1350 pm_genpd_remove(&pg->genpd);
1351
1352remove_resets:
1353 reset_control_put(pg->reset);
1354
1355remove_clks:
1356 while (pg->num_clks--)
1357 clk_put(pg->clks[pg->num_clks]);
1358
1359 kfree(pg->clks);
1360
1361set_available:
1362 set_bit(id, pmc->powergates_available);
1363
1364free_mem:
1365 kfree(pg);
1366
1367 return err;
1368}
1369
1370bool tegra_pmc_core_domain_state_synced(void)
1371{
1372 return pmc->core_domain_state_synced;
1373}
1374
1375static int
1376tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain *genpd,
1377 unsigned int level)
1378{
1379 struct dev_pm_opp *opp;
1380 int err;
1381
1382 opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level);
1383 if (IS_ERR(opp)) {
1384 dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n",
1385 level, opp);
1386 return PTR_ERR(opp);
1387 }
1388
1389 mutex_lock(&pmc->powergates_lock);
1390 err = dev_pm_opp_set_opp(pmc->dev, opp);
1391 mutex_unlock(&pmc->powergates_lock);
1392
1393 dev_pm_opp_put(opp);
1394
1395 if (err) {
1396 dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n",
1397 level, err);
1398 return err;
1399 }
1400
1401 return 0;
1402}
1403
1404static unsigned int
1405tegra_pmc_core_pd_opp_to_performance_state(struct generic_pm_domain *genpd,
1406 struct dev_pm_opp *opp)
1407{
1408 return dev_pm_opp_get_level(opp);
1409}
1410
1411static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np)
1412{
1413 struct generic_pm_domain *genpd;
1414 const char *rname[] = { "core", NULL};
1415 int err;
1416
1417 genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL);
1418 if (!genpd)
1419 return -ENOMEM;
1420
1421 genpd->name = "core";
1422 genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state;
1423 genpd->opp_to_performance_state = tegra_pmc_core_pd_opp_to_performance_state;
1424
1425 err = devm_pm_opp_set_regulators(pmc->dev, rname);
1426 if (err)
1427 return dev_err_probe(pmc->dev, err,
1428 "failed to set core OPP regulator\n");
1429
1430 err = pm_genpd_init(genpd, NULL, false);
1431 if (err) {
1432 dev_err(pmc->dev, "failed to init core genpd: %d\n", err);
1433 return err;
1434 }
1435
1436 err = of_genpd_add_provider_simple(np, genpd);
1437 if (err) {
1438 dev_err(pmc->dev, "failed to add core genpd: %d\n", err);
1439 goto remove_genpd;
1440 }
1441
1442 pmc->core_domain_registered = true;
1443
1444 return 0;
1445
1446remove_genpd:
1447 pm_genpd_remove(genpd);
1448
1449 return err;
1450}
1451
1452static int tegra_powergate_init(struct tegra_pmc *pmc,
1453 struct device_node *parent)
1454{
1455 struct of_phandle_args child_args, parent_args;
1456 struct device_node *np, *child;
1457 int err = 0;
1458
1459 /*
1460 * Core power domain is the parent of powergate domains, hence it
1461 * should be registered first.
1462 */
1463 np = of_get_child_by_name(parent, "core-domain");
1464 if (np) {
1465 err = tegra_pmc_core_pd_add(pmc, np);
1466 of_node_put(np);
1467 if (err)
1468 return err;
1469 }
1470
1471 np = of_get_child_by_name(parent, "powergates");
1472 if (!np)
1473 return 0;
1474
1475 for_each_child_of_node(np, child) {
1476 err = tegra_powergate_add(pmc, child);
1477 if (err < 0) {
1478 of_node_put(child);
1479 break;
1480 }
1481
1482 if (of_parse_phandle_with_args(child, "power-domains",
1483 "#power-domain-cells",
1484 0, &parent_args))
1485 continue;
1486
1487 child_args.np = child;
1488 child_args.args_count = 0;
1489
1490 err = of_genpd_add_subdomain(&parent_args, &child_args);
1491 of_node_put(parent_args.np);
1492 if (err) {
1493 of_node_put(child);
1494 break;
1495 }
1496 }
1497
1498 of_node_put(np);
1499
1500 return err;
1501}
1502
1503static void tegra_powergate_remove(struct generic_pm_domain *genpd)
1504{
1505 struct tegra_powergate *pg = to_powergate(genpd);
1506
1507 reset_control_put(pg->reset);
1508
1509 while (pg->num_clks--)
1510 clk_put(pg->clks[pg->num_clks]);
1511
1512 kfree(pg->clks);
1513
1514 set_bit(pg->id, pmc->powergates_available);
1515
1516 kfree(pg);
1517}
1518
1519static void tegra_powergate_remove_all(struct device_node *parent)
1520{
1521 struct generic_pm_domain *genpd;
1522 struct device_node *np, *child;
1523
1524 np = of_get_child_by_name(parent, "powergates");
1525 if (!np)
1526 return;
1527
1528 for_each_child_of_node(np, child) {
1529 of_genpd_del_provider(child);
1530
1531 genpd = of_genpd_remove_last(child);
1532 if (IS_ERR(genpd))
1533 continue;
1534
1535 tegra_powergate_remove(genpd);
1536 }
1537
1538 of_node_put(np);
1539
1540 np = of_get_child_by_name(parent, "core-domain");
1541 if (np) {
1542 of_genpd_del_provider(np);
1543 of_genpd_remove_last(np);
1544 }
1545}
1546
1547static const struct tegra_io_pad_soc *
1548tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
1549{
1550 unsigned int i;
1551
1552 for (i = 0; i < pmc->soc->num_io_pads; i++)
1553 if (pmc->soc->io_pads[i].id == id)
1554 return &pmc->soc->io_pads[i];
1555
1556 return NULL;
1557}
1558
1559static int tegra_io_pad_prepare(struct tegra_pmc *pmc,
1560 const struct tegra_io_pad_soc *pad,
1561 unsigned long *request,
1562 unsigned long *status,
1563 u32 *mask)
1564{
1565 unsigned long rate, value;
1566
1567 if (pad->dpd == UINT_MAX)
1568 return -EINVAL;
1569
1570 *request = pad->request;
1571 *status = pad->status;
1572 *mask = BIT(pad->dpd);
1573
1574 if (pmc->clk) {
1575 rate = pmc->rate;
1576 if (!rate) {
1577 dev_err(pmc->dev, "failed to get clock rate\n");
1578 return -ENODEV;
1579 }
1580
1581 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);
1582
1583 /* must be at least 200 ns, in APB (PCLK) clock cycles */
1584 value = DIV_ROUND_UP(1000000000, rate);
1585 value = DIV_ROUND_UP(200, value);
1586 tegra_pmc_writel(pmc, value, SEL_DPD_TIM);
1587 }
1588
1589 return 0;
1590}
1591
1592static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset,
1593 u32 mask, u32 val, unsigned long timeout)
1594{
1595 u32 value;
1596
1597 timeout = jiffies + msecs_to_jiffies(timeout);
1598
1599 while (time_after(timeout, jiffies)) {
1600 value = tegra_pmc_readl(pmc, offset);
1601 if ((value & mask) == val)
1602 return 0;
1603
1604 usleep_range(250, 1000);
1605 }
1606
1607 return -ETIMEDOUT;
1608}
1609
1610static void tegra_io_pad_unprepare(struct tegra_pmc *pmc)
1611{
1612 if (pmc->clk)
1613 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);
1614}
1615
1616/**
1617 * tegra_io_pad_power_enable() - enable power to I/O pad
1618 * @id: Tegra I/O pad ID for which to enable power
1619 *
1620 * Returns: 0 on success or a negative error code on failure.
1621 */
1622int tegra_io_pad_power_enable(enum tegra_io_pad id)
1623{
1624 const struct tegra_io_pad_soc *pad;
1625 unsigned long request, status;
1626 u32 mask;
1627 int err;
1628
1629 pad = tegra_io_pad_find(pmc, id);
1630 if (!pad) {
1631 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1632 return -ENOENT;
1633 }
1634
1635 mutex_lock(&pmc->powergates_lock);
1636
1637 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask);
1638 if (err < 0) {
1639 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1640 goto unlock;
1641 }
1642
1643 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request);
1644
1645 err = tegra_io_pad_poll(pmc, status, mask, 0, 250);
1646 if (err < 0) {
1647 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err);
1648 goto unlock;
1649 }
1650
1651 tegra_io_pad_unprepare(pmc);
1652
1653unlock:
1654 mutex_unlock(&pmc->powergates_lock);
1655 return err;
1656}
1657EXPORT_SYMBOL(tegra_io_pad_power_enable);
1658
1659/**
1660 * tegra_io_pad_power_disable() - disable power to I/O pad
1661 * @id: Tegra I/O pad ID for which to disable power
1662 *
1663 * Returns: 0 on success or a negative error code on failure.
1664 */
1665int tegra_io_pad_power_disable(enum tegra_io_pad id)
1666{
1667 const struct tegra_io_pad_soc *pad;
1668 unsigned long request, status;
1669 u32 mask;
1670 int err;
1671
1672 pad = tegra_io_pad_find(pmc, id);
1673 if (!pad) {
1674 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1675 return -ENOENT;
1676 }
1677
1678 mutex_lock(&pmc->powergates_lock);
1679
1680 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask);
1681 if (err < 0) {
1682 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1683 goto unlock;
1684 }
1685
1686 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request);
1687
1688 err = tegra_io_pad_poll(pmc, status, mask, mask, 250);
1689 if (err < 0) {
1690 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err);
1691 goto unlock;
1692 }
1693
1694 tegra_io_pad_unprepare(pmc);
1695
1696unlock:
1697 mutex_unlock(&pmc->powergates_lock);
1698 return err;
1699}
1700EXPORT_SYMBOL(tegra_io_pad_power_disable);
1701
1702static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id)
1703{
1704 const struct tegra_io_pad_soc *pad;
1705 unsigned long status;
1706 u32 mask, value;
1707
1708 pad = tegra_io_pad_find(pmc, id);
1709 if (!pad) {
1710 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1711 return -ENOENT;
1712 }
1713
1714 if (pad->dpd == UINT_MAX)
1715 return -EINVAL;
1716
1717 status = pad->status;
1718 mask = BIT(pad->dpd);
1719
1720 value = tegra_pmc_readl(pmc, status);
1721
1722 return !(value & mask);
1723}
1724
1725static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,
1726 int voltage)
1727{
1728 const struct tegra_io_pad_soc *pad;
1729 u32 value;
1730
1731 pad = tegra_io_pad_find(pmc, id);
1732 if (!pad)
1733 return -ENOENT;
1734
1735 if (pad->voltage == UINT_MAX)
1736 return -ENOTSUPP;
1737
1738 mutex_lock(&pmc->powergates_lock);
1739
1740 if (pmc->soc->has_impl_33v_pwr) {
1741 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1742
1743 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1744 value &= ~BIT(pad->voltage);
1745 else
1746 value |= BIT(pad->voltage);
1747
1748 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);
1749 } else {
1750 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
1751 value = tegra_pmc_readl(pmc, PMC_PWR_DET);
1752 value |= BIT(pad->voltage);
1753 tegra_pmc_writel(pmc, value, PMC_PWR_DET);
1754
1755 /* update I/O voltage */
1756 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1757
1758 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1759 value &= ~BIT(pad->voltage);
1760 else
1761 value |= BIT(pad->voltage);
1762
1763 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);
1764 }
1765
1766 mutex_unlock(&pmc->powergates_lock);
1767
1768 usleep_range(100, 250);
1769
1770 return 0;
1771}
1772
1773static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id)
1774{
1775 const struct tegra_io_pad_soc *pad;
1776 u32 value;
1777
1778 pad = tegra_io_pad_find(pmc, id);
1779 if (!pad)
1780 return -ENOENT;
1781
1782 if (pad->voltage == UINT_MAX)
1783 return -ENOTSUPP;
1784
1785 if (pmc->soc->has_impl_33v_pwr)
1786 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1787 else
1788 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1789
1790 if ((value & BIT(pad->voltage)) == 0)
1791 return TEGRA_IO_PAD_VOLTAGE_1V8;
1792
1793 return TEGRA_IO_PAD_VOLTAGE_3V3;
1794}
1795
1796/**
1797 * tegra_io_rail_power_on() - enable power to I/O rail
1798 * @id: Tegra I/O pad ID for which to enable power
1799 *
1800 * See also: tegra_io_pad_power_enable()
1801 */
1802int tegra_io_rail_power_on(unsigned int id)
1803{
1804 return tegra_io_pad_power_enable(id);
1805}
1806EXPORT_SYMBOL(tegra_io_rail_power_on);
1807
1808/**
1809 * tegra_io_rail_power_off() - disable power to I/O rail
1810 * @id: Tegra I/O pad ID for which to disable power
1811 *
1812 * See also: tegra_io_pad_power_disable()
1813 */
1814int tegra_io_rail_power_off(unsigned int id)
1815{
1816 return tegra_io_pad_power_disable(id);
1817}
1818EXPORT_SYMBOL(tegra_io_rail_power_off);
1819
1820#ifdef CONFIG_PM_SLEEP
1821enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1822{
1823 return pmc->suspend_mode;
1824}
1825
1826void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1827{
1828 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1829 return;
1830
1831 pmc->suspend_mode = mode;
1832}
1833
1834void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1835{
1836 unsigned long long rate = 0;
1837 u64 ticks;
1838 u32 value;
1839
1840 switch (mode) {
1841 case TEGRA_SUSPEND_LP1:
1842 rate = 32768;
1843 break;
1844
1845 case TEGRA_SUSPEND_LP2:
1846 rate = pmc->rate;
1847 break;
1848
1849 default:
1850 break;
1851 }
1852
1853 if (WARN_ON_ONCE(rate == 0))
1854 rate = 100000000;
1855
1856 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1857 do_div(ticks, USEC_PER_SEC);
1858 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);
1859
1860 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1861 do_div(ticks, USEC_PER_SEC);
1862 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
1863
1864 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1865 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1866 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1867 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1868}
1869#endif
1870
1871static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1872{
1873 u32 value, values[2];
1874
1875 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1876 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1877 } else {
1878 switch (value) {
1879 case 0:
1880 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1881 break;
1882
1883 case 1:
1884 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1885 break;
1886
1887 case 2:
1888 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1889 break;
1890
1891 default:
1892 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1893 break;
1894 }
1895 }
1896
1897 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1898
1899 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1900 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1901
1902 pmc->cpu_good_time = value;
1903
1904 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1905 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1906
1907 pmc->cpu_off_time = value;
1908
1909 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1910 values, ARRAY_SIZE(values)))
1911 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1912
1913 pmc->core_osc_time = values[0];
1914 pmc->core_pmu_time = values[1];
1915
1916 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1917 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1918
1919 pmc->core_off_time = value;
1920
1921 pmc->corereq_high = of_property_read_bool(np,
1922 "nvidia,core-power-req-active-high");
1923
1924 pmc->sysclkreq_high = of_property_read_bool(np,
1925 "nvidia,sys-clock-req-active-high");
1926
1927 pmc->combined_req = of_property_read_bool(np,
1928 "nvidia,combined-power-req");
1929
1930 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1931 "nvidia,cpu-pwr-good-en");
1932
1933 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1934 ARRAY_SIZE(values)))
1935 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1936 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1937
1938 pmc->lp0_vec_phys = values[0];
1939 pmc->lp0_vec_size = values[1];
1940
1941 return 0;
1942}
1943
1944static int tegra_pmc_init(struct tegra_pmc *pmc)
1945{
1946 if (pmc->soc->max_wake_events > 0) {
1947 pmc->wake_type_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);
1948 if (!pmc->wake_type_level_map)
1949 return -ENOMEM;
1950
1951 pmc->wake_type_dual_edge_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);
1952 if (!pmc->wake_type_dual_edge_map)
1953 return -ENOMEM;
1954
1955 pmc->wake_sw_status_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);
1956 if (!pmc->wake_sw_status_map)
1957 return -ENOMEM;
1958
1959 pmc->wake_cntrl_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);
1960 if (!pmc->wake_cntrl_level_map)
1961 return -ENOMEM;
1962 }
1963
1964 if (pmc->soc->init)
1965 pmc->soc->init(pmc);
1966
1967 return 0;
1968}
1969
1970static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1971{
1972 static const char disabled[] = "emergency thermal reset disabled";
1973 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1974 struct device *dev = pmc->dev;
1975 struct device_node *np;
1976 u32 value, checksum;
1977
1978 if (!pmc->soc->has_tsense_reset)
1979 return;
1980
1981 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip");
1982 if (!np) {
1983 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1984 return;
1985 }
1986
1987 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1988 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1989 goto out;
1990 }
1991
1992 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1993 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1994 goto out;
1995 }
1996
1997 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) {
1998 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1999 goto out;
2000 }
2001
2002 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) {
2003 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
2004 goto out;
2005 }
2006
2007 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
2008 pinmux = 0;
2009
2010 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
2011 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
2012 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
2013
2014 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
2015 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
2016 tegra_pmc_writel(pmc, value, PMC_SCRATCH54);
2017
2018 value = PMC_SCRATCH55_RESET_TEGRA;
2019 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
2020 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
2021 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
2022
2023 /*
2024 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
2025 * contain the checksum and are currently zero, so they are not added.
2026 */
2027 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
2028 + ((value >> 24) & 0xff);
2029 checksum &= 0xff;
2030 checksum = 0x100 - checksum;
2031
2032 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
2033
2034 tegra_pmc_writel(pmc, value, PMC_SCRATCH55);
2035
2036 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
2037 value |= PMC_SENSOR_CTRL_ENABLE_RST;
2038 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
2039
2040 dev_info(pmc->dev, "emergency thermal reset enabled\n");
2041
2042out:
2043 of_node_put(np);
2044}
2045
2046static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev)
2047{
2048 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2049
2050 return pmc->soc->num_io_pads;
2051}
2052
2053static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl,
2054 unsigned int group)
2055{
2056 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl);
2057
2058 return pmc->soc->io_pads[group].name;
2059}
2060
2061static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev,
2062 unsigned int group,
2063 const unsigned int **pins,
2064 unsigned int *num_pins)
2065{
2066 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2067
2068 *pins = &pmc->soc->io_pads[group].id;
2069 *num_pins = 1;
2070
2071 return 0;
2072}
2073
2074static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = {
2075 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count,
2076 .get_group_name = tegra_io_pad_pinctrl_get_group_name,
2077 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins,
2078 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
2079 .dt_free_map = pinconf_generic_dt_free_map,
2080};
2081
2082static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev,
2083 unsigned int pin, unsigned long *config)
2084{
2085 enum pin_config_param param = pinconf_to_config_param(*config);
2086 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2087 const struct tegra_io_pad_soc *pad;
2088 int ret;
2089 u32 arg;
2090
2091 pad = tegra_io_pad_find(pmc, pin);
2092 if (!pad)
2093 return -EINVAL;
2094
2095 switch (param) {
2096 case PIN_CONFIG_POWER_SOURCE:
2097 ret = tegra_io_pad_get_voltage(pmc, pad->id);
2098 if (ret < 0)
2099 return ret;
2100
2101 arg = ret;
2102 break;
2103
2104 case PIN_CONFIG_MODE_LOW_POWER:
2105 ret = tegra_io_pad_is_powered(pmc, pad->id);
2106 if (ret < 0)
2107 return ret;
2108
2109 arg = !ret;
2110 break;
2111
2112 default:
2113 return -EINVAL;
2114 }
2115
2116 *config = pinconf_to_config_packed(param, arg);
2117
2118 return 0;
2119}
2120
2121static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev,
2122 unsigned int pin, unsigned long *configs,
2123 unsigned int num_configs)
2124{
2125 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2126 const struct tegra_io_pad_soc *pad;
2127 enum pin_config_param param;
2128 unsigned int i;
2129 int err;
2130 u32 arg;
2131
2132 pad = tegra_io_pad_find(pmc, pin);
2133 if (!pad)
2134 return -EINVAL;
2135
2136 for (i = 0; i < num_configs; ++i) {
2137 param = pinconf_to_config_param(configs[i]);
2138 arg = pinconf_to_config_argument(configs[i]);
2139
2140 switch (param) {
2141 case PIN_CONFIG_MODE_LOW_POWER:
2142 if (arg)
2143 err = tegra_io_pad_power_disable(pad->id);
2144 else
2145 err = tegra_io_pad_power_enable(pad->id);
2146 if (err)
2147 return err;
2148 break;
2149 case PIN_CONFIG_POWER_SOURCE:
2150 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 &&
2151 arg != TEGRA_IO_PAD_VOLTAGE_3V3)
2152 return -EINVAL;
2153 err = tegra_io_pad_set_voltage(pmc, pad->id, arg);
2154 if (err)
2155 return err;
2156 break;
2157 default:
2158 return -EINVAL;
2159 }
2160 }
2161
2162 return 0;
2163}
2164
2165static const struct pinconf_ops tegra_io_pad_pinconf_ops = {
2166 .pin_config_get = tegra_io_pad_pinconf_get,
2167 .pin_config_set = tegra_io_pad_pinconf_set,
2168 .is_generic = true,
2169};
2170
2171static struct pinctrl_desc tegra_pmc_pctl_desc = {
2172 .pctlops = &tegra_io_pad_pinctrl_ops,
2173 .confops = &tegra_io_pad_pinconf_ops,
2174};
2175
2176static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc)
2177{
2178 int err;
2179
2180 if (!pmc->soc->num_pin_descs)
2181 return 0;
2182
2183 tegra_pmc_pctl_desc.name = dev_name(pmc->dev);
2184 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs;
2185 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs;
2186
2187 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc,
2188 pmc);
2189 if (IS_ERR(pmc->pctl_dev)) {
2190 err = PTR_ERR(pmc->pctl_dev);
2191 dev_err(pmc->dev, "failed to register pin controller: %d\n",
2192 err);
2193 return err;
2194 }
2195
2196 return 0;
2197}
2198
2199static ssize_t reset_reason_show(struct device *dev,
2200 struct device_attribute *attr, char *buf)
2201{
2202 u32 value;
2203
2204 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
2205 value &= pmc->soc->regs->rst_source_mask;
2206 value >>= pmc->soc->regs->rst_source_shift;
2207
2208 if (WARN_ON(value >= pmc->soc->num_reset_sources))
2209 return sprintf(buf, "%s\n", "UNKNOWN");
2210
2211 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);
2212}
2213
2214static DEVICE_ATTR_RO(reset_reason);
2215
2216static ssize_t reset_level_show(struct device *dev,
2217 struct device_attribute *attr, char *buf)
2218{
2219 u32 value;
2220
2221 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
2222 value &= pmc->soc->regs->rst_level_mask;
2223 value >>= pmc->soc->regs->rst_level_shift;
2224
2225 if (WARN_ON(value >= pmc->soc->num_reset_levels))
2226 return sprintf(buf, "%s\n", "UNKNOWN");
2227
2228 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);
2229}
2230
2231static DEVICE_ATTR_RO(reset_level);
2232
2233static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc)
2234{
2235 struct device *dev = pmc->dev;
2236 int err = 0;
2237
2238 if (pmc->soc->reset_sources) {
2239 err = device_create_file(dev, &dev_attr_reset_reason);
2240 if (err < 0)
2241 dev_warn(dev,
2242 "failed to create attr \"reset_reason\": %d\n",
2243 err);
2244 }
2245
2246 if (pmc->soc->reset_levels) {
2247 err = device_create_file(dev, &dev_attr_reset_level);
2248 if (err < 0)
2249 dev_warn(dev,
2250 "failed to create attr \"reset_level\": %d\n",
2251 err);
2252 }
2253}
2254
2255static int tegra_pmc_irq_translate(struct irq_domain *domain,
2256 struct irq_fwspec *fwspec,
2257 unsigned long *hwirq,
2258 unsigned int *type)
2259{
2260 if (WARN_ON(fwspec->param_count < 2))
2261 return -EINVAL;
2262
2263 *hwirq = fwspec->param[0];
2264 *type = fwspec->param[1];
2265
2266 return 0;
2267}
2268
2269static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq,
2270 unsigned int num_irqs, void *data)
2271{
2272 struct tegra_pmc *pmc = domain->host_data;
2273 const struct tegra_pmc_soc *soc = pmc->soc;
2274 struct irq_fwspec *fwspec = data;
2275 unsigned int i;
2276 int err = 0;
2277
2278 if (WARN_ON(num_irqs > 1))
2279 return -EINVAL;
2280
2281 for (i = 0; i < soc->num_wake_events; i++) {
2282 const struct tegra_wake_event *event = &soc->wake_events[i];
2283
2284 /* IRQ and simple wake events */
2285 if (fwspec->param_count == 2) {
2286 struct irq_fwspec spec;
2287
2288 if (event->id != fwspec->param[0])
2289 continue;
2290
2291 err = irq_domain_set_hwirq_and_chip(domain, virq,
2292 event->id,
2293 &pmc->irq, pmc);
2294 if (err < 0)
2295 break;
2296
2297 /* simple hierarchies stop at the PMC level */
2298 if (event->irq == 0) {
2299 err = irq_domain_disconnect_hierarchy(domain->parent, virq);
2300 break;
2301 }
2302
2303 spec.fwnode = &pmc->dev->of_node->fwnode;
2304 spec.param_count = 3;
2305 spec.param[0] = GIC_SPI;
2306 spec.param[1] = event->irq;
2307 spec.param[2] = fwspec->param[1];
2308
2309 err = irq_domain_alloc_irqs_parent(domain, virq,
2310 num_irqs, &spec);
2311
2312 break;
2313 }
2314
2315 /* GPIO wake events */
2316 if (fwspec->param_count == 3) {
2317 if (event->gpio.instance != fwspec->param[0] ||
2318 event->gpio.pin != fwspec->param[1])
2319 continue;
2320
2321 err = irq_domain_set_hwirq_and_chip(domain, virq,
2322 event->id,
2323 &pmc->irq, pmc);
2324
2325 /* GPIO hierarchies stop at the PMC level */
2326 if (!err && domain->parent)
2327 err = irq_domain_disconnect_hierarchy(domain->parent,
2328 virq);
2329 break;
2330 }
2331 }
2332
2333 /* If there is no wake-up event, there is no PMC mapping */
2334 if (i == soc->num_wake_events)
2335 err = irq_domain_disconnect_hierarchy(domain, virq);
2336
2337 return err;
2338}
2339
2340static const struct irq_domain_ops tegra_pmc_irq_domain_ops = {
2341 .translate = tegra_pmc_irq_translate,
2342 .alloc = tegra_pmc_irq_alloc,
2343};
2344
2345static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2346{
2347 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2348 unsigned int offset, bit;
2349 u32 value;
2350
2351 offset = data->hwirq / 32;
2352 bit = data->hwirq % 32;
2353
2354 /* clear wake status */
2355 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);
2356 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);
2357
2358 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);
2359 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);
2360
2361 /* enable PMC wake */
2362 if (data->hwirq >= 32)
2363 offset = PMC_WAKE2_MASK;
2364 else
2365 offset = PMC_WAKE_MASK;
2366
2367 value = tegra_pmc_readl(pmc, offset);
2368
2369 if (on)
2370 value |= BIT(bit);
2371 else
2372 value &= ~BIT(bit);
2373
2374 tegra_pmc_writel(pmc, value, offset);
2375
2376 return 0;
2377}
2378
2379static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2380{
2381 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2382 unsigned int offset, bit;
2383 u32 value;
2384
2385 offset = data->hwirq / 32;
2386 bit = data->hwirq % 32;
2387
2388 if (data->hwirq >= 32)
2389 offset = PMC_WAKE2_LEVEL;
2390 else
2391 offset = PMC_WAKE_LEVEL;
2392
2393 value = tegra_pmc_readl(pmc, offset);
2394
2395 switch (type) {
2396 case IRQ_TYPE_EDGE_RISING:
2397 case IRQ_TYPE_LEVEL_HIGH:
2398 value |= BIT(bit);
2399 break;
2400
2401 case IRQ_TYPE_EDGE_FALLING:
2402 case IRQ_TYPE_LEVEL_LOW:
2403 value &= ~BIT(bit);
2404 break;
2405
2406 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2407 value ^= BIT(bit);
2408 break;
2409
2410 default:
2411 return -EINVAL;
2412 }
2413
2414 tegra_pmc_writel(pmc, value, offset);
2415
2416 return 0;
2417}
2418
2419static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2420{
2421 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2422 unsigned int offset, bit;
2423 u32 value;
2424
2425 offset = data->hwirq / 32;
2426 bit = data->hwirq % 32;
2427
2428 /* clear wake status */
2429 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));
2430
2431 /* route wake to tier 2 */
2432 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2433
2434 if (!on)
2435 value &= ~(1 << bit);
2436 else
2437 value |= 1 << bit;
2438
2439 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2440
2441 /* enable wakeup event */
2442 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));
2443
2444 return 0;
2445}
2446
2447static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2448{
2449 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2450 u32 value;
2451
2452 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2453
2454 switch (type) {
2455 case IRQ_TYPE_EDGE_RISING:
2456 case IRQ_TYPE_LEVEL_HIGH:
2457 value |= WAKE_AOWAKE_CNTRL_LEVEL;
2458 set_bit(data->hwirq, pmc->wake_type_level_map);
2459 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map);
2460 break;
2461
2462 case IRQ_TYPE_EDGE_FALLING:
2463 case IRQ_TYPE_LEVEL_LOW:
2464 value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
2465 clear_bit(data->hwirq, pmc->wake_type_level_map);
2466 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map);
2467 break;
2468
2469 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2470 value ^= WAKE_AOWAKE_CNTRL_LEVEL;
2471 clear_bit(data->hwirq, pmc->wake_type_level_map);
2472 set_bit(data->hwirq, pmc->wake_type_dual_edge_map);
2473 break;
2474
2475 default:
2476 return -EINVAL;
2477 }
2478
2479 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2480
2481 return 0;
2482}
2483
2484static void tegra_irq_mask_parent(struct irq_data *data)
2485{
2486 if (data->parent_data)
2487 irq_chip_mask_parent(data);
2488}
2489
2490static void tegra_irq_unmask_parent(struct irq_data *data)
2491{
2492 if (data->parent_data)
2493 irq_chip_unmask_parent(data);
2494}
2495
2496static void tegra_irq_eoi_parent(struct irq_data *data)
2497{
2498 if (data->parent_data)
2499 irq_chip_eoi_parent(data);
2500}
2501
2502static int tegra_irq_set_affinity_parent(struct irq_data *data,
2503 const struct cpumask *dest,
2504 bool force)
2505{
2506 if (data->parent_data)
2507 return irq_chip_set_affinity_parent(data, dest, force);
2508
2509 return -EINVAL;
2510}
2511
2512static int tegra_pmc_irq_init(struct tegra_pmc *pmc)
2513{
2514 struct irq_domain *parent = NULL;
2515 struct device_node *np;
2516
2517 np = of_irq_find_parent(pmc->dev->of_node);
2518 if (np) {
2519 parent = irq_find_host(np);
2520 of_node_put(np);
2521 }
2522
2523 if (!parent)
2524 return 0;
2525
2526 pmc->irq.name = dev_name(pmc->dev);
2527 pmc->irq.irq_mask = tegra_irq_mask_parent;
2528 pmc->irq.irq_unmask = tegra_irq_unmask_parent;
2529 pmc->irq.irq_eoi = tegra_irq_eoi_parent;
2530 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent;
2531 pmc->irq.irq_set_type = pmc->soc->irq_set_type;
2532 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake;
2533
2534 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node,
2535 &tegra_pmc_irq_domain_ops, pmc);
2536 if (!pmc->domain) {
2537 dev_err(pmc->dev, "failed to allocate domain\n");
2538 return -ENOMEM;
2539 }
2540
2541 return 0;
2542}
2543
2544static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
2545 unsigned long action, void *ptr)
2546{
2547 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb);
2548 struct clk_notifier_data *data = ptr;
2549
2550 switch (action) {
2551 case PRE_RATE_CHANGE:
2552 mutex_lock(&pmc->powergates_lock);
2553 break;
2554
2555 case POST_RATE_CHANGE:
2556 pmc->rate = data->new_rate;
2557 fallthrough;
2558
2559 case ABORT_RATE_CHANGE:
2560 mutex_unlock(&pmc->powergates_lock);
2561 break;
2562
2563 default:
2564 WARN_ON_ONCE(1);
2565 return notifier_from_errno(-EINVAL);
2566 }
2567
2568 return NOTIFY_OK;
2569}
2570
2571static void pmc_clk_fence_udelay(u32 offset)
2572{
2573 tegra_pmc_readl(pmc, offset);
2574 /* pmc clk propagation delay 2 us */
2575 udelay(2);
2576}
2577
2578static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
2579{
2580 struct pmc_clk *clk = to_pmc_clk(hw);
2581 u32 val;
2582
2583 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
2584 val &= PMC_CLK_OUT_MUX_MASK;
2585
2586 return val;
2587}
2588
2589static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
2590{
2591 struct pmc_clk *clk = to_pmc_clk(hw);
2592 u32 val;
2593
2594 val = tegra_pmc_readl(pmc, clk->offs);
2595 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift);
2596 val |= index << clk->mux_shift;
2597 tegra_pmc_writel(pmc, val, clk->offs);
2598 pmc_clk_fence_udelay(clk->offs);
2599
2600 return 0;
2601}
2602
2603static int pmc_clk_is_enabled(struct clk_hw *hw)
2604{
2605 struct pmc_clk *clk = to_pmc_clk(hw);
2606 u32 val;
2607
2608 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift);
2609
2610 return val ? 1 : 0;
2611}
2612
2613static void pmc_clk_set_state(unsigned long offs, u32 shift, int state)
2614{
2615 u32 val;
2616
2617 val = tegra_pmc_readl(pmc, offs);
2618 val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
2619 tegra_pmc_writel(pmc, val, offs);
2620 pmc_clk_fence_udelay(offs);
2621}
2622
2623static int pmc_clk_enable(struct clk_hw *hw)
2624{
2625 struct pmc_clk *clk = to_pmc_clk(hw);
2626
2627 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1);
2628
2629 return 0;
2630}
2631
2632static void pmc_clk_disable(struct clk_hw *hw)
2633{
2634 struct pmc_clk *clk = to_pmc_clk(hw);
2635
2636 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0);
2637}
2638
2639static const struct clk_ops pmc_clk_ops = {
2640 .get_parent = pmc_clk_mux_get_parent,
2641 .set_parent = pmc_clk_mux_set_parent,
2642 .determine_rate = __clk_mux_determine_rate,
2643 .is_enabled = pmc_clk_is_enabled,
2644 .enable = pmc_clk_enable,
2645 .disable = pmc_clk_disable,
2646};
2647
2648static struct clk *
2649tegra_pmc_clk_out_register(struct tegra_pmc *pmc,
2650 const struct pmc_clk_init_data *data,
2651 unsigned long offset)
2652{
2653 struct clk_init_data init;
2654 struct pmc_clk *pmc_clk;
2655
2656 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL);
2657 if (!pmc_clk)
2658 return ERR_PTR(-ENOMEM);
2659
2660 init.name = data->name;
2661 init.ops = &pmc_clk_ops;
2662 init.parent_names = data->parents;
2663 init.num_parents = data->num_parents;
2664 init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
2665 CLK_SET_PARENT_GATE;
2666
2667 pmc_clk->hw.init = &init;
2668 pmc_clk->offs = offset;
2669 pmc_clk->mux_shift = data->mux_shift;
2670 pmc_clk->force_en_shift = data->force_en_shift;
2671
2672 return clk_register(NULL, &pmc_clk->hw);
2673}
2674
2675static int pmc_clk_gate_is_enabled(struct clk_hw *hw)
2676{
2677 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2678
2679 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
2680}
2681
2682static int pmc_clk_gate_enable(struct clk_hw *hw)
2683{
2684 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2685
2686 pmc_clk_set_state(gate->offs, gate->shift, 1);
2687
2688 return 0;
2689}
2690
2691static void pmc_clk_gate_disable(struct clk_hw *hw)
2692{
2693 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2694
2695 pmc_clk_set_state(gate->offs, gate->shift, 0);
2696}
2697
2698static const struct clk_ops pmc_clk_gate_ops = {
2699 .is_enabled = pmc_clk_gate_is_enabled,
2700 .enable = pmc_clk_gate_enable,
2701 .disable = pmc_clk_gate_disable,
2702};
2703
2704static struct clk *
2705tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name,
2706 const char *parent_name, unsigned long offset,
2707 u32 shift)
2708{
2709 struct clk_init_data init;
2710 struct pmc_clk_gate *gate;
2711
2712 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL);
2713 if (!gate)
2714 return ERR_PTR(-ENOMEM);
2715
2716 init.name = name;
2717 init.ops = &pmc_clk_gate_ops;
2718 init.parent_names = &parent_name;
2719 init.num_parents = 1;
2720 init.flags = 0;
2721
2722 gate->hw.init = &init;
2723 gate->offs = offset;
2724 gate->shift = shift;
2725
2726 return clk_register(NULL, &gate->hw);
2727}
2728
2729static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
2730 struct device_node *np)
2731{
2732 struct clk *clk;
2733 struct clk_onecell_data *clk_data;
2734 unsigned int num_clks;
2735 int i, err;
2736
2737 num_clks = pmc->soc->num_pmc_clks;
2738 if (pmc->soc->has_blink_output)
2739 num_clks += 1;
2740
2741 if (!num_clks)
2742 return;
2743
2744 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL);
2745 if (!clk_data)
2746 return;
2747
2748 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX,
2749 sizeof(*clk_data->clks), GFP_KERNEL);
2750 if (!clk_data->clks)
2751 return;
2752
2753 clk_data->clk_num = TEGRA_PMC_CLK_MAX;
2754
2755 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)
2756 clk_data->clks[i] = ERR_PTR(-ENOENT);
2757
2758 for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
2759 const struct pmc_clk_init_data *data;
2760
2761 data = pmc->soc->pmc_clks_data + i;
2762
2763 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL);
2764 if (IS_ERR(clk)) {
2765 dev_warn(pmc->dev, "unable to register clock %s: %d\n",
2766 data->name, PTR_ERR_OR_ZERO(clk));
2767 return;
2768 }
2769
2770 err = clk_register_clkdev(clk, data->name, NULL);
2771 if (err) {
2772 dev_warn(pmc->dev,
2773 "unable to register %s clock lookup: %d\n",
2774 data->name, err);
2775 return;
2776 }
2777
2778 clk_data->clks[data->clk_id] = clk;
2779 }
2780
2781 if (pmc->soc->has_blink_output) {
2782 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER);
2783 clk = tegra_pmc_clk_gate_register(pmc,
2784 "pmc_blink_override",
2785 "clk_32k",
2786 PMC_DPD_PADS_ORIDE,
2787 PMC_DPD_PADS_ORIDE_BLINK);
2788 if (IS_ERR(clk)) {
2789 dev_warn(pmc->dev,
2790 "unable to register pmc_blink_override: %d\n",
2791 PTR_ERR_OR_ZERO(clk));
2792 return;
2793 }
2794
2795 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink",
2796 "pmc_blink_override",
2797 PMC_CNTRL,
2798 PMC_CNTRL_BLINK_EN);
2799 if (IS_ERR(clk)) {
2800 dev_warn(pmc->dev,
2801 "unable to register pmc_blink: %d\n",
2802 PTR_ERR_OR_ZERO(clk));
2803 return;
2804 }
2805
2806 err = clk_register_clkdev(clk, "pmc_blink", NULL);
2807 if (err) {
2808 dev_warn(pmc->dev,
2809 "unable to register pmc_blink lookup: %d\n",
2810 err);
2811 return;
2812 }
2813
2814 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk;
2815 }
2816
2817 err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
2818 if (err)
2819 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n",
2820 err);
2821}
2822
2823static const struct regmap_range pmc_usb_sleepwalk_ranges[] = {
2824 regmap_reg_range(PMC_USB_DEBOUNCE_DEL, PMC_USB_AO),
2825 regmap_reg_range(PMC_UTMIP_UHSIC_TRIGGERS, PMC_UTMIP_UHSIC_SAVED_STATE),
2826 regmap_reg_range(PMC_UTMIP_TERM_PAD_CFG, PMC_UTMIP_UHSIC_FAKE),
2827 regmap_reg_range(PMC_UTMIP_UHSIC_LINE_WAKEUP, PMC_UTMIP_UHSIC_LINE_WAKEUP),
2828 regmap_reg_range(PMC_UTMIP_BIAS_MASTER_CNTRL, PMC_UTMIP_MASTER_CONFIG),
2829 regmap_reg_range(PMC_UTMIP_UHSIC2_TRIGGERS, PMC_UTMIP_MASTER2_CONFIG),
2830 regmap_reg_range(PMC_UTMIP_PAD_CFG0, PMC_UTMIP_UHSIC_SLEEP_CFG1),
2831 regmap_reg_range(PMC_UTMIP_SLEEPWALK_P3, PMC_UTMIP_SLEEPWALK_P3),
2832};
2833
2834static const struct regmap_access_table pmc_usb_sleepwalk_table = {
2835 .yes_ranges = pmc_usb_sleepwalk_ranges,
2836 .n_yes_ranges = ARRAY_SIZE(pmc_usb_sleepwalk_ranges),
2837};
2838
2839static int tegra_pmc_regmap_readl(void *context, unsigned int offset, unsigned int *value)
2840{
2841 struct tegra_pmc *pmc = context;
2842
2843 *value = tegra_pmc_readl(pmc, offset);
2844 return 0;
2845}
2846
2847static int tegra_pmc_regmap_writel(void *context, unsigned int offset, unsigned int value)
2848{
2849 struct tegra_pmc *pmc = context;
2850
2851 tegra_pmc_writel(pmc, value, offset);
2852 return 0;
2853}
2854
2855static const struct regmap_config usb_sleepwalk_regmap_config = {
2856 .name = "usb_sleepwalk",
2857 .reg_bits = 32,
2858 .val_bits = 32,
2859 .reg_stride = 4,
2860 .fast_io = true,
2861 .rd_table = &pmc_usb_sleepwalk_table,
2862 .wr_table = &pmc_usb_sleepwalk_table,
2863 .reg_read = tegra_pmc_regmap_readl,
2864 .reg_write = tegra_pmc_regmap_writel,
2865};
2866
2867static int tegra_pmc_regmap_init(struct tegra_pmc *pmc)
2868{
2869 struct regmap *regmap;
2870 int err;
2871
2872 if (pmc->soc->has_usb_sleepwalk) {
2873 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config);
2874 if (IS_ERR(regmap)) {
2875 err = PTR_ERR(regmap);
2876 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err);
2877 return err;
2878 }
2879 }
2880
2881 return 0;
2882}
2883
2884static void tegra_pmc_reset_suspend_mode(void *data)
2885{
2886 pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY;
2887}
2888
2889static int tegra_pmc_probe(struct platform_device *pdev)
2890{
2891 void __iomem *base;
2892 struct resource *res;
2893 int err;
2894
2895 /*
2896 * Early initialisation should have configured an initial
2897 * register mapping and setup the soc data pointer. If these
2898 * are not valid then something went badly wrong!
2899 */
2900 if (WARN_ON(!pmc->base || !pmc->soc))
2901 return -ENODEV;
2902
2903 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
2904 if (err < 0)
2905 return err;
2906
2907 err = devm_add_action_or_reset(&pdev->dev, tegra_pmc_reset_suspend_mode,
2908 NULL);
2909 if (err)
2910 return err;
2911
2912 /* take over the memory region from the early initialization */
2913 base = devm_platform_ioremap_resource(pdev, 0);
2914 if (IS_ERR(base))
2915 return PTR_ERR(base);
2916
2917 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake");
2918 if (res) {
2919 pmc->wake = devm_ioremap_resource(&pdev->dev, res);
2920 if (IS_ERR(pmc->wake))
2921 return PTR_ERR(pmc->wake);
2922 } else {
2923 pmc->wake = base;
2924 }
2925
2926 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
2927 if (res) {
2928 pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
2929 if (IS_ERR(pmc->aotag))
2930 return PTR_ERR(pmc->aotag);
2931 } else {
2932 pmc->aotag = base;
2933 }
2934
2935 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch");
2936 if (res) {
2937 pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
2938 if (IS_ERR(pmc->scratch))
2939 return PTR_ERR(pmc->scratch);
2940 } else {
2941 pmc->scratch = base;
2942 }
2943
2944 pmc->clk = devm_clk_get_optional(&pdev->dev, "pclk");
2945 if (IS_ERR(pmc->clk))
2946 return dev_err_probe(&pdev->dev, PTR_ERR(pmc->clk),
2947 "failed to get pclk\n");
2948
2949 /*
2950 * PMC should be last resort for restarting since it soft-resets
2951 * CPU without resetting everything else.
2952 */
2953 err = devm_register_reboot_notifier(&pdev->dev,
2954 &tegra_pmc_reboot_notifier);
2955 if (err) {
2956 dev_err(&pdev->dev, "unable to register reboot notifier, %d\n",
2957 err);
2958 return err;
2959 }
2960
2961 err = devm_register_sys_off_handler(&pdev->dev,
2962 SYS_OFF_MODE_RESTART,
2963 SYS_OFF_PRIO_LOW,
2964 tegra_pmc_restart_handler, NULL);
2965 if (err) {
2966 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n",
2967 err);
2968 return err;
2969 }
2970
2971 /*
2972 * PMC should be primary power-off method if it soft-resets CPU,
2973 * asking bootloader to shutdown hardware.
2974 */
2975 err = devm_register_sys_off_handler(&pdev->dev,
2976 SYS_OFF_MODE_POWER_OFF,
2977 SYS_OFF_PRIO_FIRMWARE,
2978 tegra_pmc_power_off_handler, NULL);
2979 if (err) {
2980 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n",
2981 err);
2982 return err;
2983 }
2984
2985 /*
2986 * PCLK clock rate can't be retrieved using CLK API because it
2987 * causes lockup if CPU enters LP2 idle state from some other
2988 * CLK notifier, hence we're caching the rate's value locally.
2989 */
2990 if (pmc->clk) {
2991 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb;
2992 err = clk_notifier_register(pmc->clk, &pmc->clk_nb);
2993 if (err) {
2994 dev_err(&pdev->dev,
2995 "failed to register clk notifier\n");
2996 return err;
2997 }
2998
2999 pmc->rate = clk_get_rate(pmc->clk);
3000 }
3001
3002 pmc->dev = &pdev->dev;
3003
3004 err = tegra_pmc_init(pmc);
3005 if (err < 0) {
3006 dev_err(&pdev->dev, "failed to initialize PMC: %d\n", err);
3007 return err;
3008 }
3009
3010 tegra_pmc_init_tsense_reset(pmc);
3011
3012 tegra_pmc_reset_sysfs_init(pmc);
3013
3014 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
3015 err = tegra_powergate_debugfs_init();
3016 if (err < 0)
3017 goto cleanup_sysfs;
3018 }
3019
3020 err = tegra_pmc_pinctrl_init(pmc);
3021 if (err)
3022 goto cleanup_debugfs;
3023
3024 err = tegra_pmc_regmap_init(pmc);
3025 if (err < 0)
3026 goto cleanup_debugfs;
3027
3028 err = tegra_powergate_init(pmc, pdev->dev.of_node);
3029 if (err < 0)
3030 goto cleanup_powergates;
3031
3032 err = tegra_pmc_irq_init(pmc);
3033 if (err < 0)
3034 goto cleanup_powergates;
3035
3036 mutex_lock(&pmc->powergates_lock);
3037 iounmap(pmc->base);
3038 pmc->base = base;
3039 mutex_unlock(&pmc->powergates_lock);
3040
3041 tegra_pmc_clock_register(pmc, pdev->dev.of_node);
3042 platform_set_drvdata(pdev, pmc);
3043 tegra_pm_init_suspend();
3044
3045 return 0;
3046
3047cleanup_powergates:
3048 tegra_powergate_remove_all(pdev->dev.of_node);
3049cleanup_debugfs:
3050 debugfs_remove(pmc->debugfs);
3051cleanup_sysfs:
3052 device_remove_file(&pdev->dev, &dev_attr_reset_reason);
3053 device_remove_file(&pdev->dev, &dev_attr_reset_level);
3054 clk_notifier_unregister(pmc->clk, &pmc->clk_nb);
3055
3056 return err;
3057}
3058
3059/*
3060 * Ensures that sufficient time is passed for a register write to
3061 * serialize into the 32KHz domain.
3062 */
3063static void wke_32kwritel(struct tegra_pmc *pmc, u32 value, unsigned int offset)
3064{
3065 writel(value, pmc->wake + offset);
3066 udelay(130);
3067}
3068
3069static void wke_write_wake_level(struct tegra_pmc *pmc, int wake, int level)
3070{
3071 unsigned int offset = WAKE_AOWAKE_CNTRL(wake);
3072 u32 value;
3073
3074 value = readl(pmc->wake + offset);
3075 if (level)
3076 value |= WAKE_AOWAKE_CNTRL_LEVEL;
3077 else
3078 value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
3079
3080 writel(value, pmc->wake + offset);
3081}
3082
3083static void wke_write_wake_levels(struct tegra_pmc *pmc)
3084{
3085 unsigned int i;
3086
3087 for (i = 0; i < pmc->soc->max_wake_events; i++)
3088 wke_write_wake_level(pmc, i, test_bit(i, pmc->wake_cntrl_level_map));
3089}
3090
3091static void wke_clear_sw_wake_status(struct tegra_pmc *pmc)
3092{
3093 wke_32kwritel(pmc, 1, WAKE_AOWAKE_SW_STATUS_W_0);
3094}
3095
3096static void wke_read_sw_wake_status(struct tegra_pmc *pmc)
3097{
3098 unsigned long status;
3099 unsigned int wake, i;
3100
3101 for (i = 0; i < pmc->soc->max_wake_events; i++)
3102 wke_write_wake_level(pmc, i, 0);
3103
3104 wke_clear_sw_wake_status(pmc);
3105
3106 wke_32kwritel(pmc, 1, WAKE_LATCH_SW);
3107
3108 /*
3109 * WAKE_AOWAKE_SW_STATUS is edge triggered, so in order to
3110 * obtain the current status of the input wake signals, change
3111 * the polarity of the wake level from 0->1 while latching to force
3112 * a positive edge if the sampled signal is '1'.
3113 */
3114 for (i = 0; i < pmc->soc->max_wake_events; i++)
3115 wke_write_wake_level(pmc, i, 1);
3116
3117 /*
3118 * Wait for the update to be synced into the 32kHz domain,
3119 * and let enough time lapse, so that the wake signals have time to
3120 * be sampled.
3121 */
3122 udelay(300);
3123
3124 wke_32kwritel(pmc, 0, WAKE_LATCH_SW);
3125
3126 bitmap_zero(pmc->wake_sw_status_map, pmc->soc->max_wake_events);
3127
3128 for (i = 0; i < pmc->soc->max_wake_vectors; i++) {
3129 status = readl(pmc->wake + WAKE_AOWAKE_SW_STATUS(i));
3130
3131 for_each_set_bit(wake, &status, 32)
3132 set_bit(wake + (i * 32), pmc->wake_sw_status_map);
3133 }
3134}
3135
3136static void wke_clear_wake_status(struct tegra_pmc *pmc)
3137{
3138 unsigned long status;
3139 unsigned int i, wake;
3140 u32 mask;
3141
3142 for (i = 0; i < pmc->soc->max_wake_vectors; i++) {
3143 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i));
3144 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask;
3145
3146 for_each_set_bit(wake, &status, 32)
3147 wke_32kwritel(pmc, 0x1, WAKE_AOWAKE_STATUS_W((i * 32) + wake));
3148 }
3149}
3150
3151/* translate sc7 wake sources back into IRQs to catch edge triggered wakeups */
3152static void tegra186_pmc_process_wake_events(struct tegra_pmc *pmc, unsigned int index,
3153 unsigned long status)
3154{
3155 unsigned int wake;
3156
3157 dev_dbg(pmc->dev, "Wake[%d:%d] status=%#lx\n", (index * 32) + 31, index * 32, status);
3158
3159 for_each_set_bit(wake, &status, 32) {
3160 irq_hw_number_t hwirq = wake + 32 * index;
3161 struct irq_desc *desc;
3162 unsigned int irq;
3163
3164 irq = irq_find_mapping(pmc->domain, hwirq);
3165
3166 desc = irq_to_desc(irq);
3167 if (!desc || !desc->action || !desc->action->name) {
3168 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, IRQ %d\n", hwirq, irq);
3169 continue;
3170 }
3171
3172 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, %s\n", hwirq, desc->action->name);
3173 generic_handle_irq(irq);
3174 }
3175}
3176
3177static void tegra186_pmc_wake_syscore_resume(void)
3178{
3179 u32 status, mask;
3180 unsigned int i;
3181
3182 for (i = 0; i < pmc->soc->max_wake_vectors; i++) {
3183 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i));
3184 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask;
3185
3186 tegra186_pmc_process_wake_events(pmc, i, status);
3187 }
3188}
3189
3190static int tegra186_pmc_wake_syscore_suspend(void)
3191{
3192 wke_read_sw_wake_status(pmc);
3193
3194 /* flip the wakeup trigger for dual-edge triggered pads
3195 * which are currently asserting as wakeups
3196 */
3197 bitmap_andnot(pmc->wake_cntrl_level_map, pmc->wake_type_dual_edge_map,
3198 pmc->wake_sw_status_map, pmc->soc->max_wake_events);
3199 bitmap_or(pmc->wake_cntrl_level_map, pmc->wake_cntrl_level_map,
3200 pmc->wake_type_level_map, pmc->soc->max_wake_events);
3201
3202 /* Clear PMC Wake Status registers while going to suspend */
3203 wke_clear_wake_status(pmc);
3204 wke_write_wake_levels(pmc);
3205
3206 return 0;
3207}
3208
3209#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
3210static int tegra_pmc_suspend(struct device *dev)
3211{
3212 struct tegra_pmc *pmc = dev_get_drvdata(dev);
3213
3214 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);
3215
3216 return 0;
3217}
3218
3219static int tegra_pmc_resume(struct device *dev)
3220{
3221 struct tegra_pmc *pmc = dev_get_drvdata(dev);
3222
3223 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);
3224
3225 return 0;
3226}
3227
3228static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
3229
3230#endif
3231
3232static const char * const tegra20_powergates[] = {
3233 [TEGRA_POWERGATE_CPU] = "cpu",
3234 [TEGRA_POWERGATE_3D] = "td",
3235 [TEGRA_POWERGATE_VENC] = "venc",
3236 [TEGRA_POWERGATE_VDEC] = "vdec",
3237 [TEGRA_POWERGATE_PCIE] = "pcie",
3238 [TEGRA_POWERGATE_L2] = "l2",
3239 [TEGRA_POWERGATE_MPE] = "mpe",
3240};
3241
3242static const struct tegra_pmc_regs tegra20_pmc_regs = {
3243 .scratch0 = 0x50,
3244 .rst_status = 0x1b4,
3245 .rst_source_shift = 0x0,
3246 .rst_source_mask = 0x7,
3247 .rst_level_shift = 0x0,
3248 .rst_level_mask = 0x0,
3249};
3250
3251static void tegra20_pmc_init(struct tegra_pmc *pmc)
3252{
3253 u32 value, osc, pmu, off;
3254
3255 /* Always enable CPU power request */
3256 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3257 value |= PMC_CNTRL_CPU_PWRREQ_OE;
3258 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3259
3260 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3261
3262 if (pmc->sysclkreq_high)
3263 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
3264 else
3265 value |= PMC_CNTRL_SYSCLK_POLARITY;
3266
3267 if (pmc->corereq_high)
3268 value &= ~PMC_CNTRL_PWRREQ_POLARITY;
3269 else
3270 value |= PMC_CNTRL_PWRREQ_POLARITY;
3271
3272 /* configure the output polarity while the request is tristated */
3273 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3274
3275 /* now enable the request */
3276 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3277 value |= PMC_CNTRL_SYSCLK_OE;
3278 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3279
3280 /* program core timings which are applicable only for suspend state */
3281 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) {
3282 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000);
3283 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000);
3284 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000);
3285 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),
3286 PMC_COREPWRGOOD_TIMER);
3287 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);
3288 }
3289}
3290
3291static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3292 struct device_node *np,
3293 bool invert)
3294{
3295 u32 value;
3296
3297 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3298
3299 if (invert)
3300 value |= PMC_CNTRL_INTR_POLARITY;
3301 else
3302 value &= ~PMC_CNTRL_INTR_POLARITY;
3303
3304 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3305}
3306
3307static const struct tegra_pmc_soc tegra20_pmc_soc = {
3308 .supports_core_domain = true,
3309 .num_powergates = ARRAY_SIZE(tegra20_powergates),
3310 .powergates = tegra20_powergates,
3311 .num_cpu_powergates = 0,
3312 .cpu_powergates = NULL,
3313 .has_tsense_reset = false,
3314 .has_gpu_clamps = false,
3315 .needs_mbist_war = false,
3316 .has_impl_33v_pwr = false,
3317 .maybe_tz_only = false,
3318 .num_io_pads = 0,
3319 .io_pads = NULL,
3320 .num_pin_descs = 0,
3321 .pin_descs = NULL,
3322 .regs = &tegra20_pmc_regs,
3323 .init = tegra20_pmc_init,
3324 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3325 .powergate_set = tegra20_powergate_set,
3326 .reset_sources = NULL,
3327 .num_reset_sources = 0,
3328 .reset_levels = NULL,
3329 .num_reset_levels = 0,
3330 .pmc_clks_data = NULL,
3331 .num_pmc_clks = 0,
3332 .has_blink_output = true,
3333 .has_usb_sleepwalk = true,
3334};
3335
3336static const char * const tegra30_powergates[] = {
3337 [TEGRA_POWERGATE_CPU] = "cpu0",
3338 [TEGRA_POWERGATE_3D] = "td",
3339 [TEGRA_POWERGATE_VENC] = "venc",
3340 [TEGRA_POWERGATE_VDEC] = "vdec",
3341 [TEGRA_POWERGATE_PCIE] = "pcie",
3342 [TEGRA_POWERGATE_L2] = "l2",
3343 [TEGRA_POWERGATE_MPE] = "mpe",
3344 [TEGRA_POWERGATE_HEG] = "heg",
3345 [TEGRA_POWERGATE_SATA] = "sata",
3346 [TEGRA_POWERGATE_CPU1] = "cpu1",
3347 [TEGRA_POWERGATE_CPU2] = "cpu2",
3348 [TEGRA_POWERGATE_CPU3] = "cpu3",
3349 [TEGRA_POWERGATE_CELP] = "celp",
3350 [TEGRA_POWERGATE_3D1] = "td2",
3351};
3352
3353static const u8 tegra30_cpu_powergates[] = {
3354 TEGRA_POWERGATE_CPU,
3355 TEGRA_POWERGATE_CPU1,
3356 TEGRA_POWERGATE_CPU2,
3357 TEGRA_POWERGATE_CPU3,
3358};
3359
3360static const char * const tegra30_reset_sources[] = {
3361 "POWER_ON_RESET",
3362 "WATCHDOG",
3363 "SENSOR",
3364 "SW_MAIN",
3365 "LP0"
3366};
3367
3368static const struct tegra_pmc_soc tegra30_pmc_soc = {
3369 .supports_core_domain = true,
3370 .num_powergates = ARRAY_SIZE(tegra30_powergates),
3371 .powergates = tegra30_powergates,
3372 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
3373 .cpu_powergates = tegra30_cpu_powergates,
3374 .has_tsense_reset = true,
3375 .has_gpu_clamps = false,
3376 .needs_mbist_war = false,
3377 .has_impl_33v_pwr = false,
3378 .maybe_tz_only = false,
3379 .num_io_pads = 0,
3380 .io_pads = NULL,
3381 .num_pin_descs = 0,
3382 .pin_descs = NULL,
3383 .regs = &tegra20_pmc_regs,
3384 .init = tegra20_pmc_init,
3385 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3386 .powergate_set = tegra20_powergate_set,
3387 .reset_sources = tegra30_reset_sources,
3388 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3389 .reset_levels = NULL,
3390 .num_reset_levels = 0,
3391 .pmc_clks_data = tegra_pmc_clks_data,
3392 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3393 .has_blink_output = true,
3394 .has_usb_sleepwalk = true,
3395};
3396
3397static const char * const tegra114_powergates[] = {
3398 [TEGRA_POWERGATE_CPU] = "crail",
3399 [TEGRA_POWERGATE_3D] = "td",
3400 [TEGRA_POWERGATE_VENC] = "venc",
3401 [TEGRA_POWERGATE_VDEC] = "vdec",
3402 [TEGRA_POWERGATE_MPE] = "mpe",
3403 [TEGRA_POWERGATE_HEG] = "heg",
3404 [TEGRA_POWERGATE_CPU1] = "cpu1",
3405 [TEGRA_POWERGATE_CPU2] = "cpu2",
3406 [TEGRA_POWERGATE_CPU3] = "cpu3",
3407 [TEGRA_POWERGATE_CELP] = "celp",
3408 [TEGRA_POWERGATE_CPU0] = "cpu0",
3409 [TEGRA_POWERGATE_C0NC] = "c0nc",
3410 [TEGRA_POWERGATE_C1NC] = "c1nc",
3411 [TEGRA_POWERGATE_DIS] = "dis",
3412 [TEGRA_POWERGATE_DISB] = "disb",
3413 [TEGRA_POWERGATE_XUSBA] = "xusba",
3414 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3415 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3416};
3417
3418static const u8 tegra114_cpu_powergates[] = {
3419 TEGRA_POWERGATE_CPU0,
3420 TEGRA_POWERGATE_CPU1,
3421 TEGRA_POWERGATE_CPU2,
3422 TEGRA_POWERGATE_CPU3,
3423};
3424
3425static const struct tegra_pmc_soc tegra114_pmc_soc = {
3426 .supports_core_domain = false,
3427 .num_powergates = ARRAY_SIZE(tegra114_powergates),
3428 .powergates = tegra114_powergates,
3429 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
3430 .cpu_powergates = tegra114_cpu_powergates,
3431 .has_tsense_reset = true,
3432 .has_gpu_clamps = false,
3433 .needs_mbist_war = false,
3434 .has_impl_33v_pwr = false,
3435 .maybe_tz_only = false,
3436 .num_io_pads = 0,
3437 .io_pads = NULL,
3438 .num_pin_descs = 0,
3439 .pin_descs = NULL,
3440 .regs = &tegra20_pmc_regs,
3441 .init = tegra20_pmc_init,
3442 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3443 .powergate_set = tegra114_powergate_set,
3444 .reset_sources = tegra30_reset_sources,
3445 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3446 .reset_levels = NULL,
3447 .num_reset_levels = 0,
3448 .pmc_clks_data = tegra_pmc_clks_data,
3449 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3450 .has_blink_output = true,
3451 .has_usb_sleepwalk = true,
3452};
3453
3454static const char * const tegra124_powergates[] = {
3455 [TEGRA_POWERGATE_CPU] = "crail",
3456 [TEGRA_POWERGATE_3D] = "3d",
3457 [TEGRA_POWERGATE_VENC] = "venc",
3458 [TEGRA_POWERGATE_PCIE] = "pcie",
3459 [TEGRA_POWERGATE_VDEC] = "vdec",
3460 [TEGRA_POWERGATE_MPE] = "mpe",
3461 [TEGRA_POWERGATE_HEG] = "heg",
3462 [TEGRA_POWERGATE_SATA] = "sata",
3463 [TEGRA_POWERGATE_CPU1] = "cpu1",
3464 [TEGRA_POWERGATE_CPU2] = "cpu2",
3465 [TEGRA_POWERGATE_CPU3] = "cpu3",
3466 [TEGRA_POWERGATE_CELP] = "celp",
3467 [TEGRA_POWERGATE_CPU0] = "cpu0",
3468 [TEGRA_POWERGATE_C0NC] = "c0nc",
3469 [TEGRA_POWERGATE_C1NC] = "c1nc",
3470 [TEGRA_POWERGATE_SOR] = "sor",
3471 [TEGRA_POWERGATE_DIS] = "dis",
3472 [TEGRA_POWERGATE_DISB] = "disb",
3473 [TEGRA_POWERGATE_XUSBA] = "xusba",
3474 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3475 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3476 [TEGRA_POWERGATE_VIC] = "vic",
3477 [TEGRA_POWERGATE_IRAM] = "iram",
3478};
3479
3480static const u8 tegra124_cpu_powergates[] = {
3481 TEGRA_POWERGATE_CPU0,
3482 TEGRA_POWERGATE_CPU1,
3483 TEGRA_POWERGATE_CPU2,
3484 TEGRA_POWERGATE_CPU3,
3485};
3486
3487#define TEGRA_IO_PAD(_id, _dpd, _request, _status, _voltage, _name) \
3488 ((struct tegra_io_pad_soc) { \
3489 .id = (_id), \
3490 .dpd = (_dpd), \
3491 .request = (_request), \
3492 .status = (_status), \
3493 .voltage = (_voltage), \
3494 .name = (_name), \
3495 })
3496
3497#define TEGRA_IO_PIN_DESC(_id, _name) \
3498 ((struct pinctrl_pin_desc) { \
3499 .number = (_id), \
3500 .name = (_name), \
3501 })
3502
3503static const struct tegra_io_pad_soc tegra124_io_pads[] = {
3504 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, UINT_MAX, "audio"),
3505 TEGRA_IO_PAD(TEGRA_IO_PAD_BB, 15, 0x1b8, 0x1bc, UINT_MAX, "bb"),
3506 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, UINT_MAX, "cam"),
3507 TEGRA_IO_PAD(TEGRA_IO_PAD_COMP, 22, 0x1b8, 0x1bc, UINT_MAX, "comp"),
3508 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, "csia"),
3509 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, "csib"),
3510 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, "csie"),
3511 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, "dsi"),
3512 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"),
3513 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, "dsic"),
3514 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, "dsid"),
3515 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, "hdmi"),
3516 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, "hsic"),
3517 TEGRA_IO_PAD(TEGRA_IO_PAD_HV, 6, 0x1c0, 0x1c4, UINT_MAX, "hv"),
3518 TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, "lvds"),
3519 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"),
3520 TEGRA_IO_PAD(TEGRA_IO_PAD_NAND, 13, 0x1b8, 0x1bc, UINT_MAX, "nand"),
3521 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"),
3522 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"),
3523 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"),
3524 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x1c0, 0x1c4, UINT_MAX, "pex-cntrl"),
3525 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, UINT_MAX, "sdmmc1"),
3526 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, UINT_MAX, "sdmmc3"),
3527 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 3, 0x1c0, 0x1c4, UINT_MAX, "sdmmc4"),
3528 TEGRA_IO_PAD(TEGRA_IO_PAD_SYS_DDC, 26, 0x1c0, 0x1c4, UINT_MAX, "sys_ddc"),
3529 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, UINT_MAX, "uart"),
3530 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, "usb0"),
3531 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, "usb1"),
3532 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, "usb2"),
3533 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb_bias"),
3534};
3535
3536static const struct pinctrl_pin_desc tegra124_pin_descs[] = {
3537 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"),
3538 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_BB, "bb"),
3539 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"),
3540 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_COMP, "comp"),
3541 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),
3542 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),
3543 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),
3544 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"),
3545 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"),
3546 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"),
3547 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"),
3548 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"),
3549 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"),
3550 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HV, "hv"),
3551 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"),
3552 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
3553 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_NAND, "nand"),
3554 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"),
3555 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
3556 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3557 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
3558 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"),
3559 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"),
3560 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"),
3561 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SYS_DDC, "sys_ddc"),
3562 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"),
3563 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"),
3564 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"),
3565 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"),
3566 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb_bias"),
3567};
3568
3569static const struct tegra_pmc_soc tegra124_pmc_soc = {
3570 .supports_core_domain = false,
3571 .num_powergates = ARRAY_SIZE(tegra124_powergates),
3572 .powergates = tegra124_powergates,
3573 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
3574 .cpu_powergates = tegra124_cpu_powergates,
3575 .has_tsense_reset = true,
3576 .has_gpu_clamps = true,
3577 .needs_mbist_war = false,
3578 .has_impl_33v_pwr = false,
3579 .maybe_tz_only = false,
3580 .num_io_pads = ARRAY_SIZE(tegra124_io_pads),
3581 .io_pads = tegra124_io_pads,
3582 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs),
3583 .pin_descs = tegra124_pin_descs,
3584 .regs = &tegra20_pmc_regs,
3585 .init = tegra20_pmc_init,
3586 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3587 .powergate_set = tegra114_powergate_set,
3588 .reset_sources = tegra30_reset_sources,
3589 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3590 .reset_levels = NULL,
3591 .num_reset_levels = 0,
3592 .pmc_clks_data = tegra_pmc_clks_data,
3593 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3594 .has_blink_output = true,
3595 .has_usb_sleepwalk = true,
3596};
3597
3598static const char * const tegra210_powergates[] = {
3599 [TEGRA_POWERGATE_CPU] = "crail",
3600 [TEGRA_POWERGATE_3D] = "3d",
3601 [TEGRA_POWERGATE_VENC] = "venc",
3602 [TEGRA_POWERGATE_PCIE] = "pcie",
3603 [TEGRA_POWERGATE_MPE] = "mpe",
3604 [TEGRA_POWERGATE_SATA] = "sata",
3605 [TEGRA_POWERGATE_CPU1] = "cpu1",
3606 [TEGRA_POWERGATE_CPU2] = "cpu2",
3607 [TEGRA_POWERGATE_CPU3] = "cpu3",
3608 [TEGRA_POWERGATE_CPU0] = "cpu0",
3609 [TEGRA_POWERGATE_C0NC] = "c0nc",
3610 [TEGRA_POWERGATE_SOR] = "sor",
3611 [TEGRA_POWERGATE_DIS] = "dis",
3612 [TEGRA_POWERGATE_DISB] = "disb",
3613 [TEGRA_POWERGATE_XUSBA] = "xusba",
3614 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3615 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3616 [TEGRA_POWERGATE_VIC] = "vic",
3617 [TEGRA_POWERGATE_IRAM] = "iram",
3618 [TEGRA_POWERGATE_NVDEC] = "nvdec",
3619 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
3620 [TEGRA_POWERGATE_AUD] = "aud",
3621 [TEGRA_POWERGATE_DFD] = "dfd",
3622 [TEGRA_POWERGATE_VE2] = "ve2",
3623};
3624
3625static const u8 tegra210_cpu_powergates[] = {
3626 TEGRA_POWERGATE_CPU0,
3627 TEGRA_POWERGATE_CPU1,
3628 TEGRA_POWERGATE_CPU2,
3629 TEGRA_POWERGATE_CPU3,
3630};
3631
3632static const struct tegra_io_pad_soc tegra210_io_pads[] = {
3633 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, 5, "audio"),
3634 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x1c0, 0x1c4, 18, "audio-hv"),
3635 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, 10, "cam"),
3636 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, "csia"),
3637 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, "csib"),
3638 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 10, 0x1c0, 0x1c4, UINT_MAX, "csic"),
3639 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 11, 0x1c0, 0x1c4, UINT_MAX, "csid"),
3640 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, "csie"),
3641 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 13, 0x1c0, 0x1c4, UINT_MAX, "csif"),
3642 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x1b8, 0x1bc, 19, "dbg"),
3643 TEGRA_IO_PAD(TEGRA_IO_PAD_DEBUG_NONAO, 26, 0x1b8, 0x1bc, UINT_MAX, "debug-nonao"),
3644 TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC, 18, 0x1c0, 0x1c4, 20, "dmic"),
3645 TEGRA_IO_PAD(TEGRA_IO_PAD_DP, 19, 0x1c0, 0x1c4, UINT_MAX, "dp"),
3646 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, "dsi"),
3647 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"),
3648 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, "dsic"),
3649 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, "dsid"),
3650 TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC, 3, 0x1c0, 0x1c4, UINT_MAX, "emmc"),
3651 TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC2, 5, 0x1c0, 0x1c4, UINT_MAX, "emmc2"),
3652 TEGRA_IO_PAD(TEGRA_IO_PAD_GPIO, 27, 0x1b8, 0x1bc, 21, "gpio"),
3653 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, "hdmi"),
3654 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, "hsic"),
3655 TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, "lvds"),
3656 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"),
3657 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"),
3658 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"),
3659 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"),
3660 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, UINT_MAX, UINT_MAX, 11, "pex-cntrl"),
3661 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, 12, "sdmmc1"),
3662 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, 13, "sdmmc3"),
3663 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 14, 0x1c0, 0x1c4, 22, "spi"),
3664 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI_HV, 15, 0x1c0, 0x1c4, 23, "spi-hv"),
3665 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, 2, "uart"),
3666 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, "usb0"),
3667 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, "usb1"),
3668 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, "usb2"),
3669 TEGRA_IO_PAD(TEGRA_IO_PAD_USB3, 18, 0x1b8, 0x1bc, UINT_MAX, "usb3"),
3670 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb-bias"),
3671};
3672
3673static const struct pinctrl_pin_desc tegra210_pin_descs[] = {
3674 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"),
3675 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
3676 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"),
3677 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),
3678 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),
3679 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"),
3680 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"),
3681 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),
3682 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"),
3683 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"),
3684 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DEBUG_NONAO, "debug-nonao"),
3685 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC, "dmic"),
3686 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DP, "dp"),
3687 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"),
3688 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"),
3689 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"),
3690 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"),
3691 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC, "emmc"),
3692 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC2, "emmc2"),
3693 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GPIO, "gpio"),
3694 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"),
3695 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"),
3696 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"),
3697 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
3698 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"),
3699 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
3700 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3701 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
3702 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"),
3703 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"),
3704 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"),
3705 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI_HV, "spi-hv"),
3706 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"),
3707 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"),
3708 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"),
3709 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"),
3710 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB3, "usb3"),
3711 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"),
3712};
3713
3714static const char * const tegra210_reset_sources[] = {
3715 "POWER_ON_RESET",
3716 "WATCHDOG",
3717 "SENSOR",
3718 "SW_MAIN",
3719 "LP0",
3720 "AOTAG"
3721};
3722
3723static const struct tegra_wake_event tegra210_wake_events[] = {
3724 TEGRA_WAKE_IRQ("rtc", 16, 2),
3725 TEGRA_WAKE_IRQ("pmu", 51, 86),
3726};
3727
3728static const struct tegra_pmc_soc tegra210_pmc_soc = {
3729 .supports_core_domain = false,
3730 .num_powergates = ARRAY_SIZE(tegra210_powergates),
3731 .powergates = tegra210_powergates,
3732 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
3733 .cpu_powergates = tegra210_cpu_powergates,
3734 .has_tsense_reset = true,
3735 .has_gpu_clamps = true,
3736 .needs_mbist_war = true,
3737 .has_impl_33v_pwr = false,
3738 .maybe_tz_only = true,
3739 .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
3740 .io_pads = tegra210_io_pads,
3741 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
3742 .pin_descs = tegra210_pin_descs,
3743 .regs = &tegra20_pmc_regs,
3744 .init = tegra20_pmc_init,
3745 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3746 .powergate_set = tegra114_powergate_set,
3747 .irq_set_wake = tegra210_pmc_irq_set_wake,
3748 .irq_set_type = tegra210_pmc_irq_set_type,
3749 .reset_sources = tegra210_reset_sources,
3750 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
3751 .reset_levels = NULL,
3752 .num_reset_levels = 0,
3753 .num_wake_events = ARRAY_SIZE(tegra210_wake_events),
3754 .wake_events = tegra210_wake_events,
3755 .pmc_clks_data = tegra_pmc_clks_data,
3756 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3757 .has_blink_output = true,
3758 .has_usb_sleepwalk = true,
3759};
3760
3761static const struct tegra_io_pad_soc tegra186_io_pads[] = {
3762 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, "csia"),
3763 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, "csib"),
3764 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x74, 0x78, UINT_MAX, "dsi"),
3765 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"),
3766 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"),
3767 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"),
3768 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"),
3769 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"),
3770 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x74, 0x78, UINT_MAX, "usb0"),
3771 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x74, 0x78, UINT_MAX, "usb1"),
3772 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x74, 0x78, UINT_MAX, "usb2"),
3773 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x74, 0x78, UINT_MAX, "usb-bias"),
3774 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, "uart"),
3775 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, "audio"),
3776 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x74, 0x78, UINT_MAX, "hsic"),
3777 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, "dbg"),
3778 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"),
3779 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"),
3780 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"),
3781 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC2_HV, 2, 0x7c, 0x80, 5, "sdmmc2-hv"),
3782 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, "sdmmc4"),
3783 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, "cam"),
3784 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 8, 0x7c, 0x80, UINT_MAX, "dsib"),
3785 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 9, 0x7c, 0x80, UINT_MAX, "dsic"),
3786 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 10, 0x7c, 0x80, UINT_MAX, "dsid"),
3787 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, "csic"),
3788 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, "csid"),
3789 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, "csie"),
3790 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, "csif"),
3791 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, "spi"),
3792 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, "ufs"),
3793 TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC_HV, 20, 0x7c, 0x80, 2, "dmic-hv"),
3794 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, "edp"),
3795 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"),
3796 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"),
3797 TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, "conn"),
3798 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"),
3799 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),
3800};
3801
3802static const struct pinctrl_pin_desc tegra186_pin_descs[] = {
3803 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),
3804 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),
3805 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"),
3806 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
3807 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"),
3808 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"),
3809 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3810 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
3811 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"),
3812 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"),
3813 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"),
3814 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"),
3815 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"),
3816 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"),
3817 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"),
3818 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"),
3819 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
3820 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"),
3821 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
3822 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC2_HV, "sdmmc2-hv"),
3823 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"),
3824 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"),
3825 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"),
3826 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"),
3827 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"),
3828 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"),
3829 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"),
3830 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),
3831 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"),
3832 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"),
3833 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"),
3834 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC_HV, "dmic-hv"),
3835 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"),
3836 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),
3837 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),
3838 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"),
3839 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
3840 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),
3841};
3842
3843static const struct tegra_pmc_regs tegra186_pmc_regs = {
3844 .scratch0 = 0x2000,
3845 .rst_status = 0x70,
3846 .rst_source_shift = 0x2,
3847 .rst_source_mask = 0x3c,
3848 .rst_level_shift = 0x0,
3849 .rst_level_mask = 0x3,
3850};
3851
3852static void tegra186_pmc_init(struct tegra_pmc *pmc)
3853{
3854 pmc->syscore.suspend = tegra186_pmc_wake_syscore_suspend;
3855 pmc->syscore.resume = tegra186_pmc_wake_syscore_resume;
3856
3857 register_syscore_ops(&pmc->syscore);
3858}
3859
3860static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3861 struct device_node *np,
3862 bool invert)
3863{
3864 struct resource regs;
3865 void __iomem *wake;
3866 u32 value;
3867 int index;
3868
3869 index = of_property_match_string(np, "reg-names", "wake");
3870 if (index < 0) {
3871 dev_err(pmc->dev, "failed to find PMC wake registers\n");
3872 return;
3873 }
3874
3875 of_address_to_resource(np, index, ®s);
3876
3877 wake = ioremap(regs.start, resource_size(®s));
3878 if (!wake) {
3879 dev_err(pmc->dev, "failed to map PMC wake registers\n");
3880 return;
3881 }
3882
3883 value = readl(wake + WAKE_AOWAKE_CTRL);
3884
3885 if (invert)
3886 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
3887 else
3888 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
3889
3890 writel(value, wake + WAKE_AOWAKE_CTRL);
3891
3892 iounmap(wake);
3893}
3894
3895static const char * const tegra186_reset_sources[] = {
3896 "SYS_RESET",
3897 "AOWDT",
3898 "MCCPLEXWDT",
3899 "BPMPWDT",
3900 "SCEWDT",
3901 "SPEWDT",
3902 "APEWDT",
3903 "BCCPLEXWDT",
3904 "SENSOR",
3905 "AOTAG",
3906 "VFSENSOR",
3907 "SWREST",
3908 "SC7",
3909 "HSM",
3910 "CORESIGHT"
3911};
3912
3913static const char * const tegra186_reset_levels[] = {
3914 "L0", "L1", "L2", "WARM"
3915};
3916
3917static const struct tegra_wake_event tegra186_wake_events[] = {
3918 TEGRA_WAKE_IRQ("pmu", 24, 209),
3919 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)),
3920 TEGRA_WAKE_IRQ("rtc", 73, 10),
3921};
3922
3923static const struct tegra_pmc_soc tegra186_pmc_soc = {
3924 .supports_core_domain = false,
3925 .num_powergates = 0,
3926 .powergates = NULL,
3927 .num_cpu_powergates = 0,
3928 .cpu_powergates = NULL,
3929 .has_tsense_reset = false,
3930 .has_gpu_clamps = false,
3931 .needs_mbist_war = false,
3932 .has_impl_33v_pwr = true,
3933 .maybe_tz_only = false,
3934 .num_io_pads = ARRAY_SIZE(tegra186_io_pads),
3935 .io_pads = tegra186_io_pads,
3936 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),
3937 .pin_descs = tegra186_pin_descs,
3938 .regs = &tegra186_pmc_regs,
3939 .init = tegra186_pmc_init,
3940 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3941 .irq_set_wake = tegra186_pmc_irq_set_wake,
3942 .irq_set_type = tegra186_pmc_irq_set_type,
3943 .reset_sources = tegra186_reset_sources,
3944 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources),
3945 .reset_levels = tegra186_reset_levels,
3946 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3947 .num_wake_events = ARRAY_SIZE(tegra186_wake_events),
3948 .wake_events = tegra186_wake_events,
3949 .max_wake_events = 96,
3950 .max_wake_vectors = 3,
3951 .pmc_clks_data = NULL,
3952 .num_pmc_clks = 0,
3953 .has_blink_output = false,
3954 .has_usb_sleepwalk = false,
3955};
3956
3957static const struct tegra_io_pad_soc tegra194_io_pads[] = {
3958 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, "csia"),
3959 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, "csib"),
3960 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"),
3961 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"),
3962 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"),
3963 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"),
3964 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"),
3965 TEGRA_IO_PAD(TEGRA_IO_PAD_EQOS, 8, 0x74, 0x78, UINT_MAX, "eqos"),
3966 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, 0x74, 0x78, UINT_MAX, "pex-clk-2-bias"),
3967 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2, 10, 0x74, 0x78, UINT_MAX, "pex-clk-2"),
3968 TEGRA_IO_PAD(TEGRA_IO_PAD_DAP3, 11, 0x74, 0x78, UINT_MAX, "dap3"),
3969 TEGRA_IO_PAD(TEGRA_IO_PAD_DAP5, 12, 0x74, 0x78, UINT_MAX, "dap5"),
3970 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, "uart"),
3971 TEGRA_IO_PAD(TEGRA_IO_PAD_PWR_CTL, 15, 0x74, 0x78, UINT_MAX, "pwr-ctl"),
3972 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO53, 16, 0x74, 0x78, UINT_MAX, "soc-gpio53"),
3973 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, "audio"),
3974 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM2, 18, 0x74, 0x78, UINT_MAX, "gp-pwm2"),
3975 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM3, 19, 0x74, 0x78, UINT_MAX, "gp-pwm3"),
3976 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO12, 20, 0x74, 0x78, UINT_MAX, "soc-gpio12"),
3977 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO13, 21, 0x74, 0x78, UINT_MAX, "soc-gpio13"),
3978 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO10, 22, 0x74, 0x78, UINT_MAX, "soc-gpio10"),
3979 TEGRA_IO_PAD(TEGRA_IO_PAD_UART4, 23, 0x74, 0x78, UINT_MAX, "uart4"),
3980 TEGRA_IO_PAD(TEGRA_IO_PAD_UART5, 24, 0x74, 0x78, UINT_MAX, "uart5"),
3981 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, "dbg"),
3982 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP3, 26, 0x74, 0x78, UINT_MAX, "hdmi-dp3"),
3983 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP2, 27, 0x74, 0x78, UINT_MAX, "hdmi-dp2"),
3984 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"),
3985 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"),
3986 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"),
3987 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CTL2, 1, 0x7c, 0x80, UINT_MAX, "pex-ctl2"),
3988 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L0_RST, 2, 0x7c, 0x80, UINT_MAX, "pex-l0-rst"),
3989 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L1_RST, 3, 0x7c, 0x80, UINT_MAX, "pex-l1-rst"),
3990 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, "sdmmc4"),
3991 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L5_RST, 5, 0x7c, 0x80, UINT_MAX, "pex-l5-rst"),
3992 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, "cam"),
3993 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, "csic"),
3994 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, "csid"),
3995 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, "csie"),
3996 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, "csif"),
3997 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, "spi"),
3998 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, "ufs"),
3999 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 18, 0x7c, 0x80, UINT_MAX, "csig"),
4000 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 19, 0x7c, 0x80, UINT_MAX, "csih"),
4001 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, "edp"),
4002 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"),
4003 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"),
4004 TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, "conn"),
4005 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"),
4006 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),
4007};
4008
4009static const struct pinctrl_pin_desc tegra194_pin_descs[] = {
4010 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),
4011 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),
4012 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
4013 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"),
4014 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"),
4015 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
4016 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
4017 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EQOS, "eqos"),
4018 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2_BIAS, "pex-clk-2-bias"),
4019 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2, "pex-clk-2"),
4020 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP3, "dap3"),
4021 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP5, "dap5"),
4022 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"),
4023 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PWR_CTL, "pwr-ctl"),
4024 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO53, "soc-gpio53"),
4025 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"),
4026 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM2, "gp-pwm2"),
4027 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM3, "gp-pwm3"),
4028 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO12, "soc-gpio12"),
4029 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO13, "soc-gpio13"),
4030 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO10, "soc-gpio10"),
4031 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART4, "uart4"),
4032 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART5, "uart5"),
4033 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"),
4034 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP3, "hdmi-dp3"),
4035 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP2, "hdmi-dp2"),
4036 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
4037 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"),
4038 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
4039 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CTL2, "pex-ctl2"),
4040 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L0_RST, "pex-l0-rst"),
4041 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L1_RST, "pex-l1-rst"),
4042 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"),
4043 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L5_RST, "pex-l5-rst"),
4044 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"),
4045 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"),
4046 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"),
4047 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),
4048 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"),
4049 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"),
4050 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"),
4051 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"),
4052 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"),
4053 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"),
4054 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),
4055 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),
4056 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"),
4057 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
4058 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),
4059};
4060
4061static const struct tegra_pmc_regs tegra194_pmc_regs = {
4062 .scratch0 = 0x2000,
4063 .rst_status = 0x70,
4064 .rst_source_shift = 0x2,
4065 .rst_source_mask = 0x7c,
4066 .rst_level_shift = 0x0,
4067 .rst_level_mask = 0x3,
4068};
4069
4070static const char * const tegra194_reset_sources[] = {
4071 "SYS_RESET_N",
4072 "AOWDT",
4073 "BCCPLEXWDT",
4074 "BPMPWDT",
4075 "SCEWDT",
4076 "SPEWDT",
4077 "APEWDT",
4078 "LCCPLEXWDT",
4079 "SENSOR",
4080 "AOTAG",
4081 "VFSENSOR",
4082 "MAINSWRST",
4083 "SC7",
4084 "HSM",
4085 "CSITE",
4086 "RCEWDT",
4087 "PVA0WDT",
4088 "PVA1WDT",
4089 "L1A_ASYNC",
4090 "BPMPBOOT",
4091 "FUSECRC",
4092};
4093
4094static const struct tegra_wake_event tegra194_wake_events[] = {
4095 TEGRA_WAKE_IRQ("pmu", 24, 209),
4096 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)),
4097 TEGRA_WAKE_IRQ("rtc", 73, 10),
4098 TEGRA_WAKE_SIMPLE("usb3-port-0", 76),
4099 TEGRA_WAKE_SIMPLE("usb3-port-1", 77),
4100 TEGRA_WAKE_SIMPLE("usb3-port-2-3", 78),
4101 TEGRA_WAKE_SIMPLE("usb2-port-0", 79),
4102 TEGRA_WAKE_SIMPLE("usb2-port-1", 80),
4103 TEGRA_WAKE_SIMPLE("usb2-port-2", 81),
4104 TEGRA_WAKE_SIMPLE("usb2-port-3", 82),
4105};
4106
4107static const struct tegra_pmc_soc tegra194_pmc_soc = {
4108 .supports_core_domain = false,
4109 .num_powergates = 0,
4110 .powergates = NULL,
4111 .num_cpu_powergates = 0,
4112 .cpu_powergates = NULL,
4113 .has_tsense_reset = false,
4114 .has_gpu_clamps = false,
4115 .needs_mbist_war = false,
4116 .has_impl_33v_pwr = true,
4117 .maybe_tz_only = false,
4118 .num_io_pads = ARRAY_SIZE(tegra194_io_pads),
4119 .io_pads = tegra194_io_pads,
4120 .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs),
4121 .pin_descs = tegra194_pin_descs,
4122 .regs = &tegra194_pmc_regs,
4123 .init = tegra186_pmc_init,
4124 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
4125 .irq_set_wake = tegra186_pmc_irq_set_wake,
4126 .irq_set_type = tegra186_pmc_irq_set_type,
4127 .reset_sources = tegra194_reset_sources,
4128 .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources),
4129 .reset_levels = tegra186_reset_levels,
4130 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
4131 .num_wake_events = ARRAY_SIZE(tegra194_wake_events),
4132 .wake_events = tegra194_wake_events,
4133 .max_wake_events = 96,
4134 .max_wake_vectors = 3,
4135 .pmc_clks_data = NULL,
4136 .num_pmc_clks = 0,
4137 .has_blink_output = false,
4138 .has_usb_sleepwalk = false,
4139};
4140
4141static const struct tegra_io_pad_soc tegra234_io_pads[] = {
4142 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0xe0c0, 0xe0c4, UINT_MAX, "csia"),
4143 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0xe0c0, 0xe0c4, UINT_MAX, "csib"),
4144 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 0, 0xe0d0, 0xe0d4, UINT_MAX, "hdmi-dp0"),
4145 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 2, 0xe0c0, 0xe0c4, UINT_MAX, "csic"),
4146 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 3, 0xe0c0, 0xe0c4, UINT_MAX, "csid"),
4147 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 4, 0xe0c0, 0xe0c4, UINT_MAX, "csie"),
4148 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 5, 0xe0c0, 0xe0c4, UINT_MAX, "csif"),
4149 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 0, 0xe064, 0xe068, UINT_MAX, "ufs"),
4150 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 1, 0xe05c, 0xe060, UINT_MAX, "edp"),
4151 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 0, 0xe054, 0xe058, 4, "sdmmc1-hv"),
4152 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, UINT_MAX, UINT_MAX, UINT_MAX, 6, "sdmmc3-hv"),
4153 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 1, "audio-hv"),
4154 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),
4155 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 6, 0xe0c0, 0xe0c4, UINT_MAX, "csig"),
4156 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 7, 0xe0c0, 0xe0c4, UINT_MAX, "csih"),
4157};
4158
4159static const struct pinctrl_pin_desc tegra234_pin_descs[] = {
4160 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),
4161 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),
4162 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
4163 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"),
4164 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"),
4165 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),
4166 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"),
4167 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"),
4168 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"),
4169 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),
4170 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),
4171 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
4172 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),
4173 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"),
4174 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"),
4175};
4176
4177static const struct tegra_pmc_regs tegra234_pmc_regs = {
4178 .scratch0 = 0x2000,
4179 .rst_status = 0x70,
4180 .rst_source_shift = 0x2,
4181 .rst_source_mask = 0xfc,
4182 .rst_level_shift = 0x0,
4183 .rst_level_mask = 0x3,
4184};
4185
4186static const char * const tegra234_reset_sources[] = {
4187 "SYS_RESET_N", /* 0x0 */
4188 "AOWDT",
4189 "BCCPLEXWDT",
4190 "BPMPWDT",
4191 "SCEWDT",
4192 "SPEWDT",
4193 "APEWDT",
4194 "LCCPLEXWDT",
4195 "SENSOR", /* 0x8 */
4196 NULL,
4197 NULL,
4198 "MAINSWRST",
4199 "SC7",
4200 "HSM",
4201 NULL,
4202 "RCEWDT",
4203 NULL, /* 0x10 */
4204 NULL,
4205 NULL,
4206 "BPMPBOOT",
4207 "FUSECRC",
4208 "DCEWDT",
4209 "PSCWDT",
4210 "PSC",
4211 "CSITE_SW", /* 0x18 */
4212 "POD",
4213 "SCPM",
4214 "VREFRO_POWERBAD",
4215 "VMON",
4216 "FMON",
4217 "FSI_R5WDT",
4218 "FSI_THERM",
4219 "FSI_R52C0WDT", /* 0x20 */
4220 "FSI_R52C1WDT",
4221 "FSI_R52C2WDT",
4222 "FSI_R52C3WDT",
4223 "FSI_FMON",
4224 "FSI_VMON", /* 0x25 */
4225};
4226
4227static const struct tegra_wake_event tegra234_wake_events[] = {
4228 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)),
4229 TEGRA_WAKE_IRQ("rtc", 73, 10),
4230};
4231
4232static const struct tegra_pmc_soc tegra234_pmc_soc = {
4233 .supports_core_domain = false,
4234 .num_powergates = 0,
4235 .powergates = NULL,
4236 .num_cpu_powergates = 0,
4237 .cpu_powergates = NULL,
4238 .has_tsense_reset = false,
4239 .has_gpu_clamps = false,
4240 .needs_mbist_war = false,
4241 .has_impl_33v_pwr = true,
4242 .maybe_tz_only = false,
4243 .num_io_pads = ARRAY_SIZE(tegra234_io_pads),
4244 .io_pads = tegra234_io_pads,
4245 .num_pin_descs = ARRAY_SIZE(tegra234_pin_descs),
4246 .pin_descs = tegra234_pin_descs,
4247 .regs = &tegra234_pmc_regs,
4248 .init = tegra186_pmc_init,
4249 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
4250 .irq_set_wake = tegra186_pmc_irq_set_wake,
4251 .irq_set_type = tegra186_pmc_irq_set_type,
4252 .reset_sources = tegra234_reset_sources,
4253 .num_reset_sources = ARRAY_SIZE(tegra234_reset_sources),
4254 .reset_levels = tegra186_reset_levels,
4255 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
4256 .num_wake_events = ARRAY_SIZE(tegra234_wake_events),
4257 .wake_events = tegra234_wake_events,
4258 .max_wake_events = 96,
4259 .max_wake_vectors = 3,
4260 .pmc_clks_data = NULL,
4261 .num_pmc_clks = 0,
4262 .has_blink_output = false,
4263};
4264
4265static const struct of_device_id tegra_pmc_match[] = {
4266 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
4267 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
4268 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
4269 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
4270 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
4271 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
4272 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
4273 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
4274 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
4275 { }
4276};
4277
4278static void tegra_pmc_sync_state(struct device *dev)
4279{
4280 int err;
4281
4282 /*
4283 * Newer device-trees have power domains, but we need to prepare all
4284 * device drivers with runtime PM and OPP support first, otherwise
4285 * state syncing is unsafe.
4286 */
4287 if (!pmc->soc->supports_core_domain)
4288 return;
4289
4290 /*
4291 * Older device-trees don't have core PD, and thus, there are
4292 * no dependencies that will block the state syncing. We shouldn't
4293 * mark the domain as synced in this case.
4294 */
4295 if (!pmc->core_domain_registered)
4296 return;
4297
4298 pmc->core_domain_state_synced = true;
4299
4300 /* this is a no-op if core regulator isn't used */
4301 mutex_lock(&pmc->powergates_lock);
4302 err = dev_pm_opp_sync_regulators(dev);
4303 mutex_unlock(&pmc->powergates_lock);
4304
4305 if (err)
4306 dev_err(dev, "failed to sync regulators: %d\n", err);
4307}
4308
4309static struct platform_driver tegra_pmc_driver = {
4310 .driver = {
4311 .name = "tegra-pmc",
4312 .suppress_bind_attrs = true,
4313 .of_match_table = tegra_pmc_match,
4314#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
4315 .pm = &tegra_pmc_pm_ops,
4316#endif
4317 .sync_state = tegra_pmc_sync_state,
4318 },
4319 .probe = tegra_pmc_probe,
4320};
4321builtin_platform_driver(tegra_pmc_driver);
4322
4323static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc)
4324{
4325 u32 value, saved;
4326
4327 saved = readl(pmc->base + pmc->soc->regs->scratch0);
4328 value = saved ^ 0xffffffff;
4329
4330 if (value == 0xffffffff)
4331 value = 0xdeadbeef;
4332
4333 /* write pattern and read it back */
4334 writel(value, pmc->base + pmc->soc->regs->scratch0);
4335 value = readl(pmc->base + pmc->soc->regs->scratch0);
4336
4337 /* if we read all-zeroes, access is restricted to TZ only */
4338 if (value == 0) {
4339 pr_info("access to PMC is restricted to TZ\n");
4340 return true;
4341 }
4342
4343 /* restore original value */
4344 writel(saved, pmc->base + pmc->soc->regs->scratch0);
4345
4346 return false;
4347}
4348
4349/*
4350 * Early initialization to allow access to registers in the very early boot
4351 * process.
4352 */
4353static int __init tegra_pmc_early_init(void)
4354{
4355 const struct of_device_id *match;
4356 struct device_node *np;
4357 struct resource regs;
4358 unsigned int i;
4359 bool invert;
4360
4361 mutex_init(&pmc->powergates_lock);
4362
4363 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
4364 if (!np) {
4365 /*
4366 * Fall back to legacy initialization for 32-bit ARM only. All
4367 * 64-bit ARM device tree files for Tegra are required to have
4368 * a PMC node.
4369 *
4370 * This is for backwards-compatibility with old device trees
4371 * that didn't contain a PMC node. Note that in this case the
4372 * SoC data can't be matched and therefore powergating is
4373 * disabled.
4374 */
4375 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
4376 pr_warn("DT node not found, powergating disabled\n");
4377
4378 regs.start = 0x7000e400;
4379 regs.end = 0x7000e7ff;
4380 regs.flags = IORESOURCE_MEM;
4381
4382 pr_warn("Using memory region %pR\n", ®s);
4383 } else {
4384 /*
4385 * At this point we're not running on Tegra, so play
4386 * nice with multi-platform kernels.
4387 */
4388 return 0;
4389 }
4390 } else {
4391 /*
4392 * Extract information from the device tree if we've found a
4393 * matching node.
4394 */
4395 if (of_address_to_resource(np, 0, ®s) < 0) {
4396 pr_err("failed to get PMC registers\n");
4397 of_node_put(np);
4398 return -ENXIO;
4399 }
4400 }
4401
4402 pmc->base = ioremap(regs.start, resource_size(®s));
4403 if (!pmc->base) {
4404 pr_err("failed to map PMC registers\n");
4405 of_node_put(np);
4406 return -ENXIO;
4407 }
4408
4409 if (of_device_is_available(np)) {
4410 pmc->soc = match->data;
4411
4412 if (pmc->soc->maybe_tz_only)
4413 pmc->tz_only = tegra_pmc_detect_tz_only(pmc);
4414
4415 /* Create a bitmap of the available and valid partitions */
4416 for (i = 0; i < pmc->soc->num_powergates; i++)
4417 if (pmc->soc->powergates[i])
4418 set_bit(i, pmc->powergates_available);
4419
4420 /*
4421 * Invert the interrupt polarity if a PMC device tree node
4422 * exists and contains the nvidia,invert-interrupt property.
4423 */
4424 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
4425
4426 pmc->soc->setup_irq_polarity(pmc, np, invert);
4427
4428 of_node_put(np);
4429 }
4430
4431 return 0;
4432}
4433early_initcall(tegra_pmc_early_init);