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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * drivers/soc/tegra/pmc.c
4 *
5 * Copyright (c) 2010 Google, Inc
6 * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
7 *
8 * Author:
9 * Colin Cross <ccross@google.com>
10 */
11
12#define pr_fmt(fmt) "tegra-pmc: " fmt
13
14#include <linux/arm-smccc.h>
15#include <linux/clk.h>
16#include <linux/clk-provider.h>
17#include <linux/clkdev.h>
18#include <linux/clk/clk-conf.h>
19#include <linux/clk/tegra.h>
20#include <linux/debugfs.h>
21#include <linux/delay.h>
22#include <linux/device.h>
23#include <linux/err.h>
24#include <linux/export.h>
25#include <linux/init.h>
26#include <linux/io.h>
27#include <linux/iopoll.h>
28#include <linux/irqdomain.h>
29#include <linux/irq.h>
30#include <linux/kernel.h>
31#include <linux/of_address.h>
32#include <linux/of_clk.h>
33#include <linux/of.h>
34#include <linux/of_irq.h>
35#include <linux/of_platform.h>
36#include <linux/pinctrl/pinconf-generic.h>
37#include <linux/pinctrl/pinconf.h>
38#include <linux/pinctrl/pinctrl.h>
39#include <linux/platform_device.h>
40#include <linux/pm_domain.h>
41#include <linux/pm_opp.h>
42#include <linux/reboot.h>
43#include <linux/regmap.h>
44#include <linux/reset.h>
45#include <linux/seq_file.h>
46#include <linux/slab.h>
47#include <linux/spinlock.h>
48
49#include <soc/tegra/common.h>
50#include <soc/tegra/fuse.h>
51#include <soc/tegra/pmc.h>
52
53#include <dt-bindings/interrupt-controller/arm-gic.h>
54#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
55#include <dt-bindings/gpio/tegra186-gpio.h>
56#include <dt-bindings/gpio/tegra194-gpio.h>
57#include <dt-bindings/soc/tegra-pmc.h>
58
59#define PMC_CNTRL 0x0
60#define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
61#define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
62#define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
63#define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
64#define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
65#define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
66#define PMC_CNTRL_PWRREQ_POLARITY BIT(8)
67#define PMC_CNTRL_BLINK_EN 7
68#define PMC_CNTRL_MAIN_RST BIT(4)
69
70#define PMC_WAKE_MASK 0x0c
71#define PMC_WAKE_LEVEL 0x10
72#define PMC_WAKE_STATUS 0x14
73#define PMC_SW_WAKE_STATUS 0x18
74#define PMC_DPD_PADS_ORIDE 0x1c
75#define PMC_DPD_PADS_ORIDE_BLINK 20
76
77#define DPD_SAMPLE 0x020
78#define DPD_SAMPLE_ENABLE BIT(0)
79#define DPD_SAMPLE_DISABLE (0 << 0)
80
81#define PWRGATE_TOGGLE 0x30
82#define PWRGATE_TOGGLE_START BIT(8)
83
84#define REMOVE_CLAMPING 0x34
85
86#define PWRGATE_STATUS 0x38
87
88#define PMC_BLINK_TIMER 0x40
89#define PMC_IMPL_E_33V_PWR 0x40
90
91#define PMC_PWR_DET 0x48
92
93#define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
94#define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
95#define PMC_SCRATCH0_MODE_RCM BIT(1)
96#define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
97 PMC_SCRATCH0_MODE_BOOTLOADER | \
98 PMC_SCRATCH0_MODE_RCM)
99
100#define PMC_CPUPWRGOOD_TIMER 0xc8
101#define PMC_CPUPWROFF_TIMER 0xcc
102#define PMC_COREPWRGOOD_TIMER 0x3c
103#define PMC_COREPWROFF_TIMER 0xe0
104
105#define PMC_PWR_DET_VALUE 0xe4
106
107#define PMC_USB_DEBOUNCE_DEL 0xec
108#define PMC_USB_AO 0xf0
109
110#define PMC_SCRATCH41 0x140
111
112#define PMC_WAKE2_MASK 0x160
113#define PMC_WAKE2_LEVEL 0x164
114#define PMC_WAKE2_STATUS 0x168
115#define PMC_SW_WAKE2_STATUS 0x16c
116
117#define PMC_CLK_OUT_CNTRL 0x1a8
118#define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0)
119#define PMC_SENSOR_CTRL 0x1b0
120#define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
121#define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
122
123#define PMC_RST_STATUS_POR 0
124#define PMC_RST_STATUS_WATCHDOG 1
125#define PMC_RST_STATUS_SENSOR 2
126#define PMC_RST_STATUS_SW_MAIN 3
127#define PMC_RST_STATUS_LP0 4
128#define PMC_RST_STATUS_AOTAG 5
129
130#define IO_DPD_REQ 0x1b8
131#define IO_DPD_REQ_CODE_IDLE (0U << 30)
132#define IO_DPD_REQ_CODE_OFF (1U << 30)
133#define IO_DPD_REQ_CODE_ON (2U << 30)
134#define IO_DPD_REQ_CODE_MASK (3U << 30)
135
136#define IO_DPD_STATUS 0x1bc
137#define IO_DPD2_REQ 0x1c0
138#define IO_DPD2_STATUS 0x1c4
139#define SEL_DPD_TIM 0x1c8
140
141#define PMC_UTMIP_UHSIC_TRIGGERS 0x1ec
142#define PMC_UTMIP_UHSIC_SAVED_STATE 0x1f0
143
144#define PMC_UTMIP_TERM_PAD_CFG 0x1f8
145#define PMC_UTMIP_UHSIC_SLEEP_CFG 0x1fc
146#define PMC_UTMIP_UHSIC_FAKE 0x218
147
148#define PMC_SCRATCH54 0x258
149#define PMC_SCRATCH54_DATA_SHIFT 8
150#define PMC_SCRATCH54_ADDR_SHIFT 0
151
152#define PMC_SCRATCH55 0x25c
153#define PMC_SCRATCH55_RESET_TEGRA BIT(31)
154#define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
155#define PMC_SCRATCH55_PINMUX_SHIFT 24
156#define PMC_SCRATCH55_16BITOP BIT(15)
157#define PMC_SCRATCH55_CHECKSUM_SHIFT 16
158#define PMC_SCRATCH55_I2CSLV1_SHIFT 0
159
160#define PMC_UTMIP_UHSIC_LINE_WAKEUP 0x26c
161
162#define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270
163#define PMC_UTMIP_MASTER_CONFIG 0x274
164#define PMC_UTMIP_UHSIC2_TRIGGERS 0x27c
165#define PMC_UTMIP_MASTER2_CONFIG 0x29c
166
167#define GPU_RG_CNTRL 0x2d4
168
169#define PMC_UTMIP_PAD_CFG0 0x4c0
170#define PMC_UTMIP_UHSIC_SLEEP_CFG1 0x4d0
171#define PMC_UTMIP_SLEEPWALK_P3 0x4e0
172/* Tegra186 and later */
173#define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))
174#define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3)
175#define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2))
176#define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2))
177#define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2))
178#define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2))
179#define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2))
180#define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2))
181#define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))
182
183#define WAKE_AOWAKE_CTRL 0x4f4
184#define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
185
186/* for secure PMC */
187#define TEGRA_SMC_PMC 0xc2fffe00
188#define TEGRA_SMC_PMC_READ 0xaa
189#define TEGRA_SMC_PMC_WRITE 0xbb
190
191struct pmc_clk {
192 struct clk_hw hw;
193 unsigned long offs;
194 u32 mux_shift;
195 u32 force_en_shift;
196};
197
198#define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
199
200struct pmc_clk_gate {
201 struct clk_hw hw;
202 unsigned long offs;
203 u32 shift;
204};
205
206#define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)
207
208struct pmc_clk_init_data {
209 char *name;
210 const char *const *parents;
211 int num_parents;
212 int clk_id;
213 u8 mux_shift;
214 u8 force_en_shift;
215};
216
217static const char * const clk_out1_parents[] = { "osc", "osc_div2",
218 "osc_div4", "extern1",
219};
220
221static const char * const clk_out2_parents[] = { "osc", "osc_div2",
222 "osc_div4", "extern2",
223};
224
225static const char * const clk_out3_parents[] = { "osc", "osc_div2",
226 "osc_div4", "extern3",
227};
228
229static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
230 {
231 .name = "pmc_clk_out_1",
232 .parents = clk_out1_parents,
233 .num_parents = ARRAY_SIZE(clk_out1_parents),
234 .clk_id = TEGRA_PMC_CLK_OUT_1,
235 .mux_shift = 6,
236 .force_en_shift = 2,
237 },
238 {
239 .name = "pmc_clk_out_2",
240 .parents = clk_out2_parents,
241 .num_parents = ARRAY_SIZE(clk_out2_parents),
242 .clk_id = TEGRA_PMC_CLK_OUT_2,
243 .mux_shift = 14,
244 .force_en_shift = 10,
245 },
246 {
247 .name = "pmc_clk_out_3",
248 .parents = clk_out3_parents,
249 .num_parents = ARRAY_SIZE(clk_out3_parents),
250 .clk_id = TEGRA_PMC_CLK_OUT_3,
251 .mux_shift = 22,
252 .force_en_shift = 18,
253 },
254};
255
256struct tegra_powergate {
257 struct generic_pm_domain genpd;
258 struct tegra_pmc *pmc;
259 unsigned int id;
260 struct clk **clks;
261 unsigned int num_clks;
262 unsigned long *clk_rates;
263 struct reset_control *reset;
264};
265
266struct tegra_io_pad_soc {
267 enum tegra_io_pad id;
268 unsigned int dpd;
269 unsigned int voltage;
270 const char *name;
271};
272
273struct tegra_pmc_regs {
274 unsigned int scratch0;
275 unsigned int dpd_req;
276 unsigned int dpd_status;
277 unsigned int dpd2_req;
278 unsigned int dpd2_status;
279 unsigned int rst_status;
280 unsigned int rst_source_shift;
281 unsigned int rst_source_mask;
282 unsigned int rst_level_shift;
283 unsigned int rst_level_mask;
284};
285
286struct tegra_wake_event {
287 const char *name;
288 unsigned int id;
289 unsigned int irq;
290 struct {
291 unsigned int instance;
292 unsigned int pin;
293 } gpio;
294};
295
296#define TEGRA_WAKE_IRQ(_name, _id, _irq) \
297 { \
298 .name = _name, \
299 .id = _id, \
300 .irq = _irq, \
301 .gpio = { \
302 .instance = UINT_MAX, \
303 .pin = UINT_MAX, \
304 }, \
305 }
306
307#define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \
308 { \
309 .name = _name, \
310 .id = _id, \
311 .irq = 0, \
312 .gpio = { \
313 .instance = _instance, \
314 .pin = _pin, \
315 }, \
316 }
317
318struct tegra_pmc_soc {
319 unsigned int num_powergates;
320 const char *const *powergates;
321 unsigned int num_cpu_powergates;
322 const u8 *cpu_powergates;
323
324 bool has_tsense_reset;
325 bool has_gpu_clamps;
326 bool needs_mbist_war;
327 bool has_impl_33v_pwr;
328 bool maybe_tz_only;
329
330 const struct tegra_io_pad_soc *io_pads;
331 unsigned int num_io_pads;
332
333 const struct pinctrl_pin_desc *pin_descs;
334 unsigned int num_pin_descs;
335
336 const struct tegra_pmc_regs *regs;
337 void (*init)(struct tegra_pmc *pmc);
338 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
339 struct device_node *np,
340 bool invert);
341 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
342 int (*irq_set_type)(struct irq_data *data, unsigned int type);
343 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id,
344 bool new_state);
345
346 const char * const *reset_sources;
347 unsigned int num_reset_sources;
348 const char * const *reset_levels;
349 unsigned int num_reset_levels;
350
351 /*
352 * These describe events that can wake the system from sleep (i.e.
353 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2)
354 * are dealt with in the LIC.
355 */
356 const struct tegra_wake_event *wake_events;
357 unsigned int num_wake_events;
358
359 const struct pmc_clk_init_data *pmc_clks_data;
360 unsigned int num_pmc_clks;
361 bool has_blink_output;
362 bool has_usb_sleepwalk;
363};
364
365/**
366 * struct tegra_pmc - NVIDIA Tegra PMC
367 * @dev: pointer to PMC device structure
368 * @base: pointer to I/O remapped register region
369 * @wake: pointer to I/O remapped region for WAKE registers
370 * @aotag: pointer to I/O remapped region for AOTAG registers
371 * @scratch: pointer to I/O remapped region for scratch registers
372 * @clk: pointer to pclk clock
373 * @soc: pointer to SoC data structure
374 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone
375 * @debugfs: pointer to debugfs entry
376 * @rate: currently configured rate of pclk
377 * @suspend_mode: lowest suspend mode available
378 * @cpu_good_time: CPU power good time (in microseconds)
379 * @cpu_off_time: CPU power off time (in microsecends)
380 * @core_osc_time: core power good OSC time (in microseconds)
381 * @core_pmu_time: core power good PMU time (in microseconds)
382 * @core_off_time: core power off time (in microseconds)
383 * @corereq_high: core power request is active-high
384 * @sysclkreq_high: system clock request is active-high
385 * @combined_req: combined power request for CPU & core
386 * @cpu_pwr_good_en: CPU power good signal is enabled
387 * @lp0_vec_phys: physical base address of the LP0 warm boot code
388 * @lp0_vec_size: size of the LP0 warm boot code
389 * @powergates_available: Bitmap of available power gates
390 * @powergates_lock: mutex for power gate register access
391 * @pctl_dev: pin controller exposed by the PMC
392 * @domain: IRQ domain provided by the PMC
393 * @irq: chip implementation for the IRQ domain
394 * @clk_nb: pclk clock changes handler
395 */
396struct tegra_pmc {
397 struct device *dev;
398 void __iomem *base;
399 void __iomem *wake;
400 void __iomem *aotag;
401 void __iomem *scratch;
402 struct clk *clk;
403 struct dentry *debugfs;
404
405 const struct tegra_pmc_soc *soc;
406 bool tz_only;
407
408 unsigned long rate;
409
410 enum tegra_suspend_mode suspend_mode;
411 u32 cpu_good_time;
412 u32 cpu_off_time;
413 u32 core_osc_time;
414 u32 core_pmu_time;
415 u32 core_off_time;
416 bool corereq_high;
417 bool sysclkreq_high;
418 bool combined_req;
419 bool cpu_pwr_good_en;
420 u32 lp0_vec_phys;
421 u32 lp0_vec_size;
422 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
423
424 struct mutex powergates_lock;
425
426 struct pinctrl_dev *pctl_dev;
427
428 struct irq_domain *domain;
429 struct irq_chip irq;
430
431 struct notifier_block clk_nb;
432
433 bool core_domain_state_synced;
434 bool core_domain_registered;
435};
436
437static struct tegra_pmc *pmc = &(struct tegra_pmc) {
438 .base = NULL,
439 .suspend_mode = TEGRA_SUSPEND_NONE,
440};
441
442static inline struct tegra_powergate *
443to_powergate(struct generic_pm_domain *domain)
444{
445 return container_of(domain, struct tegra_powergate, genpd);
446}
447
448static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)
449{
450 struct arm_smccc_res res;
451
452 if (pmc->tz_only) {
453 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
454 0, 0, 0, &res);
455 if (res.a0) {
456 if (pmc->dev)
457 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
458 __func__, res.a0);
459 else
460 pr_warn("%s(): SMC failed: %lu\n", __func__,
461 res.a0);
462 }
463
464 return res.a1;
465 }
466
467 return readl(pmc->base + offset);
468}
469
470static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,
471 unsigned long offset)
472{
473 struct arm_smccc_res res;
474
475 if (pmc->tz_only) {
476 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
477 value, 0, 0, 0, 0, &res);
478 if (res.a0) {
479 if (pmc->dev)
480 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
481 __func__, res.a0);
482 else
483 pr_warn("%s(): SMC failed: %lu\n", __func__,
484 res.a0);
485 }
486 } else {
487 writel(value, pmc->base + offset);
488 }
489}
490
491static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset)
492{
493 if (pmc->tz_only)
494 return tegra_pmc_readl(pmc, offset);
495
496 return readl(pmc->scratch + offset);
497}
498
499static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value,
500 unsigned long offset)
501{
502 if (pmc->tz_only)
503 tegra_pmc_writel(pmc, value, offset);
504 else
505 writel(value, pmc->scratch + offset);
506}
507
508/*
509 * TODO Figure out a way to call this with the struct tegra_pmc * passed in.
510 * This currently doesn't work because readx_poll_timeout() can only operate
511 * on functions that take a single argument.
512 */
513static inline bool tegra_powergate_state(int id)
514{
515 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
516 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0;
517 else
518 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0;
519}
520
521static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id)
522{
523 return (pmc->soc && pmc->soc->powergates[id]);
524}
525
526static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id)
527{
528 return test_bit(id, pmc->powergates_available);
529}
530
531static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
532{
533 unsigned int i;
534
535 if (!pmc || !pmc->soc || !name)
536 return -EINVAL;
537
538 for (i = 0; i < pmc->soc->num_powergates; i++) {
539 if (!tegra_powergate_is_valid(pmc, i))
540 continue;
541
542 if (!strcmp(name, pmc->soc->powergates[i]))
543 return i;
544 }
545
546 return -ENODEV;
547}
548
549static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id,
550 bool new_state)
551{
552 unsigned int retries = 100;
553 bool status;
554 int ret;
555
556 /*
557 * As per TRM documentation, the toggle command will be dropped by PMC
558 * if there is contention with a HW-initiated toggling (i.e. CPU core
559 * power-gated), the command should be retried in that case.
560 */
561 do {
562 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
563
564 /* wait for PMC to execute the command */
565 ret = readx_poll_timeout(tegra_powergate_state, id, status,
566 status == new_state, 1, 10);
567 } while (ret == -ETIMEDOUT && retries--);
568
569 return ret;
570}
571
572static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc)
573{
574 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START);
575}
576
577static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id,
578 bool new_state)
579{
580 bool status;
581 int err;
582
583 /* wait while PMC power gating is contended */
584 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
585 status == true, 1, 100);
586 if (err)
587 return err;
588
589 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
590
591 /* wait for PMC to accept the command */
592 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
593 status == true, 1, 100);
594 if (err)
595 return err;
596
597 /* wait for PMC to execute the command */
598 err = readx_poll_timeout(tegra_powergate_state, id, status,
599 status == new_state, 10, 100000);
600 if (err)
601 return err;
602
603 return 0;
604}
605
606/**
607 * tegra_powergate_set() - set the state of a partition
608 * @pmc: power management controller
609 * @id: partition ID
610 * @new_state: new state of the partition
611 */
612static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id,
613 bool new_state)
614{
615 int err;
616
617 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
618 return -EINVAL;
619
620 mutex_lock(&pmc->powergates_lock);
621
622 if (tegra_powergate_state(id) == new_state) {
623 mutex_unlock(&pmc->powergates_lock);
624 return 0;
625 }
626
627 err = pmc->soc->powergate_set(pmc, id, new_state);
628
629 mutex_unlock(&pmc->powergates_lock);
630
631 return err;
632}
633
634static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
635 unsigned int id)
636{
637 u32 mask;
638
639 mutex_lock(&pmc->powergates_lock);
640
641 /*
642 * On Tegra124 and later, the clamps for the GPU are controlled by a
643 * separate register (with different semantics).
644 */
645 if (id == TEGRA_POWERGATE_3D) {
646 if (pmc->soc->has_gpu_clamps) {
647 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);
648 goto out;
649 }
650 }
651
652 /*
653 * Tegra 2 has a bug where PCIE and VDE clamping masks are
654 * swapped relatively to the partition ids
655 */
656 if (id == TEGRA_POWERGATE_VDEC)
657 mask = (1 << TEGRA_POWERGATE_PCIE);
658 else if (id == TEGRA_POWERGATE_PCIE)
659 mask = (1 << TEGRA_POWERGATE_VDEC);
660 else
661 mask = (1 << id);
662
663 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);
664
665out:
666 mutex_unlock(&pmc->powergates_lock);
667
668 return 0;
669}
670
671static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg)
672{
673 unsigned long safe_rate = 100 * 1000 * 1000;
674 unsigned int i;
675 int err;
676
677 for (i = 0; i < pg->num_clks; i++) {
678 pg->clk_rates[i] = clk_get_rate(pg->clks[i]);
679
680 if (!pg->clk_rates[i]) {
681 err = -EINVAL;
682 goto out;
683 }
684
685 if (pg->clk_rates[i] <= safe_rate)
686 continue;
687
688 /*
689 * We don't know whether voltage state is okay for the
690 * current clock rate, hence it's better to temporally
691 * switch clock to a safe rate which is suitable for
692 * all voltages, before enabling the clock.
693 */
694 err = clk_set_rate(pg->clks[i], safe_rate);
695 if (err)
696 goto out;
697 }
698
699 return 0;
700
701out:
702 while (i--)
703 clk_set_rate(pg->clks[i], pg->clk_rates[i]);
704
705 return err;
706}
707
708static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg)
709{
710 unsigned int i;
711 int err;
712
713 for (i = 0; i < pg->num_clks; i++) {
714 err = clk_set_rate(pg->clks[i], pg->clk_rates[i]);
715 if (err)
716 return err;
717 }
718
719 return 0;
720}
721
722static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
723{
724 unsigned int i;
725
726 for (i = 0; i < pg->num_clks; i++)
727 clk_disable_unprepare(pg->clks[i]);
728}
729
730static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
731{
732 unsigned int i;
733 int err;
734
735 for (i = 0; i < pg->num_clks; i++) {
736 err = clk_prepare_enable(pg->clks[i]);
737 if (err)
738 goto out;
739 }
740
741 return 0;
742
743out:
744 while (i--)
745 clk_disable_unprepare(pg->clks[i]);
746
747 return err;
748}
749
750static int tegra_powergate_power_up(struct tegra_powergate *pg,
751 bool disable_clocks)
752{
753 int err;
754
755 err = reset_control_assert(pg->reset);
756 if (err)
757 return err;
758
759 usleep_range(10, 20);
760
761 err = tegra_powergate_set(pg->pmc, pg->id, true);
762 if (err < 0)
763 return err;
764
765 usleep_range(10, 20);
766
767 err = tegra_powergate_prepare_clocks(pg);
768 if (err)
769 goto powergate_off;
770
771 err = tegra_powergate_enable_clocks(pg);
772 if (err)
773 goto unprepare_clks;
774
775 usleep_range(10, 20);
776
777 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);
778 if (err)
779 goto disable_clks;
780
781 usleep_range(10, 20);
782
783 err = reset_control_deassert(pg->reset);
784 if (err)
785 goto powergate_off;
786
787 usleep_range(10, 20);
788
789 if (pg->pmc->soc->needs_mbist_war)
790 err = tegra210_clk_handle_mbist_war(pg->id);
791 if (err)
792 goto disable_clks;
793
794 if (disable_clocks)
795 tegra_powergate_disable_clocks(pg);
796
797 err = tegra_powergate_unprepare_clocks(pg);
798 if (err)
799 return err;
800
801 return 0;
802
803disable_clks:
804 tegra_powergate_disable_clocks(pg);
805 usleep_range(10, 20);
806
807unprepare_clks:
808 tegra_powergate_unprepare_clocks(pg);
809
810powergate_off:
811 tegra_powergate_set(pg->pmc, pg->id, false);
812
813 return err;
814}
815
816static int tegra_powergate_power_down(struct tegra_powergate *pg)
817{
818 int err;
819
820 err = tegra_powergate_prepare_clocks(pg);
821 if (err)
822 return err;
823
824 err = tegra_powergate_enable_clocks(pg);
825 if (err)
826 goto unprepare_clks;
827
828 usleep_range(10, 20);
829
830 err = reset_control_assert(pg->reset);
831 if (err)
832 goto disable_clks;
833
834 usleep_range(10, 20);
835
836 tegra_powergate_disable_clocks(pg);
837
838 usleep_range(10, 20);
839
840 err = tegra_powergate_set(pg->pmc, pg->id, false);
841 if (err)
842 goto assert_resets;
843
844 err = tegra_powergate_unprepare_clocks(pg);
845 if (err)
846 return err;
847
848 return 0;
849
850assert_resets:
851 tegra_powergate_enable_clocks(pg);
852 usleep_range(10, 20);
853 reset_control_deassert(pg->reset);
854 usleep_range(10, 20);
855
856disable_clks:
857 tegra_powergate_disable_clocks(pg);
858
859unprepare_clks:
860 tegra_powergate_unprepare_clocks(pg);
861
862 return err;
863}
864
865static int tegra_genpd_power_on(struct generic_pm_domain *domain)
866{
867 struct tegra_powergate *pg = to_powergate(domain);
868 struct device *dev = pg->pmc->dev;
869 int err;
870
871 err = tegra_powergate_power_up(pg, true);
872 if (err) {
873 dev_err(dev, "failed to turn on PM domain %s: %d\n",
874 pg->genpd.name, err);
875 goto out;
876 }
877
878 reset_control_release(pg->reset);
879
880out:
881 return err;
882}
883
884static int tegra_genpd_power_off(struct generic_pm_domain *domain)
885{
886 struct tegra_powergate *pg = to_powergate(domain);
887 struct device *dev = pg->pmc->dev;
888 int err;
889
890 err = reset_control_acquire(pg->reset);
891 if (err < 0) {
892 dev_err(dev, "failed to acquire resets for PM domain %s: %d\n",
893 pg->genpd.name, err);
894 return err;
895 }
896
897 err = tegra_powergate_power_down(pg);
898 if (err) {
899 dev_err(dev, "failed to turn off PM domain %s: %d\n",
900 pg->genpd.name, err);
901 reset_control_release(pg->reset);
902 }
903
904 return err;
905}
906
907/**
908 * tegra_powergate_power_on() - power on partition
909 * @id: partition ID
910 */
911int tegra_powergate_power_on(unsigned int id)
912{
913 if (!tegra_powergate_is_available(pmc, id))
914 return -EINVAL;
915
916 return tegra_powergate_set(pmc, id, true);
917}
918EXPORT_SYMBOL(tegra_powergate_power_on);
919
920/**
921 * tegra_powergate_power_off() - power off partition
922 * @id: partition ID
923 */
924int tegra_powergate_power_off(unsigned int id)
925{
926 if (!tegra_powergate_is_available(pmc, id))
927 return -EINVAL;
928
929 return tegra_powergate_set(pmc, id, false);
930}
931EXPORT_SYMBOL(tegra_powergate_power_off);
932
933/**
934 * tegra_powergate_is_powered() - check if partition is powered
935 * @pmc: power management controller
936 * @id: partition ID
937 */
938static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id)
939{
940 if (!tegra_powergate_is_valid(pmc, id))
941 return -EINVAL;
942
943 return tegra_powergate_state(id);
944}
945
946/**
947 * tegra_powergate_remove_clamping() - remove power clamps for partition
948 * @id: partition ID
949 */
950int tegra_powergate_remove_clamping(unsigned int id)
951{
952 if (!tegra_powergate_is_available(pmc, id))
953 return -EINVAL;
954
955 return __tegra_powergate_remove_clamping(pmc, id);
956}
957EXPORT_SYMBOL(tegra_powergate_remove_clamping);
958
959/**
960 * tegra_powergate_sequence_power_up() - power up partition
961 * @id: partition ID
962 * @clk: clock for partition
963 * @rst: reset for partition
964 *
965 * Must be called with clk disabled, and returns with clk enabled.
966 */
967int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
968 struct reset_control *rst)
969{
970 struct tegra_powergate *pg;
971 int err;
972
973 if (!tegra_powergate_is_available(pmc, id))
974 return -EINVAL;
975
976 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
977 if (!pg)
978 return -ENOMEM;
979
980 pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL);
981 if (!pg->clk_rates) {
982 kfree(pg->clks);
983 return -ENOMEM;
984 }
985
986 pg->id = id;
987 pg->clks = &clk;
988 pg->num_clks = 1;
989 pg->reset = rst;
990 pg->pmc = pmc;
991
992 err = tegra_powergate_power_up(pg, false);
993 if (err)
994 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,
995 err);
996
997 kfree(pg->clk_rates);
998 kfree(pg);
999
1000 return err;
1001}
1002EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
1003
1004/**
1005 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
1006 * @pmc: power management controller
1007 * @cpuid: CPU partition ID
1008 *
1009 * Returns the partition ID corresponding to the CPU partition ID or a
1010 * negative error code on failure.
1011 */
1012static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc,
1013 unsigned int cpuid)
1014{
1015 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
1016 return pmc->soc->cpu_powergates[cpuid];
1017
1018 return -EINVAL;
1019}
1020
1021/**
1022 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
1023 * @cpuid: CPU partition ID
1024 */
1025bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
1026{
1027 int id;
1028
1029 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1030 if (id < 0)
1031 return false;
1032
1033 return tegra_powergate_is_powered(pmc, id);
1034}
1035
1036/**
1037 * tegra_pmc_cpu_power_on() - power on CPU partition
1038 * @cpuid: CPU partition ID
1039 */
1040int tegra_pmc_cpu_power_on(unsigned int cpuid)
1041{
1042 int id;
1043
1044 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1045 if (id < 0)
1046 return id;
1047
1048 return tegra_powergate_set(pmc, id, true);
1049}
1050
1051/**
1052 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
1053 * @cpuid: CPU partition ID
1054 */
1055int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
1056{
1057 int id;
1058
1059 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1060 if (id < 0)
1061 return id;
1062
1063 return tegra_powergate_remove_clamping(id);
1064}
1065
1066static int tegra_pmc_restart_notify(struct notifier_block *this,
1067 unsigned long action, void *data)
1068{
1069 const char *cmd = data;
1070 u32 value;
1071
1072 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0);
1073 value &= ~PMC_SCRATCH0_MODE_MASK;
1074
1075 if (cmd) {
1076 if (strcmp(cmd, "recovery") == 0)
1077 value |= PMC_SCRATCH0_MODE_RECOVERY;
1078
1079 if (strcmp(cmd, "bootloader") == 0)
1080 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
1081
1082 if (strcmp(cmd, "forced-recovery") == 0)
1083 value |= PMC_SCRATCH0_MODE_RCM;
1084 }
1085
1086 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);
1087
1088 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
1089 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1090 value |= PMC_CNTRL_MAIN_RST;
1091 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1092
1093 return NOTIFY_DONE;
1094}
1095
1096static struct notifier_block tegra_pmc_restart_handler = {
1097 .notifier_call = tegra_pmc_restart_notify,
1098 .priority = 128,
1099};
1100
1101static int powergate_show(struct seq_file *s, void *data)
1102{
1103 unsigned int i;
1104 int status;
1105
1106 seq_printf(s, " powergate powered\n");
1107 seq_printf(s, "------------------\n");
1108
1109 for (i = 0; i < pmc->soc->num_powergates; i++) {
1110 status = tegra_powergate_is_powered(pmc, i);
1111 if (status < 0)
1112 continue;
1113
1114 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
1115 status ? "yes" : "no");
1116 }
1117
1118 return 0;
1119}
1120
1121DEFINE_SHOW_ATTRIBUTE(powergate);
1122
1123static int tegra_powergate_debugfs_init(void)
1124{
1125 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
1126 &powergate_fops);
1127 if (!pmc->debugfs)
1128 return -ENOMEM;
1129
1130 return 0;
1131}
1132
1133static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
1134 struct device_node *np)
1135{
1136 struct clk *clk;
1137 unsigned int i, count;
1138 int err;
1139
1140 count = of_clk_get_parent_count(np);
1141 if (count == 0)
1142 return -ENODEV;
1143
1144 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
1145 if (!pg->clks)
1146 return -ENOMEM;
1147
1148 pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL);
1149 if (!pg->clk_rates) {
1150 kfree(pg->clks);
1151 return -ENOMEM;
1152 }
1153
1154 for (i = 0; i < count; i++) {
1155 pg->clks[i] = of_clk_get(np, i);
1156 if (IS_ERR(pg->clks[i])) {
1157 err = PTR_ERR(pg->clks[i]);
1158 goto err;
1159 }
1160 }
1161
1162 pg->num_clks = count;
1163
1164 return 0;
1165
1166err:
1167 while (i--)
1168 clk_put(pg->clks[i]);
1169
1170 kfree(pg->clk_rates);
1171 kfree(pg->clks);
1172
1173 return err;
1174}
1175
1176static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
1177 struct device_node *np, bool off)
1178{
1179 struct device *dev = pg->pmc->dev;
1180 int err;
1181
1182 pg->reset = of_reset_control_array_get_exclusive_released(np);
1183 if (IS_ERR(pg->reset)) {
1184 err = PTR_ERR(pg->reset);
1185 dev_err(dev, "failed to get device resets: %d\n", err);
1186 return err;
1187 }
1188
1189 err = reset_control_acquire(pg->reset);
1190 if (err < 0) {
1191 pr_err("failed to acquire resets: %d\n", err);
1192 goto out;
1193 }
1194
1195 if (off) {
1196 err = reset_control_assert(pg->reset);
1197 } else {
1198 err = reset_control_deassert(pg->reset);
1199 if (err < 0)
1200 goto out;
1201
1202 reset_control_release(pg->reset);
1203 }
1204
1205out:
1206 if (err) {
1207 reset_control_release(pg->reset);
1208 reset_control_put(pg->reset);
1209 }
1210
1211 return err;
1212}
1213
1214static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
1215{
1216 struct device *dev = pmc->dev;
1217 struct tegra_powergate *pg;
1218 int id, err = 0;
1219 bool off;
1220
1221 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
1222 if (!pg)
1223 return -ENOMEM;
1224
1225 id = tegra_powergate_lookup(pmc, np->name);
1226 if (id < 0) {
1227 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id);
1228 err = -ENODEV;
1229 goto free_mem;
1230 }
1231
1232 /*
1233 * Clear the bit for this powergate so it cannot be managed
1234 * directly via the legacy APIs for controlling powergates.
1235 */
1236 clear_bit(id, pmc->powergates_available);
1237
1238 pg->id = id;
1239 pg->genpd.name = np->name;
1240 pg->genpd.power_off = tegra_genpd_power_off;
1241 pg->genpd.power_on = tegra_genpd_power_on;
1242 pg->pmc = pmc;
1243
1244 off = !tegra_powergate_is_powered(pmc, pg->id);
1245
1246 err = tegra_powergate_of_get_clks(pg, np);
1247 if (err < 0) {
1248 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err);
1249 goto set_available;
1250 }
1251
1252 err = tegra_powergate_of_get_resets(pg, np, off);
1253 if (err < 0) {
1254 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err);
1255 goto remove_clks;
1256 }
1257
1258 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
1259 if (off)
1260 WARN_ON(tegra_powergate_power_up(pg, true));
1261
1262 goto remove_resets;
1263 }
1264
1265 err = pm_genpd_init(&pg->genpd, NULL, off);
1266 if (err < 0) {
1267 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np,
1268 err);
1269 goto remove_resets;
1270 }
1271
1272 err = of_genpd_add_provider_simple(np, &pg->genpd);
1273 if (err < 0) {
1274 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n",
1275 np, err);
1276 goto remove_genpd;
1277 }
1278
1279 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name);
1280
1281 return 0;
1282
1283remove_genpd:
1284 pm_genpd_remove(&pg->genpd);
1285
1286remove_resets:
1287 reset_control_put(pg->reset);
1288
1289remove_clks:
1290 while (pg->num_clks--)
1291 clk_put(pg->clks[pg->num_clks]);
1292
1293 kfree(pg->clks);
1294
1295set_available:
1296 set_bit(id, pmc->powergates_available);
1297
1298free_mem:
1299 kfree(pg);
1300
1301 return err;
1302}
1303
1304bool tegra_pmc_core_domain_state_synced(void)
1305{
1306 return pmc->core_domain_state_synced;
1307}
1308
1309static int
1310tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain *genpd,
1311 unsigned int level)
1312{
1313 struct dev_pm_opp *opp;
1314 int err;
1315
1316 opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level);
1317 if (IS_ERR(opp)) {
1318 dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n",
1319 level, opp);
1320 return PTR_ERR(opp);
1321 }
1322
1323 mutex_lock(&pmc->powergates_lock);
1324 err = dev_pm_opp_set_opp(pmc->dev, opp);
1325 mutex_unlock(&pmc->powergates_lock);
1326
1327 dev_pm_opp_put(opp);
1328
1329 if (err) {
1330 dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n",
1331 level, err);
1332 return err;
1333 }
1334
1335 return 0;
1336}
1337
1338static unsigned int
1339tegra_pmc_core_pd_opp_to_performance_state(struct generic_pm_domain *genpd,
1340 struct dev_pm_opp *opp)
1341{
1342 return dev_pm_opp_get_level(opp);
1343}
1344
1345static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np)
1346{
1347 struct generic_pm_domain *genpd;
1348 const char *rname = "core";
1349 int err;
1350
1351 genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL);
1352 if (!genpd)
1353 return -ENOMEM;
1354
1355 genpd->name = np->name;
1356 genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state;
1357 genpd->opp_to_performance_state = tegra_pmc_core_pd_opp_to_performance_state;
1358
1359 err = devm_pm_opp_set_regulators(pmc->dev, &rname, 1);
1360 if (err)
1361 return dev_err_probe(pmc->dev, err,
1362 "failed to set core OPP regulator\n");
1363
1364 err = pm_genpd_init(genpd, NULL, false);
1365 if (err) {
1366 dev_err(pmc->dev, "failed to init core genpd: %d\n", err);
1367 return err;
1368 }
1369
1370 err = of_genpd_add_provider_simple(np, genpd);
1371 if (err) {
1372 dev_err(pmc->dev, "failed to add core genpd: %d\n", err);
1373 goto remove_genpd;
1374 }
1375
1376 pmc->core_domain_registered = true;
1377
1378 return 0;
1379
1380remove_genpd:
1381 pm_genpd_remove(genpd);
1382
1383 return err;
1384}
1385
1386static int tegra_powergate_init(struct tegra_pmc *pmc,
1387 struct device_node *parent)
1388{
1389 struct of_phandle_args child_args, parent_args;
1390 struct device_node *np, *child;
1391 int err = 0;
1392
1393 /*
1394 * Core power domain is the parent of powergate domains, hence it
1395 * should be registered first.
1396 */
1397 np = of_get_child_by_name(parent, "core-domain");
1398 if (np) {
1399 err = tegra_pmc_core_pd_add(pmc, np);
1400 of_node_put(np);
1401 if (err)
1402 return err;
1403 }
1404
1405 np = of_get_child_by_name(parent, "powergates");
1406 if (!np)
1407 return 0;
1408
1409 for_each_child_of_node(np, child) {
1410 err = tegra_powergate_add(pmc, child);
1411 if (err < 0) {
1412 of_node_put(child);
1413 break;
1414 }
1415
1416 if (of_parse_phandle_with_args(child, "power-domains",
1417 "#power-domain-cells",
1418 0, &parent_args))
1419 continue;
1420
1421 child_args.np = child;
1422 child_args.args_count = 0;
1423
1424 err = of_genpd_add_subdomain(&parent_args, &child_args);
1425 of_node_put(parent_args.np);
1426 if (err) {
1427 of_node_put(child);
1428 break;
1429 }
1430 }
1431
1432 of_node_put(np);
1433
1434 return err;
1435}
1436
1437static void tegra_powergate_remove(struct generic_pm_domain *genpd)
1438{
1439 struct tegra_powergate *pg = to_powergate(genpd);
1440
1441 reset_control_put(pg->reset);
1442
1443 while (pg->num_clks--)
1444 clk_put(pg->clks[pg->num_clks]);
1445
1446 kfree(pg->clks);
1447
1448 set_bit(pg->id, pmc->powergates_available);
1449
1450 kfree(pg);
1451}
1452
1453static void tegra_powergate_remove_all(struct device_node *parent)
1454{
1455 struct generic_pm_domain *genpd;
1456 struct device_node *np, *child;
1457
1458 np = of_get_child_by_name(parent, "powergates");
1459 if (!np)
1460 return;
1461
1462 for_each_child_of_node(np, child) {
1463 of_genpd_del_provider(child);
1464
1465 genpd = of_genpd_remove_last(child);
1466 if (IS_ERR(genpd))
1467 continue;
1468
1469 tegra_powergate_remove(genpd);
1470 }
1471
1472 of_node_put(np);
1473
1474 np = of_get_child_by_name(parent, "core-domain");
1475 if (np) {
1476 of_genpd_del_provider(np);
1477 of_genpd_remove_last(np);
1478 }
1479}
1480
1481static const struct tegra_io_pad_soc *
1482tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
1483{
1484 unsigned int i;
1485
1486 for (i = 0; i < pmc->soc->num_io_pads; i++)
1487 if (pmc->soc->io_pads[i].id == id)
1488 return &pmc->soc->io_pads[i];
1489
1490 return NULL;
1491}
1492
1493static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc,
1494 enum tegra_io_pad id,
1495 unsigned long *request,
1496 unsigned long *status,
1497 u32 *mask)
1498{
1499 const struct tegra_io_pad_soc *pad;
1500
1501 pad = tegra_io_pad_find(pmc, id);
1502 if (!pad) {
1503 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1504 return -ENOENT;
1505 }
1506
1507 if (pad->dpd == UINT_MAX)
1508 return -ENOTSUPP;
1509
1510 *mask = BIT(pad->dpd % 32);
1511
1512 if (pad->dpd < 32) {
1513 *status = pmc->soc->regs->dpd_status;
1514 *request = pmc->soc->regs->dpd_req;
1515 } else {
1516 *status = pmc->soc->regs->dpd2_status;
1517 *request = pmc->soc->regs->dpd2_req;
1518 }
1519
1520 return 0;
1521}
1522
1523static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id,
1524 unsigned long *request, unsigned long *status,
1525 u32 *mask)
1526{
1527 unsigned long rate, value;
1528 int err;
1529
1530 err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask);
1531 if (err)
1532 return err;
1533
1534 if (pmc->clk) {
1535 rate = pmc->rate;
1536 if (!rate) {
1537 dev_err(pmc->dev, "failed to get clock rate\n");
1538 return -ENODEV;
1539 }
1540
1541 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);
1542
1543 /* must be at least 200 ns, in APB (PCLK) clock cycles */
1544 value = DIV_ROUND_UP(1000000000, rate);
1545 value = DIV_ROUND_UP(200, value);
1546 tegra_pmc_writel(pmc, value, SEL_DPD_TIM);
1547 }
1548
1549 return 0;
1550}
1551
1552static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset,
1553 u32 mask, u32 val, unsigned long timeout)
1554{
1555 u32 value;
1556
1557 timeout = jiffies + msecs_to_jiffies(timeout);
1558
1559 while (time_after(timeout, jiffies)) {
1560 value = tegra_pmc_readl(pmc, offset);
1561 if ((value & mask) == val)
1562 return 0;
1563
1564 usleep_range(250, 1000);
1565 }
1566
1567 return -ETIMEDOUT;
1568}
1569
1570static void tegra_io_pad_unprepare(struct tegra_pmc *pmc)
1571{
1572 if (pmc->clk)
1573 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);
1574}
1575
1576/**
1577 * tegra_io_pad_power_enable() - enable power to I/O pad
1578 * @id: Tegra I/O pad ID for which to enable power
1579 *
1580 * Returns: 0 on success or a negative error code on failure.
1581 */
1582int tegra_io_pad_power_enable(enum tegra_io_pad id)
1583{
1584 unsigned long request, status;
1585 u32 mask;
1586 int err;
1587
1588 mutex_lock(&pmc->powergates_lock);
1589
1590 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1591 if (err < 0) {
1592 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1593 goto unlock;
1594 }
1595
1596 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request);
1597
1598 err = tegra_io_pad_poll(pmc, status, mask, 0, 250);
1599 if (err < 0) {
1600 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err);
1601 goto unlock;
1602 }
1603
1604 tegra_io_pad_unprepare(pmc);
1605
1606unlock:
1607 mutex_unlock(&pmc->powergates_lock);
1608 return err;
1609}
1610EXPORT_SYMBOL(tegra_io_pad_power_enable);
1611
1612/**
1613 * tegra_io_pad_power_disable() - disable power to I/O pad
1614 * @id: Tegra I/O pad ID for which to disable power
1615 *
1616 * Returns: 0 on success or a negative error code on failure.
1617 */
1618int tegra_io_pad_power_disable(enum tegra_io_pad id)
1619{
1620 unsigned long request, status;
1621 u32 mask;
1622 int err;
1623
1624 mutex_lock(&pmc->powergates_lock);
1625
1626 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1627 if (err < 0) {
1628 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1629 goto unlock;
1630 }
1631
1632 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request);
1633
1634 err = tegra_io_pad_poll(pmc, status, mask, mask, 250);
1635 if (err < 0) {
1636 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err);
1637 goto unlock;
1638 }
1639
1640 tegra_io_pad_unprepare(pmc);
1641
1642unlock:
1643 mutex_unlock(&pmc->powergates_lock);
1644 return err;
1645}
1646EXPORT_SYMBOL(tegra_io_pad_power_disable);
1647
1648static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id)
1649{
1650 unsigned long request, status;
1651 u32 mask, value;
1652 int err;
1653
1654 err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status,
1655 &mask);
1656 if (err)
1657 return err;
1658
1659 value = tegra_pmc_readl(pmc, status);
1660
1661 return !(value & mask);
1662}
1663
1664static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,
1665 int voltage)
1666{
1667 const struct tegra_io_pad_soc *pad;
1668 u32 value;
1669
1670 pad = tegra_io_pad_find(pmc, id);
1671 if (!pad)
1672 return -ENOENT;
1673
1674 if (pad->voltage == UINT_MAX)
1675 return -ENOTSUPP;
1676
1677 mutex_lock(&pmc->powergates_lock);
1678
1679 if (pmc->soc->has_impl_33v_pwr) {
1680 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1681
1682 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1683 value &= ~BIT(pad->voltage);
1684 else
1685 value |= BIT(pad->voltage);
1686
1687 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);
1688 } else {
1689 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
1690 value = tegra_pmc_readl(pmc, PMC_PWR_DET);
1691 value |= BIT(pad->voltage);
1692 tegra_pmc_writel(pmc, value, PMC_PWR_DET);
1693
1694 /* update I/O voltage */
1695 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1696
1697 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1698 value &= ~BIT(pad->voltage);
1699 else
1700 value |= BIT(pad->voltage);
1701
1702 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);
1703 }
1704
1705 mutex_unlock(&pmc->powergates_lock);
1706
1707 usleep_range(100, 250);
1708
1709 return 0;
1710}
1711
1712static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id)
1713{
1714 const struct tegra_io_pad_soc *pad;
1715 u32 value;
1716
1717 pad = tegra_io_pad_find(pmc, id);
1718 if (!pad)
1719 return -ENOENT;
1720
1721 if (pad->voltage == UINT_MAX)
1722 return -ENOTSUPP;
1723
1724 if (pmc->soc->has_impl_33v_pwr)
1725 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1726 else
1727 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1728
1729 if ((value & BIT(pad->voltage)) == 0)
1730 return TEGRA_IO_PAD_VOLTAGE_1V8;
1731
1732 return TEGRA_IO_PAD_VOLTAGE_3V3;
1733}
1734
1735/**
1736 * tegra_io_rail_power_on() - enable power to I/O rail
1737 * @id: Tegra I/O pad ID for which to enable power
1738 *
1739 * See also: tegra_io_pad_power_enable()
1740 */
1741int tegra_io_rail_power_on(unsigned int id)
1742{
1743 return tegra_io_pad_power_enable(id);
1744}
1745EXPORT_SYMBOL(tegra_io_rail_power_on);
1746
1747/**
1748 * tegra_io_rail_power_off() - disable power to I/O rail
1749 * @id: Tegra I/O pad ID for which to disable power
1750 *
1751 * See also: tegra_io_pad_power_disable()
1752 */
1753int tegra_io_rail_power_off(unsigned int id)
1754{
1755 return tegra_io_pad_power_disable(id);
1756}
1757EXPORT_SYMBOL(tegra_io_rail_power_off);
1758
1759#ifdef CONFIG_PM_SLEEP
1760enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1761{
1762 return pmc->suspend_mode;
1763}
1764
1765void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1766{
1767 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1768 return;
1769
1770 pmc->suspend_mode = mode;
1771}
1772
1773void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1774{
1775 unsigned long long rate = 0;
1776 u64 ticks;
1777 u32 value;
1778
1779 switch (mode) {
1780 case TEGRA_SUSPEND_LP1:
1781 rate = 32768;
1782 break;
1783
1784 case TEGRA_SUSPEND_LP2:
1785 rate = pmc->rate;
1786 break;
1787
1788 default:
1789 break;
1790 }
1791
1792 if (WARN_ON_ONCE(rate == 0))
1793 rate = 100000000;
1794
1795 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1796 do_div(ticks, USEC_PER_SEC);
1797 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);
1798
1799 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1800 do_div(ticks, USEC_PER_SEC);
1801 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
1802
1803 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1804 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1805 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1806 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1807}
1808#endif
1809
1810static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1811{
1812 u32 value, values[2];
1813
1814 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1815 } else {
1816 switch (value) {
1817 case 0:
1818 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1819 break;
1820
1821 case 1:
1822 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1823 break;
1824
1825 case 2:
1826 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1827 break;
1828
1829 default:
1830 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1831 break;
1832 }
1833 }
1834
1835 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1836
1837 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1838 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1839
1840 pmc->cpu_good_time = value;
1841
1842 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1843 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1844
1845 pmc->cpu_off_time = value;
1846
1847 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1848 values, ARRAY_SIZE(values)))
1849 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1850
1851 pmc->core_osc_time = values[0];
1852 pmc->core_pmu_time = values[1];
1853
1854 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1855 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1856
1857 pmc->core_off_time = value;
1858
1859 pmc->corereq_high = of_property_read_bool(np,
1860 "nvidia,core-power-req-active-high");
1861
1862 pmc->sysclkreq_high = of_property_read_bool(np,
1863 "nvidia,sys-clock-req-active-high");
1864
1865 pmc->combined_req = of_property_read_bool(np,
1866 "nvidia,combined-power-req");
1867
1868 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1869 "nvidia,cpu-pwr-good-en");
1870
1871 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1872 ARRAY_SIZE(values)))
1873 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1874 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1875
1876 pmc->lp0_vec_phys = values[0];
1877 pmc->lp0_vec_size = values[1];
1878
1879 return 0;
1880}
1881
1882static void tegra_pmc_init(struct tegra_pmc *pmc)
1883{
1884 if (pmc->soc->init)
1885 pmc->soc->init(pmc);
1886}
1887
1888static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1889{
1890 static const char disabled[] = "emergency thermal reset disabled";
1891 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1892 struct device *dev = pmc->dev;
1893 struct device_node *np;
1894 u32 value, checksum;
1895
1896 if (!pmc->soc->has_tsense_reset)
1897 return;
1898
1899 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip");
1900 if (!np) {
1901 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1902 return;
1903 }
1904
1905 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1906 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1907 goto out;
1908 }
1909
1910 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1911 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1912 goto out;
1913 }
1914
1915 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) {
1916 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1917 goto out;
1918 }
1919
1920 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) {
1921 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
1922 goto out;
1923 }
1924
1925 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
1926 pinmux = 0;
1927
1928 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1929 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1930 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1931
1932 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
1933 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
1934 tegra_pmc_writel(pmc, value, PMC_SCRATCH54);
1935
1936 value = PMC_SCRATCH55_RESET_TEGRA;
1937 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
1938 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
1939 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
1940
1941 /*
1942 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
1943 * contain the checksum and are currently zero, so they are not added.
1944 */
1945 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
1946 + ((value >> 24) & 0xff);
1947 checksum &= 0xff;
1948 checksum = 0x100 - checksum;
1949
1950 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
1951
1952 tegra_pmc_writel(pmc, value, PMC_SCRATCH55);
1953
1954 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1955 value |= PMC_SENSOR_CTRL_ENABLE_RST;
1956 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1957
1958 dev_info(pmc->dev, "emergency thermal reset enabled\n");
1959
1960out:
1961 of_node_put(np);
1962}
1963
1964static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev)
1965{
1966 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1967
1968 return pmc->soc->num_io_pads;
1969}
1970
1971static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl,
1972 unsigned int group)
1973{
1974 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl);
1975
1976 return pmc->soc->io_pads[group].name;
1977}
1978
1979static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev,
1980 unsigned int group,
1981 const unsigned int **pins,
1982 unsigned int *num_pins)
1983{
1984 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1985
1986 *pins = &pmc->soc->io_pads[group].id;
1987 *num_pins = 1;
1988
1989 return 0;
1990}
1991
1992static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = {
1993 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count,
1994 .get_group_name = tegra_io_pad_pinctrl_get_group_name,
1995 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins,
1996 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1997 .dt_free_map = pinconf_generic_dt_free_map,
1998};
1999
2000static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev,
2001 unsigned int pin, unsigned long *config)
2002{
2003 enum pin_config_param param = pinconf_to_config_param(*config);
2004 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2005 const struct tegra_io_pad_soc *pad;
2006 int ret;
2007 u32 arg;
2008
2009 pad = tegra_io_pad_find(pmc, pin);
2010 if (!pad)
2011 return -EINVAL;
2012
2013 switch (param) {
2014 case PIN_CONFIG_POWER_SOURCE:
2015 ret = tegra_io_pad_get_voltage(pmc, pad->id);
2016 if (ret < 0)
2017 return ret;
2018
2019 arg = ret;
2020 break;
2021
2022 case PIN_CONFIG_MODE_LOW_POWER:
2023 ret = tegra_io_pad_is_powered(pmc, pad->id);
2024 if (ret < 0)
2025 return ret;
2026
2027 arg = !ret;
2028 break;
2029
2030 default:
2031 return -EINVAL;
2032 }
2033
2034 *config = pinconf_to_config_packed(param, arg);
2035
2036 return 0;
2037}
2038
2039static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev,
2040 unsigned int pin, unsigned long *configs,
2041 unsigned int num_configs)
2042{
2043 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2044 const struct tegra_io_pad_soc *pad;
2045 enum pin_config_param param;
2046 unsigned int i;
2047 int err;
2048 u32 arg;
2049
2050 pad = tegra_io_pad_find(pmc, pin);
2051 if (!pad)
2052 return -EINVAL;
2053
2054 for (i = 0; i < num_configs; ++i) {
2055 param = pinconf_to_config_param(configs[i]);
2056 arg = pinconf_to_config_argument(configs[i]);
2057
2058 switch (param) {
2059 case PIN_CONFIG_MODE_LOW_POWER:
2060 if (arg)
2061 err = tegra_io_pad_power_disable(pad->id);
2062 else
2063 err = tegra_io_pad_power_enable(pad->id);
2064 if (err)
2065 return err;
2066 break;
2067 case PIN_CONFIG_POWER_SOURCE:
2068 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 &&
2069 arg != TEGRA_IO_PAD_VOLTAGE_3V3)
2070 return -EINVAL;
2071 err = tegra_io_pad_set_voltage(pmc, pad->id, arg);
2072 if (err)
2073 return err;
2074 break;
2075 default:
2076 return -EINVAL;
2077 }
2078 }
2079
2080 return 0;
2081}
2082
2083static const struct pinconf_ops tegra_io_pad_pinconf_ops = {
2084 .pin_config_get = tegra_io_pad_pinconf_get,
2085 .pin_config_set = tegra_io_pad_pinconf_set,
2086 .is_generic = true,
2087};
2088
2089static struct pinctrl_desc tegra_pmc_pctl_desc = {
2090 .pctlops = &tegra_io_pad_pinctrl_ops,
2091 .confops = &tegra_io_pad_pinconf_ops,
2092};
2093
2094static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc)
2095{
2096 int err;
2097
2098 if (!pmc->soc->num_pin_descs)
2099 return 0;
2100
2101 tegra_pmc_pctl_desc.name = dev_name(pmc->dev);
2102 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs;
2103 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs;
2104
2105 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc,
2106 pmc);
2107 if (IS_ERR(pmc->pctl_dev)) {
2108 err = PTR_ERR(pmc->pctl_dev);
2109 dev_err(pmc->dev, "failed to register pin controller: %d\n",
2110 err);
2111 return err;
2112 }
2113
2114 return 0;
2115}
2116
2117static ssize_t reset_reason_show(struct device *dev,
2118 struct device_attribute *attr, char *buf)
2119{
2120 u32 value;
2121
2122 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
2123 value &= pmc->soc->regs->rst_source_mask;
2124 value >>= pmc->soc->regs->rst_source_shift;
2125
2126 if (WARN_ON(value >= pmc->soc->num_reset_sources))
2127 return sprintf(buf, "%s\n", "UNKNOWN");
2128
2129 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);
2130}
2131
2132static DEVICE_ATTR_RO(reset_reason);
2133
2134static ssize_t reset_level_show(struct device *dev,
2135 struct device_attribute *attr, char *buf)
2136{
2137 u32 value;
2138
2139 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
2140 value &= pmc->soc->regs->rst_level_mask;
2141 value >>= pmc->soc->regs->rst_level_shift;
2142
2143 if (WARN_ON(value >= pmc->soc->num_reset_levels))
2144 return sprintf(buf, "%s\n", "UNKNOWN");
2145
2146 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);
2147}
2148
2149static DEVICE_ATTR_RO(reset_level);
2150
2151static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc)
2152{
2153 struct device *dev = pmc->dev;
2154 int err = 0;
2155
2156 if (pmc->soc->reset_sources) {
2157 err = device_create_file(dev, &dev_attr_reset_reason);
2158 if (err < 0)
2159 dev_warn(dev,
2160 "failed to create attr \"reset_reason\": %d\n",
2161 err);
2162 }
2163
2164 if (pmc->soc->reset_levels) {
2165 err = device_create_file(dev, &dev_attr_reset_level);
2166 if (err < 0)
2167 dev_warn(dev,
2168 "failed to create attr \"reset_level\": %d\n",
2169 err);
2170 }
2171}
2172
2173static int tegra_pmc_irq_translate(struct irq_domain *domain,
2174 struct irq_fwspec *fwspec,
2175 unsigned long *hwirq,
2176 unsigned int *type)
2177{
2178 if (WARN_ON(fwspec->param_count < 2))
2179 return -EINVAL;
2180
2181 *hwirq = fwspec->param[0];
2182 *type = fwspec->param[1];
2183
2184 return 0;
2185}
2186
2187static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq,
2188 unsigned int num_irqs, void *data)
2189{
2190 struct tegra_pmc *pmc = domain->host_data;
2191 const struct tegra_pmc_soc *soc = pmc->soc;
2192 struct irq_fwspec *fwspec = data;
2193 unsigned int i;
2194 int err = 0;
2195
2196 if (WARN_ON(num_irqs > 1))
2197 return -EINVAL;
2198
2199 for (i = 0; i < soc->num_wake_events; i++) {
2200 const struct tegra_wake_event *event = &soc->wake_events[i];
2201
2202 if (fwspec->param_count == 2) {
2203 struct irq_fwspec spec;
2204
2205 if (event->id != fwspec->param[0])
2206 continue;
2207
2208 err = irq_domain_set_hwirq_and_chip(domain, virq,
2209 event->id,
2210 &pmc->irq, pmc);
2211 if (err < 0)
2212 break;
2213
2214 spec.fwnode = &pmc->dev->of_node->fwnode;
2215 spec.param_count = 3;
2216 spec.param[0] = GIC_SPI;
2217 spec.param[1] = event->irq;
2218 spec.param[2] = fwspec->param[1];
2219
2220 err = irq_domain_alloc_irqs_parent(domain, virq,
2221 num_irqs, &spec);
2222
2223 break;
2224 }
2225
2226 if (fwspec->param_count == 3) {
2227 if (event->gpio.instance != fwspec->param[0] ||
2228 event->gpio.pin != fwspec->param[1])
2229 continue;
2230
2231 err = irq_domain_set_hwirq_and_chip(domain, virq,
2232 event->id,
2233 &pmc->irq, pmc);
2234
2235 /* GPIO hierarchies stop at the PMC level */
2236 if (!err && domain->parent)
2237 err = irq_domain_disconnect_hierarchy(domain->parent,
2238 virq);
2239 break;
2240 }
2241 }
2242
2243 /* If there is no wake-up event, there is no PMC mapping */
2244 if (i == soc->num_wake_events)
2245 err = irq_domain_disconnect_hierarchy(domain, virq);
2246
2247 return err;
2248}
2249
2250static const struct irq_domain_ops tegra_pmc_irq_domain_ops = {
2251 .translate = tegra_pmc_irq_translate,
2252 .alloc = tegra_pmc_irq_alloc,
2253};
2254
2255static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2256{
2257 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2258 unsigned int offset, bit;
2259 u32 value;
2260
2261 offset = data->hwirq / 32;
2262 bit = data->hwirq % 32;
2263
2264 /* clear wake status */
2265 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);
2266 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);
2267
2268 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);
2269 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);
2270
2271 /* enable PMC wake */
2272 if (data->hwirq >= 32)
2273 offset = PMC_WAKE2_MASK;
2274 else
2275 offset = PMC_WAKE_MASK;
2276
2277 value = tegra_pmc_readl(pmc, offset);
2278
2279 if (on)
2280 value |= BIT(bit);
2281 else
2282 value &= ~BIT(bit);
2283
2284 tegra_pmc_writel(pmc, value, offset);
2285
2286 return 0;
2287}
2288
2289static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2290{
2291 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2292 unsigned int offset, bit;
2293 u32 value;
2294
2295 offset = data->hwirq / 32;
2296 bit = data->hwirq % 32;
2297
2298 if (data->hwirq >= 32)
2299 offset = PMC_WAKE2_LEVEL;
2300 else
2301 offset = PMC_WAKE_LEVEL;
2302
2303 value = tegra_pmc_readl(pmc, offset);
2304
2305 switch (type) {
2306 case IRQ_TYPE_EDGE_RISING:
2307 case IRQ_TYPE_LEVEL_HIGH:
2308 value |= BIT(bit);
2309 break;
2310
2311 case IRQ_TYPE_EDGE_FALLING:
2312 case IRQ_TYPE_LEVEL_LOW:
2313 value &= ~BIT(bit);
2314 break;
2315
2316 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2317 value ^= BIT(bit);
2318 break;
2319
2320 default:
2321 return -EINVAL;
2322 }
2323
2324 tegra_pmc_writel(pmc, value, offset);
2325
2326 return 0;
2327}
2328
2329static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2330{
2331 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2332 unsigned int offset, bit;
2333 u32 value;
2334
2335 offset = data->hwirq / 32;
2336 bit = data->hwirq % 32;
2337
2338 /* clear wake status */
2339 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));
2340
2341 /* route wake to tier 2 */
2342 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2343
2344 if (!on)
2345 value &= ~(1 << bit);
2346 else
2347 value |= 1 << bit;
2348
2349 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2350
2351 /* enable wakeup event */
2352 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));
2353
2354 return 0;
2355}
2356
2357static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2358{
2359 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2360 u32 value;
2361
2362 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2363
2364 switch (type) {
2365 case IRQ_TYPE_EDGE_RISING:
2366 case IRQ_TYPE_LEVEL_HIGH:
2367 value |= WAKE_AOWAKE_CNTRL_LEVEL;
2368 break;
2369
2370 case IRQ_TYPE_EDGE_FALLING:
2371 case IRQ_TYPE_LEVEL_LOW:
2372 value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
2373 break;
2374
2375 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2376 value ^= WAKE_AOWAKE_CNTRL_LEVEL;
2377 break;
2378
2379 default:
2380 return -EINVAL;
2381 }
2382
2383 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2384
2385 return 0;
2386}
2387
2388static void tegra_irq_mask_parent(struct irq_data *data)
2389{
2390 if (data->parent_data)
2391 irq_chip_mask_parent(data);
2392}
2393
2394static void tegra_irq_unmask_parent(struct irq_data *data)
2395{
2396 if (data->parent_data)
2397 irq_chip_unmask_parent(data);
2398}
2399
2400static void tegra_irq_eoi_parent(struct irq_data *data)
2401{
2402 if (data->parent_data)
2403 irq_chip_eoi_parent(data);
2404}
2405
2406static int tegra_irq_set_affinity_parent(struct irq_data *data,
2407 const struct cpumask *dest,
2408 bool force)
2409{
2410 if (data->parent_data)
2411 return irq_chip_set_affinity_parent(data, dest, force);
2412
2413 return -EINVAL;
2414}
2415
2416static int tegra_pmc_irq_init(struct tegra_pmc *pmc)
2417{
2418 struct irq_domain *parent = NULL;
2419 struct device_node *np;
2420
2421 np = of_irq_find_parent(pmc->dev->of_node);
2422 if (np) {
2423 parent = irq_find_host(np);
2424 of_node_put(np);
2425 }
2426
2427 if (!parent)
2428 return 0;
2429
2430 pmc->irq.name = dev_name(pmc->dev);
2431 pmc->irq.irq_mask = tegra_irq_mask_parent;
2432 pmc->irq.irq_unmask = tegra_irq_unmask_parent;
2433 pmc->irq.irq_eoi = tegra_irq_eoi_parent;
2434 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent;
2435 pmc->irq.irq_set_type = pmc->soc->irq_set_type;
2436 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake;
2437
2438 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node,
2439 &tegra_pmc_irq_domain_ops, pmc);
2440 if (!pmc->domain) {
2441 dev_err(pmc->dev, "failed to allocate domain\n");
2442 return -ENOMEM;
2443 }
2444
2445 return 0;
2446}
2447
2448static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
2449 unsigned long action, void *ptr)
2450{
2451 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb);
2452 struct clk_notifier_data *data = ptr;
2453
2454 switch (action) {
2455 case PRE_RATE_CHANGE:
2456 mutex_lock(&pmc->powergates_lock);
2457 break;
2458
2459 case POST_RATE_CHANGE:
2460 pmc->rate = data->new_rate;
2461 fallthrough;
2462
2463 case ABORT_RATE_CHANGE:
2464 mutex_unlock(&pmc->powergates_lock);
2465 break;
2466
2467 default:
2468 WARN_ON_ONCE(1);
2469 return notifier_from_errno(-EINVAL);
2470 }
2471
2472 return NOTIFY_OK;
2473}
2474
2475static void pmc_clk_fence_udelay(u32 offset)
2476{
2477 tegra_pmc_readl(pmc, offset);
2478 /* pmc clk propagation delay 2 us */
2479 udelay(2);
2480}
2481
2482static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
2483{
2484 struct pmc_clk *clk = to_pmc_clk(hw);
2485 u32 val;
2486
2487 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
2488 val &= PMC_CLK_OUT_MUX_MASK;
2489
2490 return val;
2491}
2492
2493static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
2494{
2495 struct pmc_clk *clk = to_pmc_clk(hw);
2496 u32 val;
2497
2498 val = tegra_pmc_readl(pmc, clk->offs);
2499 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift);
2500 val |= index << clk->mux_shift;
2501 tegra_pmc_writel(pmc, val, clk->offs);
2502 pmc_clk_fence_udelay(clk->offs);
2503
2504 return 0;
2505}
2506
2507static int pmc_clk_is_enabled(struct clk_hw *hw)
2508{
2509 struct pmc_clk *clk = to_pmc_clk(hw);
2510 u32 val;
2511
2512 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift);
2513
2514 return val ? 1 : 0;
2515}
2516
2517static void pmc_clk_set_state(unsigned long offs, u32 shift, int state)
2518{
2519 u32 val;
2520
2521 val = tegra_pmc_readl(pmc, offs);
2522 val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
2523 tegra_pmc_writel(pmc, val, offs);
2524 pmc_clk_fence_udelay(offs);
2525}
2526
2527static int pmc_clk_enable(struct clk_hw *hw)
2528{
2529 struct pmc_clk *clk = to_pmc_clk(hw);
2530
2531 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1);
2532
2533 return 0;
2534}
2535
2536static void pmc_clk_disable(struct clk_hw *hw)
2537{
2538 struct pmc_clk *clk = to_pmc_clk(hw);
2539
2540 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0);
2541}
2542
2543static const struct clk_ops pmc_clk_ops = {
2544 .get_parent = pmc_clk_mux_get_parent,
2545 .set_parent = pmc_clk_mux_set_parent,
2546 .determine_rate = __clk_mux_determine_rate,
2547 .is_enabled = pmc_clk_is_enabled,
2548 .enable = pmc_clk_enable,
2549 .disable = pmc_clk_disable,
2550};
2551
2552static struct clk *
2553tegra_pmc_clk_out_register(struct tegra_pmc *pmc,
2554 const struct pmc_clk_init_data *data,
2555 unsigned long offset)
2556{
2557 struct clk_init_data init;
2558 struct pmc_clk *pmc_clk;
2559
2560 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL);
2561 if (!pmc_clk)
2562 return ERR_PTR(-ENOMEM);
2563
2564 init.name = data->name;
2565 init.ops = &pmc_clk_ops;
2566 init.parent_names = data->parents;
2567 init.num_parents = data->num_parents;
2568 init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
2569 CLK_SET_PARENT_GATE;
2570
2571 pmc_clk->hw.init = &init;
2572 pmc_clk->offs = offset;
2573 pmc_clk->mux_shift = data->mux_shift;
2574 pmc_clk->force_en_shift = data->force_en_shift;
2575
2576 return clk_register(NULL, &pmc_clk->hw);
2577}
2578
2579static int pmc_clk_gate_is_enabled(struct clk_hw *hw)
2580{
2581 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2582
2583 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
2584}
2585
2586static int pmc_clk_gate_enable(struct clk_hw *hw)
2587{
2588 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2589
2590 pmc_clk_set_state(gate->offs, gate->shift, 1);
2591
2592 return 0;
2593}
2594
2595static void pmc_clk_gate_disable(struct clk_hw *hw)
2596{
2597 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2598
2599 pmc_clk_set_state(gate->offs, gate->shift, 0);
2600}
2601
2602static const struct clk_ops pmc_clk_gate_ops = {
2603 .is_enabled = pmc_clk_gate_is_enabled,
2604 .enable = pmc_clk_gate_enable,
2605 .disable = pmc_clk_gate_disable,
2606};
2607
2608static struct clk *
2609tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name,
2610 const char *parent_name, unsigned long offset,
2611 u32 shift)
2612{
2613 struct clk_init_data init;
2614 struct pmc_clk_gate *gate;
2615
2616 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL);
2617 if (!gate)
2618 return ERR_PTR(-ENOMEM);
2619
2620 init.name = name;
2621 init.ops = &pmc_clk_gate_ops;
2622 init.parent_names = &parent_name;
2623 init.num_parents = 1;
2624 init.flags = 0;
2625
2626 gate->hw.init = &init;
2627 gate->offs = offset;
2628 gate->shift = shift;
2629
2630 return clk_register(NULL, &gate->hw);
2631}
2632
2633static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
2634 struct device_node *np)
2635{
2636 struct clk *clk;
2637 struct clk_onecell_data *clk_data;
2638 unsigned int num_clks;
2639 int i, err;
2640
2641 num_clks = pmc->soc->num_pmc_clks;
2642 if (pmc->soc->has_blink_output)
2643 num_clks += 1;
2644
2645 if (!num_clks)
2646 return;
2647
2648 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL);
2649 if (!clk_data)
2650 return;
2651
2652 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX,
2653 sizeof(*clk_data->clks), GFP_KERNEL);
2654 if (!clk_data->clks)
2655 return;
2656
2657 clk_data->clk_num = TEGRA_PMC_CLK_MAX;
2658
2659 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)
2660 clk_data->clks[i] = ERR_PTR(-ENOENT);
2661
2662 for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
2663 const struct pmc_clk_init_data *data;
2664
2665 data = pmc->soc->pmc_clks_data + i;
2666
2667 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL);
2668 if (IS_ERR(clk)) {
2669 dev_warn(pmc->dev, "unable to register clock %s: %d\n",
2670 data->name, PTR_ERR_OR_ZERO(clk));
2671 return;
2672 }
2673
2674 err = clk_register_clkdev(clk, data->name, NULL);
2675 if (err) {
2676 dev_warn(pmc->dev,
2677 "unable to register %s clock lookup: %d\n",
2678 data->name, err);
2679 return;
2680 }
2681
2682 clk_data->clks[data->clk_id] = clk;
2683 }
2684
2685 if (pmc->soc->has_blink_output) {
2686 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER);
2687 clk = tegra_pmc_clk_gate_register(pmc,
2688 "pmc_blink_override",
2689 "clk_32k",
2690 PMC_DPD_PADS_ORIDE,
2691 PMC_DPD_PADS_ORIDE_BLINK);
2692 if (IS_ERR(clk)) {
2693 dev_warn(pmc->dev,
2694 "unable to register pmc_blink_override: %d\n",
2695 PTR_ERR_OR_ZERO(clk));
2696 return;
2697 }
2698
2699 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink",
2700 "pmc_blink_override",
2701 PMC_CNTRL,
2702 PMC_CNTRL_BLINK_EN);
2703 if (IS_ERR(clk)) {
2704 dev_warn(pmc->dev,
2705 "unable to register pmc_blink: %d\n",
2706 PTR_ERR_OR_ZERO(clk));
2707 return;
2708 }
2709
2710 err = clk_register_clkdev(clk, "pmc_blink", NULL);
2711 if (err) {
2712 dev_warn(pmc->dev,
2713 "unable to register pmc_blink lookup: %d\n",
2714 err);
2715 return;
2716 }
2717
2718 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk;
2719 }
2720
2721 err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
2722 if (err)
2723 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n",
2724 err);
2725}
2726
2727static const struct regmap_range pmc_usb_sleepwalk_ranges[] = {
2728 regmap_reg_range(PMC_USB_DEBOUNCE_DEL, PMC_USB_AO),
2729 regmap_reg_range(PMC_UTMIP_UHSIC_TRIGGERS, PMC_UTMIP_UHSIC_SAVED_STATE),
2730 regmap_reg_range(PMC_UTMIP_TERM_PAD_CFG, PMC_UTMIP_UHSIC_FAKE),
2731 regmap_reg_range(PMC_UTMIP_UHSIC_LINE_WAKEUP, PMC_UTMIP_UHSIC_LINE_WAKEUP),
2732 regmap_reg_range(PMC_UTMIP_BIAS_MASTER_CNTRL, PMC_UTMIP_MASTER_CONFIG),
2733 regmap_reg_range(PMC_UTMIP_UHSIC2_TRIGGERS, PMC_UTMIP_MASTER2_CONFIG),
2734 regmap_reg_range(PMC_UTMIP_PAD_CFG0, PMC_UTMIP_UHSIC_SLEEP_CFG1),
2735 regmap_reg_range(PMC_UTMIP_SLEEPWALK_P3, PMC_UTMIP_SLEEPWALK_P3),
2736};
2737
2738static const struct regmap_access_table pmc_usb_sleepwalk_table = {
2739 .yes_ranges = pmc_usb_sleepwalk_ranges,
2740 .n_yes_ranges = ARRAY_SIZE(pmc_usb_sleepwalk_ranges),
2741};
2742
2743static int tegra_pmc_regmap_readl(void *context, unsigned int offset, unsigned int *value)
2744{
2745 struct tegra_pmc *pmc = context;
2746
2747 *value = tegra_pmc_readl(pmc, offset);
2748 return 0;
2749}
2750
2751static int tegra_pmc_regmap_writel(void *context, unsigned int offset, unsigned int value)
2752{
2753 struct tegra_pmc *pmc = context;
2754
2755 tegra_pmc_writel(pmc, value, offset);
2756 return 0;
2757}
2758
2759static const struct regmap_config usb_sleepwalk_regmap_config = {
2760 .name = "usb_sleepwalk",
2761 .reg_bits = 32,
2762 .val_bits = 32,
2763 .reg_stride = 4,
2764 .fast_io = true,
2765 .rd_table = &pmc_usb_sleepwalk_table,
2766 .wr_table = &pmc_usb_sleepwalk_table,
2767 .reg_read = tegra_pmc_regmap_readl,
2768 .reg_write = tegra_pmc_regmap_writel,
2769};
2770
2771static int tegra_pmc_regmap_init(struct tegra_pmc *pmc)
2772{
2773 struct regmap *regmap;
2774 int err;
2775
2776 if (pmc->soc->has_usb_sleepwalk) {
2777 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config);
2778 if (IS_ERR(regmap)) {
2779 err = PTR_ERR(regmap);
2780 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err);
2781 return err;
2782 }
2783 }
2784
2785 return 0;
2786}
2787
2788static int tegra_pmc_probe(struct platform_device *pdev)
2789{
2790 void __iomem *base;
2791 struct resource *res;
2792 int err;
2793
2794 /*
2795 * Early initialisation should have configured an initial
2796 * register mapping and setup the soc data pointer. If these
2797 * are not valid then something went badly wrong!
2798 */
2799 if (WARN_ON(!pmc->base || !pmc->soc))
2800 return -ENODEV;
2801
2802 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
2803 if (err < 0)
2804 return err;
2805
2806 /* take over the memory region from the early initialization */
2807 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2808 base = devm_ioremap_resource(&pdev->dev, res);
2809 if (IS_ERR(base))
2810 return PTR_ERR(base);
2811
2812 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake");
2813 if (res) {
2814 pmc->wake = devm_ioremap_resource(&pdev->dev, res);
2815 if (IS_ERR(pmc->wake))
2816 return PTR_ERR(pmc->wake);
2817 } else {
2818 pmc->wake = base;
2819 }
2820
2821 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
2822 if (res) {
2823 pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
2824 if (IS_ERR(pmc->aotag))
2825 return PTR_ERR(pmc->aotag);
2826 } else {
2827 pmc->aotag = base;
2828 }
2829
2830 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch");
2831 if (res) {
2832 pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
2833 if (IS_ERR(pmc->scratch))
2834 return PTR_ERR(pmc->scratch);
2835 } else {
2836 pmc->scratch = base;
2837 }
2838
2839 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
2840 if (IS_ERR(pmc->clk)) {
2841 err = PTR_ERR(pmc->clk);
2842
2843 if (err != -ENOENT) {
2844 dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
2845 return err;
2846 }
2847
2848 pmc->clk = NULL;
2849 }
2850
2851 /*
2852 * PCLK clock rate can't be retrieved using CLK API because it
2853 * causes lockup if CPU enters LP2 idle state from some other
2854 * CLK notifier, hence we're caching the rate's value locally.
2855 */
2856 if (pmc->clk) {
2857 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb;
2858 err = clk_notifier_register(pmc->clk, &pmc->clk_nb);
2859 if (err) {
2860 dev_err(&pdev->dev,
2861 "failed to register clk notifier\n");
2862 return err;
2863 }
2864
2865 pmc->rate = clk_get_rate(pmc->clk);
2866 }
2867
2868 pmc->dev = &pdev->dev;
2869
2870 tegra_pmc_init(pmc);
2871
2872 tegra_pmc_init_tsense_reset(pmc);
2873
2874 tegra_pmc_reset_sysfs_init(pmc);
2875
2876 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2877 err = tegra_powergate_debugfs_init();
2878 if (err < 0)
2879 goto cleanup_sysfs;
2880 }
2881
2882 err = register_restart_handler(&tegra_pmc_restart_handler);
2883 if (err) {
2884 dev_err(&pdev->dev, "unable to register restart handler, %d\n",
2885 err);
2886 goto cleanup_debugfs;
2887 }
2888
2889 err = tegra_pmc_pinctrl_init(pmc);
2890 if (err)
2891 goto cleanup_restart_handler;
2892
2893 err = tegra_pmc_regmap_init(pmc);
2894 if (err < 0)
2895 goto cleanup_restart_handler;
2896
2897 err = tegra_powergate_init(pmc, pdev->dev.of_node);
2898 if (err < 0)
2899 goto cleanup_powergates;
2900
2901 err = tegra_pmc_irq_init(pmc);
2902 if (err < 0)
2903 goto cleanup_powergates;
2904
2905 mutex_lock(&pmc->powergates_lock);
2906 iounmap(pmc->base);
2907 pmc->base = base;
2908 mutex_unlock(&pmc->powergates_lock);
2909
2910 tegra_pmc_clock_register(pmc, pdev->dev.of_node);
2911 platform_set_drvdata(pdev, pmc);
2912
2913 return 0;
2914
2915cleanup_powergates:
2916 tegra_powergate_remove_all(pdev->dev.of_node);
2917cleanup_restart_handler:
2918 unregister_restart_handler(&tegra_pmc_restart_handler);
2919cleanup_debugfs:
2920 debugfs_remove(pmc->debugfs);
2921cleanup_sysfs:
2922 device_remove_file(&pdev->dev, &dev_attr_reset_reason);
2923 device_remove_file(&pdev->dev, &dev_attr_reset_level);
2924 clk_notifier_unregister(pmc->clk, &pmc->clk_nb);
2925
2926 return err;
2927}
2928
2929#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
2930static int tegra_pmc_suspend(struct device *dev)
2931{
2932 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2933
2934 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);
2935
2936 return 0;
2937}
2938
2939static int tegra_pmc_resume(struct device *dev)
2940{
2941 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2942
2943 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);
2944
2945 return 0;
2946}
2947
2948static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
2949
2950#endif
2951
2952static const char * const tegra20_powergates[] = {
2953 [TEGRA_POWERGATE_CPU] = "cpu",
2954 [TEGRA_POWERGATE_3D] = "3d",
2955 [TEGRA_POWERGATE_VENC] = "venc",
2956 [TEGRA_POWERGATE_VDEC] = "vdec",
2957 [TEGRA_POWERGATE_PCIE] = "pcie",
2958 [TEGRA_POWERGATE_L2] = "l2",
2959 [TEGRA_POWERGATE_MPE] = "mpe",
2960};
2961
2962static const struct tegra_pmc_regs tegra20_pmc_regs = {
2963 .scratch0 = 0x50,
2964 .dpd_req = 0x1b8,
2965 .dpd_status = 0x1bc,
2966 .dpd2_req = 0x1c0,
2967 .dpd2_status = 0x1c4,
2968 .rst_status = 0x1b4,
2969 .rst_source_shift = 0x0,
2970 .rst_source_mask = 0x7,
2971 .rst_level_shift = 0x0,
2972 .rst_level_mask = 0x0,
2973};
2974
2975static void tegra20_pmc_init(struct tegra_pmc *pmc)
2976{
2977 u32 value, osc, pmu, off;
2978
2979 /* Always enable CPU power request */
2980 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2981 value |= PMC_CNTRL_CPU_PWRREQ_OE;
2982 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2983
2984 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2985
2986 if (pmc->sysclkreq_high)
2987 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
2988 else
2989 value |= PMC_CNTRL_SYSCLK_POLARITY;
2990
2991 if (pmc->corereq_high)
2992 value &= ~PMC_CNTRL_PWRREQ_POLARITY;
2993 else
2994 value |= PMC_CNTRL_PWRREQ_POLARITY;
2995
2996 /* configure the output polarity while the request is tristated */
2997 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2998
2999 /* now enable the request */
3000 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3001 value |= PMC_CNTRL_SYSCLK_OE;
3002 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3003
3004 /* program core timings which are applicable only for suspend state */
3005 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) {
3006 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000);
3007 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000);
3008 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000);
3009 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),
3010 PMC_COREPWRGOOD_TIMER);
3011 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);
3012 }
3013}
3014
3015static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3016 struct device_node *np,
3017 bool invert)
3018{
3019 u32 value;
3020
3021 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3022
3023 if (invert)
3024 value |= PMC_CNTRL_INTR_POLARITY;
3025 else
3026 value &= ~PMC_CNTRL_INTR_POLARITY;
3027
3028 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3029}
3030
3031static const struct tegra_pmc_soc tegra20_pmc_soc = {
3032 .num_powergates = ARRAY_SIZE(tegra20_powergates),
3033 .powergates = tegra20_powergates,
3034 .num_cpu_powergates = 0,
3035 .cpu_powergates = NULL,
3036 .has_tsense_reset = false,
3037 .has_gpu_clamps = false,
3038 .needs_mbist_war = false,
3039 .has_impl_33v_pwr = false,
3040 .maybe_tz_only = false,
3041 .num_io_pads = 0,
3042 .io_pads = NULL,
3043 .num_pin_descs = 0,
3044 .pin_descs = NULL,
3045 .regs = &tegra20_pmc_regs,
3046 .init = tegra20_pmc_init,
3047 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3048 .powergate_set = tegra20_powergate_set,
3049 .reset_sources = NULL,
3050 .num_reset_sources = 0,
3051 .reset_levels = NULL,
3052 .num_reset_levels = 0,
3053 .pmc_clks_data = NULL,
3054 .num_pmc_clks = 0,
3055 .has_blink_output = true,
3056 .has_usb_sleepwalk = false,
3057};
3058
3059static const char * const tegra30_powergates[] = {
3060 [TEGRA_POWERGATE_CPU] = "cpu0",
3061 [TEGRA_POWERGATE_3D] = "3d0",
3062 [TEGRA_POWERGATE_VENC] = "venc",
3063 [TEGRA_POWERGATE_VDEC] = "vdec",
3064 [TEGRA_POWERGATE_PCIE] = "pcie",
3065 [TEGRA_POWERGATE_L2] = "l2",
3066 [TEGRA_POWERGATE_MPE] = "mpe",
3067 [TEGRA_POWERGATE_HEG] = "heg",
3068 [TEGRA_POWERGATE_SATA] = "sata",
3069 [TEGRA_POWERGATE_CPU1] = "cpu1",
3070 [TEGRA_POWERGATE_CPU2] = "cpu2",
3071 [TEGRA_POWERGATE_CPU3] = "cpu3",
3072 [TEGRA_POWERGATE_CELP] = "celp",
3073 [TEGRA_POWERGATE_3D1] = "3d1",
3074};
3075
3076static const u8 tegra30_cpu_powergates[] = {
3077 TEGRA_POWERGATE_CPU,
3078 TEGRA_POWERGATE_CPU1,
3079 TEGRA_POWERGATE_CPU2,
3080 TEGRA_POWERGATE_CPU3,
3081};
3082
3083static const char * const tegra30_reset_sources[] = {
3084 "POWER_ON_RESET",
3085 "WATCHDOG",
3086 "SENSOR",
3087 "SW_MAIN",
3088 "LP0"
3089};
3090
3091static const struct tegra_pmc_soc tegra30_pmc_soc = {
3092 .num_powergates = ARRAY_SIZE(tegra30_powergates),
3093 .powergates = tegra30_powergates,
3094 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
3095 .cpu_powergates = tegra30_cpu_powergates,
3096 .has_tsense_reset = true,
3097 .has_gpu_clamps = false,
3098 .needs_mbist_war = false,
3099 .has_impl_33v_pwr = false,
3100 .maybe_tz_only = false,
3101 .num_io_pads = 0,
3102 .io_pads = NULL,
3103 .num_pin_descs = 0,
3104 .pin_descs = NULL,
3105 .regs = &tegra20_pmc_regs,
3106 .init = tegra20_pmc_init,
3107 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3108 .powergate_set = tegra20_powergate_set,
3109 .reset_sources = tegra30_reset_sources,
3110 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3111 .reset_levels = NULL,
3112 .num_reset_levels = 0,
3113 .pmc_clks_data = tegra_pmc_clks_data,
3114 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3115 .has_blink_output = true,
3116 .has_usb_sleepwalk = false,
3117};
3118
3119static const char * const tegra114_powergates[] = {
3120 [TEGRA_POWERGATE_CPU] = "crail",
3121 [TEGRA_POWERGATE_3D] = "3d",
3122 [TEGRA_POWERGATE_VENC] = "venc",
3123 [TEGRA_POWERGATE_VDEC] = "vdec",
3124 [TEGRA_POWERGATE_MPE] = "mpe",
3125 [TEGRA_POWERGATE_HEG] = "heg",
3126 [TEGRA_POWERGATE_CPU1] = "cpu1",
3127 [TEGRA_POWERGATE_CPU2] = "cpu2",
3128 [TEGRA_POWERGATE_CPU3] = "cpu3",
3129 [TEGRA_POWERGATE_CELP] = "celp",
3130 [TEGRA_POWERGATE_CPU0] = "cpu0",
3131 [TEGRA_POWERGATE_C0NC] = "c0nc",
3132 [TEGRA_POWERGATE_C1NC] = "c1nc",
3133 [TEGRA_POWERGATE_DIS] = "dis",
3134 [TEGRA_POWERGATE_DISB] = "disb",
3135 [TEGRA_POWERGATE_XUSBA] = "xusba",
3136 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3137 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3138};
3139
3140static const u8 tegra114_cpu_powergates[] = {
3141 TEGRA_POWERGATE_CPU0,
3142 TEGRA_POWERGATE_CPU1,
3143 TEGRA_POWERGATE_CPU2,
3144 TEGRA_POWERGATE_CPU3,
3145};
3146
3147static const struct tegra_pmc_soc tegra114_pmc_soc = {
3148 .num_powergates = ARRAY_SIZE(tegra114_powergates),
3149 .powergates = tegra114_powergates,
3150 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
3151 .cpu_powergates = tegra114_cpu_powergates,
3152 .has_tsense_reset = true,
3153 .has_gpu_clamps = false,
3154 .needs_mbist_war = false,
3155 .has_impl_33v_pwr = false,
3156 .maybe_tz_only = false,
3157 .num_io_pads = 0,
3158 .io_pads = NULL,
3159 .num_pin_descs = 0,
3160 .pin_descs = NULL,
3161 .regs = &tegra20_pmc_regs,
3162 .init = tegra20_pmc_init,
3163 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3164 .powergate_set = tegra114_powergate_set,
3165 .reset_sources = tegra30_reset_sources,
3166 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3167 .reset_levels = NULL,
3168 .num_reset_levels = 0,
3169 .pmc_clks_data = tegra_pmc_clks_data,
3170 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3171 .has_blink_output = true,
3172 .has_usb_sleepwalk = false,
3173};
3174
3175static const char * const tegra124_powergates[] = {
3176 [TEGRA_POWERGATE_CPU] = "crail",
3177 [TEGRA_POWERGATE_3D] = "3d",
3178 [TEGRA_POWERGATE_VENC] = "venc",
3179 [TEGRA_POWERGATE_PCIE] = "pcie",
3180 [TEGRA_POWERGATE_VDEC] = "vdec",
3181 [TEGRA_POWERGATE_MPE] = "mpe",
3182 [TEGRA_POWERGATE_HEG] = "heg",
3183 [TEGRA_POWERGATE_SATA] = "sata",
3184 [TEGRA_POWERGATE_CPU1] = "cpu1",
3185 [TEGRA_POWERGATE_CPU2] = "cpu2",
3186 [TEGRA_POWERGATE_CPU3] = "cpu3",
3187 [TEGRA_POWERGATE_CELP] = "celp",
3188 [TEGRA_POWERGATE_CPU0] = "cpu0",
3189 [TEGRA_POWERGATE_C0NC] = "c0nc",
3190 [TEGRA_POWERGATE_C1NC] = "c1nc",
3191 [TEGRA_POWERGATE_SOR] = "sor",
3192 [TEGRA_POWERGATE_DIS] = "dis",
3193 [TEGRA_POWERGATE_DISB] = "disb",
3194 [TEGRA_POWERGATE_XUSBA] = "xusba",
3195 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3196 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3197 [TEGRA_POWERGATE_VIC] = "vic",
3198 [TEGRA_POWERGATE_IRAM] = "iram",
3199};
3200
3201static const u8 tegra124_cpu_powergates[] = {
3202 TEGRA_POWERGATE_CPU0,
3203 TEGRA_POWERGATE_CPU1,
3204 TEGRA_POWERGATE_CPU2,
3205 TEGRA_POWERGATE_CPU3,
3206};
3207
3208#define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \
3209 ((struct tegra_io_pad_soc) { \
3210 .id = (_id), \
3211 .dpd = (_dpd), \
3212 .voltage = (_voltage), \
3213 .name = (_name), \
3214 })
3215
3216#define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \
3217 ((struct pinctrl_pin_desc) { \
3218 .number = (_id), \
3219 .name = (_name) \
3220 })
3221
3222#define TEGRA124_IO_PAD_TABLE(_pad) \
3223 /* .id .dpd .voltage .name */ \
3224 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
3225 _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \
3226 _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \
3227 _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \
3228 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3229 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \
3230 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \
3231 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
3232 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
3233 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
3234 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
3235 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
3236 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
3237 _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \
3238 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
3239 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3240 _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \
3241 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
3242 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
3243 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3244 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3245 _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \
3246 _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \
3247 _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \
3248 _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \
3249 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
3250 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
3251 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
3252 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
3253 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias")
3254
3255static const struct tegra_io_pad_soc tegra124_io_pads[] = {
3256 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD)
3257};
3258
3259static const struct pinctrl_pin_desc tegra124_pin_descs[] = {
3260 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3261};
3262
3263static const struct tegra_pmc_soc tegra124_pmc_soc = {
3264 .num_powergates = ARRAY_SIZE(tegra124_powergates),
3265 .powergates = tegra124_powergates,
3266 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
3267 .cpu_powergates = tegra124_cpu_powergates,
3268 .has_tsense_reset = true,
3269 .has_gpu_clamps = true,
3270 .needs_mbist_war = false,
3271 .has_impl_33v_pwr = false,
3272 .maybe_tz_only = false,
3273 .num_io_pads = ARRAY_SIZE(tegra124_io_pads),
3274 .io_pads = tegra124_io_pads,
3275 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs),
3276 .pin_descs = tegra124_pin_descs,
3277 .regs = &tegra20_pmc_regs,
3278 .init = tegra20_pmc_init,
3279 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3280 .powergate_set = tegra114_powergate_set,
3281 .reset_sources = tegra30_reset_sources,
3282 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3283 .reset_levels = NULL,
3284 .num_reset_levels = 0,
3285 .pmc_clks_data = tegra_pmc_clks_data,
3286 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3287 .has_blink_output = true,
3288 .has_usb_sleepwalk = true,
3289};
3290
3291static const char * const tegra210_powergates[] = {
3292 [TEGRA_POWERGATE_CPU] = "crail",
3293 [TEGRA_POWERGATE_3D] = "3d",
3294 [TEGRA_POWERGATE_VENC] = "venc",
3295 [TEGRA_POWERGATE_PCIE] = "pcie",
3296 [TEGRA_POWERGATE_MPE] = "mpe",
3297 [TEGRA_POWERGATE_SATA] = "sata",
3298 [TEGRA_POWERGATE_CPU1] = "cpu1",
3299 [TEGRA_POWERGATE_CPU2] = "cpu2",
3300 [TEGRA_POWERGATE_CPU3] = "cpu3",
3301 [TEGRA_POWERGATE_CPU0] = "cpu0",
3302 [TEGRA_POWERGATE_C0NC] = "c0nc",
3303 [TEGRA_POWERGATE_SOR] = "sor",
3304 [TEGRA_POWERGATE_DIS] = "dis",
3305 [TEGRA_POWERGATE_DISB] = "disb",
3306 [TEGRA_POWERGATE_XUSBA] = "xusba",
3307 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3308 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3309 [TEGRA_POWERGATE_VIC] = "vic",
3310 [TEGRA_POWERGATE_IRAM] = "iram",
3311 [TEGRA_POWERGATE_NVDEC] = "nvdec",
3312 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
3313 [TEGRA_POWERGATE_AUD] = "aud",
3314 [TEGRA_POWERGATE_DFD] = "dfd",
3315 [TEGRA_POWERGATE_VE2] = "ve2",
3316};
3317
3318static const u8 tegra210_cpu_powergates[] = {
3319 TEGRA_POWERGATE_CPU0,
3320 TEGRA_POWERGATE_CPU1,
3321 TEGRA_POWERGATE_CPU2,
3322 TEGRA_POWERGATE_CPU3,
3323};
3324
3325#define TEGRA210_IO_PAD_TABLE(_pad) \
3326 /* .id .dpd .voltage .name */ \
3327 _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \
3328 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \
3329 _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \
3330 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3331 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3332 _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \
3333 _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \
3334 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \
3335 _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \
3336 _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \
3337 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \
3338 _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \
3339 _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \
3340 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
3341 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
3342 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
3343 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
3344 _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \
3345 _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \
3346 _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \
3347 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
3348 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
3349 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
3350 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3351 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
3352 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
3353 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3354 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \
3355 _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \
3356 _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \
3357 _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \
3358 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \
3359 _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \
3360 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
3361 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
3362 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
3363 _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \
3364 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias")
3365
3366static const struct tegra_io_pad_soc tegra210_io_pads[] = {
3367 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD)
3368};
3369
3370static const struct pinctrl_pin_desc tegra210_pin_descs[] = {
3371 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3372};
3373
3374static const char * const tegra210_reset_sources[] = {
3375 "POWER_ON_RESET",
3376 "WATCHDOG",
3377 "SENSOR",
3378 "SW_MAIN",
3379 "LP0",
3380 "AOTAG"
3381};
3382
3383static const struct tegra_wake_event tegra210_wake_events[] = {
3384 TEGRA_WAKE_IRQ("rtc", 16, 2),
3385 TEGRA_WAKE_IRQ("pmu", 51, 86),
3386};
3387
3388static const struct tegra_pmc_soc tegra210_pmc_soc = {
3389 .num_powergates = ARRAY_SIZE(tegra210_powergates),
3390 .powergates = tegra210_powergates,
3391 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
3392 .cpu_powergates = tegra210_cpu_powergates,
3393 .has_tsense_reset = true,
3394 .has_gpu_clamps = true,
3395 .needs_mbist_war = true,
3396 .has_impl_33v_pwr = false,
3397 .maybe_tz_only = true,
3398 .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
3399 .io_pads = tegra210_io_pads,
3400 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
3401 .pin_descs = tegra210_pin_descs,
3402 .regs = &tegra20_pmc_regs,
3403 .init = tegra20_pmc_init,
3404 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3405 .powergate_set = tegra114_powergate_set,
3406 .irq_set_wake = tegra210_pmc_irq_set_wake,
3407 .irq_set_type = tegra210_pmc_irq_set_type,
3408 .reset_sources = tegra210_reset_sources,
3409 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
3410 .reset_levels = NULL,
3411 .num_reset_levels = 0,
3412 .num_wake_events = ARRAY_SIZE(tegra210_wake_events),
3413 .wake_events = tegra210_wake_events,
3414 .pmc_clks_data = tegra_pmc_clks_data,
3415 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3416 .has_blink_output = true,
3417 .has_usb_sleepwalk = true,
3418};
3419
3420#define TEGRA186_IO_PAD_TABLE(_pad) \
3421 /* .id .dpd .voltage .name */ \
3422 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3423 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3424 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
3425 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3426 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3427 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3428 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3429 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3430 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
3431 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
3432 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
3433 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \
3434 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
3435 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
3436 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
3437 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
3438 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3439 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3440 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3441 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \
3442 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
3443 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
3444 _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \
3445 _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \
3446 _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \
3447 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
3448 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
3449 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
3450 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
3451 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
3452 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
3453 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \
3454 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
3455 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3456 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3457 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
3458 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3459 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3460
3461static const struct tegra_io_pad_soc tegra186_io_pads[] = {
3462 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD)
3463};
3464
3465static const struct pinctrl_pin_desc tegra186_pin_descs[] = {
3466 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3467};
3468
3469static const struct tegra_pmc_regs tegra186_pmc_regs = {
3470 .scratch0 = 0x2000,
3471 .dpd_req = 0x74,
3472 .dpd_status = 0x78,
3473 .dpd2_req = 0x7c,
3474 .dpd2_status = 0x80,
3475 .rst_status = 0x70,
3476 .rst_source_shift = 0x2,
3477 .rst_source_mask = 0x3c,
3478 .rst_level_shift = 0x0,
3479 .rst_level_mask = 0x3,
3480};
3481
3482static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3483 struct device_node *np,
3484 bool invert)
3485{
3486 struct resource regs;
3487 void __iomem *wake;
3488 u32 value;
3489 int index;
3490
3491 index = of_property_match_string(np, "reg-names", "wake");
3492 if (index < 0) {
3493 dev_err(pmc->dev, "failed to find PMC wake registers\n");
3494 return;
3495 }
3496
3497 of_address_to_resource(np, index, ®s);
3498
3499 wake = ioremap(regs.start, resource_size(®s));
3500 if (!wake) {
3501 dev_err(pmc->dev, "failed to map PMC wake registers\n");
3502 return;
3503 }
3504
3505 value = readl(wake + WAKE_AOWAKE_CTRL);
3506
3507 if (invert)
3508 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
3509 else
3510 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
3511
3512 writel(value, wake + WAKE_AOWAKE_CTRL);
3513
3514 iounmap(wake);
3515}
3516
3517static const char * const tegra186_reset_sources[] = {
3518 "SYS_RESET",
3519 "AOWDT",
3520 "MCCPLEXWDT",
3521 "BPMPWDT",
3522 "SCEWDT",
3523 "SPEWDT",
3524 "APEWDT",
3525 "BCCPLEXWDT",
3526 "SENSOR",
3527 "AOTAG",
3528 "VFSENSOR",
3529 "SWREST",
3530 "SC7",
3531 "HSM",
3532 "CORESIGHT"
3533};
3534
3535static const char * const tegra186_reset_levels[] = {
3536 "L0", "L1", "L2", "WARM"
3537};
3538
3539static const struct tegra_wake_event tegra186_wake_events[] = {
3540 TEGRA_WAKE_IRQ("pmu", 24, 209),
3541 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)),
3542 TEGRA_WAKE_IRQ("rtc", 73, 10),
3543};
3544
3545static const struct tegra_pmc_soc tegra186_pmc_soc = {
3546 .num_powergates = 0,
3547 .powergates = NULL,
3548 .num_cpu_powergates = 0,
3549 .cpu_powergates = NULL,
3550 .has_tsense_reset = false,
3551 .has_gpu_clamps = false,
3552 .needs_mbist_war = false,
3553 .has_impl_33v_pwr = true,
3554 .maybe_tz_only = false,
3555 .num_io_pads = ARRAY_SIZE(tegra186_io_pads),
3556 .io_pads = tegra186_io_pads,
3557 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),
3558 .pin_descs = tegra186_pin_descs,
3559 .regs = &tegra186_pmc_regs,
3560 .init = NULL,
3561 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3562 .irq_set_wake = tegra186_pmc_irq_set_wake,
3563 .irq_set_type = tegra186_pmc_irq_set_type,
3564 .reset_sources = tegra186_reset_sources,
3565 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources),
3566 .reset_levels = tegra186_reset_levels,
3567 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3568 .num_wake_events = ARRAY_SIZE(tegra186_wake_events),
3569 .wake_events = tegra186_wake_events,
3570 .pmc_clks_data = NULL,
3571 .num_pmc_clks = 0,
3572 .has_blink_output = false,
3573 .has_usb_sleepwalk = false,
3574};
3575
3576#define TEGRA194_IO_PAD_TABLE(_pad) \
3577 /* .id .dpd .voltage .name */ \
3578 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3579 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3580 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3581 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3582 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3583 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3584 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3585 _pad(TEGRA_IO_PAD_EQOS, 8, UINT_MAX, "eqos"), \
3586 _pad(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, UINT_MAX, "pex-clk-2-bias"), \
3587 _pad(TEGRA_IO_PAD_PEX_CLK_2, 10, UINT_MAX, "pex-clk-2"), \
3588 _pad(TEGRA_IO_PAD_DAP3, 11, UINT_MAX, "dap3"), \
3589 _pad(TEGRA_IO_PAD_DAP5, 12, UINT_MAX, "dap5"), \
3590 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
3591 _pad(TEGRA_IO_PAD_PWR_CTL, 15, UINT_MAX, "pwr-ctl"), \
3592 _pad(TEGRA_IO_PAD_SOC_GPIO53, 16, UINT_MAX, "soc-gpio53"), \
3593 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
3594 _pad(TEGRA_IO_PAD_GP_PWM2, 18, UINT_MAX, "gp-pwm2"), \
3595 _pad(TEGRA_IO_PAD_GP_PWM3, 19, UINT_MAX, "gp-pwm3"), \
3596 _pad(TEGRA_IO_PAD_SOC_GPIO12, 20, UINT_MAX, "soc-gpio12"), \
3597 _pad(TEGRA_IO_PAD_SOC_GPIO13, 21, UINT_MAX, "soc-gpio13"), \
3598 _pad(TEGRA_IO_PAD_SOC_GPIO10, 22, UINT_MAX, "soc-gpio10"), \
3599 _pad(TEGRA_IO_PAD_UART4, 23, UINT_MAX, "uart4"), \
3600 _pad(TEGRA_IO_PAD_UART5, 24, UINT_MAX, "uart5"), \
3601 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
3602 _pad(TEGRA_IO_PAD_HDMI_DP3, 26, UINT_MAX, "hdmi-dp3"), \
3603 _pad(TEGRA_IO_PAD_HDMI_DP2, 27, UINT_MAX, "hdmi-dp2"), \
3604 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3605 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3606 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3607 _pad(TEGRA_IO_PAD_PEX_CTL2, 33, UINT_MAX, "pex-ctl2"), \
3608 _pad(TEGRA_IO_PAD_PEX_L0_RST_N, 34, UINT_MAX, "pex-l0-rst"), \
3609 _pad(TEGRA_IO_PAD_PEX_L1_RST_N, 35, UINT_MAX, "pex-l1-rst"), \
3610 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
3611 _pad(TEGRA_IO_PAD_PEX_L5_RST_N, 37, UINT_MAX, "pex-l5-rst"), \
3612 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
3613 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
3614 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
3615 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
3616 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
3617 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
3618 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
3619 _pad(TEGRA_IO_PAD_CSIG, 50, UINT_MAX, "csig"), \
3620 _pad(TEGRA_IO_PAD_CSIH, 51, UINT_MAX, "csih"), \
3621 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
3622 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3623 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3624 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
3625 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3626 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3627
3628static const struct tegra_io_pad_soc tegra194_io_pads[] = {
3629 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PAD)
3630};
3631
3632static const struct pinctrl_pin_desc tegra194_pin_descs[] = {
3633 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3634};
3635
3636static const struct tegra_pmc_regs tegra194_pmc_regs = {
3637 .scratch0 = 0x2000,
3638 .dpd_req = 0x74,
3639 .dpd_status = 0x78,
3640 .dpd2_req = 0x7c,
3641 .dpd2_status = 0x80,
3642 .rst_status = 0x70,
3643 .rst_source_shift = 0x2,
3644 .rst_source_mask = 0x7c,
3645 .rst_level_shift = 0x0,
3646 .rst_level_mask = 0x3,
3647};
3648
3649static const char * const tegra194_reset_sources[] = {
3650 "SYS_RESET_N",
3651 "AOWDT",
3652 "BCCPLEXWDT",
3653 "BPMPWDT",
3654 "SCEWDT",
3655 "SPEWDT",
3656 "APEWDT",
3657 "LCCPLEXWDT",
3658 "SENSOR",
3659 "AOTAG",
3660 "VFSENSOR",
3661 "MAINSWRST",
3662 "SC7",
3663 "HSM",
3664 "CSITE",
3665 "RCEWDT",
3666 "PVA0WDT",
3667 "PVA1WDT",
3668 "L1A_ASYNC",
3669 "BPMPBOOT",
3670 "FUSECRC",
3671};
3672
3673static const struct tegra_wake_event tegra194_wake_events[] = {
3674 TEGRA_WAKE_IRQ("pmu", 24, 209),
3675 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)),
3676 TEGRA_WAKE_IRQ("rtc", 73, 10),
3677};
3678
3679static const struct tegra_pmc_soc tegra194_pmc_soc = {
3680 .num_powergates = 0,
3681 .powergates = NULL,
3682 .num_cpu_powergates = 0,
3683 .cpu_powergates = NULL,
3684 .has_tsense_reset = false,
3685 .has_gpu_clamps = false,
3686 .needs_mbist_war = false,
3687 .has_impl_33v_pwr = true,
3688 .maybe_tz_only = false,
3689 .num_io_pads = ARRAY_SIZE(tegra194_io_pads),
3690 .io_pads = tegra194_io_pads,
3691 .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs),
3692 .pin_descs = tegra194_pin_descs,
3693 .regs = &tegra194_pmc_regs,
3694 .init = NULL,
3695 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3696 .irq_set_wake = tegra186_pmc_irq_set_wake,
3697 .irq_set_type = tegra186_pmc_irq_set_type,
3698 .reset_sources = tegra194_reset_sources,
3699 .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources),
3700 .reset_levels = tegra186_reset_levels,
3701 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3702 .num_wake_events = ARRAY_SIZE(tegra194_wake_events),
3703 .wake_events = tegra194_wake_events,
3704 .pmc_clks_data = NULL,
3705 .num_pmc_clks = 0,
3706 .has_blink_output = false,
3707 .has_usb_sleepwalk = false,
3708};
3709
3710static const struct tegra_pmc_regs tegra234_pmc_regs = {
3711 .scratch0 = 0x2000,
3712 .dpd_req = 0,
3713 .dpd_status = 0,
3714 .dpd2_req = 0,
3715 .dpd2_status = 0,
3716 .rst_status = 0x70,
3717 .rst_source_shift = 0x2,
3718 .rst_source_mask = 0xfc,
3719 .rst_level_shift = 0x0,
3720 .rst_level_mask = 0x3,
3721};
3722
3723static const char * const tegra234_reset_sources[] = {
3724 "SYS_RESET_N",
3725 "AOWDT",
3726 "BCCPLEXWDT",
3727 "BPMPWDT",
3728 "SCEWDT",
3729 "SPEWDT",
3730 "APEWDT",
3731 "LCCPLEXWDT",
3732 "SENSOR",
3733 "AOTAG",
3734 "VFSENSOR",
3735 "MAINSWRST",
3736 "SC7",
3737 "HSM",
3738 "CSITE",
3739 "RCEWDT",
3740 "PVA0WDT",
3741 "PVA1WDT",
3742 "L1A_ASYNC",
3743 "BPMPBOOT",
3744 "FUSECRC",
3745};
3746
3747static const struct tegra_pmc_soc tegra234_pmc_soc = {
3748 .num_powergates = 0,
3749 .powergates = NULL,
3750 .num_cpu_powergates = 0,
3751 .cpu_powergates = NULL,
3752 .has_tsense_reset = false,
3753 .has_gpu_clamps = false,
3754 .needs_mbist_war = false,
3755 .has_impl_33v_pwr = true,
3756 .maybe_tz_only = false,
3757 .num_io_pads = 0,
3758 .io_pads = NULL,
3759 .num_pin_descs = 0,
3760 .pin_descs = NULL,
3761 .regs = &tegra234_pmc_regs,
3762 .init = NULL,
3763 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3764 .irq_set_wake = tegra186_pmc_irq_set_wake,
3765 .irq_set_type = tegra186_pmc_irq_set_type,
3766 .reset_sources = tegra234_reset_sources,
3767 .num_reset_sources = ARRAY_SIZE(tegra234_reset_sources),
3768 .reset_levels = tegra186_reset_levels,
3769 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3770 .num_wake_events = 0,
3771 .wake_events = NULL,
3772 .pmc_clks_data = NULL,
3773 .num_pmc_clks = 0,
3774 .has_blink_output = false,
3775};
3776
3777static const struct of_device_id tegra_pmc_match[] = {
3778 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
3779 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
3780 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
3781 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
3782 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
3783 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
3784 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
3785 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
3786 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
3787 { }
3788};
3789
3790static void tegra_pmc_sync_state(struct device *dev)
3791{
3792 int err;
3793
3794 /*
3795 * Older device-trees don't have core PD, and thus, there are
3796 * no dependencies that will block the state syncing. We shouldn't
3797 * mark the domain as synced in this case.
3798 */
3799 if (!pmc->core_domain_registered)
3800 return;
3801
3802 pmc->core_domain_state_synced = true;
3803
3804 /* this is a no-op if core regulator isn't used */
3805 mutex_lock(&pmc->powergates_lock);
3806 err = dev_pm_opp_sync_regulators(dev);
3807 mutex_unlock(&pmc->powergates_lock);
3808
3809 if (err)
3810 dev_err(dev, "failed to sync regulators: %d\n", err);
3811}
3812
3813static struct platform_driver tegra_pmc_driver = {
3814 .driver = {
3815 .name = "tegra-pmc",
3816 .suppress_bind_attrs = true,
3817 .of_match_table = tegra_pmc_match,
3818#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
3819 .pm = &tegra_pmc_pm_ops,
3820#endif
3821 .sync_state = tegra_pmc_sync_state,
3822 },
3823 .probe = tegra_pmc_probe,
3824};
3825builtin_platform_driver(tegra_pmc_driver);
3826
3827static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc)
3828{
3829 u32 value, saved;
3830
3831 saved = readl(pmc->base + pmc->soc->regs->scratch0);
3832 value = saved ^ 0xffffffff;
3833
3834 if (value == 0xffffffff)
3835 value = 0xdeadbeef;
3836
3837 /* write pattern and read it back */
3838 writel(value, pmc->base + pmc->soc->regs->scratch0);
3839 value = readl(pmc->base + pmc->soc->regs->scratch0);
3840
3841 /* if we read all-zeroes, access is restricted to TZ only */
3842 if (value == 0) {
3843 pr_info("access to PMC is restricted to TZ\n");
3844 return true;
3845 }
3846
3847 /* restore original value */
3848 writel(saved, pmc->base + pmc->soc->regs->scratch0);
3849
3850 return false;
3851}
3852
3853/*
3854 * Early initialization to allow access to registers in the very early boot
3855 * process.
3856 */
3857static int __init tegra_pmc_early_init(void)
3858{
3859 const struct of_device_id *match;
3860 struct device_node *np;
3861 struct resource regs;
3862 unsigned int i;
3863 bool invert;
3864
3865 mutex_init(&pmc->powergates_lock);
3866
3867 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
3868 if (!np) {
3869 /*
3870 * Fall back to legacy initialization for 32-bit ARM only. All
3871 * 64-bit ARM device tree files for Tegra are required to have
3872 * a PMC node.
3873 *
3874 * This is for backwards-compatibility with old device trees
3875 * that didn't contain a PMC node. Note that in this case the
3876 * SoC data can't be matched and therefore powergating is
3877 * disabled.
3878 */
3879 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
3880 pr_warn("DT node not found, powergating disabled\n");
3881
3882 regs.start = 0x7000e400;
3883 regs.end = 0x7000e7ff;
3884 regs.flags = IORESOURCE_MEM;
3885
3886 pr_warn("Using memory region %pR\n", ®s);
3887 } else {
3888 /*
3889 * At this point we're not running on Tegra, so play
3890 * nice with multi-platform kernels.
3891 */
3892 return 0;
3893 }
3894 } else {
3895 /*
3896 * Extract information from the device tree if we've found a
3897 * matching node.
3898 */
3899 if (of_address_to_resource(np, 0, ®s) < 0) {
3900 pr_err("failed to get PMC registers\n");
3901 of_node_put(np);
3902 return -ENXIO;
3903 }
3904 }
3905
3906 pmc->base = ioremap(regs.start, resource_size(®s));
3907 if (!pmc->base) {
3908 pr_err("failed to map PMC registers\n");
3909 of_node_put(np);
3910 return -ENXIO;
3911 }
3912
3913 if (np) {
3914 pmc->soc = match->data;
3915
3916 if (pmc->soc->maybe_tz_only)
3917 pmc->tz_only = tegra_pmc_detect_tz_only(pmc);
3918
3919 /* Create a bitmap of the available and valid partitions */
3920 for (i = 0; i < pmc->soc->num_powergates; i++)
3921 if (pmc->soc->powergates[i])
3922 set_bit(i, pmc->powergates_available);
3923
3924 /*
3925 * Invert the interrupt polarity if a PMC device tree node
3926 * exists and contains the nvidia,invert-interrupt property.
3927 */
3928 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
3929
3930 pmc->soc->setup_irq_polarity(pmc, np, invert);
3931
3932 of_node_put(np);
3933 }
3934
3935 return 0;
3936}
3937early_initcall(tegra_pmc_early_init);