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1/* Low-level parallel-port routines for 8255-based PC-style hardware.
2 *
3 * Authors: Phil Blundell <philb@gnu.org>
4 * Tim Waugh <tim@cyberelk.demon.co.uk>
5 * Jose Renau <renau@acm.org>
6 * David Campbell
7 * Andrea Arcangeli
8 *
9 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell.
10 *
11 * Cleaned up include files - Russell King <linux@arm.uk.linux.org>
12 * DMA support - Bert De Jonghe <bert@sophis.be>
13 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999
14 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G.
15 * Various hacks, Fred Barnes, 04/2001
16 * Updated probing logic - Adam Belay <ambx1@neo.rr.com>
17 */
18
19/* This driver should work with any hardware that is broadly compatible
20 * with that in the IBM PC. This applies to the majority of integrated
21 * I/O chipsets that are commonly available. The expected register
22 * layout is:
23 *
24 * base+0 data
25 * base+1 status
26 * base+2 control
27 *
28 * In addition, there are some optional registers:
29 *
30 * base+3 EPP address
31 * base+4 EPP data
32 * base+0x400 ECP config A
33 * base+0x401 ECP config B
34 * base+0x402 ECP control
35 *
36 * All registers are 8 bits wide and read/write. If your hardware differs
37 * only in register addresses (eg because your registers are on 32-bit
38 * word boundaries) then you can alter the constants in parport_pc.h to
39 * accommodate this.
40 *
41 * Note that the ECP registers may not start at offset 0x400 for PCI cards,
42 * but rather will start at port->base_hi.
43 */
44
45#include <linux/module.h>
46#include <linux/init.h>
47#include <linux/sched.h>
48#include <linux/delay.h>
49#include <linux/errno.h>
50#include <linux/interrupt.h>
51#include <linux/ioport.h>
52#include <linux/kernel.h>
53#include <linux/slab.h>
54#include <linux/dma-mapping.h>
55#include <linux/pci.h>
56#include <linux/pnp.h>
57#include <linux/platform_device.h>
58#include <linux/sysctl.h>
59#include <linux/io.h>
60#include <linux/uaccess.h>
61
62#include <asm/dma.h>
63
64#include <linux/parport.h>
65#include <linux/parport_pc.h>
66#include <linux/via.h>
67#include <asm/parport.h>
68
69#define PARPORT_PC_MAX_PORTS PARPORT_MAX
70
71#ifdef CONFIG_ISA_DMA_API
72#define HAS_DMA
73#endif
74
75/* ECR modes */
76#define ECR_SPP 00
77#define ECR_PS2 01
78#define ECR_PPF 02
79#define ECR_ECP 03
80#define ECR_EPP 04
81#define ECR_VND 05
82#define ECR_TST 06
83#define ECR_CNF 07
84#define ECR_MODE_MASK 0xe0
85#define ECR_WRITE(p, v) frob_econtrol((p), 0xff, (v))
86
87#undef DEBUG
88
89#ifdef DEBUG
90#define DPRINTK printk
91#else
92#define DPRINTK(stuff...)
93#endif
94
95
96#define NR_SUPERIOS 3
97static struct superio_struct { /* For Super-IO chips autodetection */
98 int io;
99 int irq;
100 int dma;
101} superios[NR_SUPERIOS] = { {0,},};
102
103static int user_specified;
104#if defined(CONFIG_PARPORT_PC_SUPERIO) || \
105 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
106static int verbose_probing;
107#endif
108static int pci_registered_parport;
109static int pnp_registered_parport;
110
111/* frob_control, but for ECR */
112static void frob_econtrol(struct parport *pb, unsigned char m,
113 unsigned char v)
114{
115 unsigned char ectr = 0;
116
117 if (m != 0xff)
118 ectr = inb(ECONTROL(pb));
119
120 DPRINTK(KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n",
121 m, v, ectr, (ectr & ~m) ^ v);
122
123 outb((ectr & ~m) ^ v, ECONTROL(pb));
124}
125
126static inline void frob_set_mode(struct parport *p, int mode)
127{
128 frob_econtrol(p, ECR_MODE_MASK, mode << 5);
129}
130
131#ifdef CONFIG_PARPORT_PC_FIFO
132/* Safely change the mode bits in the ECR
133 Returns:
134 0 : Success
135 -EBUSY: Could not drain FIFO in some finite amount of time,
136 mode not changed!
137 */
138static int change_mode(struct parport *p, int m)
139{
140 const struct parport_pc_private *priv = p->physport->private_data;
141 unsigned char oecr;
142 int mode;
143
144 DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n", m);
145
146 if (!priv->ecr) {
147 printk(KERN_DEBUG "change_mode: but there's no ECR!\n");
148 return 0;
149 }
150
151 /* Bits <7:5> contain the mode. */
152 oecr = inb(ECONTROL(p));
153 mode = (oecr >> 5) & 0x7;
154 if (mode == m)
155 return 0;
156
157 if (mode >= 2 && !(priv->ctr & 0x20)) {
158 /* This mode resets the FIFO, so we may
159 * have to wait for it to drain first. */
160 unsigned long expire = jiffies + p->physport->cad->timeout;
161 int counter;
162 switch (mode) {
163 case ECR_PPF: /* Parallel Port FIFO mode */
164 case ECR_ECP: /* ECP Parallel Port mode */
165 /* Busy wait for 200us */
166 for (counter = 0; counter < 40; counter++) {
167 if (inb(ECONTROL(p)) & 0x01)
168 break;
169 if (signal_pending(current))
170 break;
171 udelay(5);
172 }
173
174 /* Poll slowly. */
175 while (!(inb(ECONTROL(p)) & 0x01)) {
176 if (time_after_eq(jiffies, expire))
177 /* The FIFO is stuck. */
178 return -EBUSY;
179 schedule_timeout_interruptible(
180 msecs_to_jiffies(10));
181 if (signal_pending(current))
182 break;
183 }
184 }
185 }
186
187 if (mode >= 2 && m >= 2) {
188 /* We have to go through mode 001 */
189 oecr &= ~(7 << 5);
190 oecr |= ECR_PS2 << 5;
191 ECR_WRITE(p, oecr);
192 }
193
194 /* Set the mode. */
195 oecr &= ~(7 << 5);
196 oecr |= m << 5;
197 ECR_WRITE(p, oecr);
198 return 0;
199}
200
201#ifdef CONFIG_PARPORT_1284
202/* Find FIFO lossage; FIFO is reset */
203#if 0
204static int get_fifo_residue(struct parport *p)
205{
206 int residue;
207 int cnfga;
208 const struct parport_pc_private *priv = p->physport->private_data;
209
210 /* Adjust for the contents of the FIFO. */
211 for (residue = priv->fifo_depth; ; residue--) {
212 if (inb(ECONTROL(p)) & 0x2)
213 /* Full up. */
214 break;
215
216 outb(0, FIFO(p));
217 }
218
219 printk(KERN_DEBUG "%s: %d PWords were left in FIFO\n", p->name,
220 residue);
221
222 /* Reset the FIFO. */
223 frob_set_mode(p, ECR_PS2);
224
225 /* Now change to config mode and clean up. FIXME */
226 frob_set_mode(p, ECR_CNF);
227 cnfga = inb(CONFIGA(p));
228 printk(KERN_DEBUG "%s: cnfgA contains 0x%02x\n", p->name, cnfga);
229
230 if (!(cnfga & (1<<2))) {
231 printk(KERN_DEBUG "%s: Accounting for extra byte\n", p->name);
232 residue++;
233 }
234
235 /* Don't care about partial PWords until support is added for
236 * PWord != 1 byte. */
237
238 /* Back to PS2 mode. */
239 frob_set_mode(p, ECR_PS2);
240
241 DPRINTK(KERN_DEBUG
242 "*** get_fifo_residue: done residue collecting (ecr = 0x%2.2x)\n",
243 inb(ECONTROL(p)));
244 return residue;
245}
246#endif /* 0 */
247#endif /* IEEE 1284 support */
248#endif /* FIFO support */
249
250/*
251 * Clear TIMEOUT BIT in EPP MODE
252 *
253 * This is also used in SPP detection.
254 */
255static int clear_epp_timeout(struct parport *pb)
256{
257 unsigned char r;
258
259 if (!(parport_pc_read_status(pb) & 0x01))
260 return 1;
261
262 /* To clear timeout some chips require double read */
263 parport_pc_read_status(pb);
264 r = parport_pc_read_status(pb);
265 outb(r | 0x01, STATUS(pb)); /* Some reset by writing 1 */
266 outb(r & 0xfe, STATUS(pb)); /* Others by writing 0 */
267 r = parport_pc_read_status(pb);
268
269 return !(r & 0x01);
270}
271
272/*
273 * Access functions.
274 *
275 * Most of these aren't static because they may be used by the
276 * parport_xxx_yyy macros. extern __inline__ versions of several
277 * of these are in parport_pc.h.
278 */
279
280static void parport_pc_init_state(struct pardevice *dev,
281 struct parport_state *s)
282{
283 s->u.pc.ctr = 0xc;
284 if (dev->irq_func &&
285 dev->port->irq != PARPORT_IRQ_NONE)
286 /* Set ackIntEn */
287 s->u.pc.ctr |= 0x10;
288
289 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24;
290 * D.Gruszka VScom */
291}
292
293static void parport_pc_save_state(struct parport *p, struct parport_state *s)
294{
295 const struct parport_pc_private *priv = p->physport->private_data;
296 s->u.pc.ctr = priv->ctr;
297 if (priv->ecr)
298 s->u.pc.ecr = inb(ECONTROL(p));
299}
300
301static void parport_pc_restore_state(struct parport *p,
302 struct parport_state *s)
303{
304 struct parport_pc_private *priv = p->physport->private_data;
305 register unsigned char c = s->u.pc.ctr & priv->ctr_writable;
306 outb(c, CONTROL(p));
307 priv->ctr = c;
308 if (priv->ecr)
309 ECR_WRITE(p, s->u.pc.ecr);
310}
311
312#ifdef CONFIG_PARPORT_1284
313static size_t parport_pc_epp_read_data(struct parport *port, void *buf,
314 size_t length, int flags)
315{
316 size_t got = 0;
317
318 if (flags & PARPORT_W91284PIC) {
319 unsigned char status;
320 size_t left = length;
321
322 /* use knowledge about data lines..:
323 * nFault is 0 if there is at least 1 byte in the Warp's FIFO
324 * pError is 1 if there are 16 bytes in the Warp's FIFO
325 */
326 status = inb(STATUS(port));
327
328 while (!(status & 0x08) && got < length) {
329 if (left >= 16 && (status & 0x20) && !(status & 0x08)) {
330 /* can grab 16 bytes from warp fifo */
331 if (!((long)buf & 0x03))
332 insl(EPPDATA(port), buf, 4);
333 else
334 insb(EPPDATA(port), buf, 16);
335 buf += 16;
336 got += 16;
337 left -= 16;
338 } else {
339 /* grab single byte from the warp fifo */
340 *((char *)buf) = inb(EPPDATA(port));
341 buf++;
342 got++;
343 left--;
344 }
345 status = inb(STATUS(port));
346 if (status & 0x01) {
347 /* EPP timeout should never occur... */
348 printk(KERN_DEBUG
349"%s: EPP timeout occurred while talking to w91284pic (should not have done)\n", port->name);
350 clear_epp_timeout(port);
351 }
352 }
353 return got;
354 }
355 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
356 if (!(((long)buf | length) & 0x03))
357 insl(EPPDATA(port), buf, (length >> 2));
358 else
359 insb(EPPDATA(port), buf, length);
360 if (inb(STATUS(port)) & 0x01) {
361 clear_epp_timeout(port);
362 return -EIO;
363 }
364 return length;
365 }
366 for (; got < length; got++) {
367 *((char *)buf) = inb(EPPDATA(port));
368 buf++;
369 if (inb(STATUS(port)) & 0x01) {
370 /* EPP timeout */
371 clear_epp_timeout(port);
372 break;
373 }
374 }
375
376 return got;
377}
378
379static size_t parport_pc_epp_write_data(struct parport *port, const void *buf,
380 size_t length, int flags)
381{
382 size_t written = 0;
383
384 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
385 if (!(((long)buf | length) & 0x03))
386 outsl(EPPDATA(port), buf, (length >> 2));
387 else
388 outsb(EPPDATA(port), buf, length);
389 if (inb(STATUS(port)) & 0x01) {
390 clear_epp_timeout(port);
391 return -EIO;
392 }
393 return length;
394 }
395 for (; written < length; written++) {
396 outb(*((char *)buf), EPPDATA(port));
397 buf++;
398 if (inb(STATUS(port)) & 0x01) {
399 clear_epp_timeout(port);
400 break;
401 }
402 }
403
404 return written;
405}
406
407static size_t parport_pc_epp_read_addr(struct parport *port, void *buf,
408 size_t length, int flags)
409{
410 size_t got = 0;
411
412 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
413 insb(EPPADDR(port), buf, length);
414 if (inb(STATUS(port)) & 0x01) {
415 clear_epp_timeout(port);
416 return -EIO;
417 }
418 return length;
419 }
420 for (; got < length; got++) {
421 *((char *)buf) = inb(EPPADDR(port));
422 buf++;
423 if (inb(STATUS(port)) & 0x01) {
424 clear_epp_timeout(port);
425 break;
426 }
427 }
428
429 return got;
430}
431
432static size_t parport_pc_epp_write_addr(struct parport *port,
433 const void *buf, size_t length,
434 int flags)
435{
436 size_t written = 0;
437
438 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
439 outsb(EPPADDR(port), buf, length);
440 if (inb(STATUS(port)) & 0x01) {
441 clear_epp_timeout(port);
442 return -EIO;
443 }
444 return length;
445 }
446 for (; written < length; written++) {
447 outb(*((char *)buf), EPPADDR(port));
448 buf++;
449 if (inb(STATUS(port)) & 0x01) {
450 clear_epp_timeout(port);
451 break;
452 }
453 }
454
455 return written;
456}
457
458static size_t parport_pc_ecpepp_read_data(struct parport *port, void *buf,
459 size_t length, int flags)
460{
461 size_t got;
462
463 frob_set_mode(port, ECR_EPP);
464 parport_pc_data_reverse(port);
465 parport_pc_write_control(port, 0x4);
466 got = parport_pc_epp_read_data(port, buf, length, flags);
467 frob_set_mode(port, ECR_PS2);
468
469 return got;
470}
471
472static size_t parport_pc_ecpepp_write_data(struct parport *port,
473 const void *buf, size_t length,
474 int flags)
475{
476 size_t written;
477
478 frob_set_mode(port, ECR_EPP);
479 parport_pc_write_control(port, 0x4);
480 parport_pc_data_forward(port);
481 written = parport_pc_epp_write_data(port, buf, length, flags);
482 frob_set_mode(port, ECR_PS2);
483
484 return written;
485}
486
487static size_t parport_pc_ecpepp_read_addr(struct parport *port, void *buf,
488 size_t length, int flags)
489{
490 size_t got;
491
492 frob_set_mode(port, ECR_EPP);
493 parport_pc_data_reverse(port);
494 parport_pc_write_control(port, 0x4);
495 got = parport_pc_epp_read_addr(port, buf, length, flags);
496 frob_set_mode(port, ECR_PS2);
497
498 return got;
499}
500
501static size_t parport_pc_ecpepp_write_addr(struct parport *port,
502 const void *buf, size_t length,
503 int flags)
504{
505 size_t written;
506
507 frob_set_mode(port, ECR_EPP);
508 parport_pc_write_control(port, 0x4);
509 parport_pc_data_forward(port);
510 written = parport_pc_epp_write_addr(port, buf, length, flags);
511 frob_set_mode(port, ECR_PS2);
512
513 return written;
514}
515#endif /* IEEE 1284 support */
516
517#ifdef CONFIG_PARPORT_PC_FIFO
518static size_t parport_pc_fifo_write_block_pio(struct parport *port,
519 const void *buf, size_t length)
520{
521 int ret = 0;
522 const unsigned char *bufp = buf;
523 size_t left = length;
524 unsigned long expire = jiffies + port->physport->cad->timeout;
525 const int fifo = FIFO(port);
526 int poll_for = 8; /* 80 usecs */
527 const struct parport_pc_private *priv = port->physport->private_data;
528 const int fifo_depth = priv->fifo_depth;
529
530 port = port->physport;
531
532 /* We don't want to be interrupted every character. */
533 parport_pc_disable_irq(port);
534 /* set nErrIntrEn and serviceIntr */
535 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
536
537 /* Forward mode. */
538 parport_pc_data_forward(port); /* Must be in PS2 mode */
539
540 while (left) {
541 unsigned char byte;
542 unsigned char ecrval = inb(ECONTROL(port));
543 int i = 0;
544
545 if (need_resched() && time_before(jiffies, expire))
546 /* Can't yield the port. */
547 schedule();
548
549 /* Anyone else waiting for the port? */
550 if (port->waithead) {
551 printk(KERN_DEBUG "Somebody wants the port\n");
552 break;
553 }
554
555 if (ecrval & 0x02) {
556 /* FIFO is full. Wait for interrupt. */
557
558 /* Clear serviceIntr */
559 ECR_WRITE(port, ecrval & ~(1<<2));
560false_alarm:
561 ret = parport_wait_event(port, HZ);
562 if (ret < 0)
563 break;
564 ret = 0;
565 if (!time_before(jiffies, expire)) {
566 /* Timed out. */
567 printk(KERN_DEBUG "FIFO write timed out\n");
568 break;
569 }
570 ecrval = inb(ECONTROL(port));
571 if (!(ecrval & (1<<2))) {
572 if (need_resched() &&
573 time_before(jiffies, expire))
574 schedule();
575
576 goto false_alarm;
577 }
578
579 continue;
580 }
581
582 /* Can't fail now. */
583 expire = jiffies + port->cad->timeout;
584
585poll:
586 if (signal_pending(current))
587 break;
588
589 if (ecrval & 0x01) {
590 /* FIFO is empty. Blast it full. */
591 const int n = left < fifo_depth ? left : fifo_depth;
592 outsb(fifo, bufp, n);
593 bufp += n;
594 left -= n;
595
596 /* Adjust the poll time. */
597 if (i < (poll_for - 2))
598 poll_for--;
599 continue;
600 } else if (i++ < poll_for) {
601 udelay(10);
602 ecrval = inb(ECONTROL(port));
603 goto poll;
604 }
605
606 /* Half-full(call me an optimist) */
607 byte = *bufp++;
608 outb(byte, fifo);
609 left--;
610 }
611 dump_parport_state("leave fifo_write_block_pio", port);
612 return length - left;
613}
614
615#ifdef HAS_DMA
616static size_t parport_pc_fifo_write_block_dma(struct parport *port,
617 const void *buf, size_t length)
618{
619 int ret = 0;
620 unsigned long dmaflag;
621 size_t left = length;
622 const struct parport_pc_private *priv = port->physport->private_data;
623 struct device *dev = port->physport->dev;
624 dma_addr_t dma_addr, dma_handle;
625 size_t maxlen = 0x10000; /* max 64k per DMA transfer */
626 unsigned long start = (unsigned long) buf;
627 unsigned long end = (unsigned long) buf + length - 1;
628
629 dump_parport_state("enter fifo_write_block_dma", port);
630 if (end < MAX_DMA_ADDRESS) {
631 /* If it would cross a 64k boundary, cap it at the end. */
632 if ((start ^ end) & ~0xffffUL)
633 maxlen = 0x10000 - (start & 0xffff);
634
635 dma_addr = dma_handle = dma_map_single(dev, (void *)buf, length,
636 DMA_TO_DEVICE);
637 } else {
638 /* above 16 MB we use a bounce buffer as ISA-DMA
639 is not possible */
640 maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */
641 dma_addr = priv->dma_handle;
642 dma_handle = 0;
643 }
644
645 port = port->physport;
646
647 /* We don't want to be interrupted every character. */
648 parport_pc_disable_irq(port);
649 /* set nErrIntrEn and serviceIntr */
650 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
651
652 /* Forward mode. */
653 parport_pc_data_forward(port); /* Must be in PS2 mode */
654
655 while (left) {
656 unsigned long expire = jiffies + port->physport->cad->timeout;
657
658 size_t count = left;
659
660 if (count > maxlen)
661 count = maxlen;
662
663 if (!dma_handle) /* bounce buffer ! */
664 memcpy(priv->dma_buf, buf, count);
665
666 dmaflag = claim_dma_lock();
667 disable_dma(port->dma);
668 clear_dma_ff(port->dma);
669 set_dma_mode(port->dma, DMA_MODE_WRITE);
670 set_dma_addr(port->dma, dma_addr);
671 set_dma_count(port->dma, count);
672
673 /* Set DMA mode */
674 frob_econtrol(port, 1<<3, 1<<3);
675
676 /* Clear serviceIntr */
677 frob_econtrol(port, 1<<2, 0);
678
679 enable_dma(port->dma);
680 release_dma_lock(dmaflag);
681
682 /* assume DMA will be successful */
683 left -= count;
684 buf += count;
685 if (dma_handle)
686 dma_addr += count;
687
688 /* Wait for interrupt. */
689false_alarm:
690 ret = parport_wait_event(port, HZ);
691 if (ret < 0)
692 break;
693 ret = 0;
694 if (!time_before(jiffies, expire)) {
695 /* Timed out. */
696 printk(KERN_DEBUG "DMA write timed out\n");
697 break;
698 }
699 /* Is serviceIntr set? */
700 if (!(inb(ECONTROL(port)) & (1<<2))) {
701 cond_resched();
702
703 goto false_alarm;
704 }
705
706 dmaflag = claim_dma_lock();
707 disable_dma(port->dma);
708 clear_dma_ff(port->dma);
709 count = get_dma_residue(port->dma);
710 release_dma_lock(dmaflag);
711
712 cond_resched(); /* Can't yield the port. */
713
714 /* Anyone else waiting for the port? */
715 if (port->waithead) {
716 printk(KERN_DEBUG "Somebody wants the port\n");
717 break;
718 }
719
720 /* update for possible DMA residue ! */
721 buf -= count;
722 left += count;
723 if (dma_handle)
724 dma_addr -= count;
725 }
726
727 /* Maybe got here through break, so adjust for DMA residue! */
728 dmaflag = claim_dma_lock();
729 disable_dma(port->dma);
730 clear_dma_ff(port->dma);
731 left += get_dma_residue(port->dma);
732 release_dma_lock(dmaflag);
733
734 /* Turn off DMA mode */
735 frob_econtrol(port, 1<<3, 0);
736
737 if (dma_handle)
738 dma_unmap_single(dev, dma_handle, length, DMA_TO_DEVICE);
739
740 dump_parport_state("leave fifo_write_block_dma", port);
741 return length - left;
742}
743#endif
744
745static inline size_t parport_pc_fifo_write_block(struct parport *port,
746 const void *buf, size_t length)
747{
748#ifdef HAS_DMA
749 if (port->dma != PARPORT_DMA_NONE)
750 return parport_pc_fifo_write_block_dma(port, buf, length);
751#endif
752 return parport_pc_fifo_write_block_pio(port, buf, length);
753}
754
755/* Parallel Port FIFO mode (ECP chipsets) */
756static size_t parport_pc_compat_write_block_pio(struct parport *port,
757 const void *buf, size_t length,
758 int flags)
759{
760 size_t written;
761 int r;
762 unsigned long expire;
763 const struct parport_pc_private *priv = port->physport->private_data;
764
765 /* Special case: a timeout of zero means we cannot call schedule().
766 * Also if O_NONBLOCK is set then use the default implementation. */
767 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
768 return parport_ieee1284_write_compat(port, buf,
769 length, flags);
770
771 /* Set up parallel port FIFO mode.*/
772 parport_pc_data_forward(port); /* Must be in PS2 mode */
773 parport_pc_frob_control(port, PARPORT_CONTROL_STROBE, 0);
774 r = change_mode(port, ECR_PPF); /* Parallel port FIFO */
775 if (r)
776 printk(KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n",
777 port->name);
778
779 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
780
781 /* Write the data to the FIFO. */
782 written = parport_pc_fifo_write_block(port, buf, length);
783
784 /* Finish up. */
785 /* For some hardware we don't want to touch the mode until
786 * the FIFO is empty, so allow 4 seconds for each position
787 * in the fifo.
788 */
789 expire = jiffies + (priv->fifo_depth * HZ * 4);
790 do {
791 /* Wait for the FIFO to empty */
792 r = change_mode(port, ECR_PS2);
793 if (r != -EBUSY)
794 break;
795 } while (time_before(jiffies, expire));
796 if (r == -EBUSY) {
797
798 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
799
800 /* Prevent further data transfer. */
801 frob_set_mode(port, ECR_TST);
802
803 /* Adjust for the contents of the FIFO. */
804 for (written -= priv->fifo_depth; ; written++) {
805 if (inb(ECONTROL(port)) & 0x2) {
806 /* Full up. */
807 break;
808 }
809 outb(0, FIFO(port));
810 }
811
812 /* Reset the FIFO and return to PS2 mode. */
813 frob_set_mode(port, ECR_PS2);
814 }
815
816 r = parport_wait_peripheral(port,
817 PARPORT_STATUS_BUSY,
818 PARPORT_STATUS_BUSY);
819 if (r)
820 printk(KERN_DEBUG
821 "%s: BUSY timeout (%d) in compat_write_block_pio\n",
822 port->name, r);
823
824 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
825
826 return written;
827}
828
829/* ECP */
830#ifdef CONFIG_PARPORT_1284
831static size_t parport_pc_ecp_write_block_pio(struct parport *port,
832 const void *buf, size_t length,
833 int flags)
834{
835 size_t written;
836 int r;
837 unsigned long expire;
838 const struct parport_pc_private *priv = port->physport->private_data;
839
840 /* Special case: a timeout of zero means we cannot call schedule().
841 * Also if O_NONBLOCK is set then use the default implementation. */
842 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
843 return parport_ieee1284_ecp_write_data(port, buf,
844 length, flags);
845
846 /* Switch to forward mode if necessary. */
847 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
848 /* Event 47: Set nInit high. */
849 parport_frob_control(port,
850 PARPORT_CONTROL_INIT
851 | PARPORT_CONTROL_AUTOFD,
852 PARPORT_CONTROL_INIT
853 | PARPORT_CONTROL_AUTOFD);
854
855 /* Event 49: PError goes high. */
856 r = parport_wait_peripheral(port,
857 PARPORT_STATUS_PAPEROUT,
858 PARPORT_STATUS_PAPEROUT);
859 if (r) {
860 printk(KERN_DEBUG "%s: PError timeout (%d) "
861 "in ecp_write_block_pio\n", port->name, r);
862 }
863 }
864
865 /* Set up ECP parallel port mode.*/
866 parport_pc_data_forward(port); /* Must be in PS2 mode */
867 parport_pc_frob_control(port,
868 PARPORT_CONTROL_STROBE |
869 PARPORT_CONTROL_AUTOFD,
870 0);
871 r = change_mode(port, ECR_ECP); /* ECP FIFO */
872 if (r)
873 printk(KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n",
874 port->name);
875 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
876
877 /* Write the data to the FIFO. */
878 written = parport_pc_fifo_write_block(port, buf, length);
879
880 /* Finish up. */
881 /* For some hardware we don't want to touch the mode until
882 * the FIFO is empty, so allow 4 seconds for each position
883 * in the fifo.
884 */
885 expire = jiffies + (priv->fifo_depth * (HZ * 4));
886 do {
887 /* Wait for the FIFO to empty */
888 r = change_mode(port, ECR_PS2);
889 if (r != -EBUSY)
890 break;
891 } while (time_before(jiffies, expire));
892 if (r == -EBUSY) {
893
894 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
895
896 /* Prevent further data transfer. */
897 frob_set_mode(port, ECR_TST);
898
899 /* Adjust for the contents of the FIFO. */
900 for (written -= priv->fifo_depth; ; written++) {
901 if (inb(ECONTROL(port)) & 0x2) {
902 /* Full up. */
903 break;
904 }
905 outb(0, FIFO(port));
906 }
907
908 /* Reset the FIFO and return to PS2 mode. */
909 frob_set_mode(port, ECR_PS2);
910
911 /* Host transfer recovery. */
912 parport_pc_data_reverse(port); /* Must be in PS2 mode */
913 udelay(5);
914 parport_frob_control(port, PARPORT_CONTROL_INIT, 0);
915 r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0);
916 if (r)
917 printk(KERN_DEBUG "%s: PE,1 timeout (%d) "
918 "in ecp_write_block_pio\n", port->name, r);
919
920 parport_frob_control(port,
921 PARPORT_CONTROL_INIT,
922 PARPORT_CONTROL_INIT);
923 r = parport_wait_peripheral(port,
924 PARPORT_STATUS_PAPEROUT,
925 PARPORT_STATUS_PAPEROUT);
926 if (r)
927 printk(KERN_DEBUG "%s: PE,2 timeout (%d) "
928 "in ecp_write_block_pio\n", port->name, r);
929 }
930
931 r = parport_wait_peripheral(port,
932 PARPORT_STATUS_BUSY,
933 PARPORT_STATUS_BUSY);
934 if (r)
935 printk(KERN_DEBUG
936 "%s: BUSY timeout (%d) in ecp_write_block_pio\n",
937 port->name, r);
938
939 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
940
941 return written;
942}
943
944#if 0
945static size_t parport_pc_ecp_read_block_pio(struct parport *port,
946 void *buf, size_t length,
947 int flags)
948{
949 size_t left = length;
950 size_t fifofull;
951 int r;
952 const int fifo = FIFO(port);
953 const struct parport_pc_private *priv = port->physport->private_data;
954 const int fifo_depth = priv->fifo_depth;
955 char *bufp = buf;
956
957 port = port->physport;
958 DPRINTK(KERN_DEBUG "parport_pc: parport_pc_ecp_read_block_pio\n");
959 dump_parport_state("enter fcn", port);
960
961 /* Special case: a timeout of zero means we cannot call schedule().
962 * Also if O_NONBLOCK is set then use the default implementation. */
963 if (port->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
964 return parport_ieee1284_ecp_read_data(port, buf,
965 length, flags);
966
967 if (port->ieee1284.mode == IEEE1284_MODE_ECPRLE) {
968 /* If the peripheral is allowed to send RLE compressed
969 * data, it is possible for a byte to expand to 128
970 * bytes in the FIFO. */
971 fifofull = 128;
972 } else {
973 fifofull = fifo_depth;
974 }
975
976 /* If the caller wants less than a full FIFO's worth of data,
977 * go through software emulation. Otherwise we may have to throw
978 * away data. */
979 if (length < fifofull)
980 return parport_ieee1284_ecp_read_data(port, buf,
981 length, flags);
982
983 if (port->ieee1284.phase != IEEE1284_PH_REV_IDLE) {
984 /* change to reverse-idle phase (must be in forward-idle) */
985
986 /* Event 38: Set nAutoFd low (also make sure nStrobe is high) */
987 parport_frob_control(port,
988 PARPORT_CONTROL_AUTOFD
989 | PARPORT_CONTROL_STROBE,
990 PARPORT_CONTROL_AUTOFD);
991 parport_pc_data_reverse(port); /* Must be in PS2 mode */
992 udelay(5);
993 /* Event 39: Set nInit low to initiate bus reversal */
994 parport_frob_control(port,
995 PARPORT_CONTROL_INIT,
996 0);
997 /* Event 40: Wait for nAckReverse (PError) to go low */
998 r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0);
999 if (r) {
1000 printk(KERN_DEBUG "%s: PE timeout Event 40 (%d) "
1001 "in ecp_read_block_pio\n", port->name, r);
1002 return 0;
1003 }
1004 }
1005
1006 /* Set up ECP FIFO mode.*/
1007/* parport_pc_frob_control(port,
1008 PARPORT_CONTROL_STROBE |
1009 PARPORT_CONTROL_AUTOFD,
1010 PARPORT_CONTROL_AUTOFD); */
1011 r = change_mode(port, ECR_ECP); /* ECP FIFO */
1012 if (r)
1013 printk(KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n",
1014 port->name);
1015
1016 port->ieee1284.phase = IEEE1284_PH_REV_DATA;
1017
1018 /* the first byte must be collected manually */
1019 dump_parport_state("pre 43", port);
1020 /* Event 43: Wait for nAck to go low */
1021 r = parport_wait_peripheral(port, PARPORT_STATUS_ACK, 0);
1022 if (r) {
1023 /* timed out while reading -- no data */
1024 printk(KERN_DEBUG "PIO read timed out (initial byte)\n");
1025 goto out_no_data;
1026 }
1027 /* read byte */
1028 *bufp++ = inb(DATA(port));
1029 left--;
1030 dump_parport_state("43-44", port);
1031 /* Event 44: nAutoFd (HostAck) goes high to acknowledge */
1032 parport_pc_frob_control(port,
1033 PARPORT_CONTROL_AUTOFD,
1034 0);
1035 dump_parport_state("pre 45", port);
1036 /* Event 45: Wait for nAck to go high */
1037 /* r = parport_wait_peripheral(port, PARPORT_STATUS_ACK,
1038 PARPORT_STATUS_ACK); */
1039 dump_parport_state("post 45", port);
1040 r = 0;
1041 if (r) {
1042 /* timed out while waiting for peripheral to respond to ack */
1043 printk(KERN_DEBUG "ECP PIO read timed out (waiting for nAck)\n");
1044
1045 /* keep hold of the byte we've got already */
1046 goto out_no_data;
1047 }
1048 /* Event 46: nAutoFd (HostAck) goes low to accept more data */
1049 parport_pc_frob_control(port,
1050 PARPORT_CONTROL_AUTOFD,
1051 PARPORT_CONTROL_AUTOFD);
1052
1053
1054 dump_parport_state("rev idle", port);
1055 /* Do the transfer. */
1056 while (left > fifofull) {
1057 int ret;
1058 unsigned long expire = jiffies + port->cad->timeout;
1059 unsigned char ecrval = inb(ECONTROL(port));
1060
1061 if (need_resched() && time_before(jiffies, expire))
1062 /* Can't yield the port. */
1063 schedule();
1064
1065 /* At this point, the FIFO may already be full. In
1066 * that case ECP is already holding back the
1067 * peripheral (assuming proper design) with a delayed
1068 * handshake. Work fast to avoid a peripheral
1069 * timeout. */
1070
1071 if (ecrval & 0x01) {
1072 /* FIFO is empty. Wait for interrupt. */
1073 dump_parport_state("FIFO empty", port);
1074
1075 /* Anyone else waiting for the port? */
1076 if (port->waithead) {
1077 printk(KERN_DEBUG "Somebody wants the port\n");
1078 break;
1079 }
1080
1081 /* Clear serviceIntr */
1082 ECR_WRITE(port, ecrval & ~(1<<2));
1083false_alarm:
1084 dump_parport_state("waiting", port);
1085 ret = parport_wait_event(port, HZ);
1086 DPRINTK(KERN_DEBUG "parport_wait_event returned %d\n",
1087 ret);
1088 if (ret < 0)
1089 break;
1090 ret = 0;
1091 if (!time_before(jiffies, expire)) {
1092 /* Timed out. */
1093 dump_parport_state("timeout", port);
1094 printk(KERN_DEBUG "PIO read timed out\n");
1095 break;
1096 }
1097 ecrval = inb(ECONTROL(port));
1098 if (!(ecrval & (1<<2))) {
1099 if (need_resched() &&
1100 time_before(jiffies, expire)) {
1101 schedule();
1102 }
1103 goto false_alarm;
1104 }
1105
1106 /* Depending on how the FIFO threshold was
1107 * set, how long interrupt service took, and
1108 * how fast the peripheral is, we might be
1109 * lucky and have a just filled FIFO. */
1110 continue;
1111 }
1112
1113 if (ecrval & 0x02) {
1114 /* FIFO is full. */
1115 dump_parport_state("FIFO full", port);
1116 insb(fifo, bufp, fifo_depth);
1117 bufp += fifo_depth;
1118 left -= fifo_depth;
1119 continue;
1120 }
1121
1122 DPRINTK(KERN_DEBUG
1123 "*** ecp_read_block_pio: reading one byte from the FIFO\n");
1124
1125 /* FIFO not filled. We will cycle this loop for a while
1126 * and either the peripheral will fill it faster,
1127 * tripping a fast empty with insb, or we empty it. */
1128 *bufp++ = inb(fifo);
1129 left--;
1130 }
1131
1132 /* scoop up anything left in the FIFO */
1133 while (left && !(inb(ECONTROL(port) & 0x01))) {
1134 *bufp++ = inb(fifo);
1135 left--;
1136 }
1137
1138 port->ieee1284.phase = IEEE1284_PH_REV_IDLE;
1139 dump_parport_state("rev idle2", port);
1140
1141out_no_data:
1142
1143 /* Go to forward idle mode to shut the peripheral up (event 47). */
1144 parport_frob_control(port, PARPORT_CONTROL_INIT, PARPORT_CONTROL_INIT);
1145
1146 /* event 49: PError goes high */
1147 r = parport_wait_peripheral(port,
1148 PARPORT_STATUS_PAPEROUT,
1149 PARPORT_STATUS_PAPEROUT);
1150 if (r) {
1151 printk(KERN_DEBUG
1152 "%s: PE timeout FWDIDLE (%d) in ecp_read_block_pio\n",
1153 port->name, r);
1154 }
1155
1156 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
1157
1158 /* Finish up. */
1159 {
1160 int lost = get_fifo_residue(port);
1161 if (lost)
1162 /* Shouldn't happen with compliant peripherals. */
1163 printk(KERN_DEBUG "%s: DATA LOSS (%d bytes)!\n",
1164 port->name, lost);
1165 }
1166
1167 dump_parport_state("fwd idle", port);
1168 return length - left;
1169}
1170#endif /* 0 */
1171#endif /* IEEE 1284 support */
1172#endif /* Allowed to use FIFO/DMA */
1173
1174
1175/*
1176 * ******************************************
1177 * INITIALISATION AND MODULE STUFF BELOW HERE
1178 * ******************************************
1179 */
1180
1181/* GCC is not inlining extern inline function later overwriten to non-inline,
1182 so we use outlined_ variants here. */
1183static const struct parport_operations parport_pc_ops = {
1184 .write_data = parport_pc_write_data,
1185 .read_data = parport_pc_read_data,
1186
1187 .write_control = parport_pc_write_control,
1188 .read_control = parport_pc_read_control,
1189 .frob_control = parport_pc_frob_control,
1190
1191 .read_status = parport_pc_read_status,
1192
1193 .enable_irq = parport_pc_enable_irq,
1194 .disable_irq = parport_pc_disable_irq,
1195
1196 .data_forward = parport_pc_data_forward,
1197 .data_reverse = parport_pc_data_reverse,
1198
1199 .init_state = parport_pc_init_state,
1200 .save_state = parport_pc_save_state,
1201 .restore_state = parport_pc_restore_state,
1202
1203 .epp_write_data = parport_ieee1284_epp_write_data,
1204 .epp_read_data = parport_ieee1284_epp_read_data,
1205 .epp_write_addr = parport_ieee1284_epp_write_addr,
1206 .epp_read_addr = parport_ieee1284_epp_read_addr,
1207
1208 .ecp_write_data = parport_ieee1284_ecp_write_data,
1209 .ecp_read_data = parport_ieee1284_ecp_read_data,
1210 .ecp_write_addr = parport_ieee1284_ecp_write_addr,
1211
1212 .compat_write_data = parport_ieee1284_write_compat,
1213 .nibble_read_data = parport_ieee1284_read_nibble,
1214 .byte_read_data = parport_ieee1284_read_byte,
1215
1216 .owner = THIS_MODULE,
1217};
1218
1219#ifdef CONFIG_PARPORT_PC_SUPERIO
1220
1221static struct superio_struct *find_free_superio(void)
1222{
1223 int i;
1224 for (i = 0; i < NR_SUPERIOS; i++)
1225 if (superios[i].io == 0)
1226 return &superios[i];
1227 return NULL;
1228}
1229
1230
1231/* Super-IO chipset detection, Winbond, SMSC */
1232static void __devinit show_parconfig_smsc37c669(int io, int key)
1233{
1234 int cr1, cr4, cra, cr23, cr26, cr27;
1235 struct superio_struct *s;
1236
1237 static const char *const modes[] = {
1238 "SPP and Bidirectional (PS/2)",
1239 "EPP and SPP",
1240 "ECP",
1241 "ECP and EPP" };
1242
1243 outb(key, io);
1244 outb(key, io);
1245 outb(1, io);
1246 cr1 = inb(io + 1);
1247 outb(4, io);
1248 cr4 = inb(io + 1);
1249 outb(0x0a, io);
1250 cra = inb(io + 1);
1251 outb(0x23, io);
1252 cr23 = inb(io + 1);
1253 outb(0x26, io);
1254 cr26 = inb(io + 1);
1255 outb(0x27, io);
1256 cr27 = inb(io + 1);
1257 outb(0xaa, io);
1258
1259 if (verbose_probing) {
1260 printk(KERN_INFO
1261 "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, "
1262 "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n",
1263 cr1, cr4, cra, cr23, cr26, cr27);
1264
1265 /* The documentation calls DMA and IRQ-Lines by letters, so
1266 the board maker can/will wire them
1267 appropriately/randomly... G=reserved H=IDE-irq, */
1268 printk(KERN_INFO
1269 "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, fifo threshold=%d\n",
1270 cr23 * 4,
1271 (cr27 & 0x0f) ? 'A' - 1 + (cr27 & 0x0f) : '-',
1272 (cr26 & 0x0f) ? 'A' - 1 + (cr26 & 0x0f) : '-',
1273 cra & 0x0f);
1274 printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n",
1275 (cr23 * 4 >= 0x100) ? "yes" : "no",
1276 (cr1 & 4) ? "yes" : "no");
1277 printk(KERN_INFO
1278 "SMSC LPT Config: Port mode=%s, EPP version =%s\n",
1279 (cr1 & 0x08) ? "Standard mode only (SPP)"
1280 : modes[cr4 & 0x03],
1281 (cr4 & 0x40) ? "1.7" : "1.9");
1282 }
1283
1284 /* Heuristics ! BIOS setup for this mainboard device limits
1285 the choices to standard settings, i.e. io-address and IRQ
1286 are related, however DMA can be 1 or 3, assume DMA_A=DMA1,
1287 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */
1288 if (cr23 * 4 >= 0x100) { /* if active */
1289 s = find_free_superio();
1290 if (s == NULL)
1291 printk(KERN_INFO "Super-IO: too many chips!\n");
1292 else {
1293 int d;
1294 switch (cr23 * 4) {
1295 case 0x3bc:
1296 s->io = 0x3bc;
1297 s->irq = 7;
1298 break;
1299 case 0x378:
1300 s->io = 0x378;
1301 s->irq = 7;
1302 break;
1303 case 0x278:
1304 s->io = 0x278;
1305 s->irq = 5;
1306 }
1307 d = (cr26 & 0x0f);
1308 if (d == 1 || d == 3)
1309 s->dma = d;
1310 else
1311 s->dma = PARPORT_DMA_NONE;
1312 }
1313 }
1314}
1315
1316
1317static void __devinit show_parconfig_winbond(int io, int key)
1318{
1319 int cr30, cr60, cr61, cr70, cr74, crf0;
1320 struct superio_struct *s;
1321 static const char *const modes[] = {
1322 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */
1323 "EPP-1.9 and SPP",
1324 "ECP",
1325 "ECP and EPP-1.9",
1326 "Standard (SPP)",
1327 "EPP-1.7 and SPP", /* 5 */
1328 "undefined!",
1329 "ECP and EPP-1.7" };
1330 static char *const irqtypes[] = {
1331 "pulsed low, high-Z",
1332 "follows nACK" };
1333
1334 /* The registers are called compatible-PnP because the
1335 register layout is modelled after ISA-PnP, the access
1336 method is just another ... */
1337 outb(key, io);
1338 outb(key, io);
1339 outb(0x07, io); /* Register 7: Select Logical Device */
1340 outb(0x01, io + 1); /* LD1 is Parallel Port */
1341 outb(0x30, io);
1342 cr30 = inb(io + 1);
1343 outb(0x60, io);
1344 cr60 = inb(io + 1);
1345 outb(0x61, io);
1346 cr61 = inb(io + 1);
1347 outb(0x70, io);
1348 cr70 = inb(io + 1);
1349 outb(0x74, io);
1350 cr74 = inb(io + 1);
1351 outb(0xf0, io);
1352 crf0 = inb(io + 1);
1353 outb(0xaa, io);
1354
1355 if (verbose_probing) {
1356 printk(KERN_INFO
1357 "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x 70=%02x 74=%02x, f0=%02x\n",
1358 cr30, cr60, cr61, cr70, cr74, crf0);
1359 printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
1360 (cr30 & 0x01) ? "yes" : "no", cr60, cr61, cr70 & 0x0f);
1361 if ((cr74 & 0x07) > 3)
1362 printk("dma=none\n");
1363 else
1364 printk("dma=%d\n", cr74 & 0x07);
1365 printk(KERN_INFO
1366 "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n",
1367 irqtypes[crf0>>7], (crf0>>3)&0x0f);
1368 printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n",
1369 modes[crf0 & 0x07]);
1370 }
1371
1372 if (cr30 & 0x01) { /* the settings can be interrogated later ... */
1373 s = find_free_superio();
1374 if (s == NULL)
1375 printk(KERN_INFO "Super-IO: too many chips!\n");
1376 else {
1377 s->io = (cr60 << 8) | cr61;
1378 s->irq = cr70 & 0x0f;
1379 s->dma = (((cr74 & 0x07) > 3) ?
1380 PARPORT_DMA_NONE : (cr74 & 0x07));
1381 }
1382 }
1383}
1384
1385static void __devinit decode_winbond(int efer, int key, int devid,
1386 int devrev, int oldid)
1387{
1388 const char *type = "unknown";
1389 int id, progif = 2;
1390
1391 if (devid == devrev)
1392 /* simple heuristics, we happened to read some
1393 non-winbond register */
1394 return;
1395
1396 id = (devid << 8) | devrev;
1397
1398 /* Values are from public data sheets pdf files, I can just
1399 confirm 83977TF is correct :-) */
1400 if (id == 0x9771)
1401 type = "83977F/AF";
1402 else if (id == 0x9773)
1403 type = "83977TF / SMSC 97w33x/97w34x";
1404 else if (id == 0x9774)
1405 type = "83977ATF";
1406 else if ((id & ~0x0f) == 0x5270)
1407 type = "83977CTF / SMSC 97w36x";
1408 else if ((id & ~0x0f) == 0x52f0)
1409 type = "83977EF / SMSC 97w35x";
1410 else if ((id & ~0x0f) == 0x5210)
1411 type = "83627";
1412 else if ((id & ~0x0f) == 0x6010)
1413 type = "83697HF";
1414 else if ((oldid & 0x0f) == 0x0a) {
1415 type = "83877F";
1416 progif = 1;
1417 } else if ((oldid & 0x0f) == 0x0b) {
1418 type = "83877AF";
1419 progif = 1;
1420 } else if ((oldid & 0x0f) == 0x0c) {
1421 type = "83877TF";
1422 progif = 1;
1423 } else if ((oldid & 0x0f) == 0x0d) {
1424 type = "83877ATF";
1425 progif = 1;
1426 } else
1427 progif = 0;
1428
1429 if (verbose_probing)
1430 printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x "
1431 "devid=%02x devrev=%02x oldid=%02x type=%s\n",
1432 efer, key, devid, devrev, oldid, type);
1433
1434 if (progif == 2)
1435 show_parconfig_winbond(efer, key);
1436}
1437
1438static void __devinit decode_smsc(int efer, int key, int devid, int devrev)
1439{
1440 const char *type = "unknown";
1441 void (*func)(int io, int key);
1442 int id;
1443
1444 if (devid == devrev)
1445 /* simple heuristics, we happened to read some
1446 non-smsc register */
1447 return;
1448
1449 func = NULL;
1450 id = (devid << 8) | devrev;
1451
1452 if (id == 0x0302) {
1453 type = "37c669";
1454 func = show_parconfig_smsc37c669;
1455 } else if (id == 0x6582)
1456 type = "37c665IR";
1457 else if (devid == 0x65)
1458 type = "37c665GT";
1459 else if (devid == 0x66)
1460 type = "37c666GT";
1461
1462 if (verbose_probing)
1463 printk(KERN_INFO "SMSC chip at EFER=0x%x "
1464 "key=0x%02x devid=%02x devrev=%02x type=%s\n",
1465 efer, key, devid, devrev, type);
1466
1467 if (func)
1468 func(efer, key);
1469}
1470
1471
1472static void __devinit winbond_check(int io, int key)
1473{
1474 int origval, devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1475
1476 if (!request_region(io, 3, __func__))
1477 return;
1478
1479 origval = inb(io); /* Save original value */
1480
1481 /* First probe without key */
1482 outb(0x20, io);
1483 x_devid = inb(io + 1);
1484 outb(0x21, io);
1485 x_devrev = inb(io + 1);
1486 outb(0x09, io);
1487 x_oldid = inb(io + 1);
1488
1489 outb(key, io);
1490 outb(key, io); /* Write Magic Sequence to EFER, extended
1491 function enable register */
1492 outb(0x20, io); /* Write EFIR, extended function index register */
1493 devid = inb(io + 1); /* Read EFDR, extended function data register */
1494 outb(0x21, io);
1495 devrev = inb(io + 1);
1496 outb(0x09, io);
1497 oldid = inb(io + 1);
1498 outb(0xaa, io); /* Magic Seal */
1499
1500 outb(origval, io); /* in case we poked some entirely different hardware */
1501
1502 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1503 goto out; /* protection against false positives */
1504
1505 decode_winbond(io, key, devid, devrev, oldid);
1506out:
1507 release_region(io, 3);
1508}
1509
1510static void __devinit winbond_check2(int io, int key)
1511{
1512 int origval[3], devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1513
1514 if (!request_region(io, 3, __func__))
1515 return;
1516
1517 origval[0] = inb(io); /* Save original values */
1518 origval[1] = inb(io + 1);
1519 origval[2] = inb(io + 2);
1520
1521 /* First probe without the key */
1522 outb(0x20, io + 2);
1523 x_devid = inb(io + 2);
1524 outb(0x21, io + 1);
1525 x_devrev = inb(io + 2);
1526 outb(0x09, io + 1);
1527 x_oldid = inb(io + 2);
1528
1529 outb(key, io); /* Write Magic Byte to EFER, extended
1530 function enable register */
1531 outb(0x20, io + 2); /* Write EFIR, extended function index register */
1532 devid = inb(io + 2); /* Read EFDR, extended function data register */
1533 outb(0x21, io + 1);
1534 devrev = inb(io + 2);
1535 outb(0x09, io + 1);
1536 oldid = inb(io + 2);
1537 outb(0xaa, io); /* Magic Seal */
1538
1539 outb(origval[0], io); /* in case we poked some entirely different hardware */
1540 outb(origval[1], io + 1);
1541 outb(origval[2], io + 2);
1542
1543 if (x_devid == devid && x_devrev == devrev && x_oldid == oldid)
1544 goto out; /* protection against false positives */
1545
1546 decode_winbond(io, key, devid, devrev, oldid);
1547out:
1548 release_region(io, 3);
1549}
1550
1551static void __devinit smsc_check(int io, int key)
1552{
1553 int origval, id, rev, oldid, oldrev, x_id, x_rev, x_oldid, x_oldrev;
1554
1555 if (!request_region(io, 3, __func__))
1556 return;
1557
1558 origval = inb(io); /* Save original value */
1559
1560 /* First probe without the key */
1561 outb(0x0d, io);
1562 x_oldid = inb(io + 1);
1563 outb(0x0e, io);
1564 x_oldrev = inb(io + 1);
1565 outb(0x20, io);
1566 x_id = inb(io + 1);
1567 outb(0x21, io);
1568 x_rev = inb(io + 1);
1569
1570 outb(key, io);
1571 outb(key, io); /* Write Magic Sequence to EFER, extended
1572 function enable register */
1573 outb(0x0d, io); /* Write EFIR, extended function index register */
1574 oldid = inb(io + 1); /* Read EFDR, extended function data register */
1575 outb(0x0e, io);
1576 oldrev = inb(io + 1);
1577 outb(0x20, io);
1578 id = inb(io + 1);
1579 outb(0x21, io);
1580 rev = inb(io + 1);
1581 outb(0xaa, io); /* Magic Seal */
1582
1583 outb(origval, io); /* in case we poked some entirely different hardware */
1584
1585 if (x_id == id && x_oldrev == oldrev &&
1586 x_oldid == oldid && x_rev == rev)
1587 goto out; /* protection against false positives */
1588
1589 decode_smsc(io, key, oldid, oldrev);
1590out:
1591 release_region(io, 3);
1592}
1593
1594
1595static void __devinit detect_and_report_winbond(void)
1596{
1597 if (verbose_probing)
1598 printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n");
1599 winbond_check(0x3f0, 0x87);
1600 winbond_check(0x370, 0x87);
1601 winbond_check(0x2e , 0x87);
1602 winbond_check(0x4e , 0x87);
1603 winbond_check(0x3f0, 0x86);
1604 winbond_check2(0x250, 0x88);
1605 winbond_check2(0x250, 0x89);
1606}
1607
1608static void __devinit detect_and_report_smsc(void)
1609{
1610 if (verbose_probing)
1611 printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n");
1612 smsc_check(0x3f0, 0x55);
1613 smsc_check(0x370, 0x55);
1614 smsc_check(0x3f0, 0x44);
1615 smsc_check(0x370, 0x44);
1616}
1617
1618static void __devinit detect_and_report_it87(void)
1619{
1620 u16 dev;
1621 u8 origval, r;
1622 if (verbose_probing)
1623 printk(KERN_DEBUG "IT8705 Super-IO detection, now testing port 2E ...\n");
1624 if (!request_muxed_region(0x2e, 2, __func__))
1625 return;
1626 origval = inb(0x2e); /* Save original value */
1627 outb(0x87, 0x2e);
1628 outb(0x01, 0x2e);
1629 outb(0x55, 0x2e);
1630 outb(0x55, 0x2e);
1631 outb(0x20, 0x2e);
1632 dev = inb(0x2f) << 8;
1633 outb(0x21, 0x2e);
1634 dev |= inb(0x2f);
1635 if (dev == 0x8712 || dev == 0x8705 || dev == 0x8715 ||
1636 dev == 0x8716 || dev == 0x8718 || dev == 0x8726) {
1637 printk(KERN_INFO "IT%04X SuperIO detected.\n", dev);
1638 outb(0x07, 0x2E); /* Parallel Port */
1639 outb(0x03, 0x2F);
1640 outb(0xF0, 0x2E); /* BOOT 0x80 off */
1641 r = inb(0x2f);
1642 outb(0xF0, 0x2E);
1643 outb(r | 8, 0x2F);
1644 outb(0x02, 0x2E); /* Lock */
1645 outb(0x02, 0x2F);
1646 } else {
1647 outb(origval, 0x2e); /* Oops, sorry to disturb */
1648 }
1649 release_region(0x2e, 2);
1650}
1651#endif /* CONFIG_PARPORT_PC_SUPERIO */
1652
1653static struct superio_struct *find_superio(struct parport *p)
1654{
1655 int i;
1656 for (i = 0; i < NR_SUPERIOS; i++)
1657 if (superios[i].io != p->base)
1658 return &superios[i];
1659 return NULL;
1660}
1661
1662static int get_superio_dma(struct parport *p)
1663{
1664 struct superio_struct *s = find_superio(p);
1665 if (s)
1666 return s->dma;
1667 return PARPORT_DMA_NONE;
1668}
1669
1670static int get_superio_irq(struct parport *p)
1671{
1672 struct superio_struct *s = find_superio(p);
1673 if (s)
1674 return s->irq;
1675 return PARPORT_IRQ_NONE;
1676}
1677
1678
1679/* --- Mode detection ------------------------------------- */
1680
1681/*
1682 * Checks for port existence, all ports support SPP MODE
1683 * Returns:
1684 * 0 : No parallel port at this address
1685 * PARPORT_MODE_PCSPP : SPP port detected
1686 * (if the user specified an ioport himself,
1687 * this shall always be the case!)
1688 *
1689 */
1690static int parport_SPP_supported(struct parport *pb)
1691{
1692 unsigned char r, w;
1693
1694 /*
1695 * first clear an eventually pending EPP timeout
1696 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset
1697 * that does not even respond to SPP cycles if an EPP
1698 * timeout is pending
1699 */
1700 clear_epp_timeout(pb);
1701
1702 /* Do a simple read-write test to make sure the port exists. */
1703 w = 0xc;
1704 outb(w, CONTROL(pb));
1705
1706 /* Is there a control register that we can read from? Some
1707 * ports don't allow reads, so read_control just returns a
1708 * software copy. Some ports _do_ allow reads, so bypass the
1709 * software copy here. In addition, some bits aren't
1710 * writable. */
1711 r = inb(CONTROL(pb));
1712 if ((r & 0xf) == w) {
1713 w = 0xe;
1714 outb(w, CONTROL(pb));
1715 r = inb(CONTROL(pb));
1716 outb(0xc, CONTROL(pb));
1717 if ((r & 0xf) == w)
1718 return PARPORT_MODE_PCSPP;
1719 }
1720
1721 if (user_specified)
1722 /* That didn't work, but the user thinks there's a
1723 * port here. */
1724 printk(KERN_INFO "parport 0x%lx (WARNING): CTR: "
1725 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1726
1727 /* Try the data register. The data lines aren't tri-stated at
1728 * this stage, so we expect back what we wrote. */
1729 w = 0xaa;
1730 parport_pc_write_data(pb, w);
1731 r = parport_pc_read_data(pb);
1732 if (r == w) {
1733 w = 0x55;
1734 parport_pc_write_data(pb, w);
1735 r = parport_pc_read_data(pb);
1736 if (r == w)
1737 return PARPORT_MODE_PCSPP;
1738 }
1739
1740 if (user_specified) {
1741 /* Didn't work, but the user is convinced this is the
1742 * place. */
1743 printk(KERN_INFO "parport 0x%lx (WARNING): DATA: "
1744 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1745 printk(KERN_INFO "parport 0x%lx: You gave this address, "
1746 "but there is probably no parallel port there!\n",
1747 pb->base);
1748 }
1749
1750 /* It's possible that we can't read the control register or
1751 * the data register. In that case just believe the user. */
1752 if (user_specified)
1753 return PARPORT_MODE_PCSPP;
1754
1755 return 0;
1756}
1757
1758/* Check for ECR
1759 *
1760 * Old style XT ports alias io ports every 0x400, hence accessing ECR
1761 * on these cards actually accesses the CTR.
1762 *
1763 * Modern cards don't do this but reading from ECR will return 0xff
1764 * regardless of what is written here if the card does NOT support
1765 * ECP.
1766 *
1767 * We first check to see if ECR is the same as CTR. If not, the low
1768 * two bits of ECR aren't writable, so we check by writing ECR and
1769 * reading it back to see if it's what we expect.
1770 */
1771static int parport_ECR_present(struct parport *pb)
1772{
1773 struct parport_pc_private *priv = pb->private_data;
1774 unsigned char r = 0xc;
1775
1776 outb(r, CONTROL(pb));
1777 if ((inb(ECONTROL(pb)) & 0x3) == (r & 0x3)) {
1778 outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */
1779
1780 r = inb(CONTROL(pb));
1781 if ((inb(ECONTROL(pb)) & 0x2) == (r & 0x2))
1782 goto no_reg; /* Sure that no ECR register exists */
1783 }
1784
1785 if ((inb(ECONTROL(pb)) & 0x3) != 0x1)
1786 goto no_reg;
1787
1788 ECR_WRITE(pb, 0x34);
1789 if (inb(ECONTROL(pb)) != 0x35)
1790 goto no_reg;
1791
1792 priv->ecr = 1;
1793 outb(0xc, CONTROL(pb));
1794
1795 /* Go to mode 000 */
1796 frob_set_mode(pb, ECR_SPP);
1797
1798 return 1;
1799
1800 no_reg:
1801 outb(0xc, CONTROL(pb));
1802 return 0;
1803}
1804
1805#ifdef CONFIG_PARPORT_1284
1806/* Detect PS/2 support.
1807 *
1808 * Bit 5 (0x20) sets the PS/2 data direction; setting this high
1809 * allows us to read data from the data lines. In theory we would get back
1810 * 0xff but any peripheral attached to the port may drag some or all of the
1811 * lines down to zero. So if we get back anything that isn't the contents
1812 * of the data register we deem PS/2 support to be present.
1813 *
1814 * Some SPP ports have "half PS/2" ability - you can't turn off the line
1815 * drivers, but an external peripheral with sufficiently beefy drivers of
1816 * its own can overpower them and assert its own levels onto the bus, from
1817 * where they can then be read back as normal. Ports with this property
1818 * and the right type of device attached are likely to fail the SPP test,
1819 * (as they will appear to have stuck bits) and so the fact that they might
1820 * be misdetected here is rather academic.
1821 */
1822
1823static int parport_PS2_supported(struct parport *pb)
1824{
1825 int ok = 0;
1826
1827 clear_epp_timeout(pb);
1828
1829 /* try to tri-state the buffer */
1830 parport_pc_data_reverse(pb);
1831
1832 parport_pc_write_data(pb, 0x55);
1833 if (parport_pc_read_data(pb) != 0x55)
1834 ok++;
1835
1836 parport_pc_write_data(pb, 0xaa);
1837 if (parport_pc_read_data(pb) != 0xaa)
1838 ok++;
1839
1840 /* cancel input mode */
1841 parport_pc_data_forward(pb);
1842
1843 if (ok) {
1844 pb->modes |= PARPORT_MODE_TRISTATE;
1845 } else {
1846 struct parport_pc_private *priv = pb->private_data;
1847 priv->ctr_writable &= ~0x20;
1848 }
1849
1850 return ok;
1851}
1852
1853#ifdef CONFIG_PARPORT_PC_FIFO
1854static int parport_ECP_supported(struct parport *pb)
1855{
1856 int i;
1857 int config, configb;
1858 int pword;
1859 struct parport_pc_private *priv = pb->private_data;
1860 /* Translate ECP intrLine to ISA irq value */
1861 static const int intrline[] = { 0, 7, 9, 10, 11, 14, 15, 5 };
1862
1863 /* If there is no ECR, we have no hope of supporting ECP. */
1864 if (!priv->ecr)
1865 return 0;
1866
1867 /* Find out FIFO depth */
1868 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1869 ECR_WRITE(pb, ECR_TST << 5); /* TEST FIFO */
1870 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02); i++)
1871 outb(0xaa, FIFO(pb));
1872
1873 /*
1874 * Using LGS chipset it uses ECR register, but
1875 * it doesn't support ECP or FIFO MODE
1876 */
1877 if (i == 1024) {
1878 ECR_WRITE(pb, ECR_SPP << 5);
1879 return 0;
1880 }
1881
1882 priv->fifo_depth = i;
1883 if (verbose_probing)
1884 printk(KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i);
1885
1886 /* Find out writeIntrThreshold */
1887 frob_econtrol(pb, 1<<2, 1<<2);
1888 frob_econtrol(pb, 1<<2, 0);
1889 for (i = 1; i <= priv->fifo_depth; i++) {
1890 inb(FIFO(pb));
1891 udelay(50);
1892 if (inb(ECONTROL(pb)) & (1<<2))
1893 break;
1894 }
1895
1896 if (i <= priv->fifo_depth) {
1897 if (verbose_probing)
1898 printk(KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n",
1899 pb->base, i);
1900 } else
1901 /* Number of bytes we know we can write if we get an
1902 interrupt. */
1903 i = 0;
1904
1905 priv->writeIntrThreshold = i;
1906
1907 /* Find out readIntrThreshold */
1908 frob_set_mode(pb, ECR_PS2); /* Reset FIFO and enable PS2 */
1909 parport_pc_data_reverse(pb); /* Must be in PS2 mode */
1910 frob_set_mode(pb, ECR_TST); /* Test FIFO */
1911 frob_econtrol(pb, 1<<2, 1<<2);
1912 frob_econtrol(pb, 1<<2, 0);
1913 for (i = 1; i <= priv->fifo_depth; i++) {
1914 outb(0xaa, FIFO(pb));
1915 if (inb(ECONTROL(pb)) & (1<<2))
1916 break;
1917 }
1918
1919 if (i <= priv->fifo_depth) {
1920 if (verbose_probing)
1921 printk(KERN_INFO "0x%lx: readIntrThreshold is %d\n",
1922 pb->base, i);
1923 } else
1924 /* Number of bytes we can read if we get an interrupt. */
1925 i = 0;
1926
1927 priv->readIntrThreshold = i;
1928
1929 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1930 ECR_WRITE(pb, 0xf4); /* Configuration mode */
1931 config = inb(CONFIGA(pb));
1932 pword = (config >> 4) & 0x7;
1933 switch (pword) {
1934 case 0:
1935 pword = 2;
1936 printk(KERN_WARNING "0x%lx: Unsupported pword size!\n",
1937 pb->base);
1938 break;
1939 case 2:
1940 pword = 4;
1941 printk(KERN_WARNING "0x%lx: Unsupported pword size!\n",
1942 pb->base);
1943 break;
1944 default:
1945 printk(KERN_WARNING "0x%lx: Unknown implementation ID\n",
1946 pb->base);
1947 /* Assume 1 */
1948 case 1:
1949 pword = 1;
1950 }
1951 priv->pword = pword;
1952
1953 if (verbose_probing) {
1954 printk(KERN_DEBUG "0x%lx: PWord is %d bits\n",
1955 pb->base, 8 * pword);
1956
1957 printk(KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base,
1958 config & 0x80 ? "Level" : "Pulses");
1959
1960 configb = inb(CONFIGB(pb));
1961 printk(KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
1962 pb->base, config, configb);
1963 printk(KERN_DEBUG "0x%lx: ECP settings irq=", pb->base);
1964 if ((configb >> 3) & 0x07)
1965 printk("%d", intrline[(configb >> 3) & 0x07]);
1966 else
1967 printk("<none or set by other means>");
1968 printk(" dma=");
1969 if ((configb & 0x03) == 0x00)
1970 printk("<none or set by other means>\n");
1971 else
1972 printk("%d\n", configb & 0x07);
1973 }
1974
1975 /* Go back to mode 000 */
1976 frob_set_mode(pb, ECR_SPP);
1977
1978 return 1;
1979}
1980#endif
1981
1982static int parport_ECPPS2_supported(struct parport *pb)
1983{
1984 const struct parport_pc_private *priv = pb->private_data;
1985 int result;
1986 unsigned char oecr;
1987
1988 if (!priv->ecr)
1989 return 0;
1990
1991 oecr = inb(ECONTROL(pb));
1992 ECR_WRITE(pb, ECR_PS2 << 5);
1993 result = parport_PS2_supported(pb);
1994 ECR_WRITE(pb, oecr);
1995 return result;
1996}
1997
1998/* EPP mode detection */
1999
2000static int parport_EPP_supported(struct parport *pb)
2001{
2002 const struct parport_pc_private *priv = pb->private_data;
2003
2004 /*
2005 * Theory:
2006 * Bit 0 of STR is the EPP timeout bit, this bit is 0
2007 * when EPP is possible and is set high when an EPP timeout
2008 * occurs (EPP uses the HALT line to stop the CPU while it does
2009 * the byte transfer, an EPP timeout occurs if the attached
2010 * device fails to respond after 10 micro seconds).
2011 *
2012 * This bit is cleared by either reading it (National Semi)
2013 * or writing a 1 to the bit (SMC, UMC, WinBond), others ???
2014 * This bit is always high in non EPP modes.
2015 */
2016
2017 /* If EPP timeout bit clear then EPP available */
2018 if (!clear_epp_timeout(pb))
2019 return 0; /* No way to clear timeout */
2020
2021 /* Check for Intel bug. */
2022 if (priv->ecr) {
2023 unsigned char i;
2024 for (i = 0x00; i < 0x80; i += 0x20) {
2025 ECR_WRITE(pb, i);
2026 if (clear_epp_timeout(pb)) {
2027 /* Phony EPP in ECP. */
2028 return 0;
2029 }
2030 }
2031 }
2032
2033 pb->modes |= PARPORT_MODE_EPP;
2034
2035 /* Set up access functions to use EPP hardware. */
2036 pb->ops->epp_read_data = parport_pc_epp_read_data;
2037 pb->ops->epp_write_data = parport_pc_epp_write_data;
2038 pb->ops->epp_read_addr = parport_pc_epp_read_addr;
2039 pb->ops->epp_write_addr = parport_pc_epp_write_addr;
2040
2041 return 1;
2042}
2043
2044static int parport_ECPEPP_supported(struct parport *pb)
2045{
2046 struct parport_pc_private *priv = pb->private_data;
2047 int result;
2048 unsigned char oecr;
2049
2050 if (!priv->ecr)
2051 return 0;
2052
2053 oecr = inb(ECONTROL(pb));
2054 /* Search for SMC style EPP+ECP mode */
2055 ECR_WRITE(pb, 0x80);
2056 outb(0x04, CONTROL(pb));
2057 result = parport_EPP_supported(pb);
2058
2059 ECR_WRITE(pb, oecr);
2060
2061 if (result) {
2062 /* Set up access functions to use ECP+EPP hardware. */
2063 pb->ops->epp_read_data = parport_pc_ecpepp_read_data;
2064 pb->ops->epp_write_data = parport_pc_ecpepp_write_data;
2065 pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr;
2066 pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr;
2067 }
2068
2069 return result;
2070}
2071
2072#else /* No IEEE 1284 support */
2073
2074/* Don't bother probing for modes we know we won't use. */
2075static int __devinit parport_PS2_supported(struct parport *pb) { return 0; }
2076#ifdef CONFIG_PARPORT_PC_FIFO
2077static int parport_ECP_supported(struct parport *pb)
2078{
2079 return 0;
2080}
2081#endif
2082static int __devinit parport_EPP_supported(struct parport *pb)
2083{
2084 return 0;
2085}
2086
2087static int __devinit parport_ECPEPP_supported(struct parport *pb)
2088{
2089 return 0;
2090}
2091
2092static int __devinit parport_ECPPS2_supported(struct parport *pb)
2093{
2094 return 0;
2095}
2096
2097#endif /* No IEEE 1284 support */
2098
2099/* --- IRQ detection -------------------------------------- */
2100
2101/* Only if supports ECP mode */
2102static int programmable_irq_support(struct parport *pb)
2103{
2104 int irq, intrLine;
2105 unsigned char oecr = inb(ECONTROL(pb));
2106 static const int lookup[8] = {
2107 PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5
2108 };
2109
2110 ECR_WRITE(pb, ECR_CNF << 5); /* Configuration MODE */
2111
2112 intrLine = (inb(CONFIGB(pb)) >> 3) & 0x07;
2113 irq = lookup[intrLine];
2114
2115 ECR_WRITE(pb, oecr);
2116 return irq;
2117}
2118
2119static int irq_probe_ECP(struct parport *pb)
2120{
2121 int i;
2122 unsigned long irqs;
2123
2124 irqs = probe_irq_on();
2125
2126 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
2127 ECR_WRITE(pb, (ECR_TST << 5) | 0x04);
2128 ECR_WRITE(pb, ECR_TST << 5);
2129
2130 /* If Full FIFO sure that writeIntrThreshold is generated */
2131 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02) ; i++)
2132 outb(0xaa, FIFO(pb));
2133
2134 pb->irq = probe_irq_off(irqs);
2135 ECR_WRITE(pb, ECR_SPP << 5);
2136
2137 if (pb->irq <= 0)
2138 pb->irq = PARPORT_IRQ_NONE;
2139
2140 return pb->irq;
2141}
2142
2143/*
2144 * This detection seems that only works in National Semiconductors
2145 * This doesn't work in SMC, LGS, and Winbond
2146 */
2147static int irq_probe_EPP(struct parport *pb)
2148{
2149#ifndef ADVANCED_DETECT
2150 return PARPORT_IRQ_NONE;
2151#else
2152 int irqs;
2153 unsigned char oecr;
2154
2155 if (pb->modes & PARPORT_MODE_PCECR)
2156 oecr = inb(ECONTROL(pb));
2157
2158 irqs = probe_irq_on();
2159
2160 if (pb->modes & PARPORT_MODE_PCECR)
2161 frob_econtrol(pb, 0x10, 0x10);
2162
2163 clear_epp_timeout(pb);
2164 parport_pc_frob_control(pb, 0x20, 0x20);
2165 parport_pc_frob_control(pb, 0x10, 0x10);
2166 clear_epp_timeout(pb);
2167
2168 /* Device isn't expecting an EPP read
2169 * and generates an IRQ.
2170 */
2171 parport_pc_read_epp(pb);
2172 udelay(20);
2173
2174 pb->irq = probe_irq_off(irqs);
2175 if (pb->modes & PARPORT_MODE_PCECR)
2176 ECR_WRITE(pb, oecr);
2177 parport_pc_write_control(pb, 0xc);
2178
2179 if (pb->irq <= 0)
2180 pb->irq = PARPORT_IRQ_NONE;
2181
2182 return pb->irq;
2183#endif /* Advanced detection */
2184}
2185
2186static int irq_probe_SPP(struct parport *pb)
2187{
2188 /* Don't even try to do this. */
2189 return PARPORT_IRQ_NONE;
2190}
2191
2192/* We will attempt to share interrupt requests since other devices
2193 * such as sound cards and network cards seem to like using the
2194 * printer IRQs.
2195 *
2196 * When ECP is available we can autoprobe for IRQs.
2197 * NOTE: If we can autoprobe it, we can register the IRQ.
2198 */
2199static int parport_irq_probe(struct parport *pb)
2200{
2201 struct parport_pc_private *priv = pb->private_data;
2202
2203 if (priv->ecr) {
2204 pb->irq = programmable_irq_support(pb);
2205
2206 if (pb->irq == PARPORT_IRQ_NONE)
2207 pb->irq = irq_probe_ECP(pb);
2208 }
2209
2210 if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr &&
2211 (pb->modes & PARPORT_MODE_EPP))
2212 pb->irq = irq_probe_EPP(pb);
2213
2214 clear_epp_timeout(pb);
2215
2216 if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP))
2217 pb->irq = irq_probe_EPP(pb);
2218
2219 clear_epp_timeout(pb);
2220
2221 if (pb->irq == PARPORT_IRQ_NONE)
2222 pb->irq = irq_probe_SPP(pb);
2223
2224 if (pb->irq == PARPORT_IRQ_NONE)
2225 pb->irq = get_superio_irq(pb);
2226
2227 return pb->irq;
2228}
2229
2230/* --- DMA detection -------------------------------------- */
2231
2232/* Only if chipset conforms to ECP ISA Interface Standard */
2233static int programmable_dma_support(struct parport *p)
2234{
2235 unsigned char oecr = inb(ECONTROL(p));
2236 int dma;
2237
2238 frob_set_mode(p, ECR_CNF);
2239
2240 dma = inb(CONFIGB(p)) & 0x07;
2241 /* 000: Indicates jumpered 8-bit DMA if read-only.
2242 100: Indicates jumpered 16-bit DMA if read-only. */
2243 if ((dma & 0x03) == 0)
2244 dma = PARPORT_DMA_NONE;
2245
2246 ECR_WRITE(p, oecr);
2247 return dma;
2248}
2249
2250static int parport_dma_probe(struct parport *p)
2251{
2252 const struct parport_pc_private *priv = p->private_data;
2253 if (priv->ecr) /* ask ECP chipset first */
2254 p->dma = programmable_dma_support(p);
2255 if (p->dma == PARPORT_DMA_NONE) {
2256 /* ask known Super-IO chips proper, although these
2257 claim ECP compatible, some don't report their DMA
2258 conforming to ECP standards */
2259 p->dma = get_superio_dma(p);
2260 }
2261
2262 return p->dma;
2263}
2264
2265/* --- Initialisation code -------------------------------- */
2266
2267static LIST_HEAD(ports_list);
2268static DEFINE_SPINLOCK(ports_lock);
2269
2270struct parport *parport_pc_probe_port(unsigned long int base,
2271 unsigned long int base_hi,
2272 int irq, int dma,
2273 struct device *dev,
2274 int irqflags)
2275{
2276 struct parport_pc_private *priv;
2277 struct parport_operations *ops;
2278 struct parport *p;
2279 int probedirq = PARPORT_IRQ_NONE;
2280 struct resource *base_res;
2281 struct resource *ECR_res = NULL;
2282 struct resource *EPP_res = NULL;
2283 struct platform_device *pdev = NULL;
2284
2285 if (!dev) {
2286 /* We need a physical device to attach to, but none was
2287 * provided. Create our own. */
2288 pdev = platform_device_register_simple("parport_pc",
2289 base, NULL, 0);
2290 if (IS_ERR(pdev))
2291 return NULL;
2292 dev = &pdev->dev;
2293
2294 dev->coherent_dma_mask = DMA_BIT_MASK(24);
2295 dev->dma_mask = &dev->coherent_dma_mask;
2296 }
2297
2298 ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL);
2299 if (!ops)
2300 goto out1;
2301
2302 priv = kmalloc(sizeof(struct parport_pc_private), GFP_KERNEL);
2303 if (!priv)
2304 goto out2;
2305
2306 /* a misnomer, actually - it's allocate and reserve parport number */
2307 p = parport_register_port(base, irq, dma, ops);
2308 if (!p)
2309 goto out3;
2310
2311 base_res = request_region(base, 3, p->name);
2312 if (!base_res)
2313 goto out4;
2314
2315 memcpy(ops, &parport_pc_ops, sizeof(struct parport_operations));
2316 priv->ctr = 0xc;
2317 priv->ctr_writable = ~0x10;
2318 priv->ecr = 0;
2319 priv->fifo_depth = 0;
2320 priv->dma_buf = NULL;
2321 priv->dma_handle = 0;
2322 INIT_LIST_HEAD(&priv->list);
2323 priv->port = p;
2324
2325 p->dev = dev;
2326 p->base_hi = base_hi;
2327 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
2328 p->private_data = priv;
2329
2330 if (base_hi) {
2331 ECR_res = request_region(base_hi, 3, p->name);
2332 if (ECR_res)
2333 parport_ECR_present(p);
2334 }
2335
2336 if (base != 0x3bc) {
2337 EPP_res = request_region(base+0x3, 5, p->name);
2338 if (EPP_res)
2339 if (!parport_EPP_supported(p))
2340 parport_ECPEPP_supported(p);
2341 }
2342 if (!parport_SPP_supported(p))
2343 /* No port. */
2344 goto out5;
2345 if (priv->ecr)
2346 parport_ECPPS2_supported(p);
2347 else
2348 parport_PS2_supported(p);
2349
2350 p->size = (p->modes & PARPORT_MODE_EPP) ? 8 : 3;
2351
2352 printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base);
2353 if (p->base_hi && priv->ecr)
2354 printk(" (0x%lx)", p->base_hi);
2355 if (p->irq == PARPORT_IRQ_AUTO) {
2356 p->irq = PARPORT_IRQ_NONE;
2357 parport_irq_probe(p);
2358 } else if (p->irq == PARPORT_IRQ_PROBEONLY) {
2359 p->irq = PARPORT_IRQ_NONE;
2360 parport_irq_probe(p);
2361 probedirq = p->irq;
2362 p->irq = PARPORT_IRQ_NONE;
2363 }
2364 if (p->irq != PARPORT_IRQ_NONE) {
2365 printk(", irq %d", p->irq);
2366 priv->ctr_writable |= 0x10;
2367
2368 if (p->dma == PARPORT_DMA_AUTO) {
2369 p->dma = PARPORT_DMA_NONE;
2370 parport_dma_probe(p);
2371 }
2372 }
2373 if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq
2374 is mandatory (see above) */
2375 p->dma = PARPORT_DMA_NONE;
2376
2377#ifdef CONFIG_PARPORT_PC_FIFO
2378 if (parport_ECP_supported(p) &&
2379 p->dma != PARPORT_DMA_NOFIFO &&
2380 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) {
2381 p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT;
2382 p->ops->compat_write_data = parport_pc_compat_write_block_pio;
2383#ifdef CONFIG_PARPORT_1284
2384 p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
2385 /* currently broken, but working on it.. (FB) */
2386 /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */
2387#endif /* IEEE 1284 support */
2388 if (p->dma != PARPORT_DMA_NONE) {
2389 printk(", dma %d", p->dma);
2390 p->modes |= PARPORT_MODE_DMA;
2391 } else
2392 printk(", using FIFO");
2393 } else
2394 /* We can't use the DMA channel after all. */
2395 p->dma = PARPORT_DMA_NONE;
2396#endif /* Allowed to use FIFO/DMA */
2397
2398 printk(" [");
2399
2400#define printmode(x) \
2401 {\
2402 if (p->modes & PARPORT_MODE_##x) {\
2403 printk("%s%s", f ? "," : "", #x);\
2404 f++;\
2405 } \
2406 }
2407
2408 {
2409 int f = 0;
2410 printmode(PCSPP);
2411 printmode(TRISTATE);
2412 printmode(COMPAT)
2413 printmode(EPP);
2414 printmode(ECP);
2415 printmode(DMA);
2416 }
2417#undef printmode
2418#ifndef CONFIG_PARPORT_1284
2419 printk("(,...)");
2420#endif /* CONFIG_PARPORT_1284 */
2421 printk("]\n");
2422 if (probedirq != PARPORT_IRQ_NONE)
2423 printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq);
2424
2425 /* If No ECP release the ports grabbed above. */
2426 if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) {
2427 release_region(base_hi, 3);
2428 ECR_res = NULL;
2429 }
2430 /* Likewise for EEP ports */
2431 if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) {
2432 release_region(base+3, 5);
2433 EPP_res = NULL;
2434 }
2435 if (p->irq != PARPORT_IRQ_NONE) {
2436 if (request_irq(p->irq, parport_irq_handler,
2437 irqflags, p->name, p)) {
2438 printk(KERN_WARNING "%s: irq %d in use, "
2439 "resorting to polled operation\n",
2440 p->name, p->irq);
2441 p->irq = PARPORT_IRQ_NONE;
2442 p->dma = PARPORT_DMA_NONE;
2443 }
2444
2445#ifdef CONFIG_PARPORT_PC_FIFO
2446#ifdef HAS_DMA
2447 if (p->dma != PARPORT_DMA_NONE) {
2448 if (request_dma(p->dma, p->name)) {
2449 printk(KERN_WARNING "%s: dma %d in use, "
2450 "resorting to PIO operation\n",
2451 p->name, p->dma);
2452 p->dma = PARPORT_DMA_NONE;
2453 } else {
2454 priv->dma_buf =
2455 dma_alloc_coherent(dev,
2456 PAGE_SIZE,
2457 &priv->dma_handle,
2458 GFP_KERNEL);
2459 if (!priv->dma_buf) {
2460 printk(KERN_WARNING "%s: "
2461 "cannot get buffer for DMA, "
2462 "resorting to PIO operation\n",
2463 p->name);
2464 free_dma(p->dma);
2465 p->dma = PARPORT_DMA_NONE;
2466 }
2467 }
2468 }
2469#endif
2470#endif
2471 }
2472
2473 /* Done probing. Now put the port into a sensible start-up state. */
2474 if (priv->ecr)
2475 /*
2476 * Put the ECP detected port in PS2 mode.
2477 * Do this also for ports that have ECR but don't do ECP.
2478 */
2479 ECR_WRITE(p, 0x34);
2480
2481 parport_pc_write_data(p, 0);
2482 parport_pc_data_forward(p);
2483
2484 /* Now that we've told the sharing engine about the port, and
2485 found out its characteristics, let the high-level drivers
2486 know about it. */
2487 spin_lock(&ports_lock);
2488 list_add(&priv->list, &ports_list);
2489 spin_unlock(&ports_lock);
2490 parport_announce_port(p);
2491
2492 return p;
2493
2494out5:
2495 if (ECR_res)
2496 release_region(base_hi, 3);
2497 if (EPP_res)
2498 release_region(base+0x3, 5);
2499 release_region(base, 3);
2500out4:
2501 parport_put_port(p);
2502out3:
2503 kfree(priv);
2504out2:
2505 kfree(ops);
2506out1:
2507 if (pdev)
2508 platform_device_unregister(pdev);
2509 return NULL;
2510}
2511EXPORT_SYMBOL(parport_pc_probe_port);
2512
2513void parport_pc_unregister_port(struct parport *p)
2514{
2515 struct parport_pc_private *priv = p->private_data;
2516 struct parport_operations *ops = p->ops;
2517
2518 parport_remove_port(p);
2519 spin_lock(&ports_lock);
2520 list_del_init(&priv->list);
2521 spin_unlock(&ports_lock);
2522#if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2523 if (p->dma != PARPORT_DMA_NONE)
2524 free_dma(p->dma);
2525#endif
2526 if (p->irq != PARPORT_IRQ_NONE)
2527 free_irq(p->irq, p);
2528 release_region(p->base, 3);
2529 if (p->size > 3)
2530 release_region(p->base + 3, p->size - 3);
2531 if (p->modes & PARPORT_MODE_ECP)
2532 release_region(p->base_hi, 3);
2533#if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2534 if (priv->dma_buf)
2535 dma_free_coherent(p->physport->dev, PAGE_SIZE,
2536 priv->dma_buf,
2537 priv->dma_handle);
2538#endif
2539 kfree(p->private_data);
2540 parport_put_port(p);
2541 kfree(ops); /* hope no-one cached it */
2542}
2543EXPORT_SYMBOL(parport_pc_unregister_port);
2544
2545#ifdef CONFIG_PCI
2546
2547/* ITE support maintained by Rich Liu <richliu@poorman.org> */
2548static int __devinit sio_ite_8872_probe(struct pci_dev *pdev, int autoirq,
2549 int autodma,
2550 const struct parport_pc_via_data *via)
2551{
2552 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 };
2553 u32 ite8872set;
2554 u32 ite8872_lpt, ite8872_lpthi;
2555 u8 ite8872_irq, type;
2556 int irq;
2557 int i;
2558
2559 DPRINTK(KERN_DEBUG "sio_ite_8872_probe()\n");
2560
2561 /* make sure which one chip */
2562 for (i = 0; i < 5; i++) {
2563 if (request_region(inta_addr[i], 32, "it887x")) {
2564 int test;
2565 pci_write_config_dword(pdev, 0x60,
2566 0xe5000000 | inta_addr[i]);
2567 pci_write_config_dword(pdev, 0x78,
2568 0x00000000 | inta_addr[i]);
2569 test = inb(inta_addr[i]);
2570 if (test != 0xff)
2571 break;
2572 release_region(inta_addr[i], 32);
2573 }
2574 }
2575 if (i >= 5) {
2576 printk(KERN_INFO "parport_pc: cannot find ITE8872 INTA\n");
2577 return 0;
2578 }
2579
2580 type = inb(inta_addr[i] + 0x18);
2581 type &= 0x0f;
2582
2583 switch (type) {
2584 case 0x2:
2585 printk(KERN_INFO "parport_pc: ITE8871 found (1P)\n");
2586 ite8872set = 0x64200000;
2587 break;
2588 case 0xa:
2589 printk(KERN_INFO "parport_pc: ITE8875 found (1P)\n");
2590 ite8872set = 0x64200000;
2591 break;
2592 case 0xe:
2593 printk(KERN_INFO "parport_pc: ITE8872 found (2S1P)\n");
2594 ite8872set = 0x64e00000;
2595 break;
2596 case 0x6:
2597 printk(KERN_INFO "parport_pc: ITE8873 found (1S)\n");
2598 return 0;
2599 case 0x8:
2600 printk(KERN_INFO "parport_pc: ITE8874 found (2S)\n");
2601 return 0;
2602 default:
2603 printk(KERN_INFO "parport_pc: unknown ITE887x\n");
2604 printk(KERN_INFO "parport_pc: please mail 'lspci -nvv' "
2605 "output to Rich.Liu@ite.com.tw\n");
2606 return 0;
2607 }
2608
2609 pci_read_config_byte(pdev, 0x3c, &ite8872_irq);
2610 pci_read_config_dword(pdev, 0x1c, &ite8872_lpt);
2611 ite8872_lpt &= 0x0000ff00;
2612 pci_read_config_dword(pdev, 0x20, &ite8872_lpthi);
2613 ite8872_lpthi &= 0x0000ff00;
2614 pci_write_config_dword(pdev, 0x6c, 0xe3000000 | ite8872_lpt);
2615 pci_write_config_dword(pdev, 0x70, 0xe3000000 | ite8872_lpthi);
2616 pci_write_config_dword(pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt);
2617 /* SET SPP&EPP , Parallel Port NO DMA , Enable All Function */
2618 /* SET Parallel IRQ */
2619 pci_write_config_dword(pdev, 0x9c,
2620 ite8872set | (ite8872_irq * 0x11111));
2621
2622 DPRINTK(KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq);
2623 DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n",
2624 ite8872_lpt);
2625 DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n",
2626 ite8872_lpthi);
2627
2628 /* Let the user (or defaults) steer us away from interrupts */
2629 irq = ite8872_irq;
2630 if (autoirq != PARPORT_IRQ_AUTO)
2631 irq = PARPORT_IRQ_NONE;
2632
2633 /*
2634 * Release the resource so that parport_pc_probe_port can get it.
2635 */
2636 release_region(inta_addr[i], 32);
2637 if (parport_pc_probe_port(ite8872_lpt, ite8872_lpthi,
2638 irq, PARPORT_DMA_NONE, &pdev->dev, 0)) {
2639 printk(KERN_INFO
2640 "parport_pc: ITE 8872 parallel port: io=0x%X",
2641 ite8872_lpt);
2642 if (irq != PARPORT_IRQ_NONE)
2643 printk(", irq=%d", irq);
2644 printk("\n");
2645 return 1;
2646 }
2647
2648 return 0;
2649}
2650
2651/* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru>
2652 based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */
2653static int __devinitdata parport_init_mode;
2654
2655/* Data for two known VIA chips */
2656static struct parport_pc_via_data via_686a_data __devinitdata = {
2657 0x51,
2658 0x50,
2659 0x85,
2660 0x02,
2661 0xE2,
2662 0xF0,
2663 0xE6
2664};
2665static struct parport_pc_via_data via_8231_data __devinitdata = {
2666 0x45,
2667 0x44,
2668 0x50,
2669 0x04,
2670 0xF2,
2671 0xFA,
2672 0xF6
2673};
2674
2675static int __devinit sio_via_probe(struct pci_dev *pdev, int autoirq,
2676 int autodma,
2677 const struct parport_pc_via_data *via)
2678{
2679 u8 tmp, tmp2, siofunc;
2680 u8 ppcontrol = 0;
2681 int dma, irq;
2682 unsigned port1, port2;
2683 unsigned have_epp = 0;
2684
2685 printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n");
2686
2687 switch (parport_init_mode) {
2688 case 1:
2689 printk(KERN_DEBUG "parport_pc: setting SPP mode\n");
2690 siofunc = VIA_FUNCTION_PARPORT_SPP;
2691 break;
2692 case 2:
2693 printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n");
2694 siofunc = VIA_FUNCTION_PARPORT_SPP;
2695 ppcontrol = VIA_PARPORT_BIDIR;
2696 break;
2697 case 3:
2698 printk(KERN_DEBUG "parport_pc: setting EPP mode\n");
2699 siofunc = VIA_FUNCTION_PARPORT_EPP;
2700 ppcontrol = VIA_PARPORT_BIDIR;
2701 have_epp = 1;
2702 break;
2703 case 4:
2704 printk(KERN_DEBUG "parport_pc: setting ECP mode\n");
2705 siofunc = VIA_FUNCTION_PARPORT_ECP;
2706 ppcontrol = VIA_PARPORT_BIDIR;
2707 break;
2708 case 5:
2709 printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n");
2710 siofunc = VIA_FUNCTION_PARPORT_ECP;
2711 ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP;
2712 have_epp = 1;
2713 break;
2714 default:
2715 printk(KERN_DEBUG
2716 "parport_pc: probing current configuration\n");
2717 siofunc = VIA_FUNCTION_PROBE;
2718 break;
2719 }
2720 /*
2721 * unlock super i/o configuration
2722 */
2723 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2724 tmp |= via->via_pci_superio_config_data;
2725 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2726
2727 /* Bits 1-0: Parallel Port Mode / Enable */
2728 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2729 tmp = inb(VIA_CONFIG_DATA);
2730 /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */
2731 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2732 tmp2 = inb(VIA_CONFIG_DATA);
2733 if (siofunc == VIA_FUNCTION_PROBE) {
2734 siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE;
2735 ppcontrol = tmp2;
2736 } else {
2737 tmp &= ~VIA_FUNCTION_PARPORT_DISABLE;
2738 tmp |= siofunc;
2739 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2740 outb(tmp, VIA_CONFIG_DATA);
2741 tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP);
2742 tmp2 |= ppcontrol;
2743 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2744 outb(tmp2, VIA_CONFIG_DATA);
2745 }
2746
2747 /* Parallel Port I/O Base Address, bits 9-2 */
2748 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2749 port1 = inb(VIA_CONFIG_DATA) << 2;
2750
2751 printk(KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",
2752 port1);
2753 if (port1 == 0x3BC && have_epp) {
2754 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2755 outb((0x378 >> 2), VIA_CONFIG_DATA);
2756 printk(KERN_DEBUG
2757 "parport_pc: Parallel port base changed to 0x378\n");
2758 port1 = 0x378;
2759 }
2760
2761 /*
2762 * lock super i/o configuration
2763 */
2764 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2765 tmp &= ~via->via_pci_superio_config_data;
2766 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2767
2768 if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) {
2769 printk(KERN_INFO "parport_pc: VIA parallel port disabled in BIOS\n");
2770 return 0;
2771 }
2772
2773 /* Bits 7-4: PnP Routing for Parallel Port IRQ */
2774 pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp);
2775 irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4);
2776
2777 if (siofunc == VIA_FUNCTION_PARPORT_ECP) {
2778 /* Bits 3-2: PnP Routing for Parallel Port DMA */
2779 pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp);
2780 dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2);
2781 } else
2782 /* if ECP not enabled, DMA is not enabled, assumed
2783 bogus 'dma' value */
2784 dma = PARPORT_DMA_NONE;
2785
2786 /* Let the user (or defaults) steer us away from interrupts and DMA */
2787 if (autoirq == PARPORT_IRQ_NONE) {
2788 irq = PARPORT_IRQ_NONE;
2789 dma = PARPORT_DMA_NONE;
2790 }
2791 if (autodma == PARPORT_DMA_NONE)
2792 dma = PARPORT_DMA_NONE;
2793
2794 switch (port1) {
2795 case 0x3bc:
2796 port2 = 0x7bc; break;
2797 case 0x378:
2798 port2 = 0x778; break;
2799 case 0x278:
2800 port2 = 0x678; break;
2801 default:
2802 printk(KERN_INFO
2803 "parport_pc: Weird VIA parport base 0x%X, ignoring\n",
2804 port1);
2805 return 0;
2806 }
2807
2808 /* filter bogus IRQs */
2809 switch (irq) {
2810 case 0:
2811 case 2:
2812 case 8:
2813 case 13:
2814 irq = PARPORT_IRQ_NONE;
2815 break;
2816
2817 default: /* do nothing */
2818 break;
2819 }
2820
2821 /* finally, do the probe with values obtained */
2822 if (parport_pc_probe_port(port1, port2, irq, dma, &pdev->dev, 0)) {
2823 printk(KERN_INFO
2824 "parport_pc: VIA parallel port: io=0x%X", port1);
2825 if (irq != PARPORT_IRQ_NONE)
2826 printk(", irq=%d", irq);
2827 if (dma != PARPORT_DMA_NONE)
2828 printk(", dma=%d", dma);
2829 printk("\n");
2830 return 1;
2831 }
2832
2833 printk(KERN_WARNING "parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n",
2834 port1, irq, dma);
2835 return 0;
2836}
2837
2838
2839enum parport_pc_sio_types {
2840 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */
2841 sio_via_8231, /* Via VT8231 south bridge integrated Super IO */
2842 sio_ite_8872,
2843 last_sio
2844};
2845
2846/* each element directly indexed from enum list, above */
2847static struct parport_pc_superio {
2848 int (*probe) (struct pci_dev *pdev, int autoirq, int autodma,
2849 const struct parport_pc_via_data *via);
2850 const struct parport_pc_via_data *via;
2851} parport_pc_superio_info[] __devinitdata = {
2852 { sio_via_probe, &via_686a_data, },
2853 { sio_via_probe, &via_8231_data, },
2854 { sio_ite_8872_probe, NULL, },
2855};
2856
2857enum parport_pc_pci_cards {
2858 siig_1p_10x = last_sio,
2859 siig_2p_10x,
2860 siig_1p_20x,
2861 siig_2p_20x,
2862 lava_parallel,
2863 lava_parallel_dual_a,
2864 lava_parallel_dual_b,
2865 boca_ioppar,
2866 plx_9050,
2867 timedia_4006a,
2868 timedia_4014,
2869 timedia_4008a,
2870 timedia_4018,
2871 timedia_9018a,
2872 syba_2p_epp,
2873 syba_1p_ecp,
2874 titan_010l,
2875 titan_1284p1,
2876 titan_1284p2,
2877 avlab_1p,
2878 avlab_2p,
2879 oxsemi_952,
2880 oxsemi_954,
2881 oxsemi_840,
2882 oxsemi_pcie_pport,
2883 aks_0100,
2884 mobility_pp,
2885 netmos_9705,
2886 netmos_9715,
2887 netmos_9755,
2888 netmos_9805,
2889 netmos_9815,
2890 netmos_9901,
2891 netmos_9865,
2892 quatech_sppxp100,
2893};
2894
2895
2896/* each element directly indexed from enum list, above
2897 * (but offset by last_sio) */
2898static struct parport_pc_pci {
2899 int numports;
2900 struct { /* BAR (base address registers) numbers in the config
2901 space header */
2902 int lo;
2903 int hi;
2904 /* -1 if not there, >6 for offset-method (max BAR is 6) */
2905 } addr[4];
2906
2907 /* If set, this is called immediately after pci_enable_device.
2908 * If it returns non-zero, no probing will take place and the
2909 * ports will not be used. */
2910 int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma);
2911
2912 /* If set, this is called after probing for ports. If 'failed'
2913 * is non-zero we couldn't use any of the ports. */
2914 void (*postinit_hook) (struct pci_dev *pdev, int failed);
2915} cards[] = {
2916 /* siig_1p_10x */ { 1, { { 2, 3 }, } },
2917 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } },
2918 /* siig_1p_20x */ { 1, { { 0, 1 }, } },
2919 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
2920 /* lava_parallel */ { 1, { { 0, -1 }, } },
2921 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
2922 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
2923 /* boca_ioppar */ { 1, { { 0, -1 }, } },
2924 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } },
2925 /* timedia_4006a */ { 1, { { 0, -1 }, } },
2926 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2927 /* timedia_4008a */ { 1, { { 0, 1 }, } },
2928 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2929 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
2930 /* SYBA uses fixed offsets in
2931 a 1K io window */
2932 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
2933 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
2934 /* titan_010l */ { 1, { { 3, -1 }, } },
2935 /* titan_1284p1 */ { 1, { { 0, 1 }, } },
2936 /* titan_1284p2 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2937 /* avlab_1p */ { 1, { { 0, 1}, } },
2938 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
2939 /* The Oxford Semi cards are unusual: 954 doesn't support ECP,
2940 * and 840 locks up if you write 1 to bit 2! */
2941 /* oxsemi_952 */ { 1, { { 0, 1 }, } },
2942 /* oxsemi_954 */ { 1, { { 0, -1 }, } },
2943 /* oxsemi_840 */ { 1, { { 0, 1 }, } },
2944 /* oxsemi_pcie_pport */ { 1, { { 0, 1 }, } },
2945 /* aks_0100 */ { 1, { { 0, -1 }, } },
2946 /* mobility_pp */ { 1, { { 0, 1 }, } },
2947
2948 /* The netmos entries below are untested */
2949 /* netmos_9705 */ { 1, { { 0, -1 }, } },
2950 /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} },
2951 /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} },
2952 /* netmos_9805 */ { 1, { { 0, -1 }, } },
2953 /* netmos_9815 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2954 /* netmos_9901 */ { 1, { { 0, -1 }, } },
2955 /* netmos_9865 */ { 1, { { 0, -1 }, } },
2956 /* quatech_sppxp100 */ { 1, { { 0, 1 }, } },
2957};
2958
2959static const struct pci_device_id parport_pc_pci_tbl[] = {
2960 /* Super-IO onboard chips */
2961 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
2962 { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 },
2963 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2964 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 },
2965
2966 /* PCI cards */
2967 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x,
2968 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
2969 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x,
2970 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
2971 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x,
2972 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
2973 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x,
2974 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
2975 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL,
2976 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
2977 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A,
2978 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
2979 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B,
2980 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
2981 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR,
2982 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
2983 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2984 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0, 0, plx_9050 },
2985 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
2986 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
2987 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
2988 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
2989 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
2990 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
2991 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
2992 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
2993 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
2994 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
2995 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L,
2996 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
2997 { 0x9710, 0x9805, 0x1000, 0x0010, 0, 0, titan_1284p1 },
2998 { 0x9710, 0x9815, 0x1000, 0x0020, 0, 0, titan_1284p2 },
2999 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
3000 /* AFAVLAB_TK9902 */
3001 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p},
3002 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p},
3003 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952PP,
3004 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_952 },
3005 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP,
3006 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
3007 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
3008 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
3009 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840,
3010 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
3011 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840_G,
3012 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
3013 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0,
3014 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
3015 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0_G,
3016 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
3017 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1,
3018 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
3019 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_G,
3020 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
3021 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_U,
3022 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
3023 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU,
3024 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
3025 { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
3026 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
3027 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
3028 /* NetMos communication controllers */
3029 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705,
3030 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 },
3031 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715,
3032 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 },
3033 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755,
3034 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 },
3035 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805,
3036 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 },
3037 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815,
3038 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 },
3039 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
3040 0xA000, 0x2000, 0, 0, netmos_9901 },
3041 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3042 0xA000, 0x1000, 0, 0, netmos_9865 },
3043 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3044 0xA000, 0x2000, 0, 0, netmos_9865 },
3045 /* Quatech SPPXP-100 Parallel port PCI ExpressCard */
3046 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SPPXP_100,
3047 PCI_ANY_ID, PCI_ANY_ID, 0, 0, quatech_sppxp100 },
3048 { 0, } /* terminate list */
3049};
3050MODULE_DEVICE_TABLE(pci, parport_pc_pci_tbl);
3051
3052struct pci_parport_data {
3053 int num;
3054 struct parport *ports[2];
3055};
3056
3057static int parport_pc_pci_probe(struct pci_dev *dev,
3058 const struct pci_device_id *id)
3059{
3060 int err, count, n, i = id->driver_data;
3061 struct pci_parport_data *data;
3062
3063 if (i < last_sio)
3064 /* This is an onboard Super-IO and has already been probed */
3065 return 0;
3066
3067 /* This is a PCI card */
3068 i -= last_sio;
3069 count = 0;
3070 err = pci_enable_device(dev);
3071 if (err)
3072 return err;
3073
3074 data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL);
3075 if (!data)
3076 return -ENOMEM;
3077
3078 if (cards[i].preinit_hook &&
3079 cards[i].preinit_hook(dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) {
3080 kfree(data);
3081 return -ENODEV;
3082 }
3083
3084 for (n = 0; n < cards[i].numports; n++) {
3085 int lo = cards[i].addr[n].lo;
3086 int hi = cards[i].addr[n].hi;
3087 int irq;
3088 unsigned long io_lo, io_hi;
3089 io_lo = pci_resource_start(dev, lo);
3090 io_hi = 0;
3091 if ((hi >= 0) && (hi <= 6))
3092 io_hi = pci_resource_start(dev, hi);
3093 else if (hi > 6)
3094 io_lo += hi; /* Reinterpret the meaning of
3095 "hi" as an offset (see SYBA
3096 def.) */
3097 /* TODO: test if sharing interrupts works */
3098 irq = dev->irq;
3099 if (irq == IRQ_NONE) {
3100 printk(KERN_DEBUG
3101 "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n",
3102 parport_pc_pci_tbl[i + last_sio].vendor,
3103 parport_pc_pci_tbl[i + last_sio].device,
3104 io_lo, io_hi);
3105 irq = PARPORT_IRQ_NONE;
3106 } else {
3107 printk(KERN_DEBUG
3108 "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n",
3109 parport_pc_pci_tbl[i + last_sio].vendor,
3110 parport_pc_pci_tbl[i + last_sio].device,
3111 io_lo, io_hi, irq);
3112 }
3113 data->ports[count] =
3114 parport_pc_probe_port(io_lo, io_hi, irq,
3115 PARPORT_DMA_NONE, &dev->dev,
3116 IRQF_SHARED);
3117 if (data->ports[count])
3118 count++;
3119 }
3120
3121 data->num = count;
3122
3123 if (cards[i].postinit_hook)
3124 cards[i].postinit_hook(dev, count == 0);
3125
3126 if (count) {
3127 pci_set_drvdata(dev, data);
3128 return 0;
3129 }
3130
3131 kfree(data);
3132
3133 return -ENODEV;
3134}
3135
3136static void __devexit parport_pc_pci_remove(struct pci_dev *dev)
3137{
3138 struct pci_parport_data *data = pci_get_drvdata(dev);
3139 int i;
3140
3141 pci_set_drvdata(dev, NULL);
3142
3143 if (data) {
3144 for (i = data->num - 1; i >= 0; i--)
3145 parport_pc_unregister_port(data->ports[i]);
3146
3147 kfree(data);
3148 }
3149}
3150
3151static struct pci_driver parport_pc_pci_driver = {
3152 .name = "parport_pc",
3153 .id_table = parport_pc_pci_tbl,
3154 .probe = parport_pc_pci_probe,
3155 .remove = __devexit_p(parport_pc_pci_remove),
3156};
3157
3158static int __init parport_pc_init_superio(int autoirq, int autodma)
3159{
3160 const struct pci_device_id *id;
3161 struct pci_dev *pdev = NULL;
3162 int ret = 0;
3163
3164 for_each_pci_dev(pdev) {
3165 id = pci_match_id(parport_pc_pci_tbl, pdev);
3166 if (id == NULL || id->driver_data >= last_sio)
3167 continue;
3168
3169 if (parport_pc_superio_info[id->driver_data].probe(
3170 pdev, autoirq, autodma,
3171 parport_pc_superio_info[id->driver_data].via)) {
3172 ret++;
3173 }
3174 }
3175
3176 return ret; /* number of devices found */
3177}
3178#else
3179static struct pci_driver parport_pc_pci_driver;
3180static int __init parport_pc_init_superio(int autoirq, int autodma)
3181{
3182 return 0;
3183}
3184#endif /* CONFIG_PCI */
3185
3186#ifdef CONFIG_PNP
3187
3188static const struct pnp_device_id parport_pc_pnp_tbl[] = {
3189 /* Standard LPT Printer Port */
3190 {.id = "PNP0400", .driver_data = 0},
3191 /* ECP Printer Port */
3192 {.id = "PNP0401", .driver_data = 0},
3193 { }
3194};
3195
3196MODULE_DEVICE_TABLE(pnp, parport_pc_pnp_tbl);
3197
3198static int parport_pc_pnp_probe(struct pnp_dev *dev,
3199 const struct pnp_device_id *id)
3200{
3201 struct parport *pdata;
3202 unsigned long io_lo, io_hi;
3203 int dma, irq;
3204
3205 if (pnp_port_valid(dev, 0) &&
3206 !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED)) {
3207 io_lo = pnp_port_start(dev, 0);
3208 } else
3209 return -EINVAL;
3210
3211 if (pnp_port_valid(dev, 1) &&
3212 !(pnp_port_flags(dev, 1) & IORESOURCE_DISABLED)) {
3213 io_hi = pnp_port_start(dev, 1);
3214 } else
3215 io_hi = 0;
3216
3217 if (pnp_irq_valid(dev, 0) &&
3218 !(pnp_irq_flags(dev, 0) & IORESOURCE_DISABLED)) {
3219 irq = pnp_irq(dev, 0);
3220 } else
3221 irq = PARPORT_IRQ_NONE;
3222
3223 if (pnp_dma_valid(dev, 0) &&
3224 !(pnp_dma_flags(dev, 0) & IORESOURCE_DISABLED)) {
3225 dma = pnp_dma(dev, 0);
3226 } else
3227 dma = PARPORT_DMA_NONE;
3228
3229 dev_info(&dev->dev, "reported by %s\n", dev->protocol->name);
3230 pdata = parport_pc_probe_port(io_lo, io_hi, irq, dma, &dev->dev, 0);
3231 if (pdata == NULL)
3232 return -ENODEV;
3233
3234 pnp_set_drvdata(dev, pdata);
3235 return 0;
3236}
3237
3238static void parport_pc_pnp_remove(struct pnp_dev *dev)
3239{
3240 struct parport *pdata = (struct parport *)pnp_get_drvdata(dev);
3241 if (!pdata)
3242 return;
3243
3244 parport_pc_unregister_port(pdata);
3245}
3246
3247/* we only need the pnp layer to activate the device, at least for now */
3248static struct pnp_driver parport_pc_pnp_driver = {
3249 .name = "parport_pc",
3250 .id_table = parport_pc_pnp_tbl,
3251 .probe = parport_pc_pnp_probe,
3252 .remove = parport_pc_pnp_remove,
3253};
3254
3255#else
3256static struct pnp_driver parport_pc_pnp_driver;
3257#endif /* CONFIG_PNP */
3258
3259static int __devinit parport_pc_platform_probe(struct platform_device *pdev)
3260{
3261 /* Always succeed, the actual probing is done in
3262 * parport_pc_probe_port(). */
3263 return 0;
3264}
3265
3266static struct platform_driver parport_pc_platform_driver = {
3267 .driver = {
3268 .owner = THIS_MODULE,
3269 .name = "parport_pc",
3270 },
3271 .probe = parport_pc_platform_probe,
3272};
3273
3274/* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */
3275static int __devinit __attribute__((unused))
3276parport_pc_find_isa_ports(int autoirq, int autodma)
3277{
3278 int count = 0;
3279
3280 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL, 0))
3281 count++;
3282 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL, 0))
3283 count++;
3284 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL, 0))
3285 count++;
3286
3287 return count;
3288}
3289
3290/* This function is called by parport_pc_init if the user didn't
3291 * specify any ports to probe. Its job is to find some ports. Order
3292 * is important here -- we want ISA ports to be registered first,
3293 * followed by PCI cards (for least surprise), but before that we want
3294 * to do chipset-specific tests for some onboard ports that we know
3295 * about.
3296 *
3297 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY
3298 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO
3299 */
3300static void __init parport_pc_find_ports(int autoirq, int autodma)
3301{
3302 int count = 0, err;
3303
3304#ifdef CONFIG_PARPORT_PC_SUPERIO
3305 detect_and_report_it87();
3306 detect_and_report_winbond();
3307 detect_and_report_smsc();
3308#endif
3309
3310 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */
3311 count += parport_pc_init_superio(autoirq, autodma);
3312
3313 /* PnP ports, skip detection if SuperIO already found them */
3314 if (!count) {
3315 err = pnp_register_driver(&parport_pc_pnp_driver);
3316 if (!err)
3317 pnp_registered_parport = 1;
3318 }
3319
3320 /* ISA ports and whatever (see asm/parport.h). */
3321 parport_pc_find_nonpci_ports(autoirq, autodma);
3322
3323 err = pci_register_driver(&parport_pc_pci_driver);
3324 if (!err)
3325 pci_registered_parport = 1;
3326}
3327
3328/*
3329 * Piles of crap below pretend to be a parser for module and kernel
3330 * parameters. Say "thank you" to whoever had come up with that
3331 * syntax and keep in mind that code below is a cleaned up version.
3332 */
3333
3334static int __initdata io[PARPORT_PC_MAX_PORTS+1] = {
3335 [0 ... PARPORT_PC_MAX_PORTS] = 0
3336};
3337static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] = {
3338 [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO
3339};
3340static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = {
3341 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE
3342};
3343static int __initdata irqval[PARPORT_PC_MAX_PORTS] = {
3344 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY
3345};
3346
3347static int __init parport_parse_param(const char *s, int *val,
3348 int automatic, int none, int nofifo)
3349{
3350 if (!s)
3351 return 0;
3352 if (!strncmp(s, "auto", 4))
3353 *val = automatic;
3354 else if (!strncmp(s, "none", 4))
3355 *val = none;
3356 else if (nofifo && !strncmp(s, "nofifo", 6))
3357 *val = nofifo;
3358 else {
3359 char *ep;
3360 unsigned long r = simple_strtoul(s, &ep, 0);
3361 if (ep != s)
3362 *val = r;
3363 else {
3364 printk(KERN_ERR "parport: bad specifier `%s'\n", s);
3365 return -1;
3366 }
3367 }
3368 return 0;
3369}
3370
3371static int __init parport_parse_irq(const char *irqstr, int *val)
3372{
3373 return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO,
3374 PARPORT_IRQ_NONE, 0);
3375}
3376
3377static int __init parport_parse_dma(const char *dmastr, int *val)
3378{
3379 return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO,
3380 PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO);
3381}
3382
3383#ifdef CONFIG_PCI
3384static int __init parport_init_mode_setup(char *str)
3385{
3386 printk(KERN_DEBUG
3387 "parport_pc.c: Specified parameter parport_init_mode=%s\n", str);
3388
3389 if (!strcmp(str, "spp"))
3390 parport_init_mode = 1;
3391 if (!strcmp(str, "ps2"))
3392 parport_init_mode = 2;
3393 if (!strcmp(str, "epp"))
3394 parport_init_mode = 3;
3395 if (!strcmp(str, "ecp"))
3396 parport_init_mode = 4;
3397 if (!strcmp(str, "ecpepp"))
3398 parport_init_mode = 5;
3399 return 1;
3400}
3401#endif
3402
3403#ifdef MODULE
3404static const char *irq[PARPORT_PC_MAX_PORTS];
3405static const char *dma[PARPORT_PC_MAX_PORTS];
3406
3407MODULE_PARM_DESC(io, "Base I/O address (SPP regs)");
3408module_param_array(io, int, NULL, 0);
3409MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)");
3410module_param_array(io_hi, int, NULL, 0);
3411MODULE_PARM_DESC(irq, "IRQ line");
3412module_param_array(irq, charp, NULL, 0);
3413MODULE_PARM_DESC(dma, "DMA channel");
3414module_param_array(dma, charp, NULL, 0);
3415#if defined(CONFIG_PARPORT_PC_SUPERIO) || \
3416 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
3417MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation");
3418module_param(verbose_probing, int, 0644);
3419#endif
3420#ifdef CONFIG_PCI
3421static char *init_mode;
3422MODULE_PARM_DESC(init_mode,
3423 "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)");
3424module_param(init_mode, charp, 0);
3425#endif
3426
3427static int __init parse_parport_params(void)
3428{
3429 unsigned int i;
3430 int val;
3431
3432#ifdef CONFIG_PCI
3433 if (init_mode)
3434 parport_init_mode_setup(init_mode);
3435#endif
3436
3437 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) {
3438 if (parport_parse_irq(irq[i], &val))
3439 return 1;
3440 irqval[i] = val;
3441 if (parport_parse_dma(dma[i], &val))
3442 return 1;
3443 dmaval[i] = val;
3444 }
3445 if (!io[0]) {
3446 /* The user can make us use any IRQs or DMAs we find. */
3447 if (irq[0] && !parport_parse_irq(irq[0], &val))
3448 switch (val) {
3449 case PARPORT_IRQ_NONE:
3450 case PARPORT_IRQ_AUTO:
3451 irqval[0] = val;
3452 break;
3453 default:
3454 printk(KERN_WARNING
3455 "parport_pc: irq specified "
3456 "without base address. Use 'io=' "
3457 "to specify one\n");
3458 }
3459
3460 if (dma[0] && !parport_parse_dma(dma[0], &val))
3461 switch (val) {
3462 case PARPORT_DMA_NONE:
3463 case PARPORT_DMA_AUTO:
3464 dmaval[0] = val;
3465 break;
3466 default:
3467 printk(KERN_WARNING
3468 "parport_pc: dma specified "
3469 "without base address. Use 'io=' "
3470 "to specify one\n");
3471 }
3472 }
3473 return 0;
3474}
3475
3476#else
3477
3478static int parport_setup_ptr __initdata;
3479
3480/*
3481 * Acceptable parameters:
3482 *
3483 * parport=0
3484 * parport=auto
3485 * parport=0xBASE[,IRQ[,DMA]]
3486 *
3487 * IRQ/DMA may be numeric or 'auto' or 'none'
3488 */
3489static int __init parport_setup(char *str)
3490{
3491 char *endptr;
3492 char *sep;
3493 int val;
3494
3495 if (!str || !*str || (*str == '0' && !*(str+1))) {
3496 /* Disable parport if "parport=0" in cmdline */
3497 io[0] = PARPORT_DISABLE;
3498 return 1;
3499 }
3500
3501 if (!strncmp(str, "auto", 4)) {
3502 irqval[0] = PARPORT_IRQ_AUTO;
3503 dmaval[0] = PARPORT_DMA_AUTO;
3504 return 1;
3505 }
3506
3507 val = simple_strtoul(str, &endptr, 0);
3508 if (endptr == str) {
3509 printk(KERN_WARNING "parport=%s not understood\n", str);
3510 return 1;
3511 }
3512
3513 if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) {
3514 printk(KERN_ERR "parport=%s ignored, too many ports\n", str);
3515 return 1;
3516 }
3517
3518 io[parport_setup_ptr] = val;
3519 irqval[parport_setup_ptr] = PARPORT_IRQ_NONE;
3520 dmaval[parport_setup_ptr] = PARPORT_DMA_NONE;
3521
3522 sep = strchr(str, ',');
3523 if (sep++) {
3524 if (parport_parse_irq(sep, &val))
3525 return 1;
3526 irqval[parport_setup_ptr] = val;
3527 sep = strchr(sep, ',');
3528 if (sep++) {
3529 if (parport_parse_dma(sep, &val))
3530 return 1;
3531 dmaval[parport_setup_ptr] = val;
3532 }
3533 }
3534 parport_setup_ptr++;
3535 return 1;
3536}
3537
3538static int __init parse_parport_params(void)
3539{
3540 return io[0] == PARPORT_DISABLE;
3541}
3542
3543__setup("parport=", parport_setup);
3544
3545/*
3546 * Acceptable parameters:
3547 *
3548 * parport_init_mode=[spp|ps2|epp|ecp|ecpepp]
3549 */
3550#ifdef CONFIG_PCI
3551__setup("parport_init_mode=", parport_init_mode_setup);
3552#endif
3553#endif
3554
3555/* "Parser" ends here */
3556
3557static int __init parport_pc_init(void)
3558{
3559 int err;
3560
3561 if (parse_parport_params())
3562 return -EINVAL;
3563
3564 err = platform_driver_register(&parport_pc_platform_driver);
3565 if (err)
3566 return err;
3567
3568 if (io[0]) {
3569 int i;
3570 /* Only probe the ports we were given. */
3571 user_specified = 1;
3572 for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) {
3573 if (!io[i])
3574 break;
3575 if (io_hi[i] == PARPORT_IOHI_AUTO)
3576 io_hi[i] = 0x400 + io[i];
3577 parport_pc_probe_port(io[i], io_hi[i],
3578 irqval[i], dmaval[i], NULL, 0);
3579 }
3580 } else
3581 parport_pc_find_ports(irqval[0], dmaval[0]);
3582
3583 return 0;
3584}
3585
3586static void __exit parport_pc_exit(void)
3587{
3588 if (pci_registered_parport)
3589 pci_unregister_driver(&parport_pc_pci_driver);
3590 if (pnp_registered_parport)
3591 pnp_unregister_driver(&parport_pc_pnp_driver);
3592 platform_driver_unregister(&parport_pc_platform_driver);
3593
3594 while (!list_empty(&ports_list)) {
3595 struct parport_pc_private *priv;
3596 struct parport *port;
3597 priv = list_entry(ports_list.next,
3598 struct parport_pc_private, list);
3599 port = priv->port;
3600 if (port->dev && port->dev->bus == &platform_bus_type)
3601 platform_device_unregister(
3602 to_platform_device(port->dev));
3603 parport_pc_unregister_port(port);
3604 }
3605}
3606
3607MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
3608MODULE_DESCRIPTION("PC-style parallel port driver");
3609MODULE_LICENSE("GPL");
3610module_init(parport_pc_init)
3611module_exit(parport_pc_exit)
1// SPDX-License-Identifier: GPL-2.0-only
2/* Low-level parallel-port routines for 8255-based PC-style hardware.
3 *
4 * Authors: Phil Blundell <philb@gnu.org>
5 * Tim Waugh <tim@cyberelk.demon.co.uk>
6 * Jose Renau <renau@acm.org>
7 * David Campbell
8 * Andrea Arcangeli
9 *
10 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell.
11 *
12 * Cleaned up include files - Russell King <linux@arm.uk.linux.org>
13 * DMA support - Bert De Jonghe <bert@sophis.be>
14 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999
15 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G.
16 * Various hacks, Fred Barnes, 04/2001
17 * Updated probing logic - Adam Belay <ambx1@neo.rr.com>
18 */
19
20/* This driver should work with any hardware that is broadly compatible
21 * with that in the IBM PC. This applies to the majority of integrated
22 * I/O chipsets that are commonly available. The expected register
23 * layout is:
24 *
25 * base+0 data
26 * base+1 status
27 * base+2 control
28 *
29 * In addition, there are some optional registers:
30 *
31 * base+3 EPP address
32 * base+4 EPP data
33 * base+0x400 ECP config A
34 * base+0x401 ECP config B
35 * base+0x402 ECP control
36 *
37 * All registers are 8 bits wide and read/write. If your hardware differs
38 * only in register addresses (eg because your registers are on 32-bit
39 * word boundaries) then you can alter the constants in parport_pc.h to
40 * accommodate this.
41 *
42 * Note that the ECP registers may not start at offset 0x400 for PCI cards,
43 * but rather will start at port->base_hi.
44 */
45
46#include <linux/module.h>
47#include <linux/init.h>
48#include <linux/sched/signal.h>
49#include <linux/delay.h>
50#include <linux/errno.h>
51#include <linux/interrupt.h>
52#include <linux/ioport.h>
53#include <linux/kernel.h>
54#include <linux/slab.h>
55#include <linux/dma-mapping.h>
56#include <linux/pci.h>
57#include <linux/pnp.h>
58#include <linux/platform_device.h>
59#include <linux/sysctl.h>
60#include <linux/io.h>
61#include <linux/uaccess.h>
62
63#include <asm/dma.h>
64
65#include <linux/parport.h>
66#include <linux/parport_pc.h>
67#include <linux/via.h>
68#include <asm/parport.h>
69
70#define PARPORT_PC_MAX_PORTS PARPORT_MAX
71
72#ifdef CONFIG_ISA_DMA_API
73#define HAS_DMA
74#endif
75
76/* ECR modes */
77#define ECR_SPP 00
78#define ECR_PS2 01
79#define ECR_PPF 02
80#define ECR_ECP 03
81#define ECR_EPP 04
82#define ECR_VND 05
83#define ECR_TST 06
84#define ECR_CNF 07
85#define ECR_MODE_MASK 0xe0
86#define ECR_WRITE(p, v) frob_econtrol((p), 0xff, (v))
87
88#undef DEBUG
89
90#define NR_SUPERIOS 3
91static struct superio_struct { /* For Super-IO chips autodetection */
92 int io;
93 int irq;
94 int dma;
95} superios[NR_SUPERIOS] = { {0,},};
96
97static int user_specified;
98#if defined(CONFIG_PARPORT_PC_SUPERIO) || \
99 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
100static int verbose_probing;
101#endif
102static int pci_registered_parport;
103static int pnp_registered_parport;
104
105/* frob_control, but for ECR */
106static void frob_econtrol(struct parport *pb, unsigned char m,
107 unsigned char v)
108{
109 unsigned char ectr = 0;
110
111 if (m != 0xff)
112 ectr = inb(ECONTROL(pb));
113
114 pr_debug("frob_econtrol(%02x,%02x): %02x -> %02x\n",
115 m, v, ectr, (ectr & ~m) ^ v);
116
117 outb((ectr & ~m) ^ v, ECONTROL(pb));
118}
119
120static inline void frob_set_mode(struct parport *p, int mode)
121{
122 frob_econtrol(p, ECR_MODE_MASK, mode << 5);
123}
124
125#ifdef CONFIG_PARPORT_PC_FIFO
126/* Safely change the mode bits in the ECR
127 Returns:
128 0 : Success
129 -EBUSY: Could not drain FIFO in some finite amount of time,
130 mode not changed!
131 */
132static int change_mode(struct parport *p, int m)
133{
134 const struct parport_pc_private *priv = p->physport->private_data;
135 unsigned char oecr;
136 int mode;
137
138 pr_debug("parport change_mode ECP-ISA to mode 0x%02x\n", m);
139
140 if (!priv->ecr) {
141 printk(KERN_DEBUG "change_mode: but there's no ECR!\n");
142 return 0;
143 }
144
145 /* Bits <7:5> contain the mode. */
146 oecr = inb(ECONTROL(p));
147 mode = (oecr >> 5) & 0x7;
148 if (mode == m)
149 return 0;
150
151 if (mode >= 2 && !(priv->ctr & 0x20)) {
152 /* This mode resets the FIFO, so we may
153 * have to wait for it to drain first. */
154 unsigned long expire = jiffies + p->physport->cad->timeout;
155 int counter;
156 switch (mode) {
157 case ECR_PPF: /* Parallel Port FIFO mode */
158 case ECR_ECP: /* ECP Parallel Port mode */
159 /* Busy wait for 200us */
160 for (counter = 0; counter < 40; counter++) {
161 if (inb(ECONTROL(p)) & 0x01)
162 break;
163 if (signal_pending(current))
164 break;
165 udelay(5);
166 }
167
168 /* Poll slowly. */
169 while (!(inb(ECONTROL(p)) & 0x01)) {
170 if (time_after_eq(jiffies, expire))
171 /* The FIFO is stuck. */
172 return -EBUSY;
173 schedule_timeout_interruptible(
174 msecs_to_jiffies(10));
175 if (signal_pending(current))
176 break;
177 }
178 }
179 }
180
181 if (mode >= 2 && m >= 2) {
182 /* We have to go through mode 001 */
183 oecr &= ~(7 << 5);
184 oecr |= ECR_PS2 << 5;
185 ECR_WRITE(p, oecr);
186 }
187
188 /* Set the mode. */
189 oecr &= ~(7 << 5);
190 oecr |= m << 5;
191 ECR_WRITE(p, oecr);
192 return 0;
193}
194#endif /* FIFO support */
195
196/*
197 * Clear TIMEOUT BIT in EPP MODE
198 *
199 * This is also used in SPP detection.
200 */
201static int clear_epp_timeout(struct parport *pb)
202{
203 unsigned char r;
204
205 if (!(parport_pc_read_status(pb) & 0x01))
206 return 1;
207
208 /* To clear timeout some chips require double read */
209 parport_pc_read_status(pb);
210 r = parport_pc_read_status(pb);
211 outb(r | 0x01, STATUS(pb)); /* Some reset by writing 1 */
212 outb(r & 0xfe, STATUS(pb)); /* Others by writing 0 */
213 r = parport_pc_read_status(pb);
214
215 return !(r & 0x01);
216}
217
218/*
219 * Access functions.
220 *
221 * Most of these aren't static because they may be used by the
222 * parport_xxx_yyy macros. extern __inline__ versions of several
223 * of these are in parport_pc.h.
224 */
225
226static void parport_pc_init_state(struct pardevice *dev,
227 struct parport_state *s)
228{
229 s->u.pc.ctr = 0xc;
230 if (dev->irq_func &&
231 dev->port->irq != PARPORT_IRQ_NONE)
232 /* Set ackIntEn */
233 s->u.pc.ctr |= 0x10;
234
235 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24;
236 * D.Gruszka VScom */
237}
238
239static void parport_pc_save_state(struct parport *p, struct parport_state *s)
240{
241 const struct parport_pc_private *priv = p->physport->private_data;
242 s->u.pc.ctr = priv->ctr;
243 if (priv->ecr)
244 s->u.pc.ecr = inb(ECONTROL(p));
245}
246
247static void parport_pc_restore_state(struct parport *p,
248 struct parport_state *s)
249{
250 struct parport_pc_private *priv = p->physport->private_data;
251 register unsigned char c = s->u.pc.ctr & priv->ctr_writable;
252 outb(c, CONTROL(p));
253 priv->ctr = c;
254 if (priv->ecr)
255 ECR_WRITE(p, s->u.pc.ecr);
256}
257
258#ifdef CONFIG_PARPORT_1284
259static size_t parport_pc_epp_read_data(struct parport *port, void *buf,
260 size_t length, int flags)
261{
262 size_t got = 0;
263
264 if (flags & PARPORT_W91284PIC) {
265 unsigned char status;
266 size_t left = length;
267
268 /* use knowledge about data lines..:
269 * nFault is 0 if there is at least 1 byte in the Warp's FIFO
270 * pError is 1 if there are 16 bytes in the Warp's FIFO
271 */
272 status = inb(STATUS(port));
273
274 while (!(status & 0x08) && got < length) {
275 if (left >= 16 && (status & 0x20) && !(status & 0x08)) {
276 /* can grab 16 bytes from warp fifo */
277 if (!((long)buf & 0x03))
278 insl(EPPDATA(port), buf, 4);
279 else
280 insb(EPPDATA(port), buf, 16);
281 buf += 16;
282 got += 16;
283 left -= 16;
284 } else {
285 /* grab single byte from the warp fifo */
286 *((char *)buf) = inb(EPPDATA(port));
287 buf++;
288 got++;
289 left--;
290 }
291 status = inb(STATUS(port));
292 if (status & 0x01) {
293 /* EPP timeout should never occur... */
294 printk(KERN_DEBUG "%s: EPP timeout occurred while talking to w91284pic (should not have done)\n",
295 port->name);
296 clear_epp_timeout(port);
297 }
298 }
299 return got;
300 }
301 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
302 if (!(((long)buf | length) & 0x03))
303 insl(EPPDATA(port), buf, (length >> 2));
304 else
305 insb(EPPDATA(port), buf, length);
306 if (inb(STATUS(port)) & 0x01) {
307 clear_epp_timeout(port);
308 return -EIO;
309 }
310 return length;
311 }
312 for (; got < length; got++) {
313 *((char *)buf) = inb(EPPDATA(port));
314 buf++;
315 if (inb(STATUS(port)) & 0x01) {
316 /* EPP timeout */
317 clear_epp_timeout(port);
318 break;
319 }
320 }
321
322 return got;
323}
324
325static size_t parport_pc_epp_write_data(struct parport *port, const void *buf,
326 size_t length, int flags)
327{
328 size_t written = 0;
329
330 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
331 if (!(((long)buf | length) & 0x03))
332 outsl(EPPDATA(port), buf, (length >> 2));
333 else
334 outsb(EPPDATA(port), buf, length);
335 if (inb(STATUS(port)) & 0x01) {
336 clear_epp_timeout(port);
337 return -EIO;
338 }
339 return length;
340 }
341 for (; written < length; written++) {
342 outb(*((char *)buf), EPPDATA(port));
343 buf++;
344 if (inb(STATUS(port)) & 0x01) {
345 clear_epp_timeout(port);
346 break;
347 }
348 }
349
350 return written;
351}
352
353static size_t parport_pc_epp_read_addr(struct parport *port, void *buf,
354 size_t length, int flags)
355{
356 size_t got = 0;
357
358 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
359 insb(EPPADDR(port), buf, length);
360 if (inb(STATUS(port)) & 0x01) {
361 clear_epp_timeout(port);
362 return -EIO;
363 }
364 return length;
365 }
366 for (; got < length; got++) {
367 *((char *)buf) = inb(EPPADDR(port));
368 buf++;
369 if (inb(STATUS(port)) & 0x01) {
370 clear_epp_timeout(port);
371 break;
372 }
373 }
374
375 return got;
376}
377
378static size_t parport_pc_epp_write_addr(struct parport *port,
379 const void *buf, size_t length,
380 int flags)
381{
382 size_t written = 0;
383
384 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
385 outsb(EPPADDR(port), buf, length);
386 if (inb(STATUS(port)) & 0x01) {
387 clear_epp_timeout(port);
388 return -EIO;
389 }
390 return length;
391 }
392 for (; written < length; written++) {
393 outb(*((char *)buf), EPPADDR(port));
394 buf++;
395 if (inb(STATUS(port)) & 0x01) {
396 clear_epp_timeout(port);
397 break;
398 }
399 }
400
401 return written;
402}
403
404static size_t parport_pc_ecpepp_read_data(struct parport *port, void *buf,
405 size_t length, int flags)
406{
407 size_t got;
408
409 frob_set_mode(port, ECR_EPP);
410 parport_pc_data_reverse(port);
411 parport_pc_write_control(port, 0x4);
412 got = parport_pc_epp_read_data(port, buf, length, flags);
413 frob_set_mode(port, ECR_PS2);
414
415 return got;
416}
417
418static size_t parport_pc_ecpepp_write_data(struct parport *port,
419 const void *buf, size_t length,
420 int flags)
421{
422 size_t written;
423
424 frob_set_mode(port, ECR_EPP);
425 parport_pc_write_control(port, 0x4);
426 parport_pc_data_forward(port);
427 written = parport_pc_epp_write_data(port, buf, length, flags);
428 frob_set_mode(port, ECR_PS2);
429
430 return written;
431}
432
433static size_t parport_pc_ecpepp_read_addr(struct parport *port, void *buf,
434 size_t length, int flags)
435{
436 size_t got;
437
438 frob_set_mode(port, ECR_EPP);
439 parport_pc_data_reverse(port);
440 parport_pc_write_control(port, 0x4);
441 got = parport_pc_epp_read_addr(port, buf, length, flags);
442 frob_set_mode(port, ECR_PS2);
443
444 return got;
445}
446
447static size_t parport_pc_ecpepp_write_addr(struct parport *port,
448 const void *buf, size_t length,
449 int flags)
450{
451 size_t written;
452
453 frob_set_mode(port, ECR_EPP);
454 parport_pc_write_control(port, 0x4);
455 parport_pc_data_forward(port);
456 written = parport_pc_epp_write_addr(port, buf, length, flags);
457 frob_set_mode(port, ECR_PS2);
458
459 return written;
460}
461#endif /* IEEE 1284 support */
462
463#ifdef CONFIG_PARPORT_PC_FIFO
464static size_t parport_pc_fifo_write_block_pio(struct parport *port,
465 const void *buf, size_t length)
466{
467 int ret = 0;
468 const unsigned char *bufp = buf;
469 size_t left = length;
470 unsigned long expire = jiffies + port->physport->cad->timeout;
471 const unsigned long fifo = FIFO(port);
472 int poll_for = 8; /* 80 usecs */
473 const struct parport_pc_private *priv = port->physport->private_data;
474 const int fifo_depth = priv->fifo_depth;
475
476 port = port->physport;
477
478 /* We don't want to be interrupted every character. */
479 parport_pc_disable_irq(port);
480 /* set nErrIntrEn and serviceIntr */
481 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
482
483 /* Forward mode. */
484 parport_pc_data_forward(port); /* Must be in PS2 mode */
485
486 while (left) {
487 unsigned char byte;
488 unsigned char ecrval = inb(ECONTROL(port));
489 int i = 0;
490
491 if (need_resched() && time_before(jiffies, expire))
492 /* Can't yield the port. */
493 schedule();
494
495 /* Anyone else waiting for the port? */
496 if (port->waithead) {
497 printk(KERN_DEBUG "Somebody wants the port\n");
498 break;
499 }
500
501 if (ecrval & 0x02) {
502 /* FIFO is full. Wait for interrupt. */
503
504 /* Clear serviceIntr */
505 ECR_WRITE(port, ecrval & ~(1<<2));
506false_alarm:
507 ret = parport_wait_event(port, HZ);
508 if (ret < 0)
509 break;
510 ret = 0;
511 if (!time_before(jiffies, expire)) {
512 /* Timed out. */
513 printk(KERN_DEBUG "FIFO write timed out\n");
514 break;
515 }
516 ecrval = inb(ECONTROL(port));
517 if (!(ecrval & (1<<2))) {
518 if (need_resched() &&
519 time_before(jiffies, expire))
520 schedule();
521
522 goto false_alarm;
523 }
524
525 continue;
526 }
527
528 /* Can't fail now. */
529 expire = jiffies + port->cad->timeout;
530
531poll:
532 if (signal_pending(current))
533 break;
534
535 if (ecrval & 0x01) {
536 /* FIFO is empty. Blast it full. */
537 const int n = left < fifo_depth ? left : fifo_depth;
538 outsb(fifo, bufp, n);
539 bufp += n;
540 left -= n;
541
542 /* Adjust the poll time. */
543 if (i < (poll_for - 2))
544 poll_for--;
545 continue;
546 } else if (i++ < poll_for) {
547 udelay(10);
548 ecrval = inb(ECONTROL(port));
549 goto poll;
550 }
551
552 /* Half-full(call me an optimist) */
553 byte = *bufp++;
554 outb(byte, fifo);
555 left--;
556 }
557 dump_parport_state("leave fifo_write_block_pio", port);
558 return length - left;
559}
560
561#ifdef HAS_DMA
562static size_t parport_pc_fifo_write_block_dma(struct parport *port,
563 const void *buf, size_t length)
564{
565 int ret = 0;
566 unsigned long dmaflag;
567 size_t left = length;
568 const struct parport_pc_private *priv = port->physport->private_data;
569 struct device *dev = port->physport->dev;
570 dma_addr_t dma_addr, dma_handle;
571 size_t maxlen = 0x10000; /* max 64k per DMA transfer */
572 unsigned long start = (unsigned long) buf;
573 unsigned long end = (unsigned long) buf + length - 1;
574
575 dump_parport_state("enter fifo_write_block_dma", port);
576 if (end < MAX_DMA_ADDRESS) {
577 /* If it would cross a 64k boundary, cap it at the end. */
578 if ((start ^ end) & ~0xffffUL)
579 maxlen = 0x10000 - (start & 0xffff);
580
581 dma_addr = dma_handle = dma_map_single(dev, (void *)buf, length,
582 DMA_TO_DEVICE);
583 } else {
584 /* above 16 MB we use a bounce buffer as ISA-DMA
585 is not possible */
586 maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */
587 dma_addr = priv->dma_handle;
588 dma_handle = 0;
589 }
590
591 port = port->physport;
592
593 /* We don't want to be interrupted every character. */
594 parport_pc_disable_irq(port);
595 /* set nErrIntrEn and serviceIntr */
596 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
597
598 /* Forward mode. */
599 parport_pc_data_forward(port); /* Must be in PS2 mode */
600
601 while (left) {
602 unsigned long expire = jiffies + port->physport->cad->timeout;
603
604 size_t count = left;
605
606 if (count > maxlen)
607 count = maxlen;
608
609 if (!dma_handle) /* bounce buffer ! */
610 memcpy(priv->dma_buf, buf, count);
611
612 dmaflag = claim_dma_lock();
613 disable_dma(port->dma);
614 clear_dma_ff(port->dma);
615 set_dma_mode(port->dma, DMA_MODE_WRITE);
616 set_dma_addr(port->dma, dma_addr);
617 set_dma_count(port->dma, count);
618
619 /* Set DMA mode */
620 frob_econtrol(port, 1<<3, 1<<3);
621
622 /* Clear serviceIntr */
623 frob_econtrol(port, 1<<2, 0);
624
625 enable_dma(port->dma);
626 release_dma_lock(dmaflag);
627
628 /* assume DMA will be successful */
629 left -= count;
630 buf += count;
631 if (dma_handle)
632 dma_addr += count;
633
634 /* Wait for interrupt. */
635false_alarm:
636 ret = parport_wait_event(port, HZ);
637 if (ret < 0)
638 break;
639 ret = 0;
640 if (!time_before(jiffies, expire)) {
641 /* Timed out. */
642 printk(KERN_DEBUG "DMA write timed out\n");
643 break;
644 }
645 /* Is serviceIntr set? */
646 if (!(inb(ECONTROL(port)) & (1<<2))) {
647 cond_resched();
648
649 goto false_alarm;
650 }
651
652 dmaflag = claim_dma_lock();
653 disable_dma(port->dma);
654 clear_dma_ff(port->dma);
655 count = get_dma_residue(port->dma);
656 release_dma_lock(dmaflag);
657
658 cond_resched(); /* Can't yield the port. */
659
660 /* Anyone else waiting for the port? */
661 if (port->waithead) {
662 printk(KERN_DEBUG "Somebody wants the port\n");
663 break;
664 }
665
666 /* update for possible DMA residue ! */
667 buf -= count;
668 left += count;
669 if (dma_handle)
670 dma_addr -= count;
671 }
672
673 /* Maybe got here through break, so adjust for DMA residue! */
674 dmaflag = claim_dma_lock();
675 disable_dma(port->dma);
676 clear_dma_ff(port->dma);
677 left += get_dma_residue(port->dma);
678 release_dma_lock(dmaflag);
679
680 /* Turn off DMA mode */
681 frob_econtrol(port, 1<<3, 0);
682
683 if (dma_handle)
684 dma_unmap_single(dev, dma_handle, length, DMA_TO_DEVICE);
685
686 dump_parport_state("leave fifo_write_block_dma", port);
687 return length - left;
688}
689#endif
690
691static inline size_t parport_pc_fifo_write_block(struct parport *port,
692 const void *buf, size_t length)
693{
694#ifdef HAS_DMA
695 if (port->dma != PARPORT_DMA_NONE)
696 return parport_pc_fifo_write_block_dma(port, buf, length);
697#endif
698 return parport_pc_fifo_write_block_pio(port, buf, length);
699}
700
701/* Parallel Port FIFO mode (ECP chipsets) */
702static size_t parport_pc_compat_write_block_pio(struct parport *port,
703 const void *buf, size_t length,
704 int flags)
705{
706 size_t written;
707 int r;
708 unsigned long expire;
709 const struct parport_pc_private *priv = port->physport->private_data;
710
711 /* Special case: a timeout of zero means we cannot call schedule().
712 * Also if O_NONBLOCK is set then use the default implementation. */
713 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
714 return parport_ieee1284_write_compat(port, buf,
715 length, flags);
716
717 /* Set up parallel port FIFO mode.*/
718 parport_pc_data_forward(port); /* Must be in PS2 mode */
719 parport_pc_frob_control(port, PARPORT_CONTROL_STROBE, 0);
720 r = change_mode(port, ECR_PPF); /* Parallel port FIFO */
721 if (r)
722 printk(KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n",
723 port->name);
724
725 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
726
727 /* Write the data to the FIFO. */
728 written = parport_pc_fifo_write_block(port, buf, length);
729
730 /* Finish up. */
731 /* For some hardware we don't want to touch the mode until
732 * the FIFO is empty, so allow 4 seconds for each position
733 * in the fifo.
734 */
735 expire = jiffies + (priv->fifo_depth * HZ * 4);
736 do {
737 /* Wait for the FIFO to empty */
738 r = change_mode(port, ECR_PS2);
739 if (r != -EBUSY)
740 break;
741 } while (time_before(jiffies, expire));
742 if (r == -EBUSY) {
743
744 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
745
746 /* Prevent further data transfer. */
747 frob_set_mode(port, ECR_TST);
748
749 /* Adjust for the contents of the FIFO. */
750 for (written -= priv->fifo_depth; ; written++) {
751 if (inb(ECONTROL(port)) & 0x2) {
752 /* Full up. */
753 break;
754 }
755 outb(0, FIFO(port));
756 }
757
758 /* Reset the FIFO and return to PS2 mode. */
759 frob_set_mode(port, ECR_PS2);
760 }
761
762 r = parport_wait_peripheral(port,
763 PARPORT_STATUS_BUSY,
764 PARPORT_STATUS_BUSY);
765 if (r)
766 printk(KERN_DEBUG "%s: BUSY timeout (%d) in compat_write_block_pio\n",
767 port->name, r);
768
769 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
770
771 return written;
772}
773
774/* ECP */
775#ifdef CONFIG_PARPORT_1284
776static size_t parport_pc_ecp_write_block_pio(struct parport *port,
777 const void *buf, size_t length,
778 int flags)
779{
780 size_t written;
781 int r;
782 unsigned long expire;
783 const struct parport_pc_private *priv = port->physport->private_data;
784
785 /* Special case: a timeout of zero means we cannot call schedule().
786 * Also if O_NONBLOCK is set then use the default implementation. */
787 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
788 return parport_ieee1284_ecp_write_data(port, buf,
789 length, flags);
790
791 /* Switch to forward mode if necessary. */
792 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
793 /* Event 47: Set nInit high. */
794 parport_frob_control(port,
795 PARPORT_CONTROL_INIT
796 | PARPORT_CONTROL_AUTOFD,
797 PARPORT_CONTROL_INIT
798 | PARPORT_CONTROL_AUTOFD);
799
800 /* Event 49: PError goes high. */
801 r = parport_wait_peripheral(port,
802 PARPORT_STATUS_PAPEROUT,
803 PARPORT_STATUS_PAPEROUT);
804 if (r) {
805 printk(KERN_DEBUG "%s: PError timeout (%d) in ecp_write_block_pio\n",
806 port->name, r);
807 }
808 }
809
810 /* Set up ECP parallel port mode.*/
811 parport_pc_data_forward(port); /* Must be in PS2 mode */
812 parport_pc_frob_control(port,
813 PARPORT_CONTROL_STROBE |
814 PARPORT_CONTROL_AUTOFD,
815 0);
816 r = change_mode(port, ECR_ECP); /* ECP FIFO */
817 if (r)
818 printk(KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n",
819 port->name);
820 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
821
822 /* Write the data to the FIFO. */
823 written = parport_pc_fifo_write_block(port, buf, length);
824
825 /* Finish up. */
826 /* For some hardware we don't want to touch the mode until
827 * the FIFO is empty, so allow 4 seconds for each position
828 * in the fifo.
829 */
830 expire = jiffies + (priv->fifo_depth * (HZ * 4));
831 do {
832 /* Wait for the FIFO to empty */
833 r = change_mode(port, ECR_PS2);
834 if (r != -EBUSY)
835 break;
836 } while (time_before(jiffies, expire));
837 if (r == -EBUSY) {
838
839 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
840
841 /* Prevent further data transfer. */
842 frob_set_mode(port, ECR_TST);
843
844 /* Adjust for the contents of the FIFO. */
845 for (written -= priv->fifo_depth; ; written++) {
846 if (inb(ECONTROL(port)) & 0x2) {
847 /* Full up. */
848 break;
849 }
850 outb(0, FIFO(port));
851 }
852
853 /* Reset the FIFO and return to PS2 mode. */
854 frob_set_mode(port, ECR_PS2);
855
856 /* Host transfer recovery. */
857 parport_pc_data_reverse(port); /* Must be in PS2 mode */
858 udelay(5);
859 parport_frob_control(port, PARPORT_CONTROL_INIT, 0);
860 r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0);
861 if (r)
862 printk(KERN_DEBUG "%s: PE,1 timeout (%d) in ecp_write_block_pio\n",
863 port->name, r);
864
865 parport_frob_control(port,
866 PARPORT_CONTROL_INIT,
867 PARPORT_CONTROL_INIT);
868 r = parport_wait_peripheral(port,
869 PARPORT_STATUS_PAPEROUT,
870 PARPORT_STATUS_PAPEROUT);
871 if (r)
872 printk(KERN_DEBUG "%s: PE,2 timeout (%d) in ecp_write_block_pio\n",
873 port->name, r);
874 }
875
876 r = parport_wait_peripheral(port,
877 PARPORT_STATUS_BUSY,
878 PARPORT_STATUS_BUSY);
879 if (r)
880 printk(KERN_DEBUG "%s: BUSY timeout (%d) in ecp_write_block_pio\n",
881 port->name, r);
882
883 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
884
885 return written;
886}
887#endif /* IEEE 1284 support */
888#endif /* Allowed to use FIFO/DMA */
889
890
891/*
892 * ******************************************
893 * INITIALISATION AND MODULE STUFF BELOW HERE
894 * ******************************************
895 */
896
897/* GCC is not inlining extern inline function later overwritten to non-inline,
898 so we use outlined_ variants here. */
899static const struct parport_operations parport_pc_ops = {
900 .write_data = parport_pc_write_data,
901 .read_data = parport_pc_read_data,
902
903 .write_control = parport_pc_write_control,
904 .read_control = parport_pc_read_control,
905 .frob_control = parport_pc_frob_control,
906
907 .read_status = parport_pc_read_status,
908
909 .enable_irq = parport_pc_enable_irq,
910 .disable_irq = parport_pc_disable_irq,
911
912 .data_forward = parport_pc_data_forward,
913 .data_reverse = parport_pc_data_reverse,
914
915 .init_state = parport_pc_init_state,
916 .save_state = parport_pc_save_state,
917 .restore_state = parport_pc_restore_state,
918
919 .epp_write_data = parport_ieee1284_epp_write_data,
920 .epp_read_data = parport_ieee1284_epp_read_data,
921 .epp_write_addr = parport_ieee1284_epp_write_addr,
922 .epp_read_addr = parport_ieee1284_epp_read_addr,
923
924 .ecp_write_data = parport_ieee1284_ecp_write_data,
925 .ecp_read_data = parport_ieee1284_ecp_read_data,
926 .ecp_write_addr = parport_ieee1284_ecp_write_addr,
927
928 .compat_write_data = parport_ieee1284_write_compat,
929 .nibble_read_data = parport_ieee1284_read_nibble,
930 .byte_read_data = parport_ieee1284_read_byte,
931
932 .owner = THIS_MODULE,
933};
934
935#ifdef CONFIG_PARPORT_PC_SUPERIO
936
937static struct superio_struct *find_free_superio(void)
938{
939 int i;
940 for (i = 0; i < NR_SUPERIOS; i++)
941 if (superios[i].io == 0)
942 return &superios[i];
943 return NULL;
944}
945
946
947/* Super-IO chipset detection, Winbond, SMSC */
948static void show_parconfig_smsc37c669(int io, int key)
949{
950 int cr1, cr4, cra, cr23, cr26, cr27;
951 struct superio_struct *s;
952
953 static const char *const modes[] = {
954 "SPP and Bidirectional (PS/2)",
955 "EPP and SPP",
956 "ECP",
957 "ECP and EPP" };
958
959 outb(key, io);
960 outb(key, io);
961 outb(1, io);
962 cr1 = inb(io + 1);
963 outb(4, io);
964 cr4 = inb(io + 1);
965 outb(0x0a, io);
966 cra = inb(io + 1);
967 outb(0x23, io);
968 cr23 = inb(io + 1);
969 outb(0x26, io);
970 cr26 = inb(io + 1);
971 outb(0x27, io);
972 cr27 = inb(io + 1);
973 outb(0xaa, io);
974
975 if (verbose_probing) {
976 pr_info("SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n",
977 cr1, cr4, cra, cr23, cr26, cr27);
978
979 /* The documentation calls DMA and IRQ-Lines by letters, so
980 the board maker can/will wire them
981 appropriately/randomly... G=reserved H=IDE-irq, */
982 pr_info("SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, fifo threshold=%d\n",
983 cr23 * 4,
984 (cr27 & 0x0f) ? 'A' - 1 + (cr27 & 0x0f) : '-',
985 (cr26 & 0x0f) ? 'A' - 1 + (cr26 & 0x0f) : '-',
986 cra & 0x0f);
987 pr_info("SMSC LPT Config: enabled=%s power=%s\n",
988 (cr23 * 4 >= 0x100) ? "yes" : "no",
989 (cr1 & 4) ? "yes" : "no");
990 pr_info("SMSC LPT Config: Port mode=%s, EPP version =%s\n",
991 (cr1 & 0x08) ? "Standard mode only (SPP)"
992 : modes[cr4 & 0x03],
993 (cr4 & 0x40) ? "1.7" : "1.9");
994 }
995
996 /* Heuristics ! BIOS setup for this mainboard device limits
997 the choices to standard settings, i.e. io-address and IRQ
998 are related, however DMA can be 1 or 3, assume DMA_A=DMA1,
999 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */
1000 if (cr23 * 4 >= 0x100) { /* if active */
1001 s = find_free_superio();
1002 if (s == NULL)
1003 pr_info("Super-IO: too many chips!\n");
1004 else {
1005 int d;
1006 switch (cr23 * 4) {
1007 case 0x3bc:
1008 s->io = 0x3bc;
1009 s->irq = 7;
1010 break;
1011 case 0x378:
1012 s->io = 0x378;
1013 s->irq = 7;
1014 break;
1015 case 0x278:
1016 s->io = 0x278;
1017 s->irq = 5;
1018 }
1019 d = (cr26 & 0x0f);
1020 if (d == 1 || d == 3)
1021 s->dma = d;
1022 else
1023 s->dma = PARPORT_DMA_NONE;
1024 }
1025 }
1026}
1027
1028
1029static void show_parconfig_winbond(int io, int key)
1030{
1031 int cr30, cr60, cr61, cr70, cr74, crf0;
1032 struct superio_struct *s;
1033 static const char *const modes[] = {
1034 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */
1035 "EPP-1.9 and SPP",
1036 "ECP",
1037 "ECP and EPP-1.9",
1038 "Standard (SPP)",
1039 "EPP-1.7 and SPP", /* 5 */
1040 "undefined!",
1041 "ECP and EPP-1.7" };
1042 static char *const irqtypes[] = {
1043 "pulsed low, high-Z",
1044 "follows nACK" };
1045
1046 /* The registers are called compatible-PnP because the
1047 register layout is modelled after ISA-PnP, the access
1048 method is just another ... */
1049 outb(key, io);
1050 outb(key, io);
1051 outb(0x07, io); /* Register 7: Select Logical Device */
1052 outb(0x01, io + 1); /* LD1 is Parallel Port */
1053 outb(0x30, io);
1054 cr30 = inb(io + 1);
1055 outb(0x60, io);
1056 cr60 = inb(io + 1);
1057 outb(0x61, io);
1058 cr61 = inb(io + 1);
1059 outb(0x70, io);
1060 cr70 = inb(io + 1);
1061 outb(0x74, io);
1062 cr74 = inb(io + 1);
1063 outb(0xf0, io);
1064 crf0 = inb(io + 1);
1065 outb(0xaa, io);
1066
1067 if (verbose_probing) {
1068 pr_info("Winbond LPT Config: cr_30=%02x 60,61=%02x%02x 70=%02x 74=%02x, f0=%02x\n",
1069 cr30, cr60, cr61, cr70, cr74, crf0);
1070 pr_info("Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
1071 (cr30 & 0x01) ? "yes" : "no", cr60, cr61, cr70 & 0x0f);
1072 if ((cr74 & 0x07) > 3)
1073 pr_cont("dma=none\n");
1074 else
1075 pr_cont("dma=%d\n", cr74 & 0x07);
1076 pr_info("Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n",
1077 irqtypes[crf0 >> 7], (crf0 >> 3) & 0x0f);
1078 pr_info("Winbond LPT Config: Port mode=%s\n",
1079 modes[crf0 & 0x07]);
1080 }
1081
1082 if (cr30 & 0x01) { /* the settings can be interrogated later ... */
1083 s = find_free_superio();
1084 if (s == NULL)
1085 pr_info("Super-IO: too many chips!\n");
1086 else {
1087 s->io = (cr60 << 8) | cr61;
1088 s->irq = cr70 & 0x0f;
1089 s->dma = (((cr74 & 0x07) > 3) ?
1090 PARPORT_DMA_NONE : (cr74 & 0x07));
1091 }
1092 }
1093}
1094
1095static void decode_winbond(int efer, int key, int devid, int devrev, int oldid)
1096{
1097 const char *type = "unknown";
1098 int id, progif = 2;
1099
1100 if (devid == devrev)
1101 /* simple heuristics, we happened to read some
1102 non-winbond register */
1103 return;
1104
1105 id = (devid << 8) | devrev;
1106
1107 /* Values are from public data sheets pdf files, I can just
1108 confirm 83977TF is correct :-) */
1109 if (id == 0x9771)
1110 type = "83977F/AF";
1111 else if (id == 0x9773)
1112 type = "83977TF / SMSC 97w33x/97w34x";
1113 else if (id == 0x9774)
1114 type = "83977ATF";
1115 else if ((id & ~0x0f) == 0x5270)
1116 type = "83977CTF / SMSC 97w36x";
1117 else if ((id & ~0x0f) == 0x52f0)
1118 type = "83977EF / SMSC 97w35x";
1119 else if ((id & ~0x0f) == 0x5210)
1120 type = "83627";
1121 else if ((id & ~0x0f) == 0x6010)
1122 type = "83697HF";
1123 else if ((oldid & 0x0f) == 0x0a) {
1124 type = "83877F";
1125 progif = 1;
1126 } else if ((oldid & 0x0f) == 0x0b) {
1127 type = "83877AF";
1128 progif = 1;
1129 } else if ((oldid & 0x0f) == 0x0c) {
1130 type = "83877TF";
1131 progif = 1;
1132 } else if ((oldid & 0x0f) == 0x0d) {
1133 type = "83877ATF";
1134 progif = 1;
1135 } else
1136 progif = 0;
1137
1138 if (verbose_probing)
1139 pr_info("Winbond chip at EFER=0x%x key=0x%02x devid=%02x devrev=%02x oldid=%02x type=%s\n",
1140 efer, key, devid, devrev, oldid, type);
1141
1142 if (progif == 2)
1143 show_parconfig_winbond(efer, key);
1144}
1145
1146static void decode_smsc(int efer, int key, int devid, int devrev)
1147{
1148 const char *type = "unknown";
1149 void (*func)(int io, int key);
1150 int id;
1151
1152 if (devid == devrev)
1153 /* simple heuristics, we happened to read some
1154 non-smsc register */
1155 return;
1156
1157 func = NULL;
1158 id = (devid << 8) | devrev;
1159
1160 if (id == 0x0302) {
1161 type = "37c669";
1162 func = show_parconfig_smsc37c669;
1163 } else if (id == 0x6582)
1164 type = "37c665IR";
1165 else if (devid == 0x65)
1166 type = "37c665GT";
1167 else if (devid == 0x66)
1168 type = "37c666GT";
1169
1170 if (verbose_probing)
1171 pr_info("SMSC chip at EFER=0x%x key=0x%02x devid=%02x devrev=%02x type=%s\n",
1172 efer, key, devid, devrev, type);
1173
1174 if (func)
1175 func(efer, key);
1176}
1177
1178
1179static void winbond_check(int io, int key)
1180{
1181 int origval, devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1182
1183 if (!request_region(io, 3, __func__))
1184 return;
1185
1186 origval = inb(io); /* Save original value */
1187
1188 /* First probe without key */
1189 outb(0x20, io);
1190 x_devid = inb(io + 1);
1191 outb(0x21, io);
1192 x_devrev = inb(io + 1);
1193 outb(0x09, io);
1194 x_oldid = inb(io + 1);
1195
1196 outb(key, io);
1197 outb(key, io); /* Write Magic Sequence to EFER, extended
1198 function enable register */
1199 outb(0x20, io); /* Write EFIR, extended function index register */
1200 devid = inb(io + 1); /* Read EFDR, extended function data register */
1201 outb(0x21, io);
1202 devrev = inb(io + 1);
1203 outb(0x09, io);
1204 oldid = inb(io + 1);
1205 outb(0xaa, io); /* Magic Seal */
1206
1207 outb(origval, io); /* in case we poked some entirely different hardware */
1208
1209 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1210 goto out; /* protection against false positives */
1211
1212 decode_winbond(io, key, devid, devrev, oldid);
1213out:
1214 release_region(io, 3);
1215}
1216
1217static void winbond_check2(int io, int key)
1218{
1219 int origval[3], devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1220
1221 if (!request_region(io, 3, __func__))
1222 return;
1223
1224 origval[0] = inb(io); /* Save original values */
1225 origval[1] = inb(io + 1);
1226 origval[2] = inb(io + 2);
1227
1228 /* First probe without the key */
1229 outb(0x20, io + 2);
1230 x_devid = inb(io + 2);
1231 outb(0x21, io + 1);
1232 x_devrev = inb(io + 2);
1233 outb(0x09, io + 1);
1234 x_oldid = inb(io + 2);
1235
1236 outb(key, io); /* Write Magic Byte to EFER, extended
1237 function enable register */
1238 outb(0x20, io + 2); /* Write EFIR, extended function index register */
1239 devid = inb(io + 2); /* Read EFDR, extended function data register */
1240 outb(0x21, io + 1);
1241 devrev = inb(io + 2);
1242 outb(0x09, io + 1);
1243 oldid = inb(io + 2);
1244 outb(0xaa, io); /* Magic Seal */
1245
1246 outb(origval[0], io); /* in case we poked some entirely different hardware */
1247 outb(origval[1], io + 1);
1248 outb(origval[2], io + 2);
1249
1250 if (x_devid == devid && x_devrev == devrev && x_oldid == oldid)
1251 goto out; /* protection against false positives */
1252
1253 decode_winbond(io, key, devid, devrev, oldid);
1254out:
1255 release_region(io, 3);
1256}
1257
1258static void smsc_check(int io, int key)
1259{
1260 int origval, id, rev, oldid, oldrev, x_id, x_rev, x_oldid, x_oldrev;
1261
1262 if (!request_region(io, 3, __func__))
1263 return;
1264
1265 origval = inb(io); /* Save original value */
1266
1267 /* First probe without the key */
1268 outb(0x0d, io);
1269 x_oldid = inb(io + 1);
1270 outb(0x0e, io);
1271 x_oldrev = inb(io + 1);
1272 outb(0x20, io);
1273 x_id = inb(io + 1);
1274 outb(0x21, io);
1275 x_rev = inb(io + 1);
1276
1277 outb(key, io);
1278 outb(key, io); /* Write Magic Sequence to EFER, extended
1279 function enable register */
1280 outb(0x0d, io); /* Write EFIR, extended function index register */
1281 oldid = inb(io + 1); /* Read EFDR, extended function data register */
1282 outb(0x0e, io);
1283 oldrev = inb(io + 1);
1284 outb(0x20, io);
1285 id = inb(io + 1);
1286 outb(0x21, io);
1287 rev = inb(io + 1);
1288 outb(0xaa, io); /* Magic Seal */
1289
1290 outb(origval, io); /* in case we poked some entirely different hardware */
1291
1292 if (x_id == id && x_oldrev == oldrev &&
1293 x_oldid == oldid && x_rev == rev)
1294 goto out; /* protection against false positives */
1295
1296 decode_smsc(io, key, oldid, oldrev);
1297out:
1298 release_region(io, 3);
1299}
1300
1301
1302static void detect_and_report_winbond(void)
1303{
1304 if (verbose_probing)
1305 printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n");
1306 winbond_check(0x3f0, 0x87);
1307 winbond_check(0x370, 0x87);
1308 winbond_check(0x2e , 0x87);
1309 winbond_check(0x4e , 0x87);
1310 winbond_check(0x3f0, 0x86);
1311 winbond_check2(0x250, 0x88);
1312 winbond_check2(0x250, 0x89);
1313}
1314
1315static void detect_and_report_smsc(void)
1316{
1317 if (verbose_probing)
1318 printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n");
1319 smsc_check(0x3f0, 0x55);
1320 smsc_check(0x370, 0x55);
1321 smsc_check(0x3f0, 0x44);
1322 smsc_check(0x370, 0x44);
1323}
1324
1325static void detect_and_report_it87(void)
1326{
1327 u16 dev;
1328 u8 origval, r;
1329 if (verbose_probing)
1330 printk(KERN_DEBUG "IT8705 Super-IO detection, now testing port 2E ...\n");
1331 if (!request_muxed_region(0x2e, 2, __func__))
1332 return;
1333 origval = inb(0x2e); /* Save original value */
1334 outb(0x87, 0x2e);
1335 outb(0x01, 0x2e);
1336 outb(0x55, 0x2e);
1337 outb(0x55, 0x2e);
1338 outb(0x20, 0x2e);
1339 dev = inb(0x2f) << 8;
1340 outb(0x21, 0x2e);
1341 dev |= inb(0x2f);
1342 if (dev == 0x8712 || dev == 0x8705 || dev == 0x8715 ||
1343 dev == 0x8716 || dev == 0x8718 || dev == 0x8726) {
1344 pr_info("IT%04X SuperIO detected\n", dev);
1345 outb(0x07, 0x2E); /* Parallel Port */
1346 outb(0x03, 0x2F);
1347 outb(0xF0, 0x2E); /* BOOT 0x80 off */
1348 r = inb(0x2f);
1349 outb(0xF0, 0x2E);
1350 outb(r | 8, 0x2F);
1351 outb(0x02, 0x2E); /* Lock */
1352 outb(0x02, 0x2F);
1353 } else {
1354 outb(origval, 0x2e); /* Oops, sorry to disturb */
1355 }
1356 release_region(0x2e, 2);
1357}
1358#endif /* CONFIG_PARPORT_PC_SUPERIO */
1359
1360static struct superio_struct *find_superio(struct parport *p)
1361{
1362 int i;
1363 for (i = 0; i < NR_SUPERIOS; i++)
1364 if (superios[i].io == p->base)
1365 return &superios[i];
1366 return NULL;
1367}
1368
1369static int get_superio_dma(struct parport *p)
1370{
1371 struct superio_struct *s = find_superio(p);
1372 if (s)
1373 return s->dma;
1374 return PARPORT_DMA_NONE;
1375}
1376
1377static int get_superio_irq(struct parport *p)
1378{
1379 struct superio_struct *s = find_superio(p);
1380 if (s)
1381 return s->irq;
1382 return PARPORT_IRQ_NONE;
1383}
1384
1385
1386/* --- Mode detection ------------------------------------- */
1387
1388/*
1389 * Checks for port existence, all ports support SPP MODE
1390 * Returns:
1391 * 0 : No parallel port at this address
1392 * PARPORT_MODE_PCSPP : SPP port detected
1393 * (if the user specified an ioport himself,
1394 * this shall always be the case!)
1395 *
1396 */
1397static int parport_SPP_supported(struct parport *pb)
1398{
1399 unsigned char r, w;
1400
1401 /*
1402 * first clear an eventually pending EPP timeout
1403 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset
1404 * that does not even respond to SPP cycles if an EPP
1405 * timeout is pending
1406 */
1407 clear_epp_timeout(pb);
1408
1409 /* Do a simple read-write test to make sure the port exists. */
1410 w = 0xc;
1411 outb(w, CONTROL(pb));
1412
1413 /* Is there a control register that we can read from? Some
1414 * ports don't allow reads, so read_control just returns a
1415 * software copy. Some ports _do_ allow reads, so bypass the
1416 * software copy here. In addition, some bits aren't
1417 * writable. */
1418 r = inb(CONTROL(pb));
1419 if ((r & 0xf) == w) {
1420 w = 0xe;
1421 outb(w, CONTROL(pb));
1422 r = inb(CONTROL(pb));
1423 outb(0xc, CONTROL(pb));
1424 if ((r & 0xf) == w)
1425 return PARPORT_MODE_PCSPP;
1426 }
1427
1428 if (user_specified)
1429 /* That didn't work, but the user thinks there's a
1430 * port here. */
1431 pr_info("parport 0x%lx (WARNING): CTR: wrote 0x%02x, read 0x%02x\n",
1432 pb->base, w, r);
1433
1434 /* Try the data register. The data lines aren't tri-stated at
1435 * this stage, so we expect back what we wrote. */
1436 w = 0xaa;
1437 parport_pc_write_data(pb, w);
1438 r = parport_pc_read_data(pb);
1439 if (r == w) {
1440 w = 0x55;
1441 parport_pc_write_data(pb, w);
1442 r = parport_pc_read_data(pb);
1443 if (r == w)
1444 return PARPORT_MODE_PCSPP;
1445 }
1446
1447 if (user_specified) {
1448 /* Didn't work, but the user is convinced this is the
1449 * place. */
1450 pr_info("parport 0x%lx (WARNING): DATA: wrote 0x%02x, read 0x%02x\n",
1451 pb->base, w, r);
1452 pr_info("parport 0x%lx: You gave this address, but there is probably no parallel port there!\n",
1453 pb->base);
1454 }
1455
1456 /* It's possible that we can't read the control register or
1457 * the data register. In that case just believe the user. */
1458 if (user_specified)
1459 return PARPORT_MODE_PCSPP;
1460
1461 return 0;
1462}
1463
1464/* Check for ECR
1465 *
1466 * Old style XT ports alias io ports every 0x400, hence accessing ECR
1467 * on these cards actually accesses the CTR.
1468 *
1469 * Modern cards don't do this but reading from ECR will return 0xff
1470 * regardless of what is written here if the card does NOT support
1471 * ECP.
1472 *
1473 * We first check to see if ECR is the same as CTR. If not, the low
1474 * two bits of ECR aren't writable, so we check by writing ECR and
1475 * reading it back to see if it's what we expect.
1476 */
1477static int parport_ECR_present(struct parport *pb)
1478{
1479 struct parport_pc_private *priv = pb->private_data;
1480 unsigned char r = 0xc;
1481
1482 outb(r, CONTROL(pb));
1483 if ((inb(ECONTROL(pb)) & 0x3) == (r & 0x3)) {
1484 outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */
1485
1486 r = inb(CONTROL(pb));
1487 if ((inb(ECONTROL(pb)) & 0x2) == (r & 0x2))
1488 goto no_reg; /* Sure that no ECR register exists */
1489 }
1490
1491 if ((inb(ECONTROL(pb)) & 0x3) != 0x1)
1492 goto no_reg;
1493
1494 ECR_WRITE(pb, 0x34);
1495 if (inb(ECONTROL(pb)) != 0x35)
1496 goto no_reg;
1497
1498 priv->ecr = 1;
1499 outb(0xc, CONTROL(pb));
1500
1501 /* Go to mode 000 */
1502 frob_set_mode(pb, ECR_SPP);
1503
1504 return 1;
1505
1506 no_reg:
1507 outb(0xc, CONTROL(pb));
1508 return 0;
1509}
1510
1511#ifdef CONFIG_PARPORT_1284
1512/* Detect PS/2 support.
1513 *
1514 * Bit 5 (0x20) sets the PS/2 data direction; setting this high
1515 * allows us to read data from the data lines. In theory we would get back
1516 * 0xff but any peripheral attached to the port may drag some or all of the
1517 * lines down to zero. So if we get back anything that isn't the contents
1518 * of the data register we deem PS/2 support to be present.
1519 *
1520 * Some SPP ports have "half PS/2" ability - you can't turn off the line
1521 * drivers, but an external peripheral with sufficiently beefy drivers of
1522 * its own can overpower them and assert its own levels onto the bus, from
1523 * where they can then be read back as normal. Ports with this property
1524 * and the right type of device attached are likely to fail the SPP test,
1525 * (as they will appear to have stuck bits) and so the fact that they might
1526 * be misdetected here is rather academic.
1527 */
1528
1529static int parport_PS2_supported(struct parport *pb)
1530{
1531 int ok = 0;
1532
1533 clear_epp_timeout(pb);
1534
1535 /* try to tri-state the buffer */
1536 parport_pc_data_reverse(pb);
1537
1538 parport_pc_write_data(pb, 0x55);
1539 if (parport_pc_read_data(pb) != 0x55)
1540 ok++;
1541
1542 parport_pc_write_data(pb, 0xaa);
1543 if (parport_pc_read_data(pb) != 0xaa)
1544 ok++;
1545
1546 /* cancel input mode */
1547 parport_pc_data_forward(pb);
1548
1549 if (ok) {
1550 pb->modes |= PARPORT_MODE_TRISTATE;
1551 } else {
1552 struct parport_pc_private *priv = pb->private_data;
1553 priv->ctr_writable &= ~0x20;
1554 }
1555
1556 return ok;
1557}
1558
1559#ifdef CONFIG_PARPORT_PC_FIFO
1560static int parport_ECP_supported(struct parport *pb)
1561{
1562 int i;
1563 int config, configb;
1564 int pword;
1565 struct parport_pc_private *priv = pb->private_data;
1566 /* Translate ECP intrLine to ISA irq value */
1567 static const int intrline[] = { 0, 7, 9, 10, 11, 14, 15, 5 };
1568
1569 /* If there is no ECR, we have no hope of supporting ECP. */
1570 if (!priv->ecr)
1571 return 0;
1572
1573 /* Find out FIFO depth */
1574 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1575 ECR_WRITE(pb, ECR_TST << 5); /* TEST FIFO */
1576 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02); i++)
1577 outb(0xaa, FIFO(pb));
1578
1579 /*
1580 * Using LGS chipset it uses ECR register, but
1581 * it doesn't support ECP or FIFO MODE
1582 */
1583 if (i == 1024) {
1584 ECR_WRITE(pb, ECR_SPP << 5);
1585 return 0;
1586 }
1587
1588 priv->fifo_depth = i;
1589 if (verbose_probing)
1590 printk(KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i);
1591
1592 /* Find out writeIntrThreshold */
1593 frob_econtrol(pb, 1<<2, 1<<2);
1594 frob_econtrol(pb, 1<<2, 0);
1595 for (i = 1; i <= priv->fifo_depth; i++) {
1596 inb(FIFO(pb));
1597 udelay(50);
1598 if (inb(ECONTROL(pb)) & (1<<2))
1599 break;
1600 }
1601
1602 if (i <= priv->fifo_depth) {
1603 if (verbose_probing)
1604 printk(KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n",
1605 pb->base, i);
1606 } else
1607 /* Number of bytes we know we can write if we get an
1608 interrupt. */
1609 i = 0;
1610
1611 priv->writeIntrThreshold = i;
1612
1613 /* Find out readIntrThreshold */
1614 frob_set_mode(pb, ECR_PS2); /* Reset FIFO and enable PS2 */
1615 parport_pc_data_reverse(pb); /* Must be in PS2 mode */
1616 frob_set_mode(pb, ECR_TST); /* Test FIFO */
1617 frob_econtrol(pb, 1<<2, 1<<2);
1618 frob_econtrol(pb, 1<<2, 0);
1619 for (i = 1; i <= priv->fifo_depth; i++) {
1620 outb(0xaa, FIFO(pb));
1621 if (inb(ECONTROL(pb)) & (1<<2))
1622 break;
1623 }
1624
1625 if (i <= priv->fifo_depth) {
1626 if (verbose_probing)
1627 pr_info("0x%lx: readIntrThreshold is %d\n",
1628 pb->base, i);
1629 } else
1630 /* Number of bytes we can read if we get an interrupt. */
1631 i = 0;
1632
1633 priv->readIntrThreshold = i;
1634
1635 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1636 ECR_WRITE(pb, 0xf4); /* Configuration mode */
1637 config = inb(CONFIGA(pb));
1638 pword = (config >> 4) & 0x7;
1639 switch (pword) {
1640 case 0:
1641 pword = 2;
1642 pr_warn("0x%lx: Unsupported pword size!\n", pb->base);
1643 break;
1644 case 2:
1645 pword = 4;
1646 pr_warn("0x%lx: Unsupported pword size!\n", pb->base);
1647 break;
1648 default:
1649 pr_warn("0x%lx: Unknown implementation ID\n", pb->base);
1650 fallthrough; /* Assume 1 */
1651 case 1:
1652 pword = 1;
1653 }
1654 priv->pword = pword;
1655
1656 if (verbose_probing) {
1657 printk(KERN_DEBUG "0x%lx: PWord is %d bits\n",
1658 pb->base, 8 * pword);
1659
1660 printk(KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n",
1661 pb->base, config & 0x80 ? "Level" : "Pulses");
1662
1663 configb = inb(CONFIGB(pb));
1664 printk(KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
1665 pb->base, config, configb);
1666 printk(KERN_DEBUG "0x%lx: ECP settings irq=", pb->base);
1667 if ((configb >> 3) & 0x07)
1668 pr_cont("%d", intrline[(configb >> 3) & 0x07]);
1669 else
1670 pr_cont("<none or set by other means>");
1671 pr_cont(" dma=");
1672 if ((configb & 0x03) == 0x00)
1673 pr_cont("<none or set by other means>\n");
1674 else
1675 pr_cont("%d\n", configb & 0x07);
1676 }
1677
1678 /* Go back to mode 000 */
1679 frob_set_mode(pb, ECR_SPP);
1680
1681 return 1;
1682}
1683#endif
1684
1685#ifdef CONFIG_X86_32
1686static int intel_bug_present_check_epp(struct parport *pb)
1687{
1688 const struct parport_pc_private *priv = pb->private_data;
1689 int bug_present = 0;
1690
1691 if (priv->ecr) {
1692 /* store value of ECR */
1693 unsigned char ecr = inb(ECONTROL(pb));
1694 unsigned char i;
1695 for (i = 0x00; i < 0x80; i += 0x20) {
1696 ECR_WRITE(pb, i);
1697 if (clear_epp_timeout(pb)) {
1698 /* Phony EPP in ECP. */
1699 bug_present = 1;
1700 break;
1701 }
1702 }
1703 /* return ECR into the inital state */
1704 ECR_WRITE(pb, ecr);
1705 }
1706
1707 return bug_present;
1708}
1709static int intel_bug_present(struct parport *pb)
1710{
1711/* Check whether the device is legacy, not PCI or PCMCIA. Only legacy is known to be affected. */
1712 if (pb->dev != NULL) {
1713 return 0;
1714 }
1715
1716 return intel_bug_present_check_epp(pb);
1717}
1718#else
1719static int intel_bug_present(struct parport *pb)
1720{
1721 return 0;
1722}
1723#endif /* CONFIG_X86_32 */
1724
1725static int parport_ECPPS2_supported(struct parport *pb)
1726{
1727 const struct parport_pc_private *priv = pb->private_data;
1728 int result;
1729 unsigned char oecr;
1730
1731 if (!priv->ecr)
1732 return 0;
1733
1734 oecr = inb(ECONTROL(pb));
1735 ECR_WRITE(pb, ECR_PS2 << 5);
1736 result = parport_PS2_supported(pb);
1737 ECR_WRITE(pb, oecr);
1738 return result;
1739}
1740
1741/* EPP mode detection */
1742
1743static int parport_EPP_supported(struct parport *pb)
1744{
1745 /*
1746 * Theory:
1747 * Bit 0 of STR is the EPP timeout bit, this bit is 0
1748 * when EPP is possible and is set high when an EPP timeout
1749 * occurs (EPP uses the HALT line to stop the CPU while it does
1750 * the byte transfer, an EPP timeout occurs if the attached
1751 * device fails to respond after 10 micro seconds).
1752 *
1753 * This bit is cleared by either reading it (National Semi)
1754 * or writing a 1 to the bit (SMC, UMC, WinBond), others ???
1755 * This bit is always high in non EPP modes.
1756 */
1757
1758 /* If EPP timeout bit clear then EPP available */
1759 if (!clear_epp_timeout(pb))
1760 return 0; /* No way to clear timeout */
1761
1762 /* Check for Intel bug. */
1763 if (intel_bug_present(pb))
1764 return 0;
1765
1766 pb->modes |= PARPORT_MODE_EPP;
1767
1768 /* Set up access functions to use EPP hardware. */
1769 pb->ops->epp_read_data = parport_pc_epp_read_data;
1770 pb->ops->epp_write_data = parport_pc_epp_write_data;
1771 pb->ops->epp_read_addr = parport_pc_epp_read_addr;
1772 pb->ops->epp_write_addr = parport_pc_epp_write_addr;
1773
1774 return 1;
1775}
1776
1777static int parport_ECPEPP_supported(struct parport *pb)
1778{
1779 struct parport_pc_private *priv = pb->private_data;
1780 int result;
1781 unsigned char oecr;
1782
1783 if (!priv->ecr)
1784 return 0;
1785
1786 oecr = inb(ECONTROL(pb));
1787 /* Search for SMC style EPP+ECP mode */
1788 ECR_WRITE(pb, 0x80);
1789 outb(0x04, CONTROL(pb));
1790 result = parport_EPP_supported(pb);
1791
1792 ECR_WRITE(pb, oecr);
1793
1794 if (result) {
1795 /* Set up access functions to use ECP+EPP hardware. */
1796 pb->ops->epp_read_data = parport_pc_ecpepp_read_data;
1797 pb->ops->epp_write_data = parport_pc_ecpepp_write_data;
1798 pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr;
1799 pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr;
1800 }
1801
1802 return result;
1803}
1804
1805#else /* No IEEE 1284 support */
1806
1807/* Don't bother probing for modes we know we won't use. */
1808static int parport_PS2_supported(struct parport *pb) { return 0; }
1809#ifdef CONFIG_PARPORT_PC_FIFO
1810static int parport_ECP_supported(struct parport *pb)
1811{
1812 return 0;
1813}
1814#endif
1815static int parport_EPP_supported(struct parport *pb)
1816{
1817 return 0;
1818}
1819
1820static int parport_ECPEPP_supported(struct parport *pb)
1821{
1822 return 0;
1823}
1824
1825static int parport_ECPPS2_supported(struct parport *pb)
1826{
1827 return 0;
1828}
1829
1830#endif /* No IEEE 1284 support */
1831
1832/* --- IRQ detection -------------------------------------- */
1833
1834/* Only if supports ECP mode */
1835static int programmable_irq_support(struct parport *pb)
1836{
1837 int irq, intrLine;
1838 unsigned char oecr = inb(ECONTROL(pb));
1839 static const int lookup[8] = {
1840 PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5
1841 };
1842
1843 ECR_WRITE(pb, ECR_CNF << 5); /* Configuration MODE */
1844
1845 intrLine = (inb(CONFIGB(pb)) >> 3) & 0x07;
1846 irq = lookup[intrLine];
1847
1848 ECR_WRITE(pb, oecr);
1849 return irq;
1850}
1851
1852static int irq_probe_ECP(struct parport *pb)
1853{
1854 int i;
1855 unsigned long irqs;
1856
1857 irqs = probe_irq_on();
1858
1859 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1860 ECR_WRITE(pb, (ECR_TST << 5) | 0x04);
1861 ECR_WRITE(pb, ECR_TST << 5);
1862
1863 /* If Full FIFO sure that writeIntrThreshold is generated */
1864 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02) ; i++)
1865 outb(0xaa, FIFO(pb));
1866
1867 pb->irq = probe_irq_off(irqs);
1868 ECR_WRITE(pb, ECR_SPP << 5);
1869
1870 if (pb->irq <= 0)
1871 pb->irq = PARPORT_IRQ_NONE;
1872
1873 return pb->irq;
1874}
1875
1876/*
1877 * This detection seems that only works in National Semiconductors
1878 * This doesn't work in SMC, LGS, and Winbond
1879 */
1880static int irq_probe_EPP(struct parport *pb)
1881{
1882#ifndef ADVANCED_DETECT
1883 return PARPORT_IRQ_NONE;
1884#else
1885 int irqs;
1886 unsigned char oecr;
1887
1888 if (pb->modes & PARPORT_MODE_PCECR)
1889 oecr = inb(ECONTROL(pb));
1890
1891 irqs = probe_irq_on();
1892
1893 if (pb->modes & PARPORT_MODE_PCECR)
1894 frob_econtrol(pb, 0x10, 0x10);
1895
1896 clear_epp_timeout(pb);
1897 parport_pc_frob_control(pb, 0x20, 0x20);
1898 parport_pc_frob_control(pb, 0x10, 0x10);
1899 clear_epp_timeout(pb);
1900
1901 /* Device isn't expecting an EPP read
1902 * and generates an IRQ.
1903 */
1904 parport_pc_read_epp(pb);
1905 udelay(20);
1906
1907 pb->irq = probe_irq_off(irqs);
1908 if (pb->modes & PARPORT_MODE_PCECR)
1909 ECR_WRITE(pb, oecr);
1910 parport_pc_write_control(pb, 0xc);
1911
1912 if (pb->irq <= 0)
1913 pb->irq = PARPORT_IRQ_NONE;
1914
1915 return pb->irq;
1916#endif /* Advanced detection */
1917}
1918
1919static int irq_probe_SPP(struct parport *pb)
1920{
1921 /* Don't even try to do this. */
1922 return PARPORT_IRQ_NONE;
1923}
1924
1925/* We will attempt to share interrupt requests since other devices
1926 * such as sound cards and network cards seem to like using the
1927 * printer IRQs.
1928 *
1929 * When ECP is available we can autoprobe for IRQs.
1930 * NOTE: If we can autoprobe it, we can register the IRQ.
1931 */
1932static int parport_irq_probe(struct parport *pb)
1933{
1934 struct parport_pc_private *priv = pb->private_data;
1935
1936 if (priv->ecr) {
1937 pb->irq = programmable_irq_support(pb);
1938
1939 if (pb->irq == PARPORT_IRQ_NONE)
1940 pb->irq = irq_probe_ECP(pb);
1941 }
1942
1943 if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr &&
1944 (pb->modes & PARPORT_MODE_EPP))
1945 pb->irq = irq_probe_EPP(pb);
1946
1947 clear_epp_timeout(pb);
1948
1949 if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP))
1950 pb->irq = irq_probe_EPP(pb);
1951
1952 clear_epp_timeout(pb);
1953
1954 if (pb->irq == PARPORT_IRQ_NONE)
1955 pb->irq = irq_probe_SPP(pb);
1956
1957 if (pb->irq == PARPORT_IRQ_NONE)
1958 pb->irq = get_superio_irq(pb);
1959
1960 return pb->irq;
1961}
1962
1963/* --- DMA detection -------------------------------------- */
1964
1965/* Only if chipset conforms to ECP ISA Interface Standard */
1966static int programmable_dma_support(struct parport *p)
1967{
1968 unsigned char oecr = inb(ECONTROL(p));
1969 int dma;
1970
1971 frob_set_mode(p, ECR_CNF);
1972
1973 dma = inb(CONFIGB(p)) & 0x07;
1974 /* 000: Indicates jumpered 8-bit DMA if read-only.
1975 100: Indicates jumpered 16-bit DMA if read-only. */
1976 if ((dma & 0x03) == 0)
1977 dma = PARPORT_DMA_NONE;
1978
1979 ECR_WRITE(p, oecr);
1980 return dma;
1981}
1982
1983static int parport_dma_probe(struct parport *p)
1984{
1985 const struct parport_pc_private *priv = p->private_data;
1986 if (priv->ecr) /* ask ECP chipset first */
1987 p->dma = programmable_dma_support(p);
1988 if (p->dma == PARPORT_DMA_NONE) {
1989 /* ask known Super-IO chips proper, although these
1990 claim ECP compatible, some don't report their DMA
1991 conforming to ECP standards */
1992 p->dma = get_superio_dma(p);
1993 }
1994
1995 return p->dma;
1996}
1997
1998/* --- Initialisation code -------------------------------- */
1999
2000static LIST_HEAD(ports_list);
2001static DEFINE_SPINLOCK(ports_lock);
2002
2003struct parport *parport_pc_probe_port(unsigned long int base,
2004 unsigned long int base_hi,
2005 int irq, int dma,
2006 struct device *dev,
2007 int irqflags)
2008{
2009 struct parport_pc_private *priv;
2010 struct parport_operations *ops;
2011 struct parport *p;
2012 int probedirq = PARPORT_IRQ_NONE;
2013 struct resource *base_res;
2014 struct resource *ECR_res = NULL;
2015 struct resource *EPP_res = NULL;
2016 struct platform_device *pdev = NULL;
2017 int ret;
2018
2019 if (!dev) {
2020 /* We need a physical device to attach to, but none was
2021 * provided. Create our own. */
2022 pdev = platform_device_register_simple("parport_pc",
2023 base, NULL, 0);
2024 if (IS_ERR(pdev))
2025 return NULL;
2026 dev = &pdev->dev;
2027
2028 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(24));
2029 if (ret) {
2030 dev_err(dev, "Unable to set coherent dma mask: disabling DMA\n");
2031 dma = PARPORT_DMA_NONE;
2032 }
2033 }
2034
2035 ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL);
2036 if (!ops)
2037 goto out1;
2038
2039 priv = kmalloc(sizeof(struct parport_pc_private), GFP_KERNEL);
2040 if (!priv)
2041 goto out2;
2042
2043 /* a misnomer, actually - it's allocate and reserve parport number */
2044 p = parport_register_port(base, irq, dma, ops);
2045 if (!p)
2046 goto out3;
2047
2048 base_res = request_region(base, 3, p->name);
2049 if (!base_res)
2050 goto out4;
2051
2052 memcpy(ops, &parport_pc_ops, sizeof(struct parport_operations));
2053 priv->ctr = 0xc;
2054 priv->ctr_writable = ~0x10;
2055 priv->ecr = 0;
2056 priv->fifo_depth = 0;
2057 priv->dma_buf = NULL;
2058 priv->dma_handle = 0;
2059 INIT_LIST_HEAD(&priv->list);
2060 priv->port = p;
2061
2062 p->dev = dev;
2063 p->base_hi = base_hi;
2064 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
2065 p->private_data = priv;
2066
2067 if (base_hi) {
2068 ECR_res = request_region(base_hi, 3, p->name);
2069 if (ECR_res)
2070 parport_ECR_present(p);
2071 }
2072
2073 if (base != 0x3bc) {
2074 EPP_res = request_region(base+0x3, 5, p->name);
2075 if (EPP_res)
2076 if (!parport_EPP_supported(p))
2077 parport_ECPEPP_supported(p);
2078 }
2079 if (!parport_SPP_supported(p))
2080 /* No port. */
2081 goto out5;
2082 if (priv->ecr)
2083 parport_ECPPS2_supported(p);
2084 else
2085 parport_PS2_supported(p);
2086
2087 p->size = (p->modes & PARPORT_MODE_EPP) ? 8 : 3;
2088
2089 pr_info("%s: PC-style at 0x%lx", p->name, p->base);
2090 if (p->base_hi && priv->ecr)
2091 pr_cont(" (0x%lx)", p->base_hi);
2092 if (p->irq == PARPORT_IRQ_AUTO) {
2093 p->irq = PARPORT_IRQ_NONE;
2094 parport_irq_probe(p);
2095 } else if (p->irq == PARPORT_IRQ_PROBEONLY) {
2096 p->irq = PARPORT_IRQ_NONE;
2097 parport_irq_probe(p);
2098 probedirq = p->irq;
2099 p->irq = PARPORT_IRQ_NONE;
2100 }
2101 if (p->irq != PARPORT_IRQ_NONE) {
2102 pr_cont(", irq %d", p->irq);
2103 priv->ctr_writable |= 0x10;
2104
2105 if (p->dma == PARPORT_DMA_AUTO) {
2106 p->dma = PARPORT_DMA_NONE;
2107 parport_dma_probe(p);
2108 }
2109 }
2110 if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq
2111 is mandatory (see above) */
2112 p->dma = PARPORT_DMA_NONE;
2113
2114#ifdef CONFIG_PARPORT_PC_FIFO
2115 if (parport_ECP_supported(p) &&
2116 p->dma != PARPORT_DMA_NOFIFO &&
2117 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) {
2118 p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT;
2119 p->ops->compat_write_data = parport_pc_compat_write_block_pio;
2120#ifdef CONFIG_PARPORT_1284
2121 p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
2122 /* currently broken, but working on it.. (FB) */
2123 /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */
2124#endif /* IEEE 1284 support */
2125 if (p->dma != PARPORT_DMA_NONE) {
2126 pr_cont(", dma %d", p->dma);
2127 p->modes |= PARPORT_MODE_DMA;
2128 } else
2129 pr_cont(", using FIFO");
2130 } else
2131 /* We can't use the DMA channel after all. */
2132 p->dma = PARPORT_DMA_NONE;
2133#endif /* Allowed to use FIFO/DMA */
2134
2135 pr_cont(" [");
2136
2137#define printmode(x) \
2138do { \
2139 if (p->modes & PARPORT_MODE_##x) \
2140 pr_cont("%s%s", f++ ? "," : "", #x); \
2141} while (0)
2142
2143 {
2144 int f = 0;
2145 printmode(PCSPP);
2146 printmode(TRISTATE);
2147 printmode(COMPAT);
2148 printmode(EPP);
2149 printmode(ECP);
2150 printmode(DMA);
2151 }
2152#undef printmode
2153#ifndef CONFIG_PARPORT_1284
2154 pr_cont("(,...)");
2155#endif /* CONFIG_PARPORT_1284 */
2156 pr_cont("]\n");
2157 if (probedirq != PARPORT_IRQ_NONE)
2158 pr_info("%s: irq %d detected\n", p->name, probedirq);
2159
2160 /* If No ECP release the ports grabbed above. */
2161 if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) {
2162 release_region(base_hi, 3);
2163 ECR_res = NULL;
2164 }
2165 /* Likewise for EEP ports */
2166 if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) {
2167 release_region(base+3, 5);
2168 EPP_res = NULL;
2169 }
2170 if (p->irq != PARPORT_IRQ_NONE) {
2171 if (request_irq(p->irq, parport_irq_handler,
2172 irqflags, p->name, p)) {
2173 pr_warn("%s: irq %d in use, resorting to polled operation\n",
2174 p->name, p->irq);
2175 p->irq = PARPORT_IRQ_NONE;
2176 p->dma = PARPORT_DMA_NONE;
2177 }
2178
2179#ifdef CONFIG_PARPORT_PC_FIFO
2180#ifdef HAS_DMA
2181 if (p->dma != PARPORT_DMA_NONE) {
2182 if (request_dma(p->dma, p->name)) {
2183 pr_warn("%s: dma %d in use, resorting to PIO operation\n",
2184 p->name, p->dma);
2185 p->dma = PARPORT_DMA_NONE;
2186 } else {
2187 priv->dma_buf =
2188 dma_alloc_coherent(dev,
2189 PAGE_SIZE,
2190 &priv->dma_handle,
2191 GFP_KERNEL);
2192 if (!priv->dma_buf) {
2193 pr_warn("%s: cannot get buffer for DMA, resorting to PIO operation\n",
2194 p->name);
2195 free_dma(p->dma);
2196 p->dma = PARPORT_DMA_NONE;
2197 }
2198 }
2199 }
2200#endif
2201#endif
2202 }
2203
2204 /* Done probing. Now put the port into a sensible start-up state. */
2205 if (priv->ecr)
2206 /*
2207 * Put the ECP detected port in PS2 mode.
2208 * Do this also for ports that have ECR but don't do ECP.
2209 */
2210 ECR_WRITE(p, 0x34);
2211
2212 parport_pc_write_data(p, 0);
2213 parport_pc_data_forward(p);
2214
2215 /* Now that we've told the sharing engine about the port, and
2216 found out its characteristics, let the high-level drivers
2217 know about it. */
2218 spin_lock(&ports_lock);
2219 list_add(&priv->list, &ports_list);
2220 spin_unlock(&ports_lock);
2221 parport_announce_port(p);
2222
2223 return p;
2224
2225out5:
2226 if (ECR_res)
2227 release_region(base_hi, 3);
2228 if (EPP_res)
2229 release_region(base+0x3, 5);
2230 release_region(base, 3);
2231out4:
2232 parport_del_port(p);
2233out3:
2234 kfree(priv);
2235out2:
2236 kfree(ops);
2237out1:
2238 if (pdev)
2239 platform_device_unregister(pdev);
2240 return NULL;
2241}
2242EXPORT_SYMBOL(parport_pc_probe_port);
2243
2244void parport_pc_unregister_port(struct parport *p)
2245{
2246 struct parport_pc_private *priv = p->private_data;
2247 struct parport_operations *ops = p->ops;
2248
2249 parport_remove_port(p);
2250 spin_lock(&ports_lock);
2251 list_del_init(&priv->list);
2252 spin_unlock(&ports_lock);
2253#if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2254 if (p->dma != PARPORT_DMA_NONE)
2255 free_dma(p->dma);
2256#endif
2257 if (p->irq != PARPORT_IRQ_NONE)
2258 free_irq(p->irq, p);
2259 release_region(p->base, 3);
2260 if (p->size > 3)
2261 release_region(p->base + 3, p->size - 3);
2262 if (p->modes & PARPORT_MODE_ECP)
2263 release_region(p->base_hi, 3);
2264#if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2265 if (priv->dma_buf)
2266 dma_free_coherent(p->physport->dev, PAGE_SIZE,
2267 priv->dma_buf,
2268 priv->dma_handle);
2269#endif
2270 kfree(p->private_data);
2271 parport_del_port(p);
2272 kfree(ops); /* hope no-one cached it */
2273}
2274EXPORT_SYMBOL(parport_pc_unregister_port);
2275
2276#ifdef CONFIG_PCI
2277
2278/* ITE support maintained by Rich Liu <richliu@poorman.org> */
2279static int sio_ite_8872_probe(struct pci_dev *pdev, int autoirq, int autodma,
2280 const struct parport_pc_via_data *via)
2281{
2282 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 };
2283 u32 ite8872set;
2284 u32 ite8872_lpt, ite8872_lpthi;
2285 u8 ite8872_irq, type;
2286 int irq;
2287 int i;
2288
2289 pr_debug("sio_ite_8872_probe()\n");
2290
2291 /* make sure which one chip */
2292 for (i = 0; i < 5; i++) {
2293 if (request_region(inta_addr[i], 32, "it887x")) {
2294 int test;
2295 pci_write_config_dword(pdev, 0x60,
2296 0xe5000000 | inta_addr[i]);
2297 pci_write_config_dword(pdev, 0x78,
2298 0x00000000 | inta_addr[i]);
2299 test = inb(inta_addr[i]);
2300 if (test != 0xff)
2301 break;
2302 release_region(inta_addr[i], 32);
2303 }
2304 }
2305 if (i >= 5) {
2306 pr_info("parport_pc: cannot find ITE8872 INTA\n");
2307 return 0;
2308 }
2309
2310 type = inb(inta_addr[i] + 0x18);
2311 type &= 0x0f;
2312
2313 switch (type) {
2314 case 0x2:
2315 pr_info("parport_pc: ITE8871 found (1P)\n");
2316 ite8872set = 0x64200000;
2317 break;
2318 case 0xa:
2319 pr_info("parport_pc: ITE8875 found (1P)\n");
2320 ite8872set = 0x64200000;
2321 break;
2322 case 0xe:
2323 pr_info("parport_pc: ITE8872 found (2S1P)\n");
2324 ite8872set = 0x64e00000;
2325 break;
2326 case 0x6:
2327 pr_info("parport_pc: ITE8873 found (1S)\n");
2328 release_region(inta_addr[i], 32);
2329 return 0;
2330 case 0x8:
2331 pr_info("parport_pc: ITE8874 found (2S)\n");
2332 release_region(inta_addr[i], 32);
2333 return 0;
2334 default:
2335 pr_info("parport_pc: unknown ITE887x\n");
2336 pr_info("parport_pc: please mail 'lspci -nvv' output to Rich.Liu@ite.com.tw\n");
2337 release_region(inta_addr[i], 32);
2338 return 0;
2339 }
2340
2341 pci_read_config_byte(pdev, 0x3c, &ite8872_irq);
2342 pci_read_config_dword(pdev, 0x1c, &ite8872_lpt);
2343 ite8872_lpt &= 0x0000ff00;
2344 pci_read_config_dword(pdev, 0x20, &ite8872_lpthi);
2345 ite8872_lpthi &= 0x0000ff00;
2346 pci_write_config_dword(pdev, 0x6c, 0xe3000000 | ite8872_lpt);
2347 pci_write_config_dword(pdev, 0x70, 0xe3000000 | ite8872_lpthi);
2348 pci_write_config_dword(pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt);
2349 /* SET SPP&EPP , Parallel Port NO DMA , Enable All Function */
2350 /* SET Parallel IRQ */
2351 pci_write_config_dword(pdev, 0x9c,
2352 ite8872set | (ite8872_irq * 0x11111));
2353
2354 pr_debug("ITE887x: The IRQ is %d\n", ite8872_irq);
2355 pr_debug("ITE887x: The PARALLEL I/O port is 0x%x\n", ite8872_lpt);
2356 pr_debug("ITE887x: The PARALLEL I/O porthi is 0x%x\n", ite8872_lpthi);
2357
2358 /* Let the user (or defaults) steer us away from interrupts */
2359 irq = ite8872_irq;
2360 if (autoirq != PARPORT_IRQ_AUTO)
2361 irq = PARPORT_IRQ_NONE;
2362
2363 /*
2364 * Release the resource so that parport_pc_probe_port can get it.
2365 */
2366 release_region(inta_addr[i], 32);
2367 if (parport_pc_probe_port(ite8872_lpt, ite8872_lpthi,
2368 irq, PARPORT_DMA_NONE, &pdev->dev, 0)) {
2369 pr_info("parport_pc: ITE 8872 parallel port: io=0x%X",
2370 ite8872_lpt);
2371 if (irq != PARPORT_IRQ_NONE)
2372 pr_cont(", irq=%d", irq);
2373 pr_cont("\n");
2374 return 1;
2375 }
2376
2377 return 0;
2378}
2379
2380/* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru>
2381 based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */
2382static int parport_init_mode;
2383
2384/* Data for two known VIA chips */
2385static struct parport_pc_via_data via_686a_data = {
2386 0x51,
2387 0x50,
2388 0x85,
2389 0x02,
2390 0xE2,
2391 0xF0,
2392 0xE6
2393};
2394static struct parport_pc_via_data via_8231_data = {
2395 0x45,
2396 0x44,
2397 0x50,
2398 0x04,
2399 0xF2,
2400 0xFA,
2401 0xF6
2402};
2403
2404static int sio_via_probe(struct pci_dev *pdev, int autoirq, int autodma,
2405 const struct parport_pc_via_data *via)
2406{
2407 u8 tmp, tmp2, siofunc;
2408 u8 ppcontrol = 0;
2409 int dma, irq;
2410 unsigned port1, port2;
2411 unsigned have_epp = 0;
2412
2413 printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n");
2414
2415 switch (parport_init_mode) {
2416 case 1:
2417 printk(KERN_DEBUG "parport_pc: setting SPP mode\n");
2418 siofunc = VIA_FUNCTION_PARPORT_SPP;
2419 break;
2420 case 2:
2421 printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n");
2422 siofunc = VIA_FUNCTION_PARPORT_SPP;
2423 ppcontrol = VIA_PARPORT_BIDIR;
2424 break;
2425 case 3:
2426 printk(KERN_DEBUG "parport_pc: setting EPP mode\n");
2427 siofunc = VIA_FUNCTION_PARPORT_EPP;
2428 ppcontrol = VIA_PARPORT_BIDIR;
2429 have_epp = 1;
2430 break;
2431 case 4:
2432 printk(KERN_DEBUG "parport_pc: setting ECP mode\n");
2433 siofunc = VIA_FUNCTION_PARPORT_ECP;
2434 ppcontrol = VIA_PARPORT_BIDIR;
2435 break;
2436 case 5:
2437 printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n");
2438 siofunc = VIA_FUNCTION_PARPORT_ECP;
2439 ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP;
2440 have_epp = 1;
2441 break;
2442 default:
2443 printk(KERN_DEBUG "parport_pc: probing current configuration\n");
2444 siofunc = VIA_FUNCTION_PROBE;
2445 break;
2446 }
2447 /*
2448 * unlock super i/o configuration
2449 */
2450 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2451 tmp |= via->via_pci_superio_config_data;
2452 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2453
2454 /* Bits 1-0: Parallel Port Mode / Enable */
2455 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2456 tmp = inb(VIA_CONFIG_DATA);
2457 /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */
2458 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2459 tmp2 = inb(VIA_CONFIG_DATA);
2460 if (siofunc == VIA_FUNCTION_PROBE) {
2461 siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE;
2462 ppcontrol = tmp2;
2463 } else {
2464 tmp &= ~VIA_FUNCTION_PARPORT_DISABLE;
2465 tmp |= siofunc;
2466 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2467 outb(tmp, VIA_CONFIG_DATA);
2468 tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP);
2469 tmp2 |= ppcontrol;
2470 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2471 outb(tmp2, VIA_CONFIG_DATA);
2472 }
2473
2474 /* Parallel Port I/O Base Address, bits 9-2 */
2475 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2476 port1 = inb(VIA_CONFIG_DATA) << 2;
2477
2478 printk(KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",
2479 port1);
2480 if (port1 == 0x3BC && have_epp) {
2481 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2482 outb((0x378 >> 2), VIA_CONFIG_DATA);
2483 printk(KERN_DEBUG "parport_pc: Parallel port base changed to 0x378\n");
2484 port1 = 0x378;
2485 }
2486
2487 /*
2488 * lock super i/o configuration
2489 */
2490 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2491 tmp &= ~via->via_pci_superio_config_data;
2492 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2493
2494 if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) {
2495 pr_info("parport_pc: VIA parallel port disabled in BIOS\n");
2496 return 0;
2497 }
2498
2499 /* Bits 7-4: PnP Routing for Parallel Port IRQ */
2500 pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp);
2501 irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4);
2502
2503 if (siofunc == VIA_FUNCTION_PARPORT_ECP) {
2504 /* Bits 3-2: PnP Routing for Parallel Port DMA */
2505 pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp);
2506 dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2);
2507 } else
2508 /* if ECP not enabled, DMA is not enabled, assumed
2509 bogus 'dma' value */
2510 dma = PARPORT_DMA_NONE;
2511
2512 /* Let the user (or defaults) steer us away from interrupts and DMA */
2513 if (autoirq == PARPORT_IRQ_NONE) {
2514 irq = PARPORT_IRQ_NONE;
2515 dma = PARPORT_DMA_NONE;
2516 }
2517 if (autodma == PARPORT_DMA_NONE)
2518 dma = PARPORT_DMA_NONE;
2519
2520 switch (port1) {
2521 case 0x3bc:
2522 port2 = 0x7bc; break;
2523 case 0x378:
2524 port2 = 0x778; break;
2525 case 0x278:
2526 port2 = 0x678; break;
2527 default:
2528 pr_info("parport_pc: Weird VIA parport base 0x%X, ignoring\n",
2529 port1);
2530 return 0;
2531 }
2532
2533 /* filter bogus IRQs */
2534 switch (irq) {
2535 case 0:
2536 case 2:
2537 case 8:
2538 case 13:
2539 irq = PARPORT_IRQ_NONE;
2540 break;
2541
2542 default: /* do nothing */
2543 break;
2544 }
2545
2546 /* finally, do the probe with values obtained */
2547 if (parport_pc_probe_port(port1, port2, irq, dma, &pdev->dev, 0)) {
2548 pr_info("parport_pc: VIA parallel port: io=0x%X", port1);
2549 if (irq != PARPORT_IRQ_NONE)
2550 pr_cont(", irq=%d", irq);
2551 if (dma != PARPORT_DMA_NONE)
2552 pr_cont(", dma=%d", dma);
2553 pr_cont("\n");
2554 return 1;
2555 }
2556
2557 pr_warn("parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n",
2558 port1, irq, dma);
2559 return 0;
2560}
2561
2562
2563enum parport_pc_sio_types {
2564 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */
2565 sio_via_8231, /* Via VT8231 south bridge integrated Super IO */
2566 sio_ite_8872,
2567 last_sio
2568};
2569
2570/* each element directly indexed from enum list, above */
2571static struct parport_pc_superio {
2572 int (*probe) (struct pci_dev *pdev, int autoirq, int autodma,
2573 const struct parport_pc_via_data *via);
2574 const struct parport_pc_via_data *via;
2575} parport_pc_superio_info[] = {
2576 { sio_via_probe, &via_686a_data, },
2577 { sio_via_probe, &via_8231_data, },
2578 { sio_ite_8872_probe, NULL, },
2579};
2580
2581enum parport_pc_pci_cards {
2582 siig_1p_10x = last_sio,
2583 siig_2p_10x,
2584 siig_1p_20x,
2585 siig_2p_20x,
2586 lava_parallel,
2587 lava_parallel_dual_a,
2588 lava_parallel_dual_b,
2589 boca_ioppar,
2590 plx_9050,
2591 timedia_4006a,
2592 timedia_4014,
2593 timedia_4008a,
2594 timedia_4018,
2595 timedia_9018a,
2596 syba_2p_epp,
2597 syba_1p_ecp,
2598 titan_010l,
2599 avlab_1p,
2600 avlab_2p,
2601 oxsemi_952,
2602 oxsemi_954,
2603 oxsemi_840,
2604 oxsemi_pcie_pport,
2605 aks_0100,
2606 mobility_pp,
2607 netmos_9900,
2608 netmos_9705,
2609 netmos_9715,
2610 netmos_9755,
2611 netmos_9805,
2612 netmos_9815,
2613 netmos_9901,
2614 netmos_9865,
2615 quatech_sppxp100,
2616 wch_ch382l,
2617};
2618
2619
2620/* each element directly indexed from enum list, above
2621 * (but offset by last_sio) */
2622static struct parport_pc_pci {
2623 int numports;
2624 struct { /* BAR (base address registers) numbers in the config
2625 space header */
2626 int lo;
2627 int hi;
2628 /* -1 if not there, >6 for offset-method (max BAR is 6) */
2629 } addr[4];
2630
2631 /* If set, this is called immediately after pci_enable_device.
2632 * If it returns non-zero, no probing will take place and the
2633 * ports will not be used. */
2634 int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma);
2635
2636 /* If set, this is called after probing for ports. If 'failed'
2637 * is non-zero we couldn't use any of the ports. */
2638 void (*postinit_hook) (struct pci_dev *pdev, int failed);
2639} cards[] = {
2640 /* siig_1p_10x */ { 1, { { 2, 3 }, } },
2641 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } },
2642 /* siig_1p_20x */ { 1, { { 0, 1 }, } },
2643 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
2644 /* lava_parallel */ { 1, { { 0, -1 }, } },
2645 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
2646 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
2647 /* boca_ioppar */ { 1, { { 0, -1 }, } },
2648 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } },
2649 /* timedia_4006a */ { 1, { { 0, -1 }, } },
2650 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2651 /* timedia_4008a */ { 1, { { 0, 1 }, } },
2652 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2653 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
2654 /* SYBA uses fixed offsets in
2655 a 1K io window */
2656 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
2657 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
2658 /* titan_010l */ { 1, { { 3, -1 }, } },
2659 /* avlab_1p */ { 1, { { 0, 1}, } },
2660 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
2661 /* The Oxford Semi cards are unusual: 954 doesn't support ECP,
2662 * and 840 locks up if you write 1 to bit 2! */
2663 /* oxsemi_952 */ { 1, { { 0, 1 }, } },
2664 /* oxsemi_954 */ { 1, { { 0, -1 }, } },
2665 /* oxsemi_840 */ { 1, { { 0, 1 }, } },
2666 /* oxsemi_pcie_pport */ { 1, { { 0, 1 }, } },
2667 /* aks_0100 */ { 1, { { 0, -1 }, } },
2668 /* mobility_pp */ { 1, { { 0, 1 }, } },
2669 /* netmos_9900 */ { 1, { { 0, -1 }, } },
2670
2671 /* The netmos entries below are untested */
2672 /* netmos_9705 */ { 1, { { 0, -1 }, } },
2673 /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} },
2674 /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} },
2675 /* netmos_9805 */ { 1, { { 0, 1 }, } },
2676 /* netmos_9815 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2677 /* netmos_9901 */ { 1, { { 0, -1 }, } },
2678 /* netmos_9865 */ { 1, { { 0, -1 }, } },
2679 /* quatech_sppxp100 */ { 1, { { 0, 1 }, } },
2680 /* wch_ch382l */ { 1, { { 2, -1 }, } },
2681};
2682
2683static const struct pci_device_id parport_pc_pci_tbl[] = {
2684 /* Super-IO onboard chips */
2685 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
2686 { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 },
2687 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2688 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 },
2689
2690 /* PCI cards */
2691 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x,
2692 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
2693 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x,
2694 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
2695 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x,
2696 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
2697 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x,
2698 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
2699 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL,
2700 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
2701 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A,
2702 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
2703 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B,
2704 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
2705 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR,
2706 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
2707 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2708 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0, 0, plx_9050 },
2709 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
2710 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
2711 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
2712 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
2713 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
2714 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
2715 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
2716 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
2717 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
2718 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
2719 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L,
2720 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
2721 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
2722 /* AFAVLAB_TK9902 */
2723 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p},
2724 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p},
2725 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952PP,
2726 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_952 },
2727 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP,
2728 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
2729 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
2730 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
2731 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840,
2732 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2733 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840_G,
2734 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2735 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0,
2736 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2737 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0_G,
2738 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2739 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1,
2740 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2741 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_G,
2742 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2743 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_U,
2744 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2745 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU,
2746 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2747 { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
2748 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
2749 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
2750 /* NetMos communication controllers */
2751 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
2752 0xA000, 0x2000, 0, 0, netmos_9900 },
2753 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705,
2754 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 },
2755 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715,
2756 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 },
2757 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755,
2758 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 },
2759 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805,
2760 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 },
2761 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815,
2762 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 },
2763 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
2764 0xA000, 0x2000, 0, 0, netmos_9901 },
2765 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
2766 0xA000, 0x1000, 0, 0, netmos_9865 },
2767 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
2768 0xA000, 0x2000, 0, 0, netmos_9865 },
2769 /* Quatech SPPXP-100 Parallel port PCI ExpressCard */
2770 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SPPXP_100,
2771 PCI_ANY_ID, PCI_ANY_ID, 0, 0, quatech_sppxp100 },
2772 /* WCH CH382L PCI-E single parallel port card */
2773 { 0x1c00, 0x3050, 0x1c00, 0x3050, 0, 0, wch_ch382l },
2774 { 0, } /* terminate list */
2775};
2776MODULE_DEVICE_TABLE(pci, parport_pc_pci_tbl);
2777
2778struct pci_parport_data {
2779 int num;
2780 struct parport *ports[2];
2781};
2782
2783static int parport_pc_pci_probe(struct pci_dev *dev,
2784 const struct pci_device_id *id)
2785{
2786 int err, count, n, i = id->driver_data;
2787 struct pci_parport_data *data;
2788
2789 if (i < last_sio)
2790 /* This is an onboard Super-IO and has already been probed */
2791 return 0;
2792
2793 /* This is a PCI card */
2794 i -= last_sio;
2795 count = 0;
2796 err = pci_enable_device(dev);
2797 if (err)
2798 return err;
2799
2800 data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL);
2801 if (!data)
2802 return -ENOMEM;
2803
2804 if (cards[i].preinit_hook &&
2805 cards[i].preinit_hook(dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) {
2806 kfree(data);
2807 return -ENODEV;
2808 }
2809
2810 for (n = 0; n < cards[i].numports; n++) {
2811 int lo = cards[i].addr[n].lo;
2812 int hi = cards[i].addr[n].hi;
2813 int irq;
2814 unsigned long io_lo, io_hi;
2815 io_lo = pci_resource_start(dev, lo);
2816 io_hi = 0;
2817 if ((hi >= 0) && (hi <= 6))
2818 io_hi = pci_resource_start(dev, hi);
2819 else if (hi > 6)
2820 io_lo += hi; /* Reinterpret the meaning of
2821 "hi" as an offset (see SYBA
2822 def.) */
2823 /* TODO: test if sharing interrupts works */
2824 irq = dev->irq;
2825 if (irq == IRQ_NONE) {
2826 printk(KERN_DEBUG "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n",
2827 id->vendor, id->device, io_lo, io_hi);
2828 irq = PARPORT_IRQ_NONE;
2829 } else {
2830 printk(KERN_DEBUG "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n",
2831 id->vendor, id->device, io_lo, io_hi, irq);
2832 }
2833 data->ports[count] =
2834 parport_pc_probe_port(io_lo, io_hi, irq,
2835 PARPORT_DMA_NONE, &dev->dev,
2836 IRQF_SHARED);
2837 if (data->ports[count])
2838 count++;
2839 }
2840
2841 data->num = count;
2842
2843 if (cards[i].postinit_hook)
2844 cards[i].postinit_hook(dev, count == 0);
2845
2846 if (count) {
2847 pci_set_drvdata(dev, data);
2848 return 0;
2849 }
2850
2851 kfree(data);
2852
2853 return -ENODEV;
2854}
2855
2856static void parport_pc_pci_remove(struct pci_dev *dev)
2857{
2858 struct pci_parport_data *data = pci_get_drvdata(dev);
2859 int i;
2860
2861 if (data) {
2862 for (i = data->num - 1; i >= 0; i--)
2863 parport_pc_unregister_port(data->ports[i]);
2864
2865 kfree(data);
2866 }
2867}
2868
2869static struct pci_driver parport_pc_pci_driver = {
2870 .name = "parport_pc",
2871 .id_table = parport_pc_pci_tbl,
2872 .probe = parport_pc_pci_probe,
2873 .remove = parport_pc_pci_remove,
2874};
2875
2876static int __init parport_pc_init_superio(int autoirq, int autodma)
2877{
2878 const struct pci_device_id *id;
2879 struct pci_dev *pdev = NULL;
2880 int ret = 0;
2881
2882 for_each_pci_dev(pdev) {
2883 id = pci_match_id(parport_pc_pci_tbl, pdev);
2884 if (id == NULL || id->driver_data >= last_sio)
2885 continue;
2886
2887 if (parport_pc_superio_info[id->driver_data].probe(
2888 pdev, autoirq, autodma,
2889 parport_pc_superio_info[id->driver_data].via)) {
2890 ret++;
2891 }
2892 }
2893
2894 return ret; /* number of devices found */
2895}
2896#else
2897static struct pci_driver parport_pc_pci_driver;
2898static int __init parport_pc_init_superio(int autoirq, int autodma)
2899{
2900 return 0;
2901}
2902#endif /* CONFIG_PCI */
2903
2904#ifdef CONFIG_PNP
2905
2906static const struct pnp_device_id parport_pc_pnp_tbl[] = {
2907 /* Standard LPT Printer Port */
2908 {.id = "PNP0400", .driver_data = 0},
2909 /* ECP Printer Port */
2910 {.id = "PNP0401", .driver_data = 0},
2911 { }
2912};
2913
2914MODULE_DEVICE_TABLE(pnp, parport_pc_pnp_tbl);
2915
2916static int parport_pc_pnp_probe(struct pnp_dev *dev,
2917 const struct pnp_device_id *id)
2918{
2919 struct parport *pdata;
2920 unsigned long io_lo, io_hi;
2921 int dma, irq;
2922
2923 if (pnp_port_valid(dev, 0) &&
2924 !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED)) {
2925 io_lo = pnp_port_start(dev, 0);
2926 } else
2927 return -EINVAL;
2928
2929 if (pnp_port_valid(dev, 1) &&
2930 !(pnp_port_flags(dev, 1) & IORESOURCE_DISABLED)) {
2931 io_hi = pnp_port_start(dev, 1);
2932 } else
2933 io_hi = 0;
2934
2935 if (pnp_irq_valid(dev, 0) &&
2936 !(pnp_irq_flags(dev, 0) & IORESOURCE_DISABLED)) {
2937 irq = pnp_irq(dev, 0);
2938 } else
2939 irq = PARPORT_IRQ_NONE;
2940
2941 if (pnp_dma_valid(dev, 0) &&
2942 !(pnp_dma_flags(dev, 0) & IORESOURCE_DISABLED)) {
2943 dma = pnp_dma(dev, 0);
2944 } else
2945 dma = PARPORT_DMA_NONE;
2946
2947 dev_info(&dev->dev, "reported by %s\n", dev->protocol->name);
2948 pdata = parport_pc_probe_port(io_lo, io_hi, irq, dma, &dev->dev, 0);
2949 if (pdata == NULL)
2950 return -ENODEV;
2951
2952 pnp_set_drvdata(dev, pdata);
2953 return 0;
2954}
2955
2956static void parport_pc_pnp_remove(struct pnp_dev *dev)
2957{
2958 struct parport *pdata = (struct parport *)pnp_get_drvdata(dev);
2959 if (!pdata)
2960 return;
2961
2962 parport_pc_unregister_port(pdata);
2963}
2964
2965/* we only need the pnp layer to activate the device, at least for now */
2966static struct pnp_driver parport_pc_pnp_driver = {
2967 .name = "parport_pc",
2968 .id_table = parport_pc_pnp_tbl,
2969 .probe = parport_pc_pnp_probe,
2970 .remove = parport_pc_pnp_remove,
2971};
2972
2973#else
2974static struct pnp_driver parport_pc_pnp_driver;
2975#endif /* CONFIG_PNP */
2976
2977static int parport_pc_platform_probe(struct platform_device *pdev)
2978{
2979 /* Always succeed, the actual probing is done in
2980 * parport_pc_probe_port(). */
2981 return 0;
2982}
2983
2984static struct platform_driver parport_pc_platform_driver = {
2985 .driver = {
2986 .name = "parport_pc",
2987 },
2988 .probe = parport_pc_platform_probe,
2989};
2990
2991/* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */
2992static int __attribute__((unused))
2993parport_pc_find_isa_ports(int autoirq, int autodma)
2994{
2995 int count = 0;
2996
2997 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL, 0))
2998 count++;
2999 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL, 0))
3000 count++;
3001 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL, 0))
3002 count++;
3003
3004 return count;
3005}
3006
3007/* This function is called by parport_pc_init if the user didn't
3008 * specify any ports to probe. Its job is to find some ports. Order
3009 * is important here -- we want ISA ports to be registered first,
3010 * followed by PCI cards (for least surprise), but before that we want
3011 * to do chipset-specific tests for some onboard ports that we know
3012 * about.
3013 *
3014 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY
3015 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO
3016 */
3017static void __init parport_pc_find_ports(int autoirq, int autodma)
3018{
3019 int count = 0, err;
3020
3021#ifdef CONFIG_PARPORT_PC_SUPERIO
3022 detect_and_report_it87();
3023 detect_and_report_winbond();
3024 detect_and_report_smsc();
3025#endif
3026
3027 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */
3028 count += parport_pc_init_superio(autoirq, autodma);
3029
3030 /* PnP ports, skip detection if SuperIO already found them */
3031 if (!count) {
3032 err = pnp_register_driver(&parport_pc_pnp_driver);
3033 if (!err)
3034 pnp_registered_parport = 1;
3035 }
3036
3037 /* ISA ports and whatever (see asm/parport.h). */
3038 parport_pc_find_nonpci_ports(autoirq, autodma);
3039
3040 err = pci_register_driver(&parport_pc_pci_driver);
3041 if (!err)
3042 pci_registered_parport = 1;
3043}
3044
3045/*
3046 * Piles of crap below pretend to be a parser for module and kernel
3047 * parameters. Say "thank you" to whoever had come up with that
3048 * syntax and keep in mind that code below is a cleaned up version.
3049 */
3050
3051static int __initdata io[PARPORT_PC_MAX_PORTS+1] = {
3052 [0 ... PARPORT_PC_MAX_PORTS] = 0
3053};
3054static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] = {
3055 [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO
3056};
3057static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = {
3058 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE
3059};
3060static int __initdata irqval[PARPORT_PC_MAX_PORTS] = {
3061 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY
3062};
3063
3064static int __init parport_parse_param(const char *s, int *val,
3065 int automatic, int none, int nofifo)
3066{
3067 if (!s)
3068 return 0;
3069 if (!strncmp(s, "auto", 4))
3070 *val = automatic;
3071 else if (!strncmp(s, "none", 4))
3072 *val = none;
3073 else if (nofifo && !strncmp(s, "nofifo", 6))
3074 *val = nofifo;
3075 else {
3076 char *ep;
3077 unsigned long r = simple_strtoul(s, &ep, 0);
3078 if (ep != s)
3079 *val = r;
3080 else {
3081 pr_err("parport: bad specifier `%s'\n", s);
3082 return -1;
3083 }
3084 }
3085 return 0;
3086}
3087
3088static int __init parport_parse_irq(const char *irqstr, int *val)
3089{
3090 return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO,
3091 PARPORT_IRQ_NONE, 0);
3092}
3093
3094static int __init parport_parse_dma(const char *dmastr, int *val)
3095{
3096 return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO,
3097 PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO);
3098}
3099
3100#ifdef CONFIG_PCI
3101static int __init parport_init_mode_setup(char *str)
3102{
3103 printk(KERN_DEBUG "parport_pc.c: Specified parameter parport_init_mode=%s\n",
3104 str);
3105
3106 if (!strcmp(str, "spp"))
3107 parport_init_mode = 1;
3108 if (!strcmp(str, "ps2"))
3109 parport_init_mode = 2;
3110 if (!strcmp(str, "epp"))
3111 parport_init_mode = 3;
3112 if (!strcmp(str, "ecp"))
3113 parport_init_mode = 4;
3114 if (!strcmp(str, "ecpepp"))
3115 parport_init_mode = 5;
3116 return 1;
3117}
3118#endif
3119
3120#ifdef MODULE
3121static char *irq[PARPORT_PC_MAX_PORTS];
3122static char *dma[PARPORT_PC_MAX_PORTS];
3123
3124MODULE_PARM_DESC(io, "Base I/O address (SPP regs)");
3125module_param_hw_array(io, int, ioport, NULL, 0);
3126MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)");
3127module_param_hw_array(io_hi, int, ioport, NULL, 0);
3128MODULE_PARM_DESC(irq, "IRQ line");
3129module_param_hw_array(irq, charp, irq, NULL, 0);
3130MODULE_PARM_DESC(dma, "DMA channel");
3131module_param_hw_array(dma, charp, dma, NULL, 0);
3132#if defined(CONFIG_PARPORT_PC_SUPERIO) || \
3133 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
3134MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation");
3135module_param(verbose_probing, int, 0644);
3136#endif
3137#ifdef CONFIG_PCI
3138static char *init_mode;
3139MODULE_PARM_DESC(init_mode,
3140 "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)");
3141module_param(init_mode, charp, 0);
3142#endif
3143
3144static int __init parse_parport_params(void)
3145{
3146 unsigned int i;
3147 int val;
3148
3149#ifdef CONFIG_PCI
3150 if (init_mode)
3151 parport_init_mode_setup(init_mode);
3152#endif
3153
3154 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) {
3155 if (parport_parse_irq(irq[i], &val))
3156 return 1;
3157 irqval[i] = val;
3158 if (parport_parse_dma(dma[i], &val))
3159 return 1;
3160 dmaval[i] = val;
3161 }
3162 if (!io[0]) {
3163 /* The user can make us use any IRQs or DMAs we find. */
3164 if (irq[0] && !parport_parse_irq(irq[0], &val))
3165 switch (val) {
3166 case PARPORT_IRQ_NONE:
3167 case PARPORT_IRQ_AUTO:
3168 irqval[0] = val;
3169 break;
3170 default:
3171 pr_warn("parport_pc: irq specified without base address. Use 'io=' to specify one\n");
3172 }
3173
3174 if (dma[0] && !parport_parse_dma(dma[0], &val))
3175 switch (val) {
3176 case PARPORT_DMA_NONE:
3177 case PARPORT_DMA_AUTO:
3178 dmaval[0] = val;
3179 break;
3180 default:
3181 pr_warn("parport_pc: dma specified without base address. Use 'io=' to specify one\n");
3182 }
3183 }
3184 return 0;
3185}
3186
3187#else
3188
3189static int parport_setup_ptr __initdata;
3190
3191/*
3192 * Acceptable parameters:
3193 *
3194 * parport=0
3195 * parport=auto
3196 * parport=0xBASE[,IRQ[,DMA]]
3197 *
3198 * IRQ/DMA may be numeric or 'auto' or 'none'
3199 */
3200static int __init parport_setup(char *str)
3201{
3202 char *endptr;
3203 char *sep;
3204 int val;
3205
3206 if (!str || !*str || (*str == '0' && !*(str+1))) {
3207 /* Disable parport if "parport=0" in cmdline */
3208 io[0] = PARPORT_DISABLE;
3209 return 1;
3210 }
3211
3212 if (!strncmp(str, "auto", 4)) {
3213 irqval[0] = PARPORT_IRQ_AUTO;
3214 dmaval[0] = PARPORT_DMA_AUTO;
3215 return 1;
3216 }
3217
3218 val = simple_strtoul(str, &endptr, 0);
3219 if (endptr == str) {
3220 pr_warn("parport=%s not understood\n", str);
3221 return 1;
3222 }
3223
3224 if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) {
3225 pr_err("parport=%s ignored, too many ports\n", str);
3226 return 1;
3227 }
3228
3229 io[parport_setup_ptr] = val;
3230 irqval[parport_setup_ptr] = PARPORT_IRQ_NONE;
3231 dmaval[parport_setup_ptr] = PARPORT_DMA_NONE;
3232
3233 sep = strchr(str, ',');
3234 if (sep++) {
3235 if (parport_parse_irq(sep, &val))
3236 return 1;
3237 irqval[parport_setup_ptr] = val;
3238 sep = strchr(sep, ',');
3239 if (sep++) {
3240 if (parport_parse_dma(sep, &val))
3241 return 1;
3242 dmaval[parport_setup_ptr] = val;
3243 }
3244 }
3245 parport_setup_ptr++;
3246 return 1;
3247}
3248
3249static int __init parse_parport_params(void)
3250{
3251 return io[0] == PARPORT_DISABLE;
3252}
3253
3254__setup("parport=", parport_setup);
3255
3256/*
3257 * Acceptable parameters:
3258 *
3259 * parport_init_mode=[spp|ps2|epp|ecp|ecpepp]
3260 */
3261#ifdef CONFIG_PCI
3262__setup("parport_init_mode=", parport_init_mode_setup);
3263#endif
3264#endif
3265
3266/* "Parser" ends here */
3267
3268static int __init parport_pc_init(void)
3269{
3270 int err;
3271
3272 if (parse_parport_params())
3273 return -EINVAL;
3274
3275 err = platform_driver_register(&parport_pc_platform_driver);
3276 if (err)
3277 return err;
3278
3279 if (io[0]) {
3280 int i;
3281 /* Only probe the ports we were given. */
3282 user_specified = 1;
3283 for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) {
3284 if (!io[i])
3285 break;
3286 if (io_hi[i] == PARPORT_IOHI_AUTO)
3287 io_hi[i] = 0x400 + io[i];
3288 parport_pc_probe_port(io[i], io_hi[i],
3289 irqval[i], dmaval[i], NULL, 0);
3290 }
3291 } else
3292 parport_pc_find_ports(irqval[0], dmaval[0]);
3293
3294 return 0;
3295}
3296
3297static void __exit parport_pc_exit(void)
3298{
3299 if (pci_registered_parport)
3300 pci_unregister_driver(&parport_pc_pci_driver);
3301 if (pnp_registered_parport)
3302 pnp_unregister_driver(&parport_pc_pnp_driver);
3303 platform_driver_unregister(&parport_pc_platform_driver);
3304
3305 while (!list_empty(&ports_list)) {
3306 struct parport_pc_private *priv;
3307 struct parport *port;
3308 struct device *dev;
3309 priv = list_entry(ports_list.next,
3310 struct parport_pc_private, list);
3311 port = priv->port;
3312 dev = port->dev;
3313 parport_pc_unregister_port(port);
3314 if (dev && dev->bus == &platform_bus_type)
3315 platform_device_unregister(to_platform_device(dev));
3316 }
3317}
3318
3319MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
3320MODULE_DESCRIPTION("PC-style parallel port driver");
3321MODULE_LICENSE("GPL");
3322module_init(parport_pc_init)
3323module_exit(parport_pc_exit)