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1/* Low-level parallel-port routines for 8255-based PC-style hardware.
2 *
3 * Authors: Phil Blundell <philb@gnu.org>
4 * Tim Waugh <tim@cyberelk.demon.co.uk>
5 * Jose Renau <renau@acm.org>
6 * David Campbell
7 * Andrea Arcangeli
8 *
9 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell.
10 *
11 * Cleaned up include files - Russell King <linux@arm.uk.linux.org>
12 * DMA support - Bert De Jonghe <bert@sophis.be>
13 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999
14 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G.
15 * Various hacks, Fred Barnes, 04/2001
16 * Updated probing logic - Adam Belay <ambx1@neo.rr.com>
17 */
18
19/* This driver should work with any hardware that is broadly compatible
20 * with that in the IBM PC. This applies to the majority of integrated
21 * I/O chipsets that are commonly available. The expected register
22 * layout is:
23 *
24 * base+0 data
25 * base+1 status
26 * base+2 control
27 *
28 * In addition, there are some optional registers:
29 *
30 * base+3 EPP address
31 * base+4 EPP data
32 * base+0x400 ECP config A
33 * base+0x401 ECP config B
34 * base+0x402 ECP control
35 *
36 * All registers are 8 bits wide and read/write. If your hardware differs
37 * only in register addresses (eg because your registers are on 32-bit
38 * word boundaries) then you can alter the constants in parport_pc.h to
39 * accommodate this.
40 *
41 * Note that the ECP registers may not start at offset 0x400 for PCI cards,
42 * but rather will start at port->base_hi.
43 */
44
45#include <linux/module.h>
46#include <linux/init.h>
47#include <linux/sched.h>
48#include <linux/delay.h>
49#include <linux/errno.h>
50#include <linux/interrupt.h>
51#include <linux/ioport.h>
52#include <linux/kernel.h>
53#include <linux/slab.h>
54#include <linux/dma-mapping.h>
55#include <linux/pci.h>
56#include <linux/pnp.h>
57#include <linux/platform_device.h>
58#include <linux/sysctl.h>
59#include <linux/io.h>
60#include <linux/uaccess.h>
61
62#include <asm/dma.h>
63
64#include <linux/parport.h>
65#include <linux/parport_pc.h>
66#include <linux/via.h>
67#include <asm/parport.h>
68
69#define PARPORT_PC_MAX_PORTS PARPORT_MAX
70
71#ifdef CONFIG_ISA_DMA_API
72#define HAS_DMA
73#endif
74
75/* ECR modes */
76#define ECR_SPP 00
77#define ECR_PS2 01
78#define ECR_PPF 02
79#define ECR_ECP 03
80#define ECR_EPP 04
81#define ECR_VND 05
82#define ECR_TST 06
83#define ECR_CNF 07
84#define ECR_MODE_MASK 0xe0
85#define ECR_WRITE(p, v) frob_econtrol((p), 0xff, (v))
86
87#undef DEBUG
88
89#ifdef DEBUG
90#define DPRINTK printk
91#else
92#define DPRINTK(stuff...)
93#endif
94
95
96#define NR_SUPERIOS 3
97static struct superio_struct { /* For Super-IO chips autodetection */
98 int io;
99 int irq;
100 int dma;
101} superios[NR_SUPERIOS] = { {0,},};
102
103static int user_specified;
104#if defined(CONFIG_PARPORT_PC_SUPERIO) || \
105 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
106static int verbose_probing;
107#endif
108static int pci_registered_parport;
109static int pnp_registered_parport;
110
111/* frob_control, but for ECR */
112static void frob_econtrol(struct parport *pb, unsigned char m,
113 unsigned char v)
114{
115 unsigned char ectr = 0;
116
117 if (m != 0xff)
118 ectr = inb(ECONTROL(pb));
119
120 DPRINTK(KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n",
121 m, v, ectr, (ectr & ~m) ^ v);
122
123 outb((ectr & ~m) ^ v, ECONTROL(pb));
124}
125
126static inline void frob_set_mode(struct parport *p, int mode)
127{
128 frob_econtrol(p, ECR_MODE_MASK, mode << 5);
129}
130
131#ifdef CONFIG_PARPORT_PC_FIFO
132/* Safely change the mode bits in the ECR
133 Returns:
134 0 : Success
135 -EBUSY: Could not drain FIFO in some finite amount of time,
136 mode not changed!
137 */
138static int change_mode(struct parport *p, int m)
139{
140 const struct parport_pc_private *priv = p->physport->private_data;
141 unsigned char oecr;
142 int mode;
143
144 DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n", m);
145
146 if (!priv->ecr) {
147 printk(KERN_DEBUG "change_mode: but there's no ECR!\n");
148 return 0;
149 }
150
151 /* Bits <7:5> contain the mode. */
152 oecr = inb(ECONTROL(p));
153 mode = (oecr >> 5) & 0x7;
154 if (mode == m)
155 return 0;
156
157 if (mode >= 2 && !(priv->ctr & 0x20)) {
158 /* This mode resets the FIFO, so we may
159 * have to wait for it to drain first. */
160 unsigned long expire = jiffies + p->physport->cad->timeout;
161 int counter;
162 switch (mode) {
163 case ECR_PPF: /* Parallel Port FIFO mode */
164 case ECR_ECP: /* ECP Parallel Port mode */
165 /* Busy wait for 200us */
166 for (counter = 0; counter < 40; counter++) {
167 if (inb(ECONTROL(p)) & 0x01)
168 break;
169 if (signal_pending(current))
170 break;
171 udelay(5);
172 }
173
174 /* Poll slowly. */
175 while (!(inb(ECONTROL(p)) & 0x01)) {
176 if (time_after_eq(jiffies, expire))
177 /* The FIFO is stuck. */
178 return -EBUSY;
179 schedule_timeout_interruptible(
180 msecs_to_jiffies(10));
181 if (signal_pending(current))
182 break;
183 }
184 }
185 }
186
187 if (mode >= 2 && m >= 2) {
188 /* We have to go through mode 001 */
189 oecr &= ~(7 << 5);
190 oecr |= ECR_PS2 << 5;
191 ECR_WRITE(p, oecr);
192 }
193
194 /* Set the mode. */
195 oecr &= ~(7 << 5);
196 oecr |= m << 5;
197 ECR_WRITE(p, oecr);
198 return 0;
199}
200
201#ifdef CONFIG_PARPORT_1284
202/* Find FIFO lossage; FIFO is reset */
203#if 0
204static int get_fifo_residue(struct parport *p)
205{
206 int residue;
207 int cnfga;
208 const struct parport_pc_private *priv = p->physport->private_data;
209
210 /* Adjust for the contents of the FIFO. */
211 for (residue = priv->fifo_depth; ; residue--) {
212 if (inb(ECONTROL(p)) & 0x2)
213 /* Full up. */
214 break;
215
216 outb(0, FIFO(p));
217 }
218
219 printk(KERN_DEBUG "%s: %d PWords were left in FIFO\n", p->name,
220 residue);
221
222 /* Reset the FIFO. */
223 frob_set_mode(p, ECR_PS2);
224
225 /* Now change to config mode and clean up. FIXME */
226 frob_set_mode(p, ECR_CNF);
227 cnfga = inb(CONFIGA(p));
228 printk(KERN_DEBUG "%s: cnfgA contains 0x%02x\n", p->name, cnfga);
229
230 if (!(cnfga & (1<<2))) {
231 printk(KERN_DEBUG "%s: Accounting for extra byte\n", p->name);
232 residue++;
233 }
234
235 /* Don't care about partial PWords until support is added for
236 * PWord != 1 byte. */
237
238 /* Back to PS2 mode. */
239 frob_set_mode(p, ECR_PS2);
240
241 DPRINTK(KERN_DEBUG
242 "*** get_fifo_residue: done residue collecting (ecr = 0x%2.2x)\n",
243 inb(ECONTROL(p)));
244 return residue;
245}
246#endif /* 0 */
247#endif /* IEEE 1284 support */
248#endif /* FIFO support */
249
250/*
251 * Clear TIMEOUT BIT in EPP MODE
252 *
253 * This is also used in SPP detection.
254 */
255static int clear_epp_timeout(struct parport *pb)
256{
257 unsigned char r;
258
259 if (!(parport_pc_read_status(pb) & 0x01))
260 return 1;
261
262 /* To clear timeout some chips require double read */
263 parport_pc_read_status(pb);
264 r = parport_pc_read_status(pb);
265 outb(r | 0x01, STATUS(pb)); /* Some reset by writing 1 */
266 outb(r & 0xfe, STATUS(pb)); /* Others by writing 0 */
267 r = parport_pc_read_status(pb);
268
269 return !(r & 0x01);
270}
271
272/*
273 * Access functions.
274 *
275 * Most of these aren't static because they may be used by the
276 * parport_xxx_yyy macros. extern __inline__ versions of several
277 * of these are in parport_pc.h.
278 */
279
280static void parport_pc_init_state(struct pardevice *dev,
281 struct parport_state *s)
282{
283 s->u.pc.ctr = 0xc;
284 if (dev->irq_func &&
285 dev->port->irq != PARPORT_IRQ_NONE)
286 /* Set ackIntEn */
287 s->u.pc.ctr |= 0x10;
288
289 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24;
290 * D.Gruszka VScom */
291}
292
293static void parport_pc_save_state(struct parport *p, struct parport_state *s)
294{
295 const struct parport_pc_private *priv = p->physport->private_data;
296 s->u.pc.ctr = priv->ctr;
297 if (priv->ecr)
298 s->u.pc.ecr = inb(ECONTROL(p));
299}
300
301static void parport_pc_restore_state(struct parport *p,
302 struct parport_state *s)
303{
304 struct parport_pc_private *priv = p->physport->private_data;
305 register unsigned char c = s->u.pc.ctr & priv->ctr_writable;
306 outb(c, CONTROL(p));
307 priv->ctr = c;
308 if (priv->ecr)
309 ECR_WRITE(p, s->u.pc.ecr);
310}
311
312#ifdef CONFIG_PARPORT_1284
313static size_t parport_pc_epp_read_data(struct parport *port, void *buf,
314 size_t length, int flags)
315{
316 size_t got = 0;
317
318 if (flags & PARPORT_W91284PIC) {
319 unsigned char status;
320 size_t left = length;
321
322 /* use knowledge about data lines..:
323 * nFault is 0 if there is at least 1 byte in the Warp's FIFO
324 * pError is 1 if there are 16 bytes in the Warp's FIFO
325 */
326 status = inb(STATUS(port));
327
328 while (!(status & 0x08) && got < length) {
329 if (left >= 16 && (status & 0x20) && !(status & 0x08)) {
330 /* can grab 16 bytes from warp fifo */
331 if (!((long)buf & 0x03))
332 insl(EPPDATA(port), buf, 4);
333 else
334 insb(EPPDATA(port), buf, 16);
335 buf += 16;
336 got += 16;
337 left -= 16;
338 } else {
339 /* grab single byte from the warp fifo */
340 *((char *)buf) = inb(EPPDATA(port));
341 buf++;
342 got++;
343 left--;
344 }
345 status = inb(STATUS(port));
346 if (status & 0x01) {
347 /* EPP timeout should never occur... */
348 printk(KERN_DEBUG
349"%s: EPP timeout occurred while talking to w91284pic (should not have done)\n", port->name);
350 clear_epp_timeout(port);
351 }
352 }
353 return got;
354 }
355 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
356 if (!(((long)buf | length) & 0x03))
357 insl(EPPDATA(port), buf, (length >> 2));
358 else
359 insb(EPPDATA(port), buf, length);
360 if (inb(STATUS(port)) & 0x01) {
361 clear_epp_timeout(port);
362 return -EIO;
363 }
364 return length;
365 }
366 for (; got < length; got++) {
367 *((char *)buf) = inb(EPPDATA(port));
368 buf++;
369 if (inb(STATUS(port)) & 0x01) {
370 /* EPP timeout */
371 clear_epp_timeout(port);
372 break;
373 }
374 }
375
376 return got;
377}
378
379static size_t parport_pc_epp_write_data(struct parport *port, const void *buf,
380 size_t length, int flags)
381{
382 size_t written = 0;
383
384 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
385 if (!(((long)buf | length) & 0x03))
386 outsl(EPPDATA(port), buf, (length >> 2));
387 else
388 outsb(EPPDATA(port), buf, length);
389 if (inb(STATUS(port)) & 0x01) {
390 clear_epp_timeout(port);
391 return -EIO;
392 }
393 return length;
394 }
395 for (; written < length; written++) {
396 outb(*((char *)buf), EPPDATA(port));
397 buf++;
398 if (inb(STATUS(port)) & 0x01) {
399 clear_epp_timeout(port);
400 break;
401 }
402 }
403
404 return written;
405}
406
407static size_t parport_pc_epp_read_addr(struct parport *port, void *buf,
408 size_t length, int flags)
409{
410 size_t got = 0;
411
412 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
413 insb(EPPADDR(port), buf, length);
414 if (inb(STATUS(port)) & 0x01) {
415 clear_epp_timeout(port);
416 return -EIO;
417 }
418 return length;
419 }
420 for (; got < length; got++) {
421 *((char *)buf) = inb(EPPADDR(port));
422 buf++;
423 if (inb(STATUS(port)) & 0x01) {
424 clear_epp_timeout(port);
425 break;
426 }
427 }
428
429 return got;
430}
431
432static size_t parport_pc_epp_write_addr(struct parport *port,
433 const void *buf, size_t length,
434 int flags)
435{
436 size_t written = 0;
437
438 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
439 outsb(EPPADDR(port), buf, length);
440 if (inb(STATUS(port)) & 0x01) {
441 clear_epp_timeout(port);
442 return -EIO;
443 }
444 return length;
445 }
446 for (; written < length; written++) {
447 outb(*((char *)buf), EPPADDR(port));
448 buf++;
449 if (inb(STATUS(port)) & 0x01) {
450 clear_epp_timeout(port);
451 break;
452 }
453 }
454
455 return written;
456}
457
458static size_t parport_pc_ecpepp_read_data(struct parport *port, void *buf,
459 size_t length, int flags)
460{
461 size_t got;
462
463 frob_set_mode(port, ECR_EPP);
464 parport_pc_data_reverse(port);
465 parport_pc_write_control(port, 0x4);
466 got = parport_pc_epp_read_data(port, buf, length, flags);
467 frob_set_mode(port, ECR_PS2);
468
469 return got;
470}
471
472static size_t parport_pc_ecpepp_write_data(struct parport *port,
473 const void *buf, size_t length,
474 int flags)
475{
476 size_t written;
477
478 frob_set_mode(port, ECR_EPP);
479 parport_pc_write_control(port, 0x4);
480 parport_pc_data_forward(port);
481 written = parport_pc_epp_write_data(port, buf, length, flags);
482 frob_set_mode(port, ECR_PS2);
483
484 return written;
485}
486
487static size_t parport_pc_ecpepp_read_addr(struct parport *port, void *buf,
488 size_t length, int flags)
489{
490 size_t got;
491
492 frob_set_mode(port, ECR_EPP);
493 parport_pc_data_reverse(port);
494 parport_pc_write_control(port, 0x4);
495 got = parport_pc_epp_read_addr(port, buf, length, flags);
496 frob_set_mode(port, ECR_PS2);
497
498 return got;
499}
500
501static size_t parport_pc_ecpepp_write_addr(struct parport *port,
502 const void *buf, size_t length,
503 int flags)
504{
505 size_t written;
506
507 frob_set_mode(port, ECR_EPP);
508 parport_pc_write_control(port, 0x4);
509 parport_pc_data_forward(port);
510 written = parport_pc_epp_write_addr(port, buf, length, flags);
511 frob_set_mode(port, ECR_PS2);
512
513 return written;
514}
515#endif /* IEEE 1284 support */
516
517#ifdef CONFIG_PARPORT_PC_FIFO
518static size_t parport_pc_fifo_write_block_pio(struct parport *port,
519 const void *buf, size_t length)
520{
521 int ret = 0;
522 const unsigned char *bufp = buf;
523 size_t left = length;
524 unsigned long expire = jiffies + port->physport->cad->timeout;
525 const int fifo = FIFO(port);
526 int poll_for = 8; /* 80 usecs */
527 const struct parport_pc_private *priv = port->physport->private_data;
528 const int fifo_depth = priv->fifo_depth;
529
530 port = port->physport;
531
532 /* We don't want to be interrupted every character. */
533 parport_pc_disable_irq(port);
534 /* set nErrIntrEn and serviceIntr */
535 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
536
537 /* Forward mode. */
538 parport_pc_data_forward(port); /* Must be in PS2 mode */
539
540 while (left) {
541 unsigned char byte;
542 unsigned char ecrval = inb(ECONTROL(port));
543 int i = 0;
544
545 if (need_resched() && time_before(jiffies, expire))
546 /* Can't yield the port. */
547 schedule();
548
549 /* Anyone else waiting for the port? */
550 if (port->waithead) {
551 printk(KERN_DEBUG "Somebody wants the port\n");
552 break;
553 }
554
555 if (ecrval & 0x02) {
556 /* FIFO is full. Wait for interrupt. */
557
558 /* Clear serviceIntr */
559 ECR_WRITE(port, ecrval & ~(1<<2));
560false_alarm:
561 ret = parport_wait_event(port, HZ);
562 if (ret < 0)
563 break;
564 ret = 0;
565 if (!time_before(jiffies, expire)) {
566 /* Timed out. */
567 printk(KERN_DEBUG "FIFO write timed out\n");
568 break;
569 }
570 ecrval = inb(ECONTROL(port));
571 if (!(ecrval & (1<<2))) {
572 if (need_resched() &&
573 time_before(jiffies, expire))
574 schedule();
575
576 goto false_alarm;
577 }
578
579 continue;
580 }
581
582 /* Can't fail now. */
583 expire = jiffies + port->cad->timeout;
584
585poll:
586 if (signal_pending(current))
587 break;
588
589 if (ecrval & 0x01) {
590 /* FIFO is empty. Blast it full. */
591 const int n = left < fifo_depth ? left : fifo_depth;
592 outsb(fifo, bufp, n);
593 bufp += n;
594 left -= n;
595
596 /* Adjust the poll time. */
597 if (i < (poll_for - 2))
598 poll_for--;
599 continue;
600 } else if (i++ < poll_for) {
601 udelay(10);
602 ecrval = inb(ECONTROL(port));
603 goto poll;
604 }
605
606 /* Half-full(call me an optimist) */
607 byte = *bufp++;
608 outb(byte, fifo);
609 left--;
610 }
611 dump_parport_state("leave fifo_write_block_pio", port);
612 return length - left;
613}
614
615#ifdef HAS_DMA
616static size_t parport_pc_fifo_write_block_dma(struct parport *port,
617 const void *buf, size_t length)
618{
619 int ret = 0;
620 unsigned long dmaflag;
621 size_t left = length;
622 const struct parport_pc_private *priv = port->physport->private_data;
623 struct device *dev = port->physport->dev;
624 dma_addr_t dma_addr, dma_handle;
625 size_t maxlen = 0x10000; /* max 64k per DMA transfer */
626 unsigned long start = (unsigned long) buf;
627 unsigned long end = (unsigned long) buf + length - 1;
628
629 dump_parport_state("enter fifo_write_block_dma", port);
630 if (end < MAX_DMA_ADDRESS) {
631 /* If it would cross a 64k boundary, cap it at the end. */
632 if ((start ^ end) & ~0xffffUL)
633 maxlen = 0x10000 - (start & 0xffff);
634
635 dma_addr = dma_handle = dma_map_single(dev, (void *)buf, length,
636 DMA_TO_DEVICE);
637 } else {
638 /* above 16 MB we use a bounce buffer as ISA-DMA
639 is not possible */
640 maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */
641 dma_addr = priv->dma_handle;
642 dma_handle = 0;
643 }
644
645 port = port->physport;
646
647 /* We don't want to be interrupted every character. */
648 parport_pc_disable_irq(port);
649 /* set nErrIntrEn and serviceIntr */
650 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
651
652 /* Forward mode. */
653 parport_pc_data_forward(port); /* Must be in PS2 mode */
654
655 while (left) {
656 unsigned long expire = jiffies + port->physport->cad->timeout;
657
658 size_t count = left;
659
660 if (count > maxlen)
661 count = maxlen;
662
663 if (!dma_handle) /* bounce buffer ! */
664 memcpy(priv->dma_buf, buf, count);
665
666 dmaflag = claim_dma_lock();
667 disable_dma(port->dma);
668 clear_dma_ff(port->dma);
669 set_dma_mode(port->dma, DMA_MODE_WRITE);
670 set_dma_addr(port->dma, dma_addr);
671 set_dma_count(port->dma, count);
672
673 /* Set DMA mode */
674 frob_econtrol(port, 1<<3, 1<<3);
675
676 /* Clear serviceIntr */
677 frob_econtrol(port, 1<<2, 0);
678
679 enable_dma(port->dma);
680 release_dma_lock(dmaflag);
681
682 /* assume DMA will be successful */
683 left -= count;
684 buf += count;
685 if (dma_handle)
686 dma_addr += count;
687
688 /* Wait for interrupt. */
689false_alarm:
690 ret = parport_wait_event(port, HZ);
691 if (ret < 0)
692 break;
693 ret = 0;
694 if (!time_before(jiffies, expire)) {
695 /* Timed out. */
696 printk(KERN_DEBUG "DMA write timed out\n");
697 break;
698 }
699 /* Is serviceIntr set? */
700 if (!(inb(ECONTROL(port)) & (1<<2))) {
701 cond_resched();
702
703 goto false_alarm;
704 }
705
706 dmaflag = claim_dma_lock();
707 disable_dma(port->dma);
708 clear_dma_ff(port->dma);
709 count = get_dma_residue(port->dma);
710 release_dma_lock(dmaflag);
711
712 cond_resched(); /* Can't yield the port. */
713
714 /* Anyone else waiting for the port? */
715 if (port->waithead) {
716 printk(KERN_DEBUG "Somebody wants the port\n");
717 break;
718 }
719
720 /* update for possible DMA residue ! */
721 buf -= count;
722 left += count;
723 if (dma_handle)
724 dma_addr -= count;
725 }
726
727 /* Maybe got here through break, so adjust for DMA residue! */
728 dmaflag = claim_dma_lock();
729 disable_dma(port->dma);
730 clear_dma_ff(port->dma);
731 left += get_dma_residue(port->dma);
732 release_dma_lock(dmaflag);
733
734 /* Turn off DMA mode */
735 frob_econtrol(port, 1<<3, 0);
736
737 if (dma_handle)
738 dma_unmap_single(dev, dma_handle, length, DMA_TO_DEVICE);
739
740 dump_parport_state("leave fifo_write_block_dma", port);
741 return length - left;
742}
743#endif
744
745static inline size_t parport_pc_fifo_write_block(struct parport *port,
746 const void *buf, size_t length)
747{
748#ifdef HAS_DMA
749 if (port->dma != PARPORT_DMA_NONE)
750 return parport_pc_fifo_write_block_dma(port, buf, length);
751#endif
752 return parport_pc_fifo_write_block_pio(port, buf, length);
753}
754
755/* Parallel Port FIFO mode (ECP chipsets) */
756static size_t parport_pc_compat_write_block_pio(struct parport *port,
757 const void *buf, size_t length,
758 int flags)
759{
760 size_t written;
761 int r;
762 unsigned long expire;
763 const struct parport_pc_private *priv = port->physport->private_data;
764
765 /* Special case: a timeout of zero means we cannot call schedule().
766 * Also if O_NONBLOCK is set then use the default implementation. */
767 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
768 return parport_ieee1284_write_compat(port, buf,
769 length, flags);
770
771 /* Set up parallel port FIFO mode.*/
772 parport_pc_data_forward(port); /* Must be in PS2 mode */
773 parport_pc_frob_control(port, PARPORT_CONTROL_STROBE, 0);
774 r = change_mode(port, ECR_PPF); /* Parallel port FIFO */
775 if (r)
776 printk(KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n",
777 port->name);
778
779 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
780
781 /* Write the data to the FIFO. */
782 written = parport_pc_fifo_write_block(port, buf, length);
783
784 /* Finish up. */
785 /* For some hardware we don't want to touch the mode until
786 * the FIFO is empty, so allow 4 seconds for each position
787 * in the fifo.
788 */
789 expire = jiffies + (priv->fifo_depth * HZ * 4);
790 do {
791 /* Wait for the FIFO to empty */
792 r = change_mode(port, ECR_PS2);
793 if (r != -EBUSY)
794 break;
795 } while (time_before(jiffies, expire));
796 if (r == -EBUSY) {
797
798 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
799
800 /* Prevent further data transfer. */
801 frob_set_mode(port, ECR_TST);
802
803 /* Adjust for the contents of the FIFO. */
804 for (written -= priv->fifo_depth; ; written++) {
805 if (inb(ECONTROL(port)) & 0x2) {
806 /* Full up. */
807 break;
808 }
809 outb(0, FIFO(port));
810 }
811
812 /* Reset the FIFO and return to PS2 mode. */
813 frob_set_mode(port, ECR_PS2);
814 }
815
816 r = parport_wait_peripheral(port,
817 PARPORT_STATUS_BUSY,
818 PARPORT_STATUS_BUSY);
819 if (r)
820 printk(KERN_DEBUG
821 "%s: BUSY timeout (%d) in compat_write_block_pio\n",
822 port->name, r);
823
824 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
825
826 return written;
827}
828
829/* ECP */
830#ifdef CONFIG_PARPORT_1284
831static size_t parport_pc_ecp_write_block_pio(struct parport *port,
832 const void *buf, size_t length,
833 int flags)
834{
835 size_t written;
836 int r;
837 unsigned long expire;
838 const struct parport_pc_private *priv = port->physport->private_data;
839
840 /* Special case: a timeout of zero means we cannot call schedule().
841 * Also if O_NONBLOCK is set then use the default implementation. */
842 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
843 return parport_ieee1284_ecp_write_data(port, buf,
844 length, flags);
845
846 /* Switch to forward mode if necessary. */
847 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
848 /* Event 47: Set nInit high. */
849 parport_frob_control(port,
850 PARPORT_CONTROL_INIT
851 | PARPORT_CONTROL_AUTOFD,
852 PARPORT_CONTROL_INIT
853 | PARPORT_CONTROL_AUTOFD);
854
855 /* Event 49: PError goes high. */
856 r = parport_wait_peripheral(port,
857 PARPORT_STATUS_PAPEROUT,
858 PARPORT_STATUS_PAPEROUT);
859 if (r) {
860 printk(KERN_DEBUG "%s: PError timeout (%d) "
861 "in ecp_write_block_pio\n", port->name, r);
862 }
863 }
864
865 /* Set up ECP parallel port mode.*/
866 parport_pc_data_forward(port); /* Must be in PS2 mode */
867 parport_pc_frob_control(port,
868 PARPORT_CONTROL_STROBE |
869 PARPORT_CONTROL_AUTOFD,
870 0);
871 r = change_mode(port, ECR_ECP); /* ECP FIFO */
872 if (r)
873 printk(KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n",
874 port->name);
875 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
876
877 /* Write the data to the FIFO. */
878 written = parport_pc_fifo_write_block(port, buf, length);
879
880 /* Finish up. */
881 /* For some hardware we don't want to touch the mode until
882 * the FIFO is empty, so allow 4 seconds for each position
883 * in the fifo.
884 */
885 expire = jiffies + (priv->fifo_depth * (HZ * 4));
886 do {
887 /* Wait for the FIFO to empty */
888 r = change_mode(port, ECR_PS2);
889 if (r != -EBUSY)
890 break;
891 } while (time_before(jiffies, expire));
892 if (r == -EBUSY) {
893
894 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
895
896 /* Prevent further data transfer. */
897 frob_set_mode(port, ECR_TST);
898
899 /* Adjust for the contents of the FIFO. */
900 for (written -= priv->fifo_depth; ; written++) {
901 if (inb(ECONTROL(port)) & 0x2) {
902 /* Full up. */
903 break;
904 }
905 outb(0, FIFO(port));
906 }
907
908 /* Reset the FIFO and return to PS2 mode. */
909 frob_set_mode(port, ECR_PS2);
910
911 /* Host transfer recovery. */
912 parport_pc_data_reverse(port); /* Must be in PS2 mode */
913 udelay(5);
914 parport_frob_control(port, PARPORT_CONTROL_INIT, 0);
915 r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0);
916 if (r)
917 printk(KERN_DEBUG "%s: PE,1 timeout (%d) "
918 "in ecp_write_block_pio\n", port->name, r);
919
920 parport_frob_control(port,
921 PARPORT_CONTROL_INIT,
922 PARPORT_CONTROL_INIT);
923 r = parport_wait_peripheral(port,
924 PARPORT_STATUS_PAPEROUT,
925 PARPORT_STATUS_PAPEROUT);
926 if (r)
927 printk(KERN_DEBUG "%s: PE,2 timeout (%d) "
928 "in ecp_write_block_pio\n", port->name, r);
929 }
930
931 r = parport_wait_peripheral(port,
932 PARPORT_STATUS_BUSY,
933 PARPORT_STATUS_BUSY);
934 if (r)
935 printk(KERN_DEBUG
936 "%s: BUSY timeout (%d) in ecp_write_block_pio\n",
937 port->name, r);
938
939 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
940
941 return written;
942}
943
944#if 0
945static size_t parport_pc_ecp_read_block_pio(struct parport *port,
946 void *buf, size_t length,
947 int flags)
948{
949 size_t left = length;
950 size_t fifofull;
951 int r;
952 const int fifo = FIFO(port);
953 const struct parport_pc_private *priv = port->physport->private_data;
954 const int fifo_depth = priv->fifo_depth;
955 char *bufp = buf;
956
957 port = port->physport;
958 DPRINTK(KERN_DEBUG "parport_pc: parport_pc_ecp_read_block_pio\n");
959 dump_parport_state("enter fcn", port);
960
961 /* Special case: a timeout of zero means we cannot call schedule().
962 * Also if O_NONBLOCK is set then use the default implementation. */
963 if (port->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
964 return parport_ieee1284_ecp_read_data(port, buf,
965 length, flags);
966
967 if (port->ieee1284.mode == IEEE1284_MODE_ECPRLE) {
968 /* If the peripheral is allowed to send RLE compressed
969 * data, it is possible for a byte to expand to 128
970 * bytes in the FIFO. */
971 fifofull = 128;
972 } else {
973 fifofull = fifo_depth;
974 }
975
976 /* If the caller wants less than a full FIFO's worth of data,
977 * go through software emulation. Otherwise we may have to throw
978 * away data. */
979 if (length < fifofull)
980 return parport_ieee1284_ecp_read_data(port, buf,
981 length, flags);
982
983 if (port->ieee1284.phase != IEEE1284_PH_REV_IDLE) {
984 /* change to reverse-idle phase (must be in forward-idle) */
985
986 /* Event 38: Set nAutoFd low (also make sure nStrobe is high) */
987 parport_frob_control(port,
988 PARPORT_CONTROL_AUTOFD
989 | PARPORT_CONTROL_STROBE,
990 PARPORT_CONTROL_AUTOFD);
991 parport_pc_data_reverse(port); /* Must be in PS2 mode */
992 udelay(5);
993 /* Event 39: Set nInit low to initiate bus reversal */
994 parport_frob_control(port,
995 PARPORT_CONTROL_INIT,
996 0);
997 /* Event 40: Wait for nAckReverse (PError) to go low */
998 r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0);
999 if (r) {
1000 printk(KERN_DEBUG "%s: PE timeout Event 40 (%d) "
1001 "in ecp_read_block_pio\n", port->name, r);
1002 return 0;
1003 }
1004 }
1005
1006 /* Set up ECP FIFO mode.*/
1007/* parport_pc_frob_control(port,
1008 PARPORT_CONTROL_STROBE |
1009 PARPORT_CONTROL_AUTOFD,
1010 PARPORT_CONTROL_AUTOFD); */
1011 r = change_mode(port, ECR_ECP); /* ECP FIFO */
1012 if (r)
1013 printk(KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n",
1014 port->name);
1015
1016 port->ieee1284.phase = IEEE1284_PH_REV_DATA;
1017
1018 /* the first byte must be collected manually */
1019 dump_parport_state("pre 43", port);
1020 /* Event 43: Wait for nAck to go low */
1021 r = parport_wait_peripheral(port, PARPORT_STATUS_ACK, 0);
1022 if (r) {
1023 /* timed out while reading -- no data */
1024 printk(KERN_DEBUG "PIO read timed out (initial byte)\n");
1025 goto out_no_data;
1026 }
1027 /* read byte */
1028 *bufp++ = inb(DATA(port));
1029 left--;
1030 dump_parport_state("43-44", port);
1031 /* Event 44: nAutoFd (HostAck) goes high to acknowledge */
1032 parport_pc_frob_control(port,
1033 PARPORT_CONTROL_AUTOFD,
1034 0);
1035 dump_parport_state("pre 45", port);
1036 /* Event 45: Wait for nAck to go high */
1037 /* r = parport_wait_peripheral(port, PARPORT_STATUS_ACK,
1038 PARPORT_STATUS_ACK); */
1039 dump_parport_state("post 45", port);
1040 r = 0;
1041 if (r) {
1042 /* timed out while waiting for peripheral to respond to ack */
1043 printk(KERN_DEBUG "ECP PIO read timed out (waiting for nAck)\n");
1044
1045 /* keep hold of the byte we've got already */
1046 goto out_no_data;
1047 }
1048 /* Event 46: nAutoFd (HostAck) goes low to accept more data */
1049 parport_pc_frob_control(port,
1050 PARPORT_CONTROL_AUTOFD,
1051 PARPORT_CONTROL_AUTOFD);
1052
1053
1054 dump_parport_state("rev idle", port);
1055 /* Do the transfer. */
1056 while (left > fifofull) {
1057 int ret;
1058 unsigned long expire = jiffies + port->cad->timeout;
1059 unsigned char ecrval = inb(ECONTROL(port));
1060
1061 if (need_resched() && time_before(jiffies, expire))
1062 /* Can't yield the port. */
1063 schedule();
1064
1065 /* At this point, the FIFO may already be full. In
1066 * that case ECP is already holding back the
1067 * peripheral (assuming proper design) with a delayed
1068 * handshake. Work fast to avoid a peripheral
1069 * timeout. */
1070
1071 if (ecrval & 0x01) {
1072 /* FIFO is empty. Wait for interrupt. */
1073 dump_parport_state("FIFO empty", port);
1074
1075 /* Anyone else waiting for the port? */
1076 if (port->waithead) {
1077 printk(KERN_DEBUG "Somebody wants the port\n");
1078 break;
1079 }
1080
1081 /* Clear serviceIntr */
1082 ECR_WRITE(port, ecrval & ~(1<<2));
1083false_alarm:
1084 dump_parport_state("waiting", port);
1085 ret = parport_wait_event(port, HZ);
1086 DPRINTK(KERN_DEBUG "parport_wait_event returned %d\n",
1087 ret);
1088 if (ret < 0)
1089 break;
1090 ret = 0;
1091 if (!time_before(jiffies, expire)) {
1092 /* Timed out. */
1093 dump_parport_state("timeout", port);
1094 printk(KERN_DEBUG "PIO read timed out\n");
1095 break;
1096 }
1097 ecrval = inb(ECONTROL(port));
1098 if (!(ecrval & (1<<2))) {
1099 if (need_resched() &&
1100 time_before(jiffies, expire)) {
1101 schedule();
1102 }
1103 goto false_alarm;
1104 }
1105
1106 /* Depending on how the FIFO threshold was
1107 * set, how long interrupt service took, and
1108 * how fast the peripheral is, we might be
1109 * lucky and have a just filled FIFO. */
1110 continue;
1111 }
1112
1113 if (ecrval & 0x02) {
1114 /* FIFO is full. */
1115 dump_parport_state("FIFO full", port);
1116 insb(fifo, bufp, fifo_depth);
1117 bufp += fifo_depth;
1118 left -= fifo_depth;
1119 continue;
1120 }
1121
1122 DPRINTK(KERN_DEBUG
1123 "*** ecp_read_block_pio: reading one byte from the FIFO\n");
1124
1125 /* FIFO not filled. We will cycle this loop for a while
1126 * and either the peripheral will fill it faster,
1127 * tripping a fast empty with insb, or we empty it. */
1128 *bufp++ = inb(fifo);
1129 left--;
1130 }
1131
1132 /* scoop up anything left in the FIFO */
1133 while (left && !(inb(ECONTROL(port) & 0x01))) {
1134 *bufp++ = inb(fifo);
1135 left--;
1136 }
1137
1138 port->ieee1284.phase = IEEE1284_PH_REV_IDLE;
1139 dump_parport_state("rev idle2", port);
1140
1141out_no_data:
1142
1143 /* Go to forward idle mode to shut the peripheral up (event 47). */
1144 parport_frob_control(port, PARPORT_CONTROL_INIT, PARPORT_CONTROL_INIT);
1145
1146 /* event 49: PError goes high */
1147 r = parport_wait_peripheral(port,
1148 PARPORT_STATUS_PAPEROUT,
1149 PARPORT_STATUS_PAPEROUT);
1150 if (r) {
1151 printk(KERN_DEBUG
1152 "%s: PE timeout FWDIDLE (%d) in ecp_read_block_pio\n",
1153 port->name, r);
1154 }
1155
1156 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
1157
1158 /* Finish up. */
1159 {
1160 int lost = get_fifo_residue(port);
1161 if (lost)
1162 /* Shouldn't happen with compliant peripherals. */
1163 printk(KERN_DEBUG "%s: DATA LOSS (%d bytes)!\n",
1164 port->name, lost);
1165 }
1166
1167 dump_parport_state("fwd idle", port);
1168 return length - left;
1169}
1170#endif /* 0 */
1171#endif /* IEEE 1284 support */
1172#endif /* Allowed to use FIFO/DMA */
1173
1174
1175/*
1176 * ******************************************
1177 * INITIALISATION AND MODULE STUFF BELOW HERE
1178 * ******************************************
1179 */
1180
1181/* GCC is not inlining extern inline function later overwriten to non-inline,
1182 so we use outlined_ variants here. */
1183static const struct parport_operations parport_pc_ops = {
1184 .write_data = parport_pc_write_data,
1185 .read_data = parport_pc_read_data,
1186
1187 .write_control = parport_pc_write_control,
1188 .read_control = parport_pc_read_control,
1189 .frob_control = parport_pc_frob_control,
1190
1191 .read_status = parport_pc_read_status,
1192
1193 .enable_irq = parport_pc_enable_irq,
1194 .disable_irq = parport_pc_disable_irq,
1195
1196 .data_forward = parport_pc_data_forward,
1197 .data_reverse = parport_pc_data_reverse,
1198
1199 .init_state = parport_pc_init_state,
1200 .save_state = parport_pc_save_state,
1201 .restore_state = parport_pc_restore_state,
1202
1203 .epp_write_data = parport_ieee1284_epp_write_data,
1204 .epp_read_data = parport_ieee1284_epp_read_data,
1205 .epp_write_addr = parport_ieee1284_epp_write_addr,
1206 .epp_read_addr = parport_ieee1284_epp_read_addr,
1207
1208 .ecp_write_data = parport_ieee1284_ecp_write_data,
1209 .ecp_read_data = parport_ieee1284_ecp_read_data,
1210 .ecp_write_addr = parport_ieee1284_ecp_write_addr,
1211
1212 .compat_write_data = parport_ieee1284_write_compat,
1213 .nibble_read_data = parport_ieee1284_read_nibble,
1214 .byte_read_data = parport_ieee1284_read_byte,
1215
1216 .owner = THIS_MODULE,
1217};
1218
1219#ifdef CONFIG_PARPORT_PC_SUPERIO
1220
1221static struct superio_struct *find_free_superio(void)
1222{
1223 int i;
1224 for (i = 0; i < NR_SUPERIOS; i++)
1225 if (superios[i].io == 0)
1226 return &superios[i];
1227 return NULL;
1228}
1229
1230
1231/* Super-IO chipset detection, Winbond, SMSC */
1232static void __devinit show_parconfig_smsc37c669(int io, int key)
1233{
1234 int cr1, cr4, cra, cr23, cr26, cr27;
1235 struct superio_struct *s;
1236
1237 static const char *const modes[] = {
1238 "SPP and Bidirectional (PS/2)",
1239 "EPP and SPP",
1240 "ECP",
1241 "ECP and EPP" };
1242
1243 outb(key, io);
1244 outb(key, io);
1245 outb(1, io);
1246 cr1 = inb(io + 1);
1247 outb(4, io);
1248 cr4 = inb(io + 1);
1249 outb(0x0a, io);
1250 cra = inb(io + 1);
1251 outb(0x23, io);
1252 cr23 = inb(io + 1);
1253 outb(0x26, io);
1254 cr26 = inb(io + 1);
1255 outb(0x27, io);
1256 cr27 = inb(io + 1);
1257 outb(0xaa, io);
1258
1259 if (verbose_probing) {
1260 printk(KERN_INFO
1261 "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, "
1262 "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n",
1263 cr1, cr4, cra, cr23, cr26, cr27);
1264
1265 /* The documentation calls DMA and IRQ-Lines by letters, so
1266 the board maker can/will wire them
1267 appropriately/randomly... G=reserved H=IDE-irq, */
1268 printk(KERN_INFO
1269 "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, fifo threshold=%d\n",
1270 cr23 * 4,
1271 (cr27 & 0x0f) ? 'A' - 1 + (cr27 & 0x0f) : '-',
1272 (cr26 & 0x0f) ? 'A' - 1 + (cr26 & 0x0f) : '-',
1273 cra & 0x0f);
1274 printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n",
1275 (cr23 * 4 >= 0x100) ? "yes" : "no",
1276 (cr1 & 4) ? "yes" : "no");
1277 printk(KERN_INFO
1278 "SMSC LPT Config: Port mode=%s, EPP version =%s\n",
1279 (cr1 & 0x08) ? "Standard mode only (SPP)"
1280 : modes[cr4 & 0x03],
1281 (cr4 & 0x40) ? "1.7" : "1.9");
1282 }
1283
1284 /* Heuristics ! BIOS setup for this mainboard device limits
1285 the choices to standard settings, i.e. io-address and IRQ
1286 are related, however DMA can be 1 or 3, assume DMA_A=DMA1,
1287 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */
1288 if (cr23 * 4 >= 0x100) { /* if active */
1289 s = find_free_superio();
1290 if (s == NULL)
1291 printk(KERN_INFO "Super-IO: too many chips!\n");
1292 else {
1293 int d;
1294 switch (cr23 * 4) {
1295 case 0x3bc:
1296 s->io = 0x3bc;
1297 s->irq = 7;
1298 break;
1299 case 0x378:
1300 s->io = 0x378;
1301 s->irq = 7;
1302 break;
1303 case 0x278:
1304 s->io = 0x278;
1305 s->irq = 5;
1306 }
1307 d = (cr26 & 0x0f);
1308 if (d == 1 || d == 3)
1309 s->dma = d;
1310 else
1311 s->dma = PARPORT_DMA_NONE;
1312 }
1313 }
1314}
1315
1316
1317static void __devinit show_parconfig_winbond(int io, int key)
1318{
1319 int cr30, cr60, cr61, cr70, cr74, crf0;
1320 struct superio_struct *s;
1321 static const char *const modes[] = {
1322 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */
1323 "EPP-1.9 and SPP",
1324 "ECP",
1325 "ECP and EPP-1.9",
1326 "Standard (SPP)",
1327 "EPP-1.7 and SPP", /* 5 */
1328 "undefined!",
1329 "ECP and EPP-1.7" };
1330 static char *const irqtypes[] = {
1331 "pulsed low, high-Z",
1332 "follows nACK" };
1333
1334 /* The registers are called compatible-PnP because the
1335 register layout is modelled after ISA-PnP, the access
1336 method is just another ... */
1337 outb(key, io);
1338 outb(key, io);
1339 outb(0x07, io); /* Register 7: Select Logical Device */
1340 outb(0x01, io + 1); /* LD1 is Parallel Port */
1341 outb(0x30, io);
1342 cr30 = inb(io + 1);
1343 outb(0x60, io);
1344 cr60 = inb(io + 1);
1345 outb(0x61, io);
1346 cr61 = inb(io + 1);
1347 outb(0x70, io);
1348 cr70 = inb(io + 1);
1349 outb(0x74, io);
1350 cr74 = inb(io + 1);
1351 outb(0xf0, io);
1352 crf0 = inb(io + 1);
1353 outb(0xaa, io);
1354
1355 if (verbose_probing) {
1356 printk(KERN_INFO
1357 "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x 70=%02x 74=%02x, f0=%02x\n",
1358 cr30, cr60, cr61, cr70, cr74, crf0);
1359 printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
1360 (cr30 & 0x01) ? "yes" : "no", cr60, cr61, cr70 & 0x0f);
1361 if ((cr74 & 0x07) > 3)
1362 printk("dma=none\n");
1363 else
1364 printk("dma=%d\n", cr74 & 0x07);
1365 printk(KERN_INFO
1366 "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n",
1367 irqtypes[crf0>>7], (crf0>>3)&0x0f);
1368 printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n",
1369 modes[crf0 & 0x07]);
1370 }
1371
1372 if (cr30 & 0x01) { /* the settings can be interrogated later ... */
1373 s = find_free_superio();
1374 if (s == NULL)
1375 printk(KERN_INFO "Super-IO: too many chips!\n");
1376 else {
1377 s->io = (cr60 << 8) | cr61;
1378 s->irq = cr70 & 0x0f;
1379 s->dma = (((cr74 & 0x07) > 3) ?
1380 PARPORT_DMA_NONE : (cr74 & 0x07));
1381 }
1382 }
1383}
1384
1385static void __devinit decode_winbond(int efer, int key, int devid,
1386 int devrev, int oldid)
1387{
1388 const char *type = "unknown";
1389 int id, progif = 2;
1390
1391 if (devid == devrev)
1392 /* simple heuristics, we happened to read some
1393 non-winbond register */
1394 return;
1395
1396 id = (devid << 8) | devrev;
1397
1398 /* Values are from public data sheets pdf files, I can just
1399 confirm 83977TF is correct :-) */
1400 if (id == 0x9771)
1401 type = "83977F/AF";
1402 else if (id == 0x9773)
1403 type = "83977TF / SMSC 97w33x/97w34x";
1404 else if (id == 0x9774)
1405 type = "83977ATF";
1406 else if ((id & ~0x0f) == 0x5270)
1407 type = "83977CTF / SMSC 97w36x";
1408 else if ((id & ~0x0f) == 0x52f0)
1409 type = "83977EF / SMSC 97w35x";
1410 else if ((id & ~0x0f) == 0x5210)
1411 type = "83627";
1412 else if ((id & ~0x0f) == 0x6010)
1413 type = "83697HF";
1414 else if ((oldid & 0x0f) == 0x0a) {
1415 type = "83877F";
1416 progif = 1;
1417 } else if ((oldid & 0x0f) == 0x0b) {
1418 type = "83877AF";
1419 progif = 1;
1420 } else if ((oldid & 0x0f) == 0x0c) {
1421 type = "83877TF";
1422 progif = 1;
1423 } else if ((oldid & 0x0f) == 0x0d) {
1424 type = "83877ATF";
1425 progif = 1;
1426 } else
1427 progif = 0;
1428
1429 if (verbose_probing)
1430 printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x "
1431 "devid=%02x devrev=%02x oldid=%02x type=%s\n",
1432 efer, key, devid, devrev, oldid, type);
1433
1434 if (progif == 2)
1435 show_parconfig_winbond(efer, key);
1436}
1437
1438static void __devinit decode_smsc(int efer, int key, int devid, int devrev)
1439{
1440 const char *type = "unknown";
1441 void (*func)(int io, int key);
1442 int id;
1443
1444 if (devid == devrev)
1445 /* simple heuristics, we happened to read some
1446 non-smsc register */
1447 return;
1448
1449 func = NULL;
1450 id = (devid << 8) | devrev;
1451
1452 if (id == 0x0302) {
1453 type = "37c669";
1454 func = show_parconfig_smsc37c669;
1455 } else if (id == 0x6582)
1456 type = "37c665IR";
1457 else if (devid == 0x65)
1458 type = "37c665GT";
1459 else if (devid == 0x66)
1460 type = "37c666GT";
1461
1462 if (verbose_probing)
1463 printk(KERN_INFO "SMSC chip at EFER=0x%x "
1464 "key=0x%02x devid=%02x devrev=%02x type=%s\n",
1465 efer, key, devid, devrev, type);
1466
1467 if (func)
1468 func(efer, key);
1469}
1470
1471
1472static void __devinit winbond_check(int io, int key)
1473{
1474 int origval, devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1475
1476 if (!request_region(io, 3, __func__))
1477 return;
1478
1479 origval = inb(io); /* Save original value */
1480
1481 /* First probe without key */
1482 outb(0x20, io);
1483 x_devid = inb(io + 1);
1484 outb(0x21, io);
1485 x_devrev = inb(io + 1);
1486 outb(0x09, io);
1487 x_oldid = inb(io + 1);
1488
1489 outb(key, io);
1490 outb(key, io); /* Write Magic Sequence to EFER, extended
1491 function enable register */
1492 outb(0x20, io); /* Write EFIR, extended function index register */
1493 devid = inb(io + 1); /* Read EFDR, extended function data register */
1494 outb(0x21, io);
1495 devrev = inb(io + 1);
1496 outb(0x09, io);
1497 oldid = inb(io + 1);
1498 outb(0xaa, io); /* Magic Seal */
1499
1500 outb(origval, io); /* in case we poked some entirely different hardware */
1501
1502 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1503 goto out; /* protection against false positives */
1504
1505 decode_winbond(io, key, devid, devrev, oldid);
1506out:
1507 release_region(io, 3);
1508}
1509
1510static void __devinit winbond_check2(int io, int key)
1511{
1512 int origval[3], devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1513
1514 if (!request_region(io, 3, __func__))
1515 return;
1516
1517 origval[0] = inb(io); /* Save original values */
1518 origval[1] = inb(io + 1);
1519 origval[2] = inb(io + 2);
1520
1521 /* First probe without the key */
1522 outb(0x20, io + 2);
1523 x_devid = inb(io + 2);
1524 outb(0x21, io + 1);
1525 x_devrev = inb(io + 2);
1526 outb(0x09, io + 1);
1527 x_oldid = inb(io + 2);
1528
1529 outb(key, io); /* Write Magic Byte to EFER, extended
1530 function enable register */
1531 outb(0x20, io + 2); /* Write EFIR, extended function index register */
1532 devid = inb(io + 2); /* Read EFDR, extended function data register */
1533 outb(0x21, io + 1);
1534 devrev = inb(io + 2);
1535 outb(0x09, io + 1);
1536 oldid = inb(io + 2);
1537 outb(0xaa, io); /* Magic Seal */
1538
1539 outb(origval[0], io); /* in case we poked some entirely different hardware */
1540 outb(origval[1], io + 1);
1541 outb(origval[2], io + 2);
1542
1543 if (x_devid == devid && x_devrev == devrev && x_oldid == oldid)
1544 goto out; /* protection against false positives */
1545
1546 decode_winbond(io, key, devid, devrev, oldid);
1547out:
1548 release_region(io, 3);
1549}
1550
1551static void __devinit smsc_check(int io, int key)
1552{
1553 int origval, id, rev, oldid, oldrev, x_id, x_rev, x_oldid, x_oldrev;
1554
1555 if (!request_region(io, 3, __func__))
1556 return;
1557
1558 origval = inb(io); /* Save original value */
1559
1560 /* First probe without the key */
1561 outb(0x0d, io);
1562 x_oldid = inb(io + 1);
1563 outb(0x0e, io);
1564 x_oldrev = inb(io + 1);
1565 outb(0x20, io);
1566 x_id = inb(io + 1);
1567 outb(0x21, io);
1568 x_rev = inb(io + 1);
1569
1570 outb(key, io);
1571 outb(key, io); /* Write Magic Sequence to EFER, extended
1572 function enable register */
1573 outb(0x0d, io); /* Write EFIR, extended function index register */
1574 oldid = inb(io + 1); /* Read EFDR, extended function data register */
1575 outb(0x0e, io);
1576 oldrev = inb(io + 1);
1577 outb(0x20, io);
1578 id = inb(io + 1);
1579 outb(0x21, io);
1580 rev = inb(io + 1);
1581 outb(0xaa, io); /* Magic Seal */
1582
1583 outb(origval, io); /* in case we poked some entirely different hardware */
1584
1585 if (x_id == id && x_oldrev == oldrev &&
1586 x_oldid == oldid && x_rev == rev)
1587 goto out; /* protection against false positives */
1588
1589 decode_smsc(io, key, oldid, oldrev);
1590out:
1591 release_region(io, 3);
1592}
1593
1594
1595static void __devinit detect_and_report_winbond(void)
1596{
1597 if (verbose_probing)
1598 printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n");
1599 winbond_check(0x3f0, 0x87);
1600 winbond_check(0x370, 0x87);
1601 winbond_check(0x2e , 0x87);
1602 winbond_check(0x4e , 0x87);
1603 winbond_check(0x3f0, 0x86);
1604 winbond_check2(0x250, 0x88);
1605 winbond_check2(0x250, 0x89);
1606}
1607
1608static void __devinit detect_and_report_smsc(void)
1609{
1610 if (verbose_probing)
1611 printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n");
1612 smsc_check(0x3f0, 0x55);
1613 smsc_check(0x370, 0x55);
1614 smsc_check(0x3f0, 0x44);
1615 smsc_check(0x370, 0x44);
1616}
1617
1618static void __devinit detect_and_report_it87(void)
1619{
1620 u16 dev;
1621 u8 origval, r;
1622 if (verbose_probing)
1623 printk(KERN_DEBUG "IT8705 Super-IO detection, now testing port 2E ...\n");
1624 if (!request_muxed_region(0x2e, 2, __func__))
1625 return;
1626 origval = inb(0x2e); /* Save original value */
1627 outb(0x87, 0x2e);
1628 outb(0x01, 0x2e);
1629 outb(0x55, 0x2e);
1630 outb(0x55, 0x2e);
1631 outb(0x20, 0x2e);
1632 dev = inb(0x2f) << 8;
1633 outb(0x21, 0x2e);
1634 dev |= inb(0x2f);
1635 if (dev == 0x8712 || dev == 0x8705 || dev == 0x8715 ||
1636 dev == 0x8716 || dev == 0x8718 || dev == 0x8726) {
1637 printk(KERN_INFO "IT%04X SuperIO detected.\n", dev);
1638 outb(0x07, 0x2E); /* Parallel Port */
1639 outb(0x03, 0x2F);
1640 outb(0xF0, 0x2E); /* BOOT 0x80 off */
1641 r = inb(0x2f);
1642 outb(0xF0, 0x2E);
1643 outb(r | 8, 0x2F);
1644 outb(0x02, 0x2E); /* Lock */
1645 outb(0x02, 0x2F);
1646 } else {
1647 outb(origval, 0x2e); /* Oops, sorry to disturb */
1648 }
1649 release_region(0x2e, 2);
1650}
1651#endif /* CONFIG_PARPORT_PC_SUPERIO */
1652
1653static struct superio_struct *find_superio(struct parport *p)
1654{
1655 int i;
1656 for (i = 0; i < NR_SUPERIOS; i++)
1657 if (superios[i].io != p->base)
1658 return &superios[i];
1659 return NULL;
1660}
1661
1662static int get_superio_dma(struct parport *p)
1663{
1664 struct superio_struct *s = find_superio(p);
1665 if (s)
1666 return s->dma;
1667 return PARPORT_DMA_NONE;
1668}
1669
1670static int get_superio_irq(struct parport *p)
1671{
1672 struct superio_struct *s = find_superio(p);
1673 if (s)
1674 return s->irq;
1675 return PARPORT_IRQ_NONE;
1676}
1677
1678
1679/* --- Mode detection ------------------------------------- */
1680
1681/*
1682 * Checks for port existence, all ports support SPP MODE
1683 * Returns:
1684 * 0 : No parallel port at this address
1685 * PARPORT_MODE_PCSPP : SPP port detected
1686 * (if the user specified an ioport himself,
1687 * this shall always be the case!)
1688 *
1689 */
1690static int parport_SPP_supported(struct parport *pb)
1691{
1692 unsigned char r, w;
1693
1694 /*
1695 * first clear an eventually pending EPP timeout
1696 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset
1697 * that does not even respond to SPP cycles if an EPP
1698 * timeout is pending
1699 */
1700 clear_epp_timeout(pb);
1701
1702 /* Do a simple read-write test to make sure the port exists. */
1703 w = 0xc;
1704 outb(w, CONTROL(pb));
1705
1706 /* Is there a control register that we can read from? Some
1707 * ports don't allow reads, so read_control just returns a
1708 * software copy. Some ports _do_ allow reads, so bypass the
1709 * software copy here. In addition, some bits aren't
1710 * writable. */
1711 r = inb(CONTROL(pb));
1712 if ((r & 0xf) == w) {
1713 w = 0xe;
1714 outb(w, CONTROL(pb));
1715 r = inb(CONTROL(pb));
1716 outb(0xc, CONTROL(pb));
1717 if ((r & 0xf) == w)
1718 return PARPORT_MODE_PCSPP;
1719 }
1720
1721 if (user_specified)
1722 /* That didn't work, but the user thinks there's a
1723 * port here. */
1724 printk(KERN_INFO "parport 0x%lx (WARNING): CTR: "
1725 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1726
1727 /* Try the data register. The data lines aren't tri-stated at
1728 * this stage, so we expect back what we wrote. */
1729 w = 0xaa;
1730 parport_pc_write_data(pb, w);
1731 r = parport_pc_read_data(pb);
1732 if (r == w) {
1733 w = 0x55;
1734 parport_pc_write_data(pb, w);
1735 r = parport_pc_read_data(pb);
1736 if (r == w)
1737 return PARPORT_MODE_PCSPP;
1738 }
1739
1740 if (user_specified) {
1741 /* Didn't work, but the user is convinced this is the
1742 * place. */
1743 printk(KERN_INFO "parport 0x%lx (WARNING): DATA: "
1744 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1745 printk(KERN_INFO "parport 0x%lx: You gave this address, "
1746 "but there is probably no parallel port there!\n",
1747 pb->base);
1748 }
1749
1750 /* It's possible that we can't read the control register or
1751 * the data register. In that case just believe the user. */
1752 if (user_specified)
1753 return PARPORT_MODE_PCSPP;
1754
1755 return 0;
1756}
1757
1758/* Check for ECR
1759 *
1760 * Old style XT ports alias io ports every 0x400, hence accessing ECR
1761 * on these cards actually accesses the CTR.
1762 *
1763 * Modern cards don't do this but reading from ECR will return 0xff
1764 * regardless of what is written here if the card does NOT support
1765 * ECP.
1766 *
1767 * We first check to see if ECR is the same as CTR. If not, the low
1768 * two bits of ECR aren't writable, so we check by writing ECR and
1769 * reading it back to see if it's what we expect.
1770 */
1771static int parport_ECR_present(struct parport *pb)
1772{
1773 struct parport_pc_private *priv = pb->private_data;
1774 unsigned char r = 0xc;
1775
1776 outb(r, CONTROL(pb));
1777 if ((inb(ECONTROL(pb)) & 0x3) == (r & 0x3)) {
1778 outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */
1779
1780 r = inb(CONTROL(pb));
1781 if ((inb(ECONTROL(pb)) & 0x2) == (r & 0x2))
1782 goto no_reg; /* Sure that no ECR register exists */
1783 }
1784
1785 if ((inb(ECONTROL(pb)) & 0x3) != 0x1)
1786 goto no_reg;
1787
1788 ECR_WRITE(pb, 0x34);
1789 if (inb(ECONTROL(pb)) != 0x35)
1790 goto no_reg;
1791
1792 priv->ecr = 1;
1793 outb(0xc, CONTROL(pb));
1794
1795 /* Go to mode 000 */
1796 frob_set_mode(pb, ECR_SPP);
1797
1798 return 1;
1799
1800 no_reg:
1801 outb(0xc, CONTROL(pb));
1802 return 0;
1803}
1804
1805#ifdef CONFIG_PARPORT_1284
1806/* Detect PS/2 support.
1807 *
1808 * Bit 5 (0x20) sets the PS/2 data direction; setting this high
1809 * allows us to read data from the data lines. In theory we would get back
1810 * 0xff but any peripheral attached to the port may drag some or all of the
1811 * lines down to zero. So if we get back anything that isn't the contents
1812 * of the data register we deem PS/2 support to be present.
1813 *
1814 * Some SPP ports have "half PS/2" ability - you can't turn off the line
1815 * drivers, but an external peripheral with sufficiently beefy drivers of
1816 * its own can overpower them and assert its own levels onto the bus, from
1817 * where they can then be read back as normal. Ports with this property
1818 * and the right type of device attached are likely to fail the SPP test,
1819 * (as they will appear to have stuck bits) and so the fact that they might
1820 * be misdetected here is rather academic.
1821 */
1822
1823static int parport_PS2_supported(struct parport *pb)
1824{
1825 int ok = 0;
1826
1827 clear_epp_timeout(pb);
1828
1829 /* try to tri-state the buffer */
1830 parport_pc_data_reverse(pb);
1831
1832 parport_pc_write_data(pb, 0x55);
1833 if (parport_pc_read_data(pb) != 0x55)
1834 ok++;
1835
1836 parport_pc_write_data(pb, 0xaa);
1837 if (parport_pc_read_data(pb) != 0xaa)
1838 ok++;
1839
1840 /* cancel input mode */
1841 parport_pc_data_forward(pb);
1842
1843 if (ok) {
1844 pb->modes |= PARPORT_MODE_TRISTATE;
1845 } else {
1846 struct parport_pc_private *priv = pb->private_data;
1847 priv->ctr_writable &= ~0x20;
1848 }
1849
1850 return ok;
1851}
1852
1853#ifdef CONFIG_PARPORT_PC_FIFO
1854static int parport_ECP_supported(struct parport *pb)
1855{
1856 int i;
1857 int config, configb;
1858 int pword;
1859 struct parport_pc_private *priv = pb->private_data;
1860 /* Translate ECP intrLine to ISA irq value */
1861 static const int intrline[] = { 0, 7, 9, 10, 11, 14, 15, 5 };
1862
1863 /* If there is no ECR, we have no hope of supporting ECP. */
1864 if (!priv->ecr)
1865 return 0;
1866
1867 /* Find out FIFO depth */
1868 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1869 ECR_WRITE(pb, ECR_TST << 5); /* TEST FIFO */
1870 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02); i++)
1871 outb(0xaa, FIFO(pb));
1872
1873 /*
1874 * Using LGS chipset it uses ECR register, but
1875 * it doesn't support ECP or FIFO MODE
1876 */
1877 if (i == 1024) {
1878 ECR_WRITE(pb, ECR_SPP << 5);
1879 return 0;
1880 }
1881
1882 priv->fifo_depth = i;
1883 if (verbose_probing)
1884 printk(KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i);
1885
1886 /* Find out writeIntrThreshold */
1887 frob_econtrol(pb, 1<<2, 1<<2);
1888 frob_econtrol(pb, 1<<2, 0);
1889 for (i = 1; i <= priv->fifo_depth; i++) {
1890 inb(FIFO(pb));
1891 udelay(50);
1892 if (inb(ECONTROL(pb)) & (1<<2))
1893 break;
1894 }
1895
1896 if (i <= priv->fifo_depth) {
1897 if (verbose_probing)
1898 printk(KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n",
1899 pb->base, i);
1900 } else
1901 /* Number of bytes we know we can write if we get an
1902 interrupt. */
1903 i = 0;
1904
1905 priv->writeIntrThreshold = i;
1906
1907 /* Find out readIntrThreshold */
1908 frob_set_mode(pb, ECR_PS2); /* Reset FIFO and enable PS2 */
1909 parport_pc_data_reverse(pb); /* Must be in PS2 mode */
1910 frob_set_mode(pb, ECR_TST); /* Test FIFO */
1911 frob_econtrol(pb, 1<<2, 1<<2);
1912 frob_econtrol(pb, 1<<2, 0);
1913 for (i = 1; i <= priv->fifo_depth; i++) {
1914 outb(0xaa, FIFO(pb));
1915 if (inb(ECONTROL(pb)) & (1<<2))
1916 break;
1917 }
1918
1919 if (i <= priv->fifo_depth) {
1920 if (verbose_probing)
1921 printk(KERN_INFO "0x%lx: readIntrThreshold is %d\n",
1922 pb->base, i);
1923 } else
1924 /* Number of bytes we can read if we get an interrupt. */
1925 i = 0;
1926
1927 priv->readIntrThreshold = i;
1928
1929 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1930 ECR_WRITE(pb, 0xf4); /* Configuration mode */
1931 config = inb(CONFIGA(pb));
1932 pword = (config >> 4) & 0x7;
1933 switch (pword) {
1934 case 0:
1935 pword = 2;
1936 printk(KERN_WARNING "0x%lx: Unsupported pword size!\n",
1937 pb->base);
1938 break;
1939 case 2:
1940 pword = 4;
1941 printk(KERN_WARNING "0x%lx: Unsupported pword size!\n",
1942 pb->base);
1943 break;
1944 default:
1945 printk(KERN_WARNING "0x%lx: Unknown implementation ID\n",
1946 pb->base);
1947 /* Assume 1 */
1948 case 1:
1949 pword = 1;
1950 }
1951 priv->pword = pword;
1952
1953 if (verbose_probing) {
1954 printk(KERN_DEBUG "0x%lx: PWord is %d bits\n",
1955 pb->base, 8 * pword);
1956
1957 printk(KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base,
1958 config & 0x80 ? "Level" : "Pulses");
1959
1960 configb = inb(CONFIGB(pb));
1961 printk(KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
1962 pb->base, config, configb);
1963 printk(KERN_DEBUG "0x%lx: ECP settings irq=", pb->base);
1964 if ((configb >> 3) & 0x07)
1965 printk("%d", intrline[(configb >> 3) & 0x07]);
1966 else
1967 printk("<none or set by other means>");
1968 printk(" dma=");
1969 if ((configb & 0x03) == 0x00)
1970 printk("<none or set by other means>\n");
1971 else
1972 printk("%d\n", configb & 0x07);
1973 }
1974
1975 /* Go back to mode 000 */
1976 frob_set_mode(pb, ECR_SPP);
1977
1978 return 1;
1979}
1980#endif
1981
1982static int parport_ECPPS2_supported(struct parport *pb)
1983{
1984 const struct parport_pc_private *priv = pb->private_data;
1985 int result;
1986 unsigned char oecr;
1987
1988 if (!priv->ecr)
1989 return 0;
1990
1991 oecr = inb(ECONTROL(pb));
1992 ECR_WRITE(pb, ECR_PS2 << 5);
1993 result = parport_PS2_supported(pb);
1994 ECR_WRITE(pb, oecr);
1995 return result;
1996}
1997
1998/* EPP mode detection */
1999
2000static int parport_EPP_supported(struct parport *pb)
2001{
2002 const struct parport_pc_private *priv = pb->private_data;
2003
2004 /*
2005 * Theory:
2006 * Bit 0 of STR is the EPP timeout bit, this bit is 0
2007 * when EPP is possible and is set high when an EPP timeout
2008 * occurs (EPP uses the HALT line to stop the CPU while it does
2009 * the byte transfer, an EPP timeout occurs if the attached
2010 * device fails to respond after 10 micro seconds).
2011 *
2012 * This bit is cleared by either reading it (National Semi)
2013 * or writing a 1 to the bit (SMC, UMC, WinBond), others ???
2014 * This bit is always high in non EPP modes.
2015 */
2016
2017 /* If EPP timeout bit clear then EPP available */
2018 if (!clear_epp_timeout(pb))
2019 return 0; /* No way to clear timeout */
2020
2021 /* Check for Intel bug. */
2022 if (priv->ecr) {
2023 unsigned char i;
2024 for (i = 0x00; i < 0x80; i += 0x20) {
2025 ECR_WRITE(pb, i);
2026 if (clear_epp_timeout(pb)) {
2027 /* Phony EPP in ECP. */
2028 return 0;
2029 }
2030 }
2031 }
2032
2033 pb->modes |= PARPORT_MODE_EPP;
2034
2035 /* Set up access functions to use EPP hardware. */
2036 pb->ops->epp_read_data = parport_pc_epp_read_data;
2037 pb->ops->epp_write_data = parport_pc_epp_write_data;
2038 pb->ops->epp_read_addr = parport_pc_epp_read_addr;
2039 pb->ops->epp_write_addr = parport_pc_epp_write_addr;
2040
2041 return 1;
2042}
2043
2044static int parport_ECPEPP_supported(struct parport *pb)
2045{
2046 struct parport_pc_private *priv = pb->private_data;
2047 int result;
2048 unsigned char oecr;
2049
2050 if (!priv->ecr)
2051 return 0;
2052
2053 oecr = inb(ECONTROL(pb));
2054 /* Search for SMC style EPP+ECP mode */
2055 ECR_WRITE(pb, 0x80);
2056 outb(0x04, CONTROL(pb));
2057 result = parport_EPP_supported(pb);
2058
2059 ECR_WRITE(pb, oecr);
2060
2061 if (result) {
2062 /* Set up access functions to use ECP+EPP hardware. */
2063 pb->ops->epp_read_data = parport_pc_ecpepp_read_data;
2064 pb->ops->epp_write_data = parport_pc_ecpepp_write_data;
2065 pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr;
2066 pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr;
2067 }
2068
2069 return result;
2070}
2071
2072#else /* No IEEE 1284 support */
2073
2074/* Don't bother probing for modes we know we won't use. */
2075static int __devinit parport_PS2_supported(struct parport *pb) { return 0; }
2076#ifdef CONFIG_PARPORT_PC_FIFO
2077static int parport_ECP_supported(struct parport *pb)
2078{
2079 return 0;
2080}
2081#endif
2082static int __devinit parport_EPP_supported(struct parport *pb)
2083{
2084 return 0;
2085}
2086
2087static int __devinit parport_ECPEPP_supported(struct parport *pb)
2088{
2089 return 0;
2090}
2091
2092static int __devinit parport_ECPPS2_supported(struct parport *pb)
2093{
2094 return 0;
2095}
2096
2097#endif /* No IEEE 1284 support */
2098
2099/* --- IRQ detection -------------------------------------- */
2100
2101/* Only if supports ECP mode */
2102static int programmable_irq_support(struct parport *pb)
2103{
2104 int irq, intrLine;
2105 unsigned char oecr = inb(ECONTROL(pb));
2106 static const int lookup[8] = {
2107 PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5
2108 };
2109
2110 ECR_WRITE(pb, ECR_CNF << 5); /* Configuration MODE */
2111
2112 intrLine = (inb(CONFIGB(pb)) >> 3) & 0x07;
2113 irq = lookup[intrLine];
2114
2115 ECR_WRITE(pb, oecr);
2116 return irq;
2117}
2118
2119static int irq_probe_ECP(struct parport *pb)
2120{
2121 int i;
2122 unsigned long irqs;
2123
2124 irqs = probe_irq_on();
2125
2126 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
2127 ECR_WRITE(pb, (ECR_TST << 5) | 0x04);
2128 ECR_WRITE(pb, ECR_TST << 5);
2129
2130 /* If Full FIFO sure that writeIntrThreshold is generated */
2131 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02) ; i++)
2132 outb(0xaa, FIFO(pb));
2133
2134 pb->irq = probe_irq_off(irqs);
2135 ECR_WRITE(pb, ECR_SPP << 5);
2136
2137 if (pb->irq <= 0)
2138 pb->irq = PARPORT_IRQ_NONE;
2139
2140 return pb->irq;
2141}
2142
2143/*
2144 * This detection seems that only works in National Semiconductors
2145 * This doesn't work in SMC, LGS, and Winbond
2146 */
2147static int irq_probe_EPP(struct parport *pb)
2148{
2149#ifndef ADVANCED_DETECT
2150 return PARPORT_IRQ_NONE;
2151#else
2152 int irqs;
2153 unsigned char oecr;
2154
2155 if (pb->modes & PARPORT_MODE_PCECR)
2156 oecr = inb(ECONTROL(pb));
2157
2158 irqs = probe_irq_on();
2159
2160 if (pb->modes & PARPORT_MODE_PCECR)
2161 frob_econtrol(pb, 0x10, 0x10);
2162
2163 clear_epp_timeout(pb);
2164 parport_pc_frob_control(pb, 0x20, 0x20);
2165 parport_pc_frob_control(pb, 0x10, 0x10);
2166 clear_epp_timeout(pb);
2167
2168 /* Device isn't expecting an EPP read
2169 * and generates an IRQ.
2170 */
2171 parport_pc_read_epp(pb);
2172 udelay(20);
2173
2174 pb->irq = probe_irq_off(irqs);
2175 if (pb->modes & PARPORT_MODE_PCECR)
2176 ECR_WRITE(pb, oecr);
2177 parport_pc_write_control(pb, 0xc);
2178
2179 if (pb->irq <= 0)
2180 pb->irq = PARPORT_IRQ_NONE;
2181
2182 return pb->irq;
2183#endif /* Advanced detection */
2184}
2185
2186static int irq_probe_SPP(struct parport *pb)
2187{
2188 /* Don't even try to do this. */
2189 return PARPORT_IRQ_NONE;
2190}
2191
2192/* We will attempt to share interrupt requests since other devices
2193 * such as sound cards and network cards seem to like using the
2194 * printer IRQs.
2195 *
2196 * When ECP is available we can autoprobe for IRQs.
2197 * NOTE: If we can autoprobe it, we can register the IRQ.
2198 */
2199static int parport_irq_probe(struct parport *pb)
2200{
2201 struct parport_pc_private *priv = pb->private_data;
2202
2203 if (priv->ecr) {
2204 pb->irq = programmable_irq_support(pb);
2205
2206 if (pb->irq == PARPORT_IRQ_NONE)
2207 pb->irq = irq_probe_ECP(pb);
2208 }
2209
2210 if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr &&
2211 (pb->modes & PARPORT_MODE_EPP))
2212 pb->irq = irq_probe_EPP(pb);
2213
2214 clear_epp_timeout(pb);
2215
2216 if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP))
2217 pb->irq = irq_probe_EPP(pb);
2218
2219 clear_epp_timeout(pb);
2220
2221 if (pb->irq == PARPORT_IRQ_NONE)
2222 pb->irq = irq_probe_SPP(pb);
2223
2224 if (pb->irq == PARPORT_IRQ_NONE)
2225 pb->irq = get_superio_irq(pb);
2226
2227 return pb->irq;
2228}
2229
2230/* --- DMA detection -------------------------------------- */
2231
2232/* Only if chipset conforms to ECP ISA Interface Standard */
2233static int programmable_dma_support(struct parport *p)
2234{
2235 unsigned char oecr = inb(ECONTROL(p));
2236 int dma;
2237
2238 frob_set_mode(p, ECR_CNF);
2239
2240 dma = inb(CONFIGB(p)) & 0x07;
2241 /* 000: Indicates jumpered 8-bit DMA if read-only.
2242 100: Indicates jumpered 16-bit DMA if read-only. */
2243 if ((dma & 0x03) == 0)
2244 dma = PARPORT_DMA_NONE;
2245
2246 ECR_WRITE(p, oecr);
2247 return dma;
2248}
2249
2250static int parport_dma_probe(struct parport *p)
2251{
2252 const struct parport_pc_private *priv = p->private_data;
2253 if (priv->ecr) /* ask ECP chipset first */
2254 p->dma = programmable_dma_support(p);
2255 if (p->dma == PARPORT_DMA_NONE) {
2256 /* ask known Super-IO chips proper, although these
2257 claim ECP compatible, some don't report their DMA
2258 conforming to ECP standards */
2259 p->dma = get_superio_dma(p);
2260 }
2261
2262 return p->dma;
2263}
2264
2265/* --- Initialisation code -------------------------------- */
2266
2267static LIST_HEAD(ports_list);
2268static DEFINE_SPINLOCK(ports_lock);
2269
2270struct parport *parport_pc_probe_port(unsigned long int base,
2271 unsigned long int base_hi,
2272 int irq, int dma,
2273 struct device *dev,
2274 int irqflags)
2275{
2276 struct parport_pc_private *priv;
2277 struct parport_operations *ops;
2278 struct parport *p;
2279 int probedirq = PARPORT_IRQ_NONE;
2280 struct resource *base_res;
2281 struct resource *ECR_res = NULL;
2282 struct resource *EPP_res = NULL;
2283 struct platform_device *pdev = NULL;
2284
2285 if (!dev) {
2286 /* We need a physical device to attach to, but none was
2287 * provided. Create our own. */
2288 pdev = platform_device_register_simple("parport_pc",
2289 base, NULL, 0);
2290 if (IS_ERR(pdev))
2291 return NULL;
2292 dev = &pdev->dev;
2293
2294 dev->coherent_dma_mask = DMA_BIT_MASK(24);
2295 dev->dma_mask = &dev->coherent_dma_mask;
2296 }
2297
2298 ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL);
2299 if (!ops)
2300 goto out1;
2301
2302 priv = kmalloc(sizeof(struct parport_pc_private), GFP_KERNEL);
2303 if (!priv)
2304 goto out2;
2305
2306 /* a misnomer, actually - it's allocate and reserve parport number */
2307 p = parport_register_port(base, irq, dma, ops);
2308 if (!p)
2309 goto out3;
2310
2311 base_res = request_region(base, 3, p->name);
2312 if (!base_res)
2313 goto out4;
2314
2315 memcpy(ops, &parport_pc_ops, sizeof(struct parport_operations));
2316 priv->ctr = 0xc;
2317 priv->ctr_writable = ~0x10;
2318 priv->ecr = 0;
2319 priv->fifo_depth = 0;
2320 priv->dma_buf = NULL;
2321 priv->dma_handle = 0;
2322 INIT_LIST_HEAD(&priv->list);
2323 priv->port = p;
2324
2325 p->dev = dev;
2326 p->base_hi = base_hi;
2327 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
2328 p->private_data = priv;
2329
2330 if (base_hi) {
2331 ECR_res = request_region(base_hi, 3, p->name);
2332 if (ECR_res)
2333 parport_ECR_present(p);
2334 }
2335
2336 if (base != 0x3bc) {
2337 EPP_res = request_region(base+0x3, 5, p->name);
2338 if (EPP_res)
2339 if (!parport_EPP_supported(p))
2340 parport_ECPEPP_supported(p);
2341 }
2342 if (!parport_SPP_supported(p))
2343 /* No port. */
2344 goto out5;
2345 if (priv->ecr)
2346 parport_ECPPS2_supported(p);
2347 else
2348 parport_PS2_supported(p);
2349
2350 p->size = (p->modes & PARPORT_MODE_EPP) ? 8 : 3;
2351
2352 printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base);
2353 if (p->base_hi && priv->ecr)
2354 printk(" (0x%lx)", p->base_hi);
2355 if (p->irq == PARPORT_IRQ_AUTO) {
2356 p->irq = PARPORT_IRQ_NONE;
2357 parport_irq_probe(p);
2358 } else if (p->irq == PARPORT_IRQ_PROBEONLY) {
2359 p->irq = PARPORT_IRQ_NONE;
2360 parport_irq_probe(p);
2361 probedirq = p->irq;
2362 p->irq = PARPORT_IRQ_NONE;
2363 }
2364 if (p->irq != PARPORT_IRQ_NONE) {
2365 printk(", irq %d", p->irq);
2366 priv->ctr_writable |= 0x10;
2367
2368 if (p->dma == PARPORT_DMA_AUTO) {
2369 p->dma = PARPORT_DMA_NONE;
2370 parport_dma_probe(p);
2371 }
2372 }
2373 if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq
2374 is mandatory (see above) */
2375 p->dma = PARPORT_DMA_NONE;
2376
2377#ifdef CONFIG_PARPORT_PC_FIFO
2378 if (parport_ECP_supported(p) &&
2379 p->dma != PARPORT_DMA_NOFIFO &&
2380 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) {
2381 p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT;
2382 p->ops->compat_write_data = parport_pc_compat_write_block_pio;
2383#ifdef CONFIG_PARPORT_1284
2384 p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
2385 /* currently broken, but working on it.. (FB) */
2386 /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */
2387#endif /* IEEE 1284 support */
2388 if (p->dma != PARPORT_DMA_NONE) {
2389 printk(", dma %d", p->dma);
2390 p->modes |= PARPORT_MODE_DMA;
2391 } else
2392 printk(", using FIFO");
2393 } else
2394 /* We can't use the DMA channel after all. */
2395 p->dma = PARPORT_DMA_NONE;
2396#endif /* Allowed to use FIFO/DMA */
2397
2398 printk(" [");
2399
2400#define printmode(x) \
2401 {\
2402 if (p->modes & PARPORT_MODE_##x) {\
2403 printk("%s%s", f ? "," : "", #x);\
2404 f++;\
2405 } \
2406 }
2407
2408 {
2409 int f = 0;
2410 printmode(PCSPP);
2411 printmode(TRISTATE);
2412 printmode(COMPAT)
2413 printmode(EPP);
2414 printmode(ECP);
2415 printmode(DMA);
2416 }
2417#undef printmode
2418#ifndef CONFIG_PARPORT_1284
2419 printk("(,...)");
2420#endif /* CONFIG_PARPORT_1284 */
2421 printk("]\n");
2422 if (probedirq != PARPORT_IRQ_NONE)
2423 printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq);
2424
2425 /* If No ECP release the ports grabbed above. */
2426 if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) {
2427 release_region(base_hi, 3);
2428 ECR_res = NULL;
2429 }
2430 /* Likewise for EEP ports */
2431 if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) {
2432 release_region(base+3, 5);
2433 EPP_res = NULL;
2434 }
2435 if (p->irq != PARPORT_IRQ_NONE) {
2436 if (request_irq(p->irq, parport_irq_handler,
2437 irqflags, p->name, p)) {
2438 printk(KERN_WARNING "%s: irq %d in use, "
2439 "resorting to polled operation\n",
2440 p->name, p->irq);
2441 p->irq = PARPORT_IRQ_NONE;
2442 p->dma = PARPORT_DMA_NONE;
2443 }
2444
2445#ifdef CONFIG_PARPORT_PC_FIFO
2446#ifdef HAS_DMA
2447 if (p->dma != PARPORT_DMA_NONE) {
2448 if (request_dma(p->dma, p->name)) {
2449 printk(KERN_WARNING "%s: dma %d in use, "
2450 "resorting to PIO operation\n",
2451 p->name, p->dma);
2452 p->dma = PARPORT_DMA_NONE;
2453 } else {
2454 priv->dma_buf =
2455 dma_alloc_coherent(dev,
2456 PAGE_SIZE,
2457 &priv->dma_handle,
2458 GFP_KERNEL);
2459 if (!priv->dma_buf) {
2460 printk(KERN_WARNING "%s: "
2461 "cannot get buffer for DMA, "
2462 "resorting to PIO operation\n",
2463 p->name);
2464 free_dma(p->dma);
2465 p->dma = PARPORT_DMA_NONE;
2466 }
2467 }
2468 }
2469#endif
2470#endif
2471 }
2472
2473 /* Done probing. Now put the port into a sensible start-up state. */
2474 if (priv->ecr)
2475 /*
2476 * Put the ECP detected port in PS2 mode.
2477 * Do this also for ports that have ECR but don't do ECP.
2478 */
2479 ECR_WRITE(p, 0x34);
2480
2481 parport_pc_write_data(p, 0);
2482 parport_pc_data_forward(p);
2483
2484 /* Now that we've told the sharing engine about the port, and
2485 found out its characteristics, let the high-level drivers
2486 know about it. */
2487 spin_lock(&ports_lock);
2488 list_add(&priv->list, &ports_list);
2489 spin_unlock(&ports_lock);
2490 parport_announce_port(p);
2491
2492 return p;
2493
2494out5:
2495 if (ECR_res)
2496 release_region(base_hi, 3);
2497 if (EPP_res)
2498 release_region(base+0x3, 5);
2499 release_region(base, 3);
2500out4:
2501 parport_put_port(p);
2502out3:
2503 kfree(priv);
2504out2:
2505 kfree(ops);
2506out1:
2507 if (pdev)
2508 platform_device_unregister(pdev);
2509 return NULL;
2510}
2511EXPORT_SYMBOL(parport_pc_probe_port);
2512
2513void parport_pc_unregister_port(struct parport *p)
2514{
2515 struct parport_pc_private *priv = p->private_data;
2516 struct parport_operations *ops = p->ops;
2517
2518 parport_remove_port(p);
2519 spin_lock(&ports_lock);
2520 list_del_init(&priv->list);
2521 spin_unlock(&ports_lock);
2522#if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2523 if (p->dma != PARPORT_DMA_NONE)
2524 free_dma(p->dma);
2525#endif
2526 if (p->irq != PARPORT_IRQ_NONE)
2527 free_irq(p->irq, p);
2528 release_region(p->base, 3);
2529 if (p->size > 3)
2530 release_region(p->base + 3, p->size - 3);
2531 if (p->modes & PARPORT_MODE_ECP)
2532 release_region(p->base_hi, 3);
2533#if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2534 if (priv->dma_buf)
2535 dma_free_coherent(p->physport->dev, PAGE_SIZE,
2536 priv->dma_buf,
2537 priv->dma_handle);
2538#endif
2539 kfree(p->private_data);
2540 parport_put_port(p);
2541 kfree(ops); /* hope no-one cached it */
2542}
2543EXPORT_SYMBOL(parport_pc_unregister_port);
2544
2545#ifdef CONFIG_PCI
2546
2547/* ITE support maintained by Rich Liu <richliu@poorman.org> */
2548static int __devinit sio_ite_8872_probe(struct pci_dev *pdev, int autoirq,
2549 int autodma,
2550 const struct parport_pc_via_data *via)
2551{
2552 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 };
2553 u32 ite8872set;
2554 u32 ite8872_lpt, ite8872_lpthi;
2555 u8 ite8872_irq, type;
2556 int irq;
2557 int i;
2558
2559 DPRINTK(KERN_DEBUG "sio_ite_8872_probe()\n");
2560
2561 /* make sure which one chip */
2562 for (i = 0; i < 5; i++) {
2563 if (request_region(inta_addr[i], 32, "it887x")) {
2564 int test;
2565 pci_write_config_dword(pdev, 0x60,
2566 0xe5000000 | inta_addr[i]);
2567 pci_write_config_dword(pdev, 0x78,
2568 0x00000000 | inta_addr[i]);
2569 test = inb(inta_addr[i]);
2570 if (test != 0xff)
2571 break;
2572 release_region(inta_addr[i], 32);
2573 }
2574 }
2575 if (i >= 5) {
2576 printk(KERN_INFO "parport_pc: cannot find ITE8872 INTA\n");
2577 return 0;
2578 }
2579
2580 type = inb(inta_addr[i] + 0x18);
2581 type &= 0x0f;
2582
2583 switch (type) {
2584 case 0x2:
2585 printk(KERN_INFO "parport_pc: ITE8871 found (1P)\n");
2586 ite8872set = 0x64200000;
2587 break;
2588 case 0xa:
2589 printk(KERN_INFO "parport_pc: ITE8875 found (1P)\n");
2590 ite8872set = 0x64200000;
2591 break;
2592 case 0xe:
2593 printk(KERN_INFO "parport_pc: ITE8872 found (2S1P)\n");
2594 ite8872set = 0x64e00000;
2595 break;
2596 case 0x6:
2597 printk(KERN_INFO "parport_pc: ITE8873 found (1S)\n");
2598 return 0;
2599 case 0x8:
2600 printk(KERN_INFO "parport_pc: ITE8874 found (2S)\n");
2601 return 0;
2602 default:
2603 printk(KERN_INFO "parport_pc: unknown ITE887x\n");
2604 printk(KERN_INFO "parport_pc: please mail 'lspci -nvv' "
2605 "output to Rich.Liu@ite.com.tw\n");
2606 return 0;
2607 }
2608
2609 pci_read_config_byte(pdev, 0x3c, &ite8872_irq);
2610 pci_read_config_dword(pdev, 0x1c, &ite8872_lpt);
2611 ite8872_lpt &= 0x0000ff00;
2612 pci_read_config_dword(pdev, 0x20, &ite8872_lpthi);
2613 ite8872_lpthi &= 0x0000ff00;
2614 pci_write_config_dword(pdev, 0x6c, 0xe3000000 | ite8872_lpt);
2615 pci_write_config_dword(pdev, 0x70, 0xe3000000 | ite8872_lpthi);
2616 pci_write_config_dword(pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt);
2617 /* SET SPP&EPP , Parallel Port NO DMA , Enable All Function */
2618 /* SET Parallel IRQ */
2619 pci_write_config_dword(pdev, 0x9c,
2620 ite8872set | (ite8872_irq * 0x11111));
2621
2622 DPRINTK(KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq);
2623 DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n",
2624 ite8872_lpt);
2625 DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n",
2626 ite8872_lpthi);
2627
2628 /* Let the user (or defaults) steer us away from interrupts */
2629 irq = ite8872_irq;
2630 if (autoirq != PARPORT_IRQ_AUTO)
2631 irq = PARPORT_IRQ_NONE;
2632
2633 /*
2634 * Release the resource so that parport_pc_probe_port can get it.
2635 */
2636 release_region(inta_addr[i], 32);
2637 if (parport_pc_probe_port(ite8872_lpt, ite8872_lpthi,
2638 irq, PARPORT_DMA_NONE, &pdev->dev, 0)) {
2639 printk(KERN_INFO
2640 "parport_pc: ITE 8872 parallel port: io=0x%X",
2641 ite8872_lpt);
2642 if (irq != PARPORT_IRQ_NONE)
2643 printk(", irq=%d", irq);
2644 printk("\n");
2645 return 1;
2646 }
2647
2648 return 0;
2649}
2650
2651/* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru>
2652 based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */
2653static int __devinitdata parport_init_mode;
2654
2655/* Data for two known VIA chips */
2656static struct parport_pc_via_data via_686a_data __devinitdata = {
2657 0x51,
2658 0x50,
2659 0x85,
2660 0x02,
2661 0xE2,
2662 0xF0,
2663 0xE6
2664};
2665static struct parport_pc_via_data via_8231_data __devinitdata = {
2666 0x45,
2667 0x44,
2668 0x50,
2669 0x04,
2670 0xF2,
2671 0xFA,
2672 0xF6
2673};
2674
2675static int __devinit sio_via_probe(struct pci_dev *pdev, int autoirq,
2676 int autodma,
2677 const struct parport_pc_via_data *via)
2678{
2679 u8 tmp, tmp2, siofunc;
2680 u8 ppcontrol = 0;
2681 int dma, irq;
2682 unsigned port1, port2;
2683 unsigned have_epp = 0;
2684
2685 printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n");
2686
2687 switch (parport_init_mode) {
2688 case 1:
2689 printk(KERN_DEBUG "parport_pc: setting SPP mode\n");
2690 siofunc = VIA_FUNCTION_PARPORT_SPP;
2691 break;
2692 case 2:
2693 printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n");
2694 siofunc = VIA_FUNCTION_PARPORT_SPP;
2695 ppcontrol = VIA_PARPORT_BIDIR;
2696 break;
2697 case 3:
2698 printk(KERN_DEBUG "parport_pc: setting EPP mode\n");
2699 siofunc = VIA_FUNCTION_PARPORT_EPP;
2700 ppcontrol = VIA_PARPORT_BIDIR;
2701 have_epp = 1;
2702 break;
2703 case 4:
2704 printk(KERN_DEBUG "parport_pc: setting ECP mode\n");
2705 siofunc = VIA_FUNCTION_PARPORT_ECP;
2706 ppcontrol = VIA_PARPORT_BIDIR;
2707 break;
2708 case 5:
2709 printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n");
2710 siofunc = VIA_FUNCTION_PARPORT_ECP;
2711 ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP;
2712 have_epp = 1;
2713 break;
2714 default:
2715 printk(KERN_DEBUG
2716 "parport_pc: probing current configuration\n");
2717 siofunc = VIA_FUNCTION_PROBE;
2718 break;
2719 }
2720 /*
2721 * unlock super i/o configuration
2722 */
2723 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2724 tmp |= via->via_pci_superio_config_data;
2725 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2726
2727 /* Bits 1-0: Parallel Port Mode / Enable */
2728 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2729 tmp = inb(VIA_CONFIG_DATA);
2730 /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */
2731 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2732 tmp2 = inb(VIA_CONFIG_DATA);
2733 if (siofunc == VIA_FUNCTION_PROBE) {
2734 siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE;
2735 ppcontrol = tmp2;
2736 } else {
2737 tmp &= ~VIA_FUNCTION_PARPORT_DISABLE;
2738 tmp |= siofunc;
2739 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2740 outb(tmp, VIA_CONFIG_DATA);
2741 tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP);
2742 tmp2 |= ppcontrol;
2743 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2744 outb(tmp2, VIA_CONFIG_DATA);
2745 }
2746
2747 /* Parallel Port I/O Base Address, bits 9-2 */
2748 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2749 port1 = inb(VIA_CONFIG_DATA) << 2;
2750
2751 printk(KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",
2752 port1);
2753 if (port1 == 0x3BC && have_epp) {
2754 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2755 outb((0x378 >> 2), VIA_CONFIG_DATA);
2756 printk(KERN_DEBUG
2757 "parport_pc: Parallel port base changed to 0x378\n");
2758 port1 = 0x378;
2759 }
2760
2761 /*
2762 * lock super i/o configuration
2763 */
2764 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2765 tmp &= ~via->via_pci_superio_config_data;
2766 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2767
2768 if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) {
2769 printk(KERN_INFO "parport_pc: VIA parallel port disabled in BIOS\n");
2770 return 0;
2771 }
2772
2773 /* Bits 7-4: PnP Routing for Parallel Port IRQ */
2774 pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp);
2775 irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4);
2776
2777 if (siofunc == VIA_FUNCTION_PARPORT_ECP) {
2778 /* Bits 3-2: PnP Routing for Parallel Port DMA */
2779 pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp);
2780 dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2);
2781 } else
2782 /* if ECP not enabled, DMA is not enabled, assumed
2783 bogus 'dma' value */
2784 dma = PARPORT_DMA_NONE;
2785
2786 /* Let the user (or defaults) steer us away from interrupts and DMA */
2787 if (autoirq == PARPORT_IRQ_NONE) {
2788 irq = PARPORT_IRQ_NONE;
2789 dma = PARPORT_DMA_NONE;
2790 }
2791 if (autodma == PARPORT_DMA_NONE)
2792 dma = PARPORT_DMA_NONE;
2793
2794 switch (port1) {
2795 case 0x3bc:
2796 port2 = 0x7bc; break;
2797 case 0x378:
2798 port2 = 0x778; break;
2799 case 0x278:
2800 port2 = 0x678; break;
2801 default:
2802 printk(KERN_INFO
2803 "parport_pc: Weird VIA parport base 0x%X, ignoring\n",
2804 port1);
2805 return 0;
2806 }
2807
2808 /* filter bogus IRQs */
2809 switch (irq) {
2810 case 0:
2811 case 2:
2812 case 8:
2813 case 13:
2814 irq = PARPORT_IRQ_NONE;
2815 break;
2816
2817 default: /* do nothing */
2818 break;
2819 }
2820
2821 /* finally, do the probe with values obtained */
2822 if (parport_pc_probe_port(port1, port2, irq, dma, &pdev->dev, 0)) {
2823 printk(KERN_INFO
2824 "parport_pc: VIA parallel port: io=0x%X", port1);
2825 if (irq != PARPORT_IRQ_NONE)
2826 printk(", irq=%d", irq);
2827 if (dma != PARPORT_DMA_NONE)
2828 printk(", dma=%d", dma);
2829 printk("\n");
2830 return 1;
2831 }
2832
2833 printk(KERN_WARNING "parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n",
2834 port1, irq, dma);
2835 return 0;
2836}
2837
2838
2839enum parport_pc_sio_types {
2840 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */
2841 sio_via_8231, /* Via VT8231 south bridge integrated Super IO */
2842 sio_ite_8872,
2843 last_sio
2844};
2845
2846/* each element directly indexed from enum list, above */
2847static struct parport_pc_superio {
2848 int (*probe) (struct pci_dev *pdev, int autoirq, int autodma,
2849 const struct parport_pc_via_data *via);
2850 const struct parport_pc_via_data *via;
2851} parport_pc_superio_info[] __devinitdata = {
2852 { sio_via_probe, &via_686a_data, },
2853 { sio_via_probe, &via_8231_data, },
2854 { sio_ite_8872_probe, NULL, },
2855};
2856
2857enum parport_pc_pci_cards {
2858 siig_1p_10x = last_sio,
2859 siig_2p_10x,
2860 siig_1p_20x,
2861 siig_2p_20x,
2862 lava_parallel,
2863 lava_parallel_dual_a,
2864 lava_parallel_dual_b,
2865 boca_ioppar,
2866 plx_9050,
2867 timedia_4006a,
2868 timedia_4014,
2869 timedia_4008a,
2870 timedia_4018,
2871 timedia_9018a,
2872 syba_2p_epp,
2873 syba_1p_ecp,
2874 titan_010l,
2875 titan_1284p1,
2876 titan_1284p2,
2877 avlab_1p,
2878 avlab_2p,
2879 oxsemi_952,
2880 oxsemi_954,
2881 oxsemi_840,
2882 oxsemi_pcie_pport,
2883 aks_0100,
2884 mobility_pp,
2885 netmos_9705,
2886 netmos_9715,
2887 netmos_9755,
2888 netmos_9805,
2889 netmos_9815,
2890 netmos_9901,
2891 netmos_9865,
2892 quatech_sppxp100,
2893};
2894
2895
2896/* each element directly indexed from enum list, above
2897 * (but offset by last_sio) */
2898static struct parport_pc_pci {
2899 int numports;
2900 struct { /* BAR (base address registers) numbers in the config
2901 space header */
2902 int lo;
2903 int hi;
2904 /* -1 if not there, >6 for offset-method (max BAR is 6) */
2905 } addr[4];
2906
2907 /* If set, this is called immediately after pci_enable_device.
2908 * If it returns non-zero, no probing will take place and the
2909 * ports will not be used. */
2910 int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma);
2911
2912 /* If set, this is called after probing for ports. If 'failed'
2913 * is non-zero we couldn't use any of the ports. */
2914 void (*postinit_hook) (struct pci_dev *pdev, int failed);
2915} cards[] = {
2916 /* siig_1p_10x */ { 1, { { 2, 3 }, } },
2917 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } },
2918 /* siig_1p_20x */ { 1, { { 0, 1 }, } },
2919 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
2920 /* lava_parallel */ { 1, { { 0, -1 }, } },
2921 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
2922 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
2923 /* boca_ioppar */ { 1, { { 0, -1 }, } },
2924 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } },
2925 /* timedia_4006a */ { 1, { { 0, -1 }, } },
2926 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2927 /* timedia_4008a */ { 1, { { 0, 1 }, } },
2928 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2929 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
2930 /* SYBA uses fixed offsets in
2931 a 1K io window */
2932 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
2933 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
2934 /* titan_010l */ { 1, { { 3, -1 }, } },
2935 /* titan_1284p1 */ { 1, { { 0, 1 }, } },
2936 /* titan_1284p2 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2937 /* avlab_1p */ { 1, { { 0, 1}, } },
2938 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
2939 /* The Oxford Semi cards are unusual: 954 doesn't support ECP,
2940 * and 840 locks up if you write 1 to bit 2! */
2941 /* oxsemi_952 */ { 1, { { 0, 1 }, } },
2942 /* oxsemi_954 */ { 1, { { 0, -1 }, } },
2943 /* oxsemi_840 */ { 1, { { 0, 1 }, } },
2944 /* oxsemi_pcie_pport */ { 1, { { 0, 1 }, } },
2945 /* aks_0100 */ { 1, { { 0, -1 }, } },
2946 /* mobility_pp */ { 1, { { 0, 1 }, } },
2947
2948 /* The netmos entries below are untested */
2949 /* netmos_9705 */ { 1, { { 0, -1 }, } },
2950 /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} },
2951 /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} },
2952 /* netmos_9805 */ { 1, { { 0, -1 }, } },
2953 /* netmos_9815 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2954 /* netmos_9901 */ { 1, { { 0, -1 }, } },
2955 /* netmos_9865 */ { 1, { { 0, -1 }, } },
2956 /* quatech_sppxp100 */ { 1, { { 0, 1 }, } },
2957};
2958
2959static const struct pci_device_id parport_pc_pci_tbl[] = {
2960 /* Super-IO onboard chips */
2961 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
2962 { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 },
2963 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2964 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 },
2965
2966 /* PCI cards */
2967 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x,
2968 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
2969 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x,
2970 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
2971 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x,
2972 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
2973 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x,
2974 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
2975 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL,
2976 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
2977 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A,
2978 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
2979 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B,
2980 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
2981 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR,
2982 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
2983 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2984 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0, 0, plx_9050 },
2985 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
2986 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
2987 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
2988 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
2989 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
2990 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
2991 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
2992 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
2993 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
2994 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
2995 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L,
2996 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
2997 { 0x9710, 0x9805, 0x1000, 0x0010, 0, 0, titan_1284p1 },
2998 { 0x9710, 0x9815, 0x1000, 0x0020, 0, 0, titan_1284p2 },
2999 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
3000 /* AFAVLAB_TK9902 */
3001 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p},
3002 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p},
3003 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952PP,
3004 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_952 },
3005 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP,
3006 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
3007 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
3008 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
3009 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840,
3010 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
3011 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840_G,
3012 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
3013 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0,
3014 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
3015 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0_G,
3016 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
3017 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1,
3018 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
3019 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_G,
3020 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
3021 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_U,
3022 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
3023 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU,
3024 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
3025 { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
3026 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
3027 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
3028 /* NetMos communication controllers */
3029 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705,
3030 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 },
3031 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715,
3032 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 },
3033 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755,
3034 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 },
3035 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805,
3036 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 },
3037 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815,
3038 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 },
3039 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
3040 0xA000, 0x2000, 0, 0, netmos_9901 },
3041 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3042 0xA000, 0x1000, 0, 0, netmos_9865 },
3043 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3044 0xA000, 0x2000, 0, 0, netmos_9865 },
3045 /* Quatech SPPXP-100 Parallel port PCI ExpressCard */
3046 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SPPXP_100,
3047 PCI_ANY_ID, PCI_ANY_ID, 0, 0, quatech_sppxp100 },
3048 { 0, } /* terminate list */
3049};
3050MODULE_DEVICE_TABLE(pci, parport_pc_pci_tbl);
3051
3052struct pci_parport_data {
3053 int num;
3054 struct parport *ports[2];
3055};
3056
3057static int parport_pc_pci_probe(struct pci_dev *dev,
3058 const struct pci_device_id *id)
3059{
3060 int err, count, n, i = id->driver_data;
3061 struct pci_parport_data *data;
3062
3063 if (i < last_sio)
3064 /* This is an onboard Super-IO and has already been probed */
3065 return 0;
3066
3067 /* This is a PCI card */
3068 i -= last_sio;
3069 count = 0;
3070 err = pci_enable_device(dev);
3071 if (err)
3072 return err;
3073
3074 data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL);
3075 if (!data)
3076 return -ENOMEM;
3077
3078 if (cards[i].preinit_hook &&
3079 cards[i].preinit_hook(dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) {
3080 kfree(data);
3081 return -ENODEV;
3082 }
3083
3084 for (n = 0; n < cards[i].numports; n++) {
3085 int lo = cards[i].addr[n].lo;
3086 int hi = cards[i].addr[n].hi;
3087 int irq;
3088 unsigned long io_lo, io_hi;
3089 io_lo = pci_resource_start(dev, lo);
3090 io_hi = 0;
3091 if ((hi >= 0) && (hi <= 6))
3092 io_hi = pci_resource_start(dev, hi);
3093 else if (hi > 6)
3094 io_lo += hi; /* Reinterpret the meaning of
3095 "hi" as an offset (see SYBA
3096 def.) */
3097 /* TODO: test if sharing interrupts works */
3098 irq = dev->irq;
3099 if (irq == IRQ_NONE) {
3100 printk(KERN_DEBUG
3101 "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n",
3102 parport_pc_pci_tbl[i + last_sio].vendor,
3103 parport_pc_pci_tbl[i + last_sio].device,
3104 io_lo, io_hi);
3105 irq = PARPORT_IRQ_NONE;
3106 } else {
3107 printk(KERN_DEBUG
3108 "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n",
3109 parport_pc_pci_tbl[i + last_sio].vendor,
3110 parport_pc_pci_tbl[i + last_sio].device,
3111 io_lo, io_hi, irq);
3112 }
3113 data->ports[count] =
3114 parport_pc_probe_port(io_lo, io_hi, irq,
3115 PARPORT_DMA_NONE, &dev->dev,
3116 IRQF_SHARED);
3117 if (data->ports[count])
3118 count++;
3119 }
3120
3121 data->num = count;
3122
3123 if (cards[i].postinit_hook)
3124 cards[i].postinit_hook(dev, count == 0);
3125
3126 if (count) {
3127 pci_set_drvdata(dev, data);
3128 return 0;
3129 }
3130
3131 kfree(data);
3132
3133 return -ENODEV;
3134}
3135
3136static void __devexit parport_pc_pci_remove(struct pci_dev *dev)
3137{
3138 struct pci_parport_data *data = pci_get_drvdata(dev);
3139 int i;
3140
3141 pci_set_drvdata(dev, NULL);
3142
3143 if (data) {
3144 for (i = data->num - 1; i >= 0; i--)
3145 parport_pc_unregister_port(data->ports[i]);
3146
3147 kfree(data);
3148 }
3149}
3150
3151static struct pci_driver parport_pc_pci_driver = {
3152 .name = "parport_pc",
3153 .id_table = parport_pc_pci_tbl,
3154 .probe = parport_pc_pci_probe,
3155 .remove = __devexit_p(parport_pc_pci_remove),
3156};
3157
3158static int __init parport_pc_init_superio(int autoirq, int autodma)
3159{
3160 const struct pci_device_id *id;
3161 struct pci_dev *pdev = NULL;
3162 int ret = 0;
3163
3164 for_each_pci_dev(pdev) {
3165 id = pci_match_id(parport_pc_pci_tbl, pdev);
3166 if (id == NULL || id->driver_data >= last_sio)
3167 continue;
3168
3169 if (parport_pc_superio_info[id->driver_data].probe(
3170 pdev, autoirq, autodma,
3171 parport_pc_superio_info[id->driver_data].via)) {
3172 ret++;
3173 }
3174 }
3175
3176 return ret; /* number of devices found */
3177}
3178#else
3179static struct pci_driver parport_pc_pci_driver;
3180static int __init parport_pc_init_superio(int autoirq, int autodma)
3181{
3182 return 0;
3183}
3184#endif /* CONFIG_PCI */
3185
3186#ifdef CONFIG_PNP
3187
3188static const struct pnp_device_id parport_pc_pnp_tbl[] = {
3189 /* Standard LPT Printer Port */
3190 {.id = "PNP0400", .driver_data = 0},
3191 /* ECP Printer Port */
3192 {.id = "PNP0401", .driver_data = 0},
3193 { }
3194};
3195
3196MODULE_DEVICE_TABLE(pnp, parport_pc_pnp_tbl);
3197
3198static int parport_pc_pnp_probe(struct pnp_dev *dev,
3199 const struct pnp_device_id *id)
3200{
3201 struct parport *pdata;
3202 unsigned long io_lo, io_hi;
3203 int dma, irq;
3204
3205 if (pnp_port_valid(dev, 0) &&
3206 !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED)) {
3207 io_lo = pnp_port_start(dev, 0);
3208 } else
3209 return -EINVAL;
3210
3211 if (pnp_port_valid(dev, 1) &&
3212 !(pnp_port_flags(dev, 1) & IORESOURCE_DISABLED)) {
3213 io_hi = pnp_port_start(dev, 1);
3214 } else
3215 io_hi = 0;
3216
3217 if (pnp_irq_valid(dev, 0) &&
3218 !(pnp_irq_flags(dev, 0) & IORESOURCE_DISABLED)) {
3219 irq = pnp_irq(dev, 0);
3220 } else
3221 irq = PARPORT_IRQ_NONE;
3222
3223 if (pnp_dma_valid(dev, 0) &&
3224 !(pnp_dma_flags(dev, 0) & IORESOURCE_DISABLED)) {
3225 dma = pnp_dma(dev, 0);
3226 } else
3227 dma = PARPORT_DMA_NONE;
3228
3229 dev_info(&dev->dev, "reported by %s\n", dev->protocol->name);
3230 pdata = parport_pc_probe_port(io_lo, io_hi, irq, dma, &dev->dev, 0);
3231 if (pdata == NULL)
3232 return -ENODEV;
3233
3234 pnp_set_drvdata(dev, pdata);
3235 return 0;
3236}
3237
3238static void parport_pc_pnp_remove(struct pnp_dev *dev)
3239{
3240 struct parport *pdata = (struct parport *)pnp_get_drvdata(dev);
3241 if (!pdata)
3242 return;
3243
3244 parport_pc_unregister_port(pdata);
3245}
3246
3247/* we only need the pnp layer to activate the device, at least for now */
3248static struct pnp_driver parport_pc_pnp_driver = {
3249 .name = "parport_pc",
3250 .id_table = parport_pc_pnp_tbl,
3251 .probe = parport_pc_pnp_probe,
3252 .remove = parport_pc_pnp_remove,
3253};
3254
3255#else
3256static struct pnp_driver parport_pc_pnp_driver;
3257#endif /* CONFIG_PNP */
3258
3259static int __devinit parport_pc_platform_probe(struct platform_device *pdev)
3260{
3261 /* Always succeed, the actual probing is done in
3262 * parport_pc_probe_port(). */
3263 return 0;
3264}
3265
3266static struct platform_driver parport_pc_platform_driver = {
3267 .driver = {
3268 .owner = THIS_MODULE,
3269 .name = "parport_pc",
3270 },
3271 .probe = parport_pc_platform_probe,
3272};
3273
3274/* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */
3275static int __devinit __attribute__((unused))
3276parport_pc_find_isa_ports(int autoirq, int autodma)
3277{
3278 int count = 0;
3279
3280 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL, 0))
3281 count++;
3282 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL, 0))
3283 count++;
3284 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL, 0))
3285 count++;
3286
3287 return count;
3288}
3289
3290/* This function is called by parport_pc_init if the user didn't
3291 * specify any ports to probe. Its job is to find some ports. Order
3292 * is important here -- we want ISA ports to be registered first,
3293 * followed by PCI cards (for least surprise), but before that we want
3294 * to do chipset-specific tests for some onboard ports that we know
3295 * about.
3296 *
3297 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY
3298 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO
3299 */
3300static void __init parport_pc_find_ports(int autoirq, int autodma)
3301{
3302 int count = 0, err;
3303
3304#ifdef CONFIG_PARPORT_PC_SUPERIO
3305 detect_and_report_it87();
3306 detect_and_report_winbond();
3307 detect_and_report_smsc();
3308#endif
3309
3310 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */
3311 count += parport_pc_init_superio(autoirq, autodma);
3312
3313 /* PnP ports, skip detection if SuperIO already found them */
3314 if (!count) {
3315 err = pnp_register_driver(&parport_pc_pnp_driver);
3316 if (!err)
3317 pnp_registered_parport = 1;
3318 }
3319
3320 /* ISA ports and whatever (see asm/parport.h). */
3321 parport_pc_find_nonpci_ports(autoirq, autodma);
3322
3323 err = pci_register_driver(&parport_pc_pci_driver);
3324 if (!err)
3325 pci_registered_parport = 1;
3326}
3327
3328/*
3329 * Piles of crap below pretend to be a parser for module and kernel
3330 * parameters. Say "thank you" to whoever had come up with that
3331 * syntax and keep in mind that code below is a cleaned up version.
3332 */
3333
3334static int __initdata io[PARPORT_PC_MAX_PORTS+1] = {
3335 [0 ... PARPORT_PC_MAX_PORTS] = 0
3336};
3337static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] = {
3338 [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO
3339};
3340static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = {
3341 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE
3342};
3343static int __initdata irqval[PARPORT_PC_MAX_PORTS] = {
3344 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY
3345};
3346
3347static int __init parport_parse_param(const char *s, int *val,
3348 int automatic, int none, int nofifo)
3349{
3350 if (!s)
3351 return 0;
3352 if (!strncmp(s, "auto", 4))
3353 *val = automatic;
3354 else if (!strncmp(s, "none", 4))
3355 *val = none;
3356 else if (nofifo && !strncmp(s, "nofifo", 6))
3357 *val = nofifo;
3358 else {
3359 char *ep;
3360 unsigned long r = simple_strtoul(s, &ep, 0);
3361 if (ep != s)
3362 *val = r;
3363 else {
3364 printk(KERN_ERR "parport: bad specifier `%s'\n", s);
3365 return -1;
3366 }
3367 }
3368 return 0;
3369}
3370
3371static int __init parport_parse_irq(const char *irqstr, int *val)
3372{
3373 return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO,
3374 PARPORT_IRQ_NONE, 0);
3375}
3376
3377static int __init parport_parse_dma(const char *dmastr, int *val)
3378{
3379 return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO,
3380 PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO);
3381}
3382
3383#ifdef CONFIG_PCI
3384static int __init parport_init_mode_setup(char *str)
3385{
3386 printk(KERN_DEBUG
3387 "parport_pc.c: Specified parameter parport_init_mode=%s\n", str);
3388
3389 if (!strcmp(str, "spp"))
3390 parport_init_mode = 1;
3391 if (!strcmp(str, "ps2"))
3392 parport_init_mode = 2;
3393 if (!strcmp(str, "epp"))
3394 parport_init_mode = 3;
3395 if (!strcmp(str, "ecp"))
3396 parport_init_mode = 4;
3397 if (!strcmp(str, "ecpepp"))
3398 parport_init_mode = 5;
3399 return 1;
3400}
3401#endif
3402
3403#ifdef MODULE
3404static const char *irq[PARPORT_PC_MAX_PORTS];
3405static const char *dma[PARPORT_PC_MAX_PORTS];
3406
3407MODULE_PARM_DESC(io, "Base I/O address (SPP regs)");
3408module_param_array(io, int, NULL, 0);
3409MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)");
3410module_param_array(io_hi, int, NULL, 0);
3411MODULE_PARM_DESC(irq, "IRQ line");
3412module_param_array(irq, charp, NULL, 0);
3413MODULE_PARM_DESC(dma, "DMA channel");
3414module_param_array(dma, charp, NULL, 0);
3415#if defined(CONFIG_PARPORT_PC_SUPERIO) || \
3416 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
3417MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation");
3418module_param(verbose_probing, int, 0644);
3419#endif
3420#ifdef CONFIG_PCI
3421static char *init_mode;
3422MODULE_PARM_DESC(init_mode,
3423 "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)");
3424module_param(init_mode, charp, 0);
3425#endif
3426
3427static int __init parse_parport_params(void)
3428{
3429 unsigned int i;
3430 int val;
3431
3432#ifdef CONFIG_PCI
3433 if (init_mode)
3434 parport_init_mode_setup(init_mode);
3435#endif
3436
3437 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) {
3438 if (parport_parse_irq(irq[i], &val))
3439 return 1;
3440 irqval[i] = val;
3441 if (parport_parse_dma(dma[i], &val))
3442 return 1;
3443 dmaval[i] = val;
3444 }
3445 if (!io[0]) {
3446 /* The user can make us use any IRQs or DMAs we find. */
3447 if (irq[0] && !parport_parse_irq(irq[0], &val))
3448 switch (val) {
3449 case PARPORT_IRQ_NONE:
3450 case PARPORT_IRQ_AUTO:
3451 irqval[0] = val;
3452 break;
3453 default:
3454 printk(KERN_WARNING
3455 "parport_pc: irq specified "
3456 "without base address. Use 'io=' "
3457 "to specify one\n");
3458 }
3459
3460 if (dma[0] && !parport_parse_dma(dma[0], &val))
3461 switch (val) {
3462 case PARPORT_DMA_NONE:
3463 case PARPORT_DMA_AUTO:
3464 dmaval[0] = val;
3465 break;
3466 default:
3467 printk(KERN_WARNING
3468 "parport_pc: dma specified "
3469 "without base address. Use 'io=' "
3470 "to specify one\n");
3471 }
3472 }
3473 return 0;
3474}
3475
3476#else
3477
3478static int parport_setup_ptr __initdata;
3479
3480/*
3481 * Acceptable parameters:
3482 *
3483 * parport=0
3484 * parport=auto
3485 * parport=0xBASE[,IRQ[,DMA]]
3486 *
3487 * IRQ/DMA may be numeric or 'auto' or 'none'
3488 */
3489static int __init parport_setup(char *str)
3490{
3491 char *endptr;
3492 char *sep;
3493 int val;
3494
3495 if (!str || !*str || (*str == '0' && !*(str+1))) {
3496 /* Disable parport if "parport=0" in cmdline */
3497 io[0] = PARPORT_DISABLE;
3498 return 1;
3499 }
3500
3501 if (!strncmp(str, "auto", 4)) {
3502 irqval[0] = PARPORT_IRQ_AUTO;
3503 dmaval[0] = PARPORT_DMA_AUTO;
3504 return 1;
3505 }
3506
3507 val = simple_strtoul(str, &endptr, 0);
3508 if (endptr == str) {
3509 printk(KERN_WARNING "parport=%s not understood\n", str);
3510 return 1;
3511 }
3512
3513 if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) {
3514 printk(KERN_ERR "parport=%s ignored, too many ports\n", str);
3515 return 1;
3516 }
3517
3518 io[parport_setup_ptr] = val;
3519 irqval[parport_setup_ptr] = PARPORT_IRQ_NONE;
3520 dmaval[parport_setup_ptr] = PARPORT_DMA_NONE;
3521
3522 sep = strchr(str, ',');
3523 if (sep++) {
3524 if (parport_parse_irq(sep, &val))
3525 return 1;
3526 irqval[parport_setup_ptr] = val;
3527 sep = strchr(sep, ',');
3528 if (sep++) {
3529 if (parport_parse_dma(sep, &val))
3530 return 1;
3531 dmaval[parport_setup_ptr] = val;
3532 }
3533 }
3534 parport_setup_ptr++;
3535 return 1;
3536}
3537
3538static int __init parse_parport_params(void)
3539{
3540 return io[0] == PARPORT_DISABLE;
3541}
3542
3543__setup("parport=", parport_setup);
3544
3545/*
3546 * Acceptable parameters:
3547 *
3548 * parport_init_mode=[spp|ps2|epp|ecp|ecpepp]
3549 */
3550#ifdef CONFIG_PCI
3551__setup("parport_init_mode=", parport_init_mode_setup);
3552#endif
3553#endif
3554
3555/* "Parser" ends here */
3556
3557static int __init parport_pc_init(void)
3558{
3559 int err;
3560
3561 if (parse_parport_params())
3562 return -EINVAL;
3563
3564 err = platform_driver_register(&parport_pc_platform_driver);
3565 if (err)
3566 return err;
3567
3568 if (io[0]) {
3569 int i;
3570 /* Only probe the ports we were given. */
3571 user_specified = 1;
3572 for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) {
3573 if (!io[i])
3574 break;
3575 if (io_hi[i] == PARPORT_IOHI_AUTO)
3576 io_hi[i] = 0x400 + io[i];
3577 parport_pc_probe_port(io[i], io_hi[i],
3578 irqval[i], dmaval[i], NULL, 0);
3579 }
3580 } else
3581 parport_pc_find_ports(irqval[0], dmaval[0]);
3582
3583 return 0;
3584}
3585
3586static void __exit parport_pc_exit(void)
3587{
3588 if (pci_registered_parport)
3589 pci_unregister_driver(&parport_pc_pci_driver);
3590 if (pnp_registered_parport)
3591 pnp_unregister_driver(&parport_pc_pnp_driver);
3592 platform_driver_unregister(&parport_pc_platform_driver);
3593
3594 while (!list_empty(&ports_list)) {
3595 struct parport_pc_private *priv;
3596 struct parport *port;
3597 priv = list_entry(ports_list.next,
3598 struct parport_pc_private, list);
3599 port = priv->port;
3600 if (port->dev && port->dev->bus == &platform_bus_type)
3601 platform_device_unregister(
3602 to_platform_device(port->dev));
3603 parport_pc_unregister_port(port);
3604 }
3605}
3606
3607MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
3608MODULE_DESCRIPTION("PC-style parallel port driver");
3609MODULE_LICENSE("GPL");
3610module_init(parport_pc_init)
3611module_exit(parport_pc_exit)
1/* Low-level parallel-port routines for 8255-based PC-style hardware.
2 *
3 * Authors: Phil Blundell <philb@gnu.org>
4 * Tim Waugh <tim@cyberelk.demon.co.uk>
5 * Jose Renau <renau@acm.org>
6 * David Campbell
7 * Andrea Arcangeli
8 *
9 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell.
10 *
11 * Cleaned up include files - Russell King <linux@arm.uk.linux.org>
12 * DMA support - Bert De Jonghe <bert@sophis.be>
13 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999
14 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G.
15 * Various hacks, Fred Barnes, 04/2001
16 * Updated probing logic - Adam Belay <ambx1@neo.rr.com>
17 */
18
19/* This driver should work with any hardware that is broadly compatible
20 * with that in the IBM PC. This applies to the majority of integrated
21 * I/O chipsets that are commonly available. The expected register
22 * layout is:
23 *
24 * base+0 data
25 * base+1 status
26 * base+2 control
27 *
28 * In addition, there are some optional registers:
29 *
30 * base+3 EPP address
31 * base+4 EPP data
32 * base+0x400 ECP config A
33 * base+0x401 ECP config B
34 * base+0x402 ECP control
35 *
36 * All registers are 8 bits wide and read/write. If your hardware differs
37 * only in register addresses (eg because your registers are on 32-bit
38 * word boundaries) then you can alter the constants in parport_pc.h to
39 * accommodate this.
40 *
41 * Note that the ECP registers may not start at offset 0x400 for PCI cards,
42 * but rather will start at port->base_hi.
43 */
44
45#include <linux/module.h>
46#include <linux/init.h>
47#include <linux/sched.h>
48#include <linux/delay.h>
49#include <linux/errno.h>
50#include <linux/interrupt.h>
51#include <linux/ioport.h>
52#include <linux/kernel.h>
53#include <linux/slab.h>
54#include <linux/dma-mapping.h>
55#include <linux/pci.h>
56#include <linux/pnp.h>
57#include <linux/platform_device.h>
58#include <linux/sysctl.h>
59#include <linux/io.h>
60#include <linux/uaccess.h>
61
62#include <asm/dma.h>
63
64#include <linux/parport.h>
65#include <linux/parport_pc.h>
66#include <linux/via.h>
67#include <asm/parport.h>
68
69#define PARPORT_PC_MAX_PORTS PARPORT_MAX
70
71#ifdef CONFIG_ISA_DMA_API
72#define HAS_DMA
73#endif
74
75/* ECR modes */
76#define ECR_SPP 00
77#define ECR_PS2 01
78#define ECR_PPF 02
79#define ECR_ECP 03
80#define ECR_EPP 04
81#define ECR_VND 05
82#define ECR_TST 06
83#define ECR_CNF 07
84#define ECR_MODE_MASK 0xe0
85#define ECR_WRITE(p, v) frob_econtrol((p), 0xff, (v))
86
87#undef DEBUG
88
89#ifdef DEBUG
90#define DPRINTK printk
91#else
92#define DPRINTK(stuff...)
93#endif
94
95
96#define NR_SUPERIOS 3
97static struct superio_struct { /* For Super-IO chips autodetection */
98 int io;
99 int irq;
100 int dma;
101} superios[NR_SUPERIOS] = { {0,},};
102
103static int user_specified;
104#if defined(CONFIG_PARPORT_PC_SUPERIO) || \
105 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
106static int verbose_probing;
107#endif
108static int pci_registered_parport;
109static int pnp_registered_parport;
110
111/* frob_control, but for ECR */
112static void frob_econtrol(struct parport *pb, unsigned char m,
113 unsigned char v)
114{
115 unsigned char ectr = 0;
116
117 if (m != 0xff)
118 ectr = inb(ECONTROL(pb));
119
120 DPRINTK(KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n",
121 m, v, ectr, (ectr & ~m) ^ v);
122
123 outb((ectr & ~m) ^ v, ECONTROL(pb));
124}
125
126static inline void frob_set_mode(struct parport *p, int mode)
127{
128 frob_econtrol(p, ECR_MODE_MASK, mode << 5);
129}
130
131#ifdef CONFIG_PARPORT_PC_FIFO
132/* Safely change the mode bits in the ECR
133 Returns:
134 0 : Success
135 -EBUSY: Could not drain FIFO in some finite amount of time,
136 mode not changed!
137 */
138static int change_mode(struct parport *p, int m)
139{
140 const struct parport_pc_private *priv = p->physport->private_data;
141 unsigned char oecr;
142 int mode;
143
144 DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n", m);
145
146 if (!priv->ecr) {
147 printk(KERN_DEBUG "change_mode: but there's no ECR!\n");
148 return 0;
149 }
150
151 /* Bits <7:5> contain the mode. */
152 oecr = inb(ECONTROL(p));
153 mode = (oecr >> 5) & 0x7;
154 if (mode == m)
155 return 0;
156
157 if (mode >= 2 && !(priv->ctr & 0x20)) {
158 /* This mode resets the FIFO, so we may
159 * have to wait for it to drain first. */
160 unsigned long expire = jiffies + p->physport->cad->timeout;
161 int counter;
162 switch (mode) {
163 case ECR_PPF: /* Parallel Port FIFO mode */
164 case ECR_ECP: /* ECP Parallel Port mode */
165 /* Busy wait for 200us */
166 for (counter = 0; counter < 40; counter++) {
167 if (inb(ECONTROL(p)) & 0x01)
168 break;
169 if (signal_pending(current))
170 break;
171 udelay(5);
172 }
173
174 /* Poll slowly. */
175 while (!(inb(ECONTROL(p)) & 0x01)) {
176 if (time_after_eq(jiffies, expire))
177 /* The FIFO is stuck. */
178 return -EBUSY;
179 schedule_timeout_interruptible(
180 msecs_to_jiffies(10));
181 if (signal_pending(current))
182 break;
183 }
184 }
185 }
186
187 if (mode >= 2 && m >= 2) {
188 /* We have to go through mode 001 */
189 oecr &= ~(7 << 5);
190 oecr |= ECR_PS2 << 5;
191 ECR_WRITE(p, oecr);
192 }
193
194 /* Set the mode. */
195 oecr &= ~(7 << 5);
196 oecr |= m << 5;
197 ECR_WRITE(p, oecr);
198 return 0;
199}
200#endif /* FIFO support */
201
202/*
203 * Clear TIMEOUT BIT in EPP MODE
204 *
205 * This is also used in SPP detection.
206 */
207static int clear_epp_timeout(struct parport *pb)
208{
209 unsigned char r;
210
211 if (!(parport_pc_read_status(pb) & 0x01))
212 return 1;
213
214 /* To clear timeout some chips require double read */
215 parport_pc_read_status(pb);
216 r = parport_pc_read_status(pb);
217 outb(r | 0x01, STATUS(pb)); /* Some reset by writing 1 */
218 outb(r & 0xfe, STATUS(pb)); /* Others by writing 0 */
219 r = parport_pc_read_status(pb);
220
221 return !(r & 0x01);
222}
223
224/*
225 * Access functions.
226 *
227 * Most of these aren't static because they may be used by the
228 * parport_xxx_yyy macros. extern __inline__ versions of several
229 * of these are in parport_pc.h.
230 */
231
232static void parport_pc_init_state(struct pardevice *dev,
233 struct parport_state *s)
234{
235 s->u.pc.ctr = 0xc;
236 if (dev->irq_func &&
237 dev->port->irq != PARPORT_IRQ_NONE)
238 /* Set ackIntEn */
239 s->u.pc.ctr |= 0x10;
240
241 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24;
242 * D.Gruszka VScom */
243}
244
245static void parport_pc_save_state(struct parport *p, struct parport_state *s)
246{
247 const struct parport_pc_private *priv = p->physport->private_data;
248 s->u.pc.ctr = priv->ctr;
249 if (priv->ecr)
250 s->u.pc.ecr = inb(ECONTROL(p));
251}
252
253static void parport_pc_restore_state(struct parport *p,
254 struct parport_state *s)
255{
256 struct parport_pc_private *priv = p->physport->private_data;
257 register unsigned char c = s->u.pc.ctr & priv->ctr_writable;
258 outb(c, CONTROL(p));
259 priv->ctr = c;
260 if (priv->ecr)
261 ECR_WRITE(p, s->u.pc.ecr);
262}
263
264#ifdef CONFIG_PARPORT_1284
265static size_t parport_pc_epp_read_data(struct parport *port, void *buf,
266 size_t length, int flags)
267{
268 size_t got = 0;
269
270 if (flags & PARPORT_W91284PIC) {
271 unsigned char status;
272 size_t left = length;
273
274 /* use knowledge about data lines..:
275 * nFault is 0 if there is at least 1 byte in the Warp's FIFO
276 * pError is 1 if there are 16 bytes in the Warp's FIFO
277 */
278 status = inb(STATUS(port));
279
280 while (!(status & 0x08) && got < length) {
281 if (left >= 16 && (status & 0x20) && !(status & 0x08)) {
282 /* can grab 16 bytes from warp fifo */
283 if (!((long)buf & 0x03))
284 insl(EPPDATA(port), buf, 4);
285 else
286 insb(EPPDATA(port), buf, 16);
287 buf += 16;
288 got += 16;
289 left -= 16;
290 } else {
291 /* grab single byte from the warp fifo */
292 *((char *)buf) = inb(EPPDATA(port));
293 buf++;
294 got++;
295 left--;
296 }
297 status = inb(STATUS(port));
298 if (status & 0x01) {
299 /* EPP timeout should never occur... */
300 printk(KERN_DEBUG
301"%s: EPP timeout occurred while talking to w91284pic (should not have done)\n", port->name);
302 clear_epp_timeout(port);
303 }
304 }
305 return got;
306 }
307 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
308 if (!(((long)buf | length) & 0x03))
309 insl(EPPDATA(port), buf, (length >> 2));
310 else
311 insb(EPPDATA(port), buf, length);
312 if (inb(STATUS(port)) & 0x01) {
313 clear_epp_timeout(port);
314 return -EIO;
315 }
316 return length;
317 }
318 for (; got < length; got++) {
319 *((char *)buf) = inb(EPPDATA(port));
320 buf++;
321 if (inb(STATUS(port)) & 0x01) {
322 /* EPP timeout */
323 clear_epp_timeout(port);
324 break;
325 }
326 }
327
328 return got;
329}
330
331static size_t parport_pc_epp_write_data(struct parport *port, const void *buf,
332 size_t length, int flags)
333{
334 size_t written = 0;
335
336 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
337 if (!(((long)buf | length) & 0x03))
338 outsl(EPPDATA(port), buf, (length >> 2));
339 else
340 outsb(EPPDATA(port), buf, length);
341 if (inb(STATUS(port)) & 0x01) {
342 clear_epp_timeout(port);
343 return -EIO;
344 }
345 return length;
346 }
347 for (; written < length; written++) {
348 outb(*((char *)buf), EPPDATA(port));
349 buf++;
350 if (inb(STATUS(port)) & 0x01) {
351 clear_epp_timeout(port);
352 break;
353 }
354 }
355
356 return written;
357}
358
359static size_t parport_pc_epp_read_addr(struct parport *port, void *buf,
360 size_t length, int flags)
361{
362 size_t got = 0;
363
364 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
365 insb(EPPADDR(port), buf, length);
366 if (inb(STATUS(port)) & 0x01) {
367 clear_epp_timeout(port);
368 return -EIO;
369 }
370 return length;
371 }
372 for (; got < length; got++) {
373 *((char *)buf) = inb(EPPADDR(port));
374 buf++;
375 if (inb(STATUS(port)) & 0x01) {
376 clear_epp_timeout(port);
377 break;
378 }
379 }
380
381 return got;
382}
383
384static size_t parport_pc_epp_write_addr(struct parport *port,
385 const void *buf, size_t length,
386 int flags)
387{
388 size_t written = 0;
389
390 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
391 outsb(EPPADDR(port), buf, length);
392 if (inb(STATUS(port)) & 0x01) {
393 clear_epp_timeout(port);
394 return -EIO;
395 }
396 return length;
397 }
398 for (; written < length; written++) {
399 outb(*((char *)buf), EPPADDR(port));
400 buf++;
401 if (inb(STATUS(port)) & 0x01) {
402 clear_epp_timeout(port);
403 break;
404 }
405 }
406
407 return written;
408}
409
410static size_t parport_pc_ecpepp_read_data(struct parport *port, void *buf,
411 size_t length, int flags)
412{
413 size_t got;
414
415 frob_set_mode(port, ECR_EPP);
416 parport_pc_data_reverse(port);
417 parport_pc_write_control(port, 0x4);
418 got = parport_pc_epp_read_data(port, buf, length, flags);
419 frob_set_mode(port, ECR_PS2);
420
421 return got;
422}
423
424static size_t parport_pc_ecpepp_write_data(struct parport *port,
425 const void *buf, size_t length,
426 int flags)
427{
428 size_t written;
429
430 frob_set_mode(port, ECR_EPP);
431 parport_pc_write_control(port, 0x4);
432 parport_pc_data_forward(port);
433 written = parport_pc_epp_write_data(port, buf, length, flags);
434 frob_set_mode(port, ECR_PS2);
435
436 return written;
437}
438
439static size_t parport_pc_ecpepp_read_addr(struct parport *port, void *buf,
440 size_t length, int flags)
441{
442 size_t got;
443
444 frob_set_mode(port, ECR_EPP);
445 parport_pc_data_reverse(port);
446 parport_pc_write_control(port, 0x4);
447 got = parport_pc_epp_read_addr(port, buf, length, flags);
448 frob_set_mode(port, ECR_PS2);
449
450 return got;
451}
452
453static size_t parport_pc_ecpepp_write_addr(struct parport *port,
454 const void *buf, size_t length,
455 int flags)
456{
457 size_t written;
458
459 frob_set_mode(port, ECR_EPP);
460 parport_pc_write_control(port, 0x4);
461 parport_pc_data_forward(port);
462 written = parport_pc_epp_write_addr(port, buf, length, flags);
463 frob_set_mode(port, ECR_PS2);
464
465 return written;
466}
467#endif /* IEEE 1284 support */
468
469#ifdef CONFIG_PARPORT_PC_FIFO
470static size_t parport_pc_fifo_write_block_pio(struct parport *port,
471 const void *buf, size_t length)
472{
473 int ret = 0;
474 const unsigned char *bufp = buf;
475 size_t left = length;
476 unsigned long expire = jiffies + port->physport->cad->timeout;
477 const int fifo = FIFO(port);
478 int poll_for = 8; /* 80 usecs */
479 const struct parport_pc_private *priv = port->physport->private_data;
480 const int fifo_depth = priv->fifo_depth;
481
482 port = port->physport;
483
484 /* We don't want to be interrupted every character. */
485 parport_pc_disable_irq(port);
486 /* set nErrIntrEn and serviceIntr */
487 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
488
489 /* Forward mode. */
490 parport_pc_data_forward(port); /* Must be in PS2 mode */
491
492 while (left) {
493 unsigned char byte;
494 unsigned char ecrval = inb(ECONTROL(port));
495 int i = 0;
496
497 if (need_resched() && time_before(jiffies, expire))
498 /* Can't yield the port. */
499 schedule();
500
501 /* Anyone else waiting for the port? */
502 if (port->waithead) {
503 printk(KERN_DEBUG "Somebody wants the port\n");
504 break;
505 }
506
507 if (ecrval & 0x02) {
508 /* FIFO is full. Wait for interrupt. */
509
510 /* Clear serviceIntr */
511 ECR_WRITE(port, ecrval & ~(1<<2));
512false_alarm:
513 ret = parport_wait_event(port, HZ);
514 if (ret < 0)
515 break;
516 ret = 0;
517 if (!time_before(jiffies, expire)) {
518 /* Timed out. */
519 printk(KERN_DEBUG "FIFO write timed out\n");
520 break;
521 }
522 ecrval = inb(ECONTROL(port));
523 if (!(ecrval & (1<<2))) {
524 if (need_resched() &&
525 time_before(jiffies, expire))
526 schedule();
527
528 goto false_alarm;
529 }
530
531 continue;
532 }
533
534 /* Can't fail now. */
535 expire = jiffies + port->cad->timeout;
536
537poll:
538 if (signal_pending(current))
539 break;
540
541 if (ecrval & 0x01) {
542 /* FIFO is empty. Blast it full. */
543 const int n = left < fifo_depth ? left : fifo_depth;
544 outsb(fifo, bufp, n);
545 bufp += n;
546 left -= n;
547
548 /* Adjust the poll time. */
549 if (i < (poll_for - 2))
550 poll_for--;
551 continue;
552 } else if (i++ < poll_for) {
553 udelay(10);
554 ecrval = inb(ECONTROL(port));
555 goto poll;
556 }
557
558 /* Half-full(call me an optimist) */
559 byte = *bufp++;
560 outb(byte, fifo);
561 left--;
562 }
563 dump_parport_state("leave fifo_write_block_pio", port);
564 return length - left;
565}
566
567#ifdef HAS_DMA
568static size_t parport_pc_fifo_write_block_dma(struct parport *port,
569 const void *buf, size_t length)
570{
571 int ret = 0;
572 unsigned long dmaflag;
573 size_t left = length;
574 const struct parport_pc_private *priv = port->physport->private_data;
575 struct device *dev = port->physport->dev;
576 dma_addr_t dma_addr, dma_handle;
577 size_t maxlen = 0x10000; /* max 64k per DMA transfer */
578 unsigned long start = (unsigned long) buf;
579 unsigned long end = (unsigned long) buf + length - 1;
580
581 dump_parport_state("enter fifo_write_block_dma", port);
582 if (end < MAX_DMA_ADDRESS) {
583 /* If it would cross a 64k boundary, cap it at the end. */
584 if ((start ^ end) & ~0xffffUL)
585 maxlen = 0x10000 - (start & 0xffff);
586
587 dma_addr = dma_handle = dma_map_single(dev, (void *)buf, length,
588 DMA_TO_DEVICE);
589 } else {
590 /* above 16 MB we use a bounce buffer as ISA-DMA
591 is not possible */
592 maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */
593 dma_addr = priv->dma_handle;
594 dma_handle = 0;
595 }
596
597 port = port->physport;
598
599 /* We don't want to be interrupted every character. */
600 parport_pc_disable_irq(port);
601 /* set nErrIntrEn and serviceIntr */
602 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
603
604 /* Forward mode. */
605 parport_pc_data_forward(port); /* Must be in PS2 mode */
606
607 while (left) {
608 unsigned long expire = jiffies + port->physport->cad->timeout;
609
610 size_t count = left;
611
612 if (count > maxlen)
613 count = maxlen;
614
615 if (!dma_handle) /* bounce buffer ! */
616 memcpy(priv->dma_buf, buf, count);
617
618 dmaflag = claim_dma_lock();
619 disable_dma(port->dma);
620 clear_dma_ff(port->dma);
621 set_dma_mode(port->dma, DMA_MODE_WRITE);
622 set_dma_addr(port->dma, dma_addr);
623 set_dma_count(port->dma, count);
624
625 /* Set DMA mode */
626 frob_econtrol(port, 1<<3, 1<<3);
627
628 /* Clear serviceIntr */
629 frob_econtrol(port, 1<<2, 0);
630
631 enable_dma(port->dma);
632 release_dma_lock(dmaflag);
633
634 /* assume DMA will be successful */
635 left -= count;
636 buf += count;
637 if (dma_handle)
638 dma_addr += count;
639
640 /* Wait for interrupt. */
641false_alarm:
642 ret = parport_wait_event(port, HZ);
643 if (ret < 0)
644 break;
645 ret = 0;
646 if (!time_before(jiffies, expire)) {
647 /* Timed out. */
648 printk(KERN_DEBUG "DMA write timed out\n");
649 break;
650 }
651 /* Is serviceIntr set? */
652 if (!(inb(ECONTROL(port)) & (1<<2))) {
653 cond_resched();
654
655 goto false_alarm;
656 }
657
658 dmaflag = claim_dma_lock();
659 disable_dma(port->dma);
660 clear_dma_ff(port->dma);
661 count = get_dma_residue(port->dma);
662 release_dma_lock(dmaflag);
663
664 cond_resched(); /* Can't yield the port. */
665
666 /* Anyone else waiting for the port? */
667 if (port->waithead) {
668 printk(KERN_DEBUG "Somebody wants the port\n");
669 break;
670 }
671
672 /* update for possible DMA residue ! */
673 buf -= count;
674 left += count;
675 if (dma_handle)
676 dma_addr -= count;
677 }
678
679 /* Maybe got here through break, so adjust for DMA residue! */
680 dmaflag = claim_dma_lock();
681 disable_dma(port->dma);
682 clear_dma_ff(port->dma);
683 left += get_dma_residue(port->dma);
684 release_dma_lock(dmaflag);
685
686 /* Turn off DMA mode */
687 frob_econtrol(port, 1<<3, 0);
688
689 if (dma_handle)
690 dma_unmap_single(dev, dma_handle, length, DMA_TO_DEVICE);
691
692 dump_parport_state("leave fifo_write_block_dma", port);
693 return length - left;
694}
695#endif
696
697static inline size_t parport_pc_fifo_write_block(struct parport *port,
698 const void *buf, size_t length)
699{
700#ifdef HAS_DMA
701 if (port->dma != PARPORT_DMA_NONE)
702 return parport_pc_fifo_write_block_dma(port, buf, length);
703#endif
704 return parport_pc_fifo_write_block_pio(port, buf, length);
705}
706
707/* Parallel Port FIFO mode (ECP chipsets) */
708static size_t parport_pc_compat_write_block_pio(struct parport *port,
709 const void *buf, size_t length,
710 int flags)
711{
712 size_t written;
713 int r;
714 unsigned long expire;
715 const struct parport_pc_private *priv = port->physport->private_data;
716
717 /* Special case: a timeout of zero means we cannot call schedule().
718 * Also if O_NONBLOCK is set then use the default implementation. */
719 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
720 return parport_ieee1284_write_compat(port, buf,
721 length, flags);
722
723 /* Set up parallel port FIFO mode.*/
724 parport_pc_data_forward(port); /* Must be in PS2 mode */
725 parport_pc_frob_control(port, PARPORT_CONTROL_STROBE, 0);
726 r = change_mode(port, ECR_PPF); /* Parallel port FIFO */
727 if (r)
728 printk(KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n",
729 port->name);
730
731 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
732
733 /* Write the data to the FIFO. */
734 written = parport_pc_fifo_write_block(port, buf, length);
735
736 /* Finish up. */
737 /* For some hardware we don't want to touch the mode until
738 * the FIFO is empty, so allow 4 seconds for each position
739 * in the fifo.
740 */
741 expire = jiffies + (priv->fifo_depth * HZ * 4);
742 do {
743 /* Wait for the FIFO to empty */
744 r = change_mode(port, ECR_PS2);
745 if (r != -EBUSY)
746 break;
747 } while (time_before(jiffies, expire));
748 if (r == -EBUSY) {
749
750 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
751
752 /* Prevent further data transfer. */
753 frob_set_mode(port, ECR_TST);
754
755 /* Adjust for the contents of the FIFO. */
756 for (written -= priv->fifo_depth; ; written++) {
757 if (inb(ECONTROL(port)) & 0x2) {
758 /* Full up. */
759 break;
760 }
761 outb(0, FIFO(port));
762 }
763
764 /* Reset the FIFO and return to PS2 mode. */
765 frob_set_mode(port, ECR_PS2);
766 }
767
768 r = parport_wait_peripheral(port,
769 PARPORT_STATUS_BUSY,
770 PARPORT_STATUS_BUSY);
771 if (r)
772 printk(KERN_DEBUG
773 "%s: BUSY timeout (%d) in compat_write_block_pio\n",
774 port->name, r);
775
776 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
777
778 return written;
779}
780
781/* ECP */
782#ifdef CONFIG_PARPORT_1284
783static size_t parport_pc_ecp_write_block_pio(struct parport *port,
784 const void *buf, size_t length,
785 int flags)
786{
787 size_t written;
788 int r;
789 unsigned long expire;
790 const struct parport_pc_private *priv = port->physport->private_data;
791
792 /* Special case: a timeout of zero means we cannot call schedule().
793 * Also if O_NONBLOCK is set then use the default implementation. */
794 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
795 return parport_ieee1284_ecp_write_data(port, buf,
796 length, flags);
797
798 /* Switch to forward mode if necessary. */
799 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
800 /* Event 47: Set nInit high. */
801 parport_frob_control(port,
802 PARPORT_CONTROL_INIT
803 | PARPORT_CONTROL_AUTOFD,
804 PARPORT_CONTROL_INIT
805 | PARPORT_CONTROL_AUTOFD);
806
807 /* Event 49: PError goes high. */
808 r = parport_wait_peripheral(port,
809 PARPORT_STATUS_PAPEROUT,
810 PARPORT_STATUS_PAPEROUT);
811 if (r) {
812 printk(KERN_DEBUG "%s: PError timeout (%d) "
813 "in ecp_write_block_pio\n", port->name, r);
814 }
815 }
816
817 /* Set up ECP parallel port mode.*/
818 parport_pc_data_forward(port); /* Must be in PS2 mode */
819 parport_pc_frob_control(port,
820 PARPORT_CONTROL_STROBE |
821 PARPORT_CONTROL_AUTOFD,
822 0);
823 r = change_mode(port, ECR_ECP); /* ECP FIFO */
824 if (r)
825 printk(KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n",
826 port->name);
827 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
828
829 /* Write the data to the FIFO. */
830 written = parport_pc_fifo_write_block(port, buf, length);
831
832 /* Finish up. */
833 /* For some hardware we don't want to touch the mode until
834 * the FIFO is empty, so allow 4 seconds for each position
835 * in the fifo.
836 */
837 expire = jiffies + (priv->fifo_depth * (HZ * 4));
838 do {
839 /* Wait for the FIFO to empty */
840 r = change_mode(port, ECR_PS2);
841 if (r != -EBUSY)
842 break;
843 } while (time_before(jiffies, expire));
844 if (r == -EBUSY) {
845
846 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
847
848 /* Prevent further data transfer. */
849 frob_set_mode(port, ECR_TST);
850
851 /* Adjust for the contents of the FIFO. */
852 for (written -= priv->fifo_depth; ; written++) {
853 if (inb(ECONTROL(port)) & 0x2) {
854 /* Full up. */
855 break;
856 }
857 outb(0, FIFO(port));
858 }
859
860 /* Reset the FIFO and return to PS2 mode. */
861 frob_set_mode(port, ECR_PS2);
862
863 /* Host transfer recovery. */
864 parport_pc_data_reverse(port); /* Must be in PS2 mode */
865 udelay(5);
866 parport_frob_control(port, PARPORT_CONTROL_INIT, 0);
867 r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0);
868 if (r)
869 printk(KERN_DEBUG "%s: PE,1 timeout (%d) "
870 "in ecp_write_block_pio\n", port->name, r);
871
872 parport_frob_control(port,
873 PARPORT_CONTROL_INIT,
874 PARPORT_CONTROL_INIT);
875 r = parport_wait_peripheral(port,
876 PARPORT_STATUS_PAPEROUT,
877 PARPORT_STATUS_PAPEROUT);
878 if (r)
879 printk(KERN_DEBUG "%s: PE,2 timeout (%d) "
880 "in ecp_write_block_pio\n", port->name, r);
881 }
882
883 r = parport_wait_peripheral(port,
884 PARPORT_STATUS_BUSY,
885 PARPORT_STATUS_BUSY);
886 if (r)
887 printk(KERN_DEBUG
888 "%s: BUSY timeout (%d) in ecp_write_block_pio\n",
889 port->name, r);
890
891 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
892
893 return written;
894}
895#endif /* IEEE 1284 support */
896#endif /* Allowed to use FIFO/DMA */
897
898
899/*
900 * ******************************************
901 * INITIALISATION AND MODULE STUFF BELOW HERE
902 * ******************************************
903 */
904
905/* GCC is not inlining extern inline function later overwriten to non-inline,
906 so we use outlined_ variants here. */
907static const struct parport_operations parport_pc_ops = {
908 .write_data = parport_pc_write_data,
909 .read_data = parport_pc_read_data,
910
911 .write_control = parport_pc_write_control,
912 .read_control = parport_pc_read_control,
913 .frob_control = parport_pc_frob_control,
914
915 .read_status = parport_pc_read_status,
916
917 .enable_irq = parport_pc_enable_irq,
918 .disable_irq = parport_pc_disable_irq,
919
920 .data_forward = parport_pc_data_forward,
921 .data_reverse = parport_pc_data_reverse,
922
923 .init_state = parport_pc_init_state,
924 .save_state = parport_pc_save_state,
925 .restore_state = parport_pc_restore_state,
926
927 .epp_write_data = parport_ieee1284_epp_write_data,
928 .epp_read_data = parport_ieee1284_epp_read_data,
929 .epp_write_addr = parport_ieee1284_epp_write_addr,
930 .epp_read_addr = parport_ieee1284_epp_read_addr,
931
932 .ecp_write_data = parport_ieee1284_ecp_write_data,
933 .ecp_read_data = parport_ieee1284_ecp_read_data,
934 .ecp_write_addr = parport_ieee1284_ecp_write_addr,
935
936 .compat_write_data = parport_ieee1284_write_compat,
937 .nibble_read_data = parport_ieee1284_read_nibble,
938 .byte_read_data = parport_ieee1284_read_byte,
939
940 .owner = THIS_MODULE,
941};
942
943#ifdef CONFIG_PARPORT_PC_SUPERIO
944
945static struct superio_struct *find_free_superio(void)
946{
947 int i;
948 for (i = 0; i < NR_SUPERIOS; i++)
949 if (superios[i].io == 0)
950 return &superios[i];
951 return NULL;
952}
953
954
955/* Super-IO chipset detection, Winbond, SMSC */
956static void show_parconfig_smsc37c669(int io, int key)
957{
958 int cr1, cr4, cra, cr23, cr26, cr27;
959 struct superio_struct *s;
960
961 static const char *const modes[] = {
962 "SPP and Bidirectional (PS/2)",
963 "EPP and SPP",
964 "ECP",
965 "ECP and EPP" };
966
967 outb(key, io);
968 outb(key, io);
969 outb(1, io);
970 cr1 = inb(io + 1);
971 outb(4, io);
972 cr4 = inb(io + 1);
973 outb(0x0a, io);
974 cra = inb(io + 1);
975 outb(0x23, io);
976 cr23 = inb(io + 1);
977 outb(0x26, io);
978 cr26 = inb(io + 1);
979 outb(0x27, io);
980 cr27 = inb(io + 1);
981 outb(0xaa, io);
982
983 if (verbose_probing) {
984 printk(KERN_INFO
985 "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, "
986 "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n",
987 cr1, cr4, cra, cr23, cr26, cr27);
988
989 /* The documentation calls DMA and IRQ-Lines by letters, so
990 the board maker can/will wire them
991 appropriately/randomly... G=reserved H=IDE-irq, */
992 printk(KERN_INFO
993 "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, fifo threshold=%d\n",
994 cr23 * 4,
995 (cr27 & 0x0f) ? 'A' - 1 + (cr27 & 0x0f) : '-',
996 (cr26 & 0x0f) ? 'A' - 1 + (cr26 & 0x0f) : '-',
997 cra & 0x0f);
998 printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n",
999 (cr23 * 4 >= 0x100) ? "yes" : "no",
1000 (cr1 & 4) ? "yes" : "no");
1001 printk(KERN_INFO
1002 "SMSC LPT Config: Port mode=%s, EPP version =%s\n",
1003 (cr1 & 0x08) ? "Standard mode only (SPP)"
1004 : modes[cr4 & 0x03],
1005 (cr4 & 0x40) ? "1.7" : "1.9");
1006 }
1007
1008 /* Heuristics ! BIOS setup for this mainboard device limits
1009 the choices to standard settings, i.e. io-address and IRQ
1010 are related, however DMA can be 1 or 3, assume DMA_A=DMA1,
1011 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */
1012 if (cr23 * 4 >= 0x100) { /* if active */
1013 s = find_free_superio();
1014 if (s == NULL)
1015 printk(KERN_INFO "Super-IO: too many chips!\n");
1016 else {
1017 int d;
1018 switch (cr23 * 4) {
1019 case 0x3bc:
1020 s->io = 0x3bc;
1021 s->irq = 7;
1022 break;
1023 case 0x378:
1024 s->io = 0x378;
1025 s->irq = 7;
1026 break;
1027 case 0x278:
1028 s->io = 0x278;
1029 s->irq = 5;
1030 }
1031 d = (cr26 & 0x0f);
1032 if (d == 1 || d == 3)
1033 s->dma = d;
1034 else
1035 s->dma = PARPORT_DMA_NONE;
1036 }
1037 }
1038}
1039
1040
1041static void show_parconfig_winbond(int io, int key)
1042{
1043 int cr30, cr60, cr61, cr70, cr74, crf0;
1044 struct superio_struct *s;
1045 static const char *const modes[] = {
1046 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */
1047 "EPP-1.9 and SPP",
1048 "ECP",
1049 "ECP and EPP-1.9",
1050 "Standard (SPP)",
1051 "EPP-1.7 and SPP", /* 5 */
1052 "undefined!",
1053 "ECP and EPP-1.7" };
1054 static char *const irqtypes[] = {
1055 "pulsed low, high-Z",
1056 "follows nACK" };
1057
1058 /* The registers are called compatible-PnP because the
1059 register layout is modelled after ISA-PnP, the access
1060 method is just another ... */
1061 outb(key, io);
1062 outb(key, io);
1063 outb(0x07, io); /* Register 7: Select Logical Device */
1064 outb(0x01, io + 1); /* LD1 is Parallel Port */
1065 outb(0x30, io);
1066 cr30 = inb(io + 1);
1067 outb(0x60, io);
1068 cr60 = inb(io + 1);
1069 outb(0x61, io);
1070 cr61 = inb(io + 1);
1071 outb(0x70, io);
1072 cr70 = inb(io + 1);
1073 outb(0x74, io);
1074 cr74 = inb(io + 1);
1075 outb(0xf0, io);
1076 crf0 = inb(io + 1);
1077 outb(0xaa, io);
1078
1079 if (verbose_probing) {
1080 printk(KERN_INFO
1081 "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x 70=%02x 74=%02x, f0=%02x\n",
1082 cr30, cr60, cr61, cr70, cr74, crf0);
1083 printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
1084 (cr30 & 0x01) ? "yes" : "no", cr60, cr61, cr70 & 0x0f);
1085 if ((cr74 & 0x07) > 3)
1086 printk("dma=none\n");
1087 else
1088 printk("dma=%d\n", cr74 & 0x07);
1089 printk(KERN_INFO
1090 "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n",
1091 irqtypes[crf0>>7], (crf0>>3)&0x0f);
1092 printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n",
1093 modes[crf0 & 0x07]);
1094 }
1095
1096 if (cr30 & 0x01) { /* the settings can be interrogated later ... */
1097 s = find_free_superio();
1098 if (s == NULL)
1099 printk(KERN_INFO "Super-IO: too many chips!\n");
1100 else {
1101 s->io = (cr60 << 8) | cr61;
1102 s->irq = cr70 & 0x0f;
1103 s->dma = (((cr74 & 0x07) > 3) ?
1104 PARPORT_DMA_NONE : (cr74 & 0x07));
1105 }
1106 }
1107}
1108
1109static void decode_winbond(int efer, int key, int devid, int devrev, int oldid)
1110{
1111 const char *type = "unknown";
1112 int id, progif = 2;
1113
1114 if (devid == devrev)
1115 /* simple heuristics, we happened to read some
1116 non-winbond register */
1117 return;
1118
1119 id = (devid << 8) | devrev;
1120
1121 /* Values are from public data sheets pdf files, I can just
1122 confirm 83977TF is correct :-) */
1123 if (id == 0x9771)
1124 type = "83977F/AF";
1125 else if (id == 0x9773)
1126 type = "83977TF / SMSC 97w33x/97w34x";
1127 else if (id == 0x9774)
1128 type = "83977ATF";
1129 else if ((id & ~0x0f) == 0x5270)
1130 type = "83977CTF / SMSC 97w36x";
1131 else if ((id & ~0x0f) == 0x52f0)
1132 type = "83977EF / SMSC 97w35x";
1133 else if ((id & ~0x0f) == 0x5210)
1134 type = "83627";
1135 else if ((id & ~0x0f) == 0x6010)
1136 type = "83697HF";
1137 else if ((oldid & 0x0f) == 0x0a) {
1138 type = "83877F";
1139 progif = 1;
1140 } else if ((oldid & 0x0f) == 0x0b) {
1141 type = "83877AF";
1142 progif = 1;
1143 } else if ((oldid & 0x0f) == 0x0c) {
1144 type = "83877TF";
1145 progif = 1;
1146 } else if ((oldid & 0x0f) == 0x0d) {
1147 type = "83877ATF";
1148 progif = 1;
1149 } else
1150 progif = 0;
1151
1152 if (verbose_probing)
1153 printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x "
1154 "devid=%02x devrev=%02x oldid=%02x type=%s\n",
1155 efer, key, devid, devrev, oldid, type);
1156
1157 if (progif == 2)
1158 show_parconfig_winbond(efer, key);
1159}
1160
1161static void decode_smsc(int efer, int key, int devid, int devrev)
1162{
1163 const char *type = "unknown";
1164 void (*func)(int io, int key);
1165 int id;
1166
1167 if (devid == devrev)
1168 /* simple heuristics, we happened to read some
1169 non-smsc register */
1170 return;
1171
1172 func = NULL;
1173 id = (devid << 8) | devrev;
1174
1175 if (id == 0x0302) {
1176 type = "37c669";
1177 func = show_parconfig_smsc37c669;
1178 } else if (id == 0x6582)
1179 type = "37c665IR";
1180 else if (devid == 0x65)
1181 type = "37c665GT";
1182 else if (devid == 0x66)
1183 type = "37c666GT";
1184
1185 if (verbose_probing)
1186 printk(KERN_INFO "SMSC chip at EFER=0x%x "
1187 "key=0x%02x devid=%02x devrev=%02x type=%s\n",
1188 efer, key, devid, devrev, type);
1189
1190 if (func)
1191 func(efer, key);
1192}
1193
1194
1195static void winbond_check(int io, int key)
1196{
1197 int origval, devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1198
1199 if (!request_region(io, 3, __func__))
1200 return;
1201
1202 origval = inb(io); /* Save original value */
1203
1204 /* First probe without key */
1205 outb(0x20, io);
1206 x_devid = inb(io + 1);
1207 outb(0x21, io);
1208 x_devrev = inb(io + 1);
1209 outb(0x09, io);
1210 x_oldid = inb(io + 1);
1211
1212 outb(key, io);
1213 outb(key, io); /* Write Magic Sequence to EFER, extended
1214 function enable register */
1215 outb(0x20, io); /* Write EFIR, extended function index register */
1216 devid = inb(io + 1); /* Read EFDR, extended function data register */
1217 outb(0x21, io);
1218 devrev = inb(io + 1);
1219 outb(0x09, io);
1220 oldid = inb(io + 1);
1221 outb(0xaa, io); /* Magic Seal */
1222
1223 outb(origval, io); /* in case we poked some entirely different hardware */
1224
1225 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1226 goto out; /* protection against false positives */
1227
1228 decode_winbond(io, key, devid, devrev, oldid);
1229out:
1230 release_region(io, 3);
1231}
1232
1233static void winbond_check2(int io, int key)
1234{
1235 int origval[3], devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1236
1237 if (!request_region(io, 3, __func__))
1238 return;
1239
1240 origval[0] = inb(io); /* Save original values */
1241 origval[1] = inb(io + 1);
1242 origval[2] = inb(io + 2);
1243
1244 /* First probe without the key */
1245 outb(0x20, io + 2);
1246 x_devid = inb(io + 2);
1247 outb(0x21, io + 1);
1248 x_devrev = inb(io + 2);
1249 outb(0x09, io + 1);
1250 x_oldid = inb(io + 2);
1251
1252 outb(key, io); /* Write Magic Byte to EFER, extended
1253 function enable register */
1254 outb(0x20, io + 2); /* Write EFIR, extended function index register */
1255 devid = inb(io + 2); /* Read EFDR, extended function data register */
1256 outb(0x21, io + 1);
1257 devrev = inb(io + 2);
1258 outb(0x09, io + 1);
1259 oldid = inb(io + 2);
1260 outb(0xaa, io); /* Magic Seal */
1261
1262 outb(origval[0], io); /* in case we poked some entirely different hardware */
1263 outb(origval[1], io + 1);
1264 outb(origval[2], io + 2);
1265
1266 if (x_devid == devid && x_devrev == devrev && x_oldid == oldid)
1267 goto out; /* protection against false positives */
1268
1269 decode_winbond(io, key, devid, devrev, oldid);
1270out:
1271 release_region(io, 3);
1272}
1273
1274static void smsc_check(int io, int key)
1275{
1276 int origval, id, rev, oldid, oldrev, x_id, x_rev, x_oldid, x_oldrev;
1277
1278 if (!request_region(io, 3, __func__))
1279 return;
1280
1281 origval = inb(io); /* Save original value */
1282
1283 /* First probe without the key */
1284 outb(0x0d, io);
1285 x_oldid = inb(io + 1);
1286 outb(0x0e, io);
1287 x_oldrev = inb(io + 1);
1288 outb(0x20, io);
1289 x_id = inb(io + 1);
1290 outb(0x21, io);
1291 x_rev = inb(io + 1);
1292
1293 outb(key, io);
1294 outb(key, io); /* Write Magic Sequence to EFER, extended
1295 function enable register */
1296 outb(0x0d, io); /* Write EFIR, extended function index register */
1297 oldid = inb(io + 1); /* Read EFDR, extended function data register */
1298 outb(0x0e, io);
1299 oldrev = inb(io + 1);
1300 outb(0x20, io);
1301 id = inb(io + 1);
1302 outb(0x21, io);
1303 rev = inb(io + 1);
1304 outb(0xaa, io); /* Magic Seal */
1305
1306 outb(origval, io); /* in case we poked some entirely different hardware */
1307
1308 if (x_id == id && x_oldrev == oldrev &&
1309 x_oldid == oldid && x_rev == rev)
1310 goto out; /* protection against false positives */
1311
1312 decode_smsc(io, key, oldid, oldrev);
1313out:
1314 release_region(io, 3);
1315}
1316
1317
1318static void detect_and_report_winbond(void)
1319{
1320 if (verbose_probing)
1321 printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n");
1322 winbond_check(0x3f0, 0x87);
1323 winbond_check(0x370, 0x87);
1324 winbond_check(0x2e , 0x87);
1325 winbond_check(0x4e , 0x87);
1326 winbond_check(0x3f0, 0x86);
1327 winbond_check2(0x250, 0x88);
1328 winbond_check2(0x250, 0x89);
1329}
1330
1331static void detect_and_report_smsc(void)
1332{
1333 if (verbose_probing)
1334 printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n");
1335 smsc_check(0x3f0, 0x55);
1336 smsc_check(0x370, 0x55);
1337 smsc_check(0x3f0, 0x44);
1338 smsc_check(0x370, 0x44);
1339}
1340
1341static void detect_and_report_it87(void)
1342{
1343 u16 dev;
1344 u8 origval, r;
1345 if (verbose_probing)
1346 printk(KERN_DEBUG "IT8705 Super-IO detection, now testing port 2E ...\n");
1347 if (!request_muxed_region(0x2e, 2, __func__))
1348 return;
1349 origval = inb(0x2e); /* Save original value */
1350 outb(0x87, 0x2e);
1351 outb(0x01, 0x2e);
1352 outb(0x55, 0x2e);
1353 outb(0x55, 0x2e);
1354 outb(0x20, 0x2e);
1355 dev = inb(0x2f) << 8;
1356 outb(0x21, 0x2e);
1357 dev |= inb(0x2f);
1358 if (dev == 0x8712 || dev == 0x8705 || dev == 0x8715 ||
1359 dev == 0x8716 || dev == 0x8718 || dev == 0x8726) {
1360 printk(KERN_INFO "IT%04X SuperIO detected.\n", dev);
1361 outb(0x07, 0x2E); /* Parallel Port */
1362 outb(0x03, 0x2F);
1363 outb(0xF0, 0x2E); /* BOOT 0x80 off */
1364 r = inb(0x2f);
1365 outb(0xF0, 0x2E);
1366 outb(r | 8, 0x2F);
1367 outb(0x02, 0x2E); /* Lock */
1368 outb(0x02, 0x2F);
1369 } else {
1370 outb(origval, 0x2e); /* Oops, sorry to disturb */
1371 }
1372 release_region(0x2e, 2);
1373}
1374#endif /* CONFIG_PARPORT_PC_SUPERIO */
1375
1376static struct superio_struct *find_superio(struct parport *p)
1377{
1378 int i;
1379 for (i = 0; i < NR_SUPERIOS; i++)
1380 if (superios[i].io != p->base)
1381 return &superios[i];
1382 return NULL;
1383}
1384
1385static int get_superio_dma(struct parport *p)
1386{
1387 struct superio_struct *s = find_superio(p);
1388 if (s)
1389 return s->dma;
1390 return PARPORT_DMA_NONE;
1391}
1392
1393static int get_superio_irq(struct parport *p)
1394{
1395 struct superio_struct *s = find_superio(p);
1396 if (s)
1397 return s->irq;
1398 return PARPORT_IRQ_NONE;
1399}
1400
1401
1402/* --- Mode detection ------------------------------------- */
1403
1404/*
1405 * Checks for port existence, all ports support SPP MODE
1406 * Returns:
1407 * 0 : No parallel port at this address
1408 * PARPORT_MODE_PCSPP : SPP port detected
1409 * (if the user specified an ioport himself,
1410 * this shall always be the case!)
1411 *
1412 */
1413static int parport_SPP_supported(struct parport *pb)
1414{
1415 unsigned char r, w;
1416
1417 /*
1418 * first clear an eventually pending EPP timeout
1419 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset
1420 * that does not even respond to SPP cycles if an EPP
1421 * timeout is pending
1422 */
1423 clear_epp_timeout(pb);
1424
1425 /* Do a simple read-write test to make sure the port exists. */
1426 w = 0xc;
1427 outb(w, CONTROL(pb));
1428
1429 /* Is there a control register that we can read from? Some
1430 * ports don't allow reads, so read_control just returns a
1431 * software copy. Some ports _do_ allow reads, so bypass the
1432 * software copy here. In addition, some bits aren't
1433 * writable. */
1434 r = inb(CONTROL(pb));
1435 if ((r & 0xf) == w) {
1436 w = 0xe;
1437 outb(w, CONTROL(pb));
1438 r = inb(CONTROL(pb));
1439 outb(0xc, CONTROL(pb));
1440 if ((r & 0xf) == w)
1441 return PARPORT_MODE_PCSPP;
1442 }
1443
1444 if (user_specified)
1445 /* That didn't work, but the user thinks there's a
1446 * port here. */
1447 printk(KERN_INFO "parport 0x%lx (WARNING): CTR: "
1448 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1449
1450 /* Try the data register. The data lines aren't tri-stated at
1451 * this stage, so we expect back what we wrote. */
1452 w = 0xaa;
1453 parport_pc_write_data(pb, w);
1454 r = parport_pc_read_data(pb);
1455 if (r == w) {
1456 w = 0x55;
1457 parport_pc_write_data(pb, w);
1458 r = parport_pc_read_data(pb);
1459 if (r == w)
1460 return PARPORT_MODE_PCSPP;
1461 }
1462
1463 if (user_specified) {
1464 /* Didn't work, but the user is convinced this is the
1465 * place. */
1466 printk(KERN_INFO "parport 0x%lx (WARNING): DATA: "
1467 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1468 printk(KERN_INFO "parport 0x%lx: You gave this address, "
1469 "but there is probably no parallel port there!\n",
1470 pb->base);
1471 }
1472
1473 /* It's possible that we can't read the control register or
1474 * the data register. In that case just believe the user. */
1475 if (user_specified)
1476 return PARPORT_MODE_PCSPP;
1477
1478 return 0;
1479}
1480
1481/* Check for ECR
1482 *
1483 * Old style XT ports alias io ports every 0x400, hence accessing ECR
1484 * on these cards actually accesses the CTR.
1485 *
1486 * Modern cards don't do this but reading from ECR will return 0xff
1487 * regardless of what is written here if the card does NOT support
1488 * ECP.
1489 *
1490 * We first check to see if ECR is the same as CTR. If not, the low
1491 * two bits of ECR aren't writable, so we check by writing ECR and
1492 * reading it back to see if it's what we expect.
1493 */
1494static int parport_ECR_present(struct parport *pb)
1495{
1496 struct parport_pc_private *priv = pb->private_data;
1497 unsigned char r = 0xc;
1498
1499 outb(r, CONTROL(pb));
1500 if ((inb(ECONTROL(pb)) & 0x3) == (r & 0x3)) {
1501 outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */
1502
1503 r = inb(CONTROL(pb));
1504 if ((inb(ECONTROL(pb)) & 0x2) == (r & 0x2))
1505 goto no_reg; /* Sure that no ECR register exists */
1506 }
1507
1508 if ((inb(ECONTROL(pb)) & 0x3) != 0x1)
1509 goto no_reg;
1510
1511 ECR_WRITE(pb, 0x34);
1512 if (inb(ECONTROL(pb)) != 0x35)
1513 goto no_reg;
1514
1515 priv->ecr = 1;
1516 outb(0xc, CONTROL(pb));
1517
1518 /* Go to mode 000 */
1519 frob_set_mode(pb, ECR_SPP);
1520
1521 return 1;
1522
1523 no_reg:
1524 outb(0xc, CONTROL(pb));
1525 return 0;
1526}
1527
1528#ifdef CONFIG_PARPORT_1284
1529/* Detect PS/2 support.
1530 *
1531 * Bit 5 (0x20) sets the PS/2 data direction; setting this high
1532 * allows us to read data from the data lines. In theory we would get back
1533 * 0xff but any peripheral attached to the port may drag some or all of the
1534 * lines down to zero. So if we get back anything that isn't the contents
1535 * of the data register we deem PS/2 support to be present.
1536 *
1537 * Some SPP ports have "half PS/2" ability - you can't turn off the line
1538 * drivers, but an external peripheral with sufficiently beefy drivers of
1539 * its own can overpower them and assert its own levels onto the bus, from
1540 * where they can then be read back as normal. Ports with this property
1541 * and the right type of device attached are likely to fail the SPP test,
1542 * (as they will appear to have stuck bits) and so the fact that they might
1543 * be misdetected here is rather academic.
1544 */
1545
1546static int parport_PS2_supported(struct parport *pb)
1547{
1548 int ok = 0;
1549
1550 clear_epp_timeout(pb);
1551
1552 /* try to tri-state the buffer */
1553 parport_pc_data_reverse(pb);
1554
1555 parport_pc_write_data(pb, 0x55);
1556 if (parport_pc_read_data(pb) != 0x55)
1557 ok++;
1558
1559 parport_pc_write_data(pb, 0xaa);
1560 if (parport_pc_read_data(pb) != 0xaa)
1561 ok++;
1562
1563 /* cancel input mode */
1564 parport_pc_data_forward(pb);
1565
1566 if (ok) {
1567 pb->modes |= PARPORT_MODE_TRISTATE;
1568 } else {
1569 struct parport_pc_private *priv = pb->private_data;
1570 priv->ctr_writable &= ~0x20;
1571 }
1572
1573 return ok;
1574}
1575
1576#ifdef CONFIG_PARPORT_PC_FIFO
1577static int parport_ECP_supported(struct parport *pb)
1578{
1579 int i;
1580 int config, configb;
1581 int pword;
1582 struct parport_pc_private *priv = pb->private_data;
1583 /* Translate ECP intrLine to ISA irq value */
1584 static const int intrline[] = { 0, 7, 9, 10, 11, 14, 15, 5 };
1585
1586 /* If there is no ECR, we have no hope of supporting ECP. */
1587 if (!priv->ecr)
1588 return 0;
1589
1590 /* Find out FIFO depth */
1591 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1592 ECR_WRITE(pb, ECR_TST << 5); /* TEST FIFO */
1593 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02); i++)
1594 outb(0xaa, FIFO(pb));
1595
1596 /*
1597 * Using LGS chipset it uses ECR register, but
1598 * it doesn't support ECP or FIFO MODE
1599 */
1600 if (i == 1024) {
1601 ECR_WRITE(pb, ECR_SPP << 5);
1602 return 0;
1603 }
1604
1605 priv->fifo_depth = i;
1606 if (verbose_probing)
1607 printk(KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i);
1608
1609 /* Find out writeIntrThreshold */
1610 frob_econtrol(pb, 1<<2, 1<<2);
1611 frob_econtrol(pb, 1<<2, 0);
1612 for (i = 1; i <= priv->fifo_depth; i++) {
1613 inb(FIFO(pb));
1614 udelay(50);
1615 if (inb(ECONTROL(pb)) & (1<<2))
1616 break;
1617 }
1618
1619 if (i <= priv->fifo_depth) {
1620 if (verbose_probing)
1621 printk(KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n",
1622 pb->base, i);
1623 } else
1624 /* Number of bytes we know we can write if we get an
1625 interrupt. */
1626 i = 0;
1627
1628 priv->writeIntrThreshold = i;
1629
1630 /* Find out readIntrThreshold */
1631 frob_set_mode(pb, ECR_PS2); /* Reset FIFO and enable PS2 */
1632 parport_pc_data_reverse(pb); /* Must be in PS2 mode */
1633 frob_set_mode(pb, ECR_TST); /* Test FIFO */
1634 frob_econtrol(pb, 1<<2, 1<<2);
1635 frob_econtrol(pb, 1<<2, 0);
1636 for (i = 1; i <= priv->fifo_depth; i++) {
1637 outb(0xaa, FIFO(pb));
1638 if (inb(ECONTROL(pb)) & (1<<2))
1639 break;
1640 }
1641
1642 if (i <= priv->fifo_depth) {
1643 if (verbose_probing)
1644 printk(KERN_INFO "0x%lx: readIntrThreshold is %d\n",
1645 pb->base, i);
1646 } else
1647 /* Number of bytes we can read if we get an interrupt. */
1648 i = 0;
1649
1650 priv->readIntrThreshold = i;
1651
1652 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1653 ECR_WRITE(pb, 0xf4); /* Configuration mode */
1654 config = inb(CONFIGA(pb));
1655 pword = (config >> 4) & 0x7;
1656 switch (pword) {
1657 case 0:
1658 pword = 2;
1659 printk(KERN_WARNING "0x%lx: Unsupported pword size!\n",
1660 pb->base);
1661 break;
1662 case 2:
1663 pword = 4;
1664 printk(KERN_WARNING "0x%lx: Unsupported pword size!\n",
1665 pb->base);
1666 break;
1667 default:
1668 printk(KERN_WARNING "0x%lx: Unknown implementation ID\n",
1669 pb->base);
1670 /* Assume 1 */
1671 case 1:
1672 pword = 1;
1673 }
1674 priv->pword = pword;
1675
1676 if (verbose_probing) {
1677 printk(KERN_DEBUG "0x%lx: PWord is %d bits\n",
1678 pb->base, 8 * pword);
1679
1680 printk(KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base,
1681 config & 0x80 ? "Level" : "Pulses");
1682
1683 configb = inb(CONFIGB(pb));
1684 printk(KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
1685 pb->base, config, configb);
1686 printk(KERN_DEBUG "0x%lx: ECP settings irq=", pb->base);
1687 if ((configb >> 3) & 0x07)
1688 printk("%d", intrline[(configb >> 3) & 0x07]);
1689 else
1690 printk("<none or set by other means>");
1691 printk(" dma=");
1692 if ((configb & 0x03) == 0x00)
1693 printk("<none or set by other means>\n");
1694 else
1695 printk("%d\n", configb & 0x07);
1696 }
1697
1698 /* Go back to mode 000 */
1699 frob_set_mode(pb, ECR_SPP);
1700
1701 return 1;
1702}
1703#endif
1704
1705#ifdef CONFIG_X86_32
1706static int intel_bug_present_check_epp(struct parport *pb)
1707{
1708 const struct parport_pc_private *priv = pb->private_data;
1709 int bug_present = 0;
1710
1711 if (priv->ecr) {
1712 /* store value of ECR */
1713 unsigned char ecr = inb(ECONTROL(pb));
1714 unsigned char i;
1715 for (i = 0x00; i < 0x80; i += 0x20) {
1716 ECR_WRITE(pb, i);
1717 if (clear_epp_timeout(pb)) {
1718 /* Phony EPP in ECP. */
1719 bug_present = 1;
1720 break;
1721 }
1722 }
1723 /* return ECR into the inital state */
1724 ECR_WRITE(pb, ecr);
1725 }
1726
1727 return bug_present;
1728}
1729static int intel_bug_present(struct parport *pb)
1730{
1731/* Check whether the device is legacy, not PCI or PCMCIA. Only legacy is known to be affected. */
1732 if (pb->dev != NULL) {
1733 return 0;
1734 }
1735
1736 return intel_bug_present_check_epp(pb);
1737}
1738#else
1739static int intel_bug_present(struct parport *pb)
1740{
1741 return 0;
1742}
1743#endif /* CONFIG_X86_32 */
1744
1745static int parport_ECPPS2_supported(struct parport *pb)
1746{
1747 const struct parport_pc_private *priv = pb->private_data;
1748 int result;
1749 unsigned char oecr;
1750
1751 if (!priv->ecr)
1752 return 0;
1753
1754 oecr = inb(ECONTROL(pb));
1755 ECR_WRITE(pb, ECR_PS2 << 5);
1756 result = parport_PS2_supported(pb);
1757 ECR_WRITE(pb, oecr);
1758 return result;
1759}
1760
1761/* EPP mode detection */
1762
1763static int parport_EPP_supported(struct parport *pb)
1764{
1765 /*
1766 * Theory:
1767 * Bit 0 of STR is the EPP timeout bit, this bit is 0
1768 * when EPP is possible and is set high when an EPP timeout
1769 * occurs (EPP uses the HALT line to stop the CPU while it does
1770 * the byte transfer, an EPP timeout occurs if the attached
1771 * device fails to respond after 10 micro seconds).
1772 *
1773 * This bit is cleared by either reading it (National Semi)
1774 * or writing a 1 to the bit (SMC, UMC, WinBond), others ???
1775 * This bit is always high in non EPP modes.
1776 */
1777
1778 /* If EPP timeout bit clear then EPP available */
1779 if (!clear_epp_timeout(pb))
1780 return 0; /* No way to clear timeout */
1781
1782 /* Check for Intel bug. */
1783 if (intel_bug_present(pb))
1784 return 0;
1785
1786 pb->modes |= PARPORT_MODE_EPP;
1787
1788 /* Set up access functions to use EPP hardware. */
1789 pb->ops->epp_read_data = parport_pc_epp_read_data;
1790 pb->ops->epp_write_data = parport_pc_epp_write_data;
1791 pb->ops->epp_read_addr = parport_pc_epp_read_addr;
1792 pb->ops->epp_write_addr = parport_pc_epp_write_addr;
1793
1794 return 1;
1795}
1796
1797static int parport_ECPEPP_supported(struct parport *pb)
1798{
1799 struct parport_pc_private *priv = pb->private_data;
1800 int result;
1801 unsigned char oecr;
1802
1803 if (!priv->ecr)
1804 return 0;
1805
1806 oecr = inb(ECONTROL(pb));
1807 /* Search for SMC style EPP+ECP mode */
1808 ECR_WRITE(pb, 0x80);
1809 outb(0x04, CONTROL(pb));
1810 result = parport_EPP_supported(pb);
1811
1812 ECR_WRITE(pb, oecr);
1813
1814 if (result) {
1815 /* Set up access functions to use ECP+EPP hardware. */
1816 pb->ops->epp_read_data = parport_pc_ecpepp_read_data;
1817 pb->ops->epp_write_data = parport_pc_ecpepp_write_data;
1818 pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr;
1819 pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr;
1820 }
1821
1822 return result;
1823}
1824
1825#else /* No IEEE 1284 support */
1826
1827/* Don't bother probing for modes we know we won't use. */
1828static int parport_PS2_supported(struct parport *pb) { return 0; }
1829#ifdef CONFIG_PARPORT_PC_FIFO
1830static int parport_ECP_supported(struct parport *pb)
1831{
1832 return 0;
1833}
1834#endif
1835static int parport_EPP_supported(struct parport *pb)
1836{
1837 return 0;
1838}
1839
1840static int parport_ECPEPP_supported(struct parport *pb)
1841{
1842 return 0;
1843}
1844
1845static int parport_ECPPS2_supported(struct parport *pb)
1846{
1847 return 0;
1848}
1849
1850#endif /* No IEEE 1284 support */
1851
1852/* --- IRQ detection -------------------------------------- */
1853
1854/* Only if supports ECP mode */
1855static int programmable_irq_support(struct parport *pb)
1856{
1857 int irq, intrLine;
1858 unsigned char oecr = inb(ECONTROL(pb));
1859 static const int lookup[8] = {
1860 PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5
1861 };
1862
1863 ECR_WRITE(pb, ECR_CNF << 5); /* Configuration MODE */
1864
1865 intrLine = (inb(CONFIGB(pb)) >> 3) & 0x07;
1866 irq = lookup[intrLine];
1867
1868 ECR_WRITE(pb, oecr);
1869 return irq;
1870}
1871
1872static int irq_probe_ECP(struct parport *pb)
1873{
1874 int i;
1875 unsigned long irqs;
1876
1877 irqs = probe_irq_on();
1878
1879 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1880 ECR_WRITE(pb, (ECR_TST << 5) | 0x04);
1881 ECR_WRITE(pb, ECR_TST << 5);
1882
1883 /* If Full FIFO sure that writeIntrThreshold is generated */
1884 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02) ; i++)
1885 outb(0xaa, FIFO(pb));
1886
1887 pb->irq = probe_irq_off(irqs);
1888 ECR_WRITE(pb, ECR_SPP << 5);
1889
1890 if (pb->irq <= 0)
1891 pb->irq = PARPORT_IRQ_NONE;
1892
1893 return pb->irq;
1894}
1895
1896/*
1897 * This detection seems that only works in National Semiconductors
1898 * This doesn't work in SMC, LGS, and Winbond
1899 */
1900static int irq_probe_EPP(struct parport *pb)
1901{
1902#ifndef ADVANCED_DETECT
1903 return PARPORT_IRQ_NONE;
1904#else
1905 int irqs;
1906 unsigned char oecr;
1907
1908 if (pb->modes & PARPORT_MODE_PCECR)
1909 oecr = inb(ECONTROL(pb));
1910
1911 irqs = probe_irq_on();
1912
1913 if (pb->modes & PARPORT_MODE_PCECR)
1914 frob_econtrol(pb, 0x10, 0x10);
1915
1916 clear_epp_timeout(pb);
1917 parport_pc_frob_control(pb, 0x20, 0x20);
1918 parport_pc_frob_control(pb, 0x10, 0x10);
1919 clear_epp_timeout(pb);
1920
1921 /* Device isn't expecting an EPP read
1922 * and generates an IRQ.
1923 */
1924 parport_pc_read_epp(pb);
1925 udelay(20);
1926
1927 pb->irq = probe_irq_off(irqs);
1928 if (pb->modes & PARPORT_MODE_PCECR)
1929 ECR_WRITE(pb, oecr);
1930 parport_pc_write_control(pb, 0xc);
1931
1932 if (pb->irq <= 0)
1933 pb->irq = PARPORT_IRQ_NONE;
1934
1935 return pb->irq;
1936#endif /* Advanced detection */
1937}
1938
1939static int irq_probe_SPP(struct parport *pb)
1940{
1941 /* Don't even try to do this. */
1942 return PARPORT_IRQ_NONE;
1943}
1944
1945/* We will attempt to share interrupt requests since other devices
1946 * such as sound cards and network cards seem to like using the
1947 * printer IRQs.
1948 *
1949 * When ECP is available we can autoprobe for IRQs.
1950 * NOTE: If we can autoprobe it, we can register the IRQ.
1951 */
1952static int parport_irq_probe(struct parport *pb)
1953{
1954 struct parport_pc_private *priv = pb->private_data;
1955
1956 if (priv->ecr) {
1957 pb->irq = programmable_irq_support(pb);
1958
1959 if (pb->irq == PARPORT_IRQ_NONE)
1960 pb->irq = irq_probe_ECP(pb);
1961 }
1962
1963 if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr &&
1964 (pb->modes & PARPORT_MODE_EPP))
1965 pb->irq = irq_probe_EPP(pb);
1966
1967 clear_epp_timeout(pb);
1968
1969 if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP))
1970 pb->irq = irq_probe_EPP(pb);
1971
1972 clear_epp_timeout(pb);
1973
1974 if (pb->irq == PARPORT_IRQ_NONE)
1975 pb->irq = irq_probe_SPP(pb);
1976
1977 if (pb->irq == PARPORT_IRQ_NONE)
1978 pb->irq = get_superio_irq(pb);
1979
1980 return pb->irq;
1981}
1982
1983/* --- DMA detection -------------------------------------- */
1984
1985/* Only if chipset conforms to ECP ISA Interface Standard */
1986static int programmable_dma_support(struct parport *p)
1987{
1988 unsigned char oecr = inb(ECONTROL(p));
1989 int dma;
1990
1991 frob_set_mode(p, ECR_CNF);
1992
1993 dma = inb(CONFIGB(p)) & 0x07;
1994 /* 000: Indicates jumpered 8-bit DMA if read-only.
1995 100: Indicates jumpered 16-bit DMA if read-only. */
1996 if ((dma & 0x03) == 0)
1997 dma = PARPORT_DMA_NONE;
1998
1999 ECR_WRITE(p, oecr);
2000 return dma;
2001}
2002
2003static int parport_dma_probe(struct parport *p)
2004{
2005 const struct parport_pc_private *priv = p->private_data;
2006 if (priv->ecr) /* ask ECP chipset first */
2007 p->dma = programmable_dma_support(p);
2008 if (p->dma == PARPORT_DMA_NONE) {
2009 /* ask known Super-IO chips proper, although these
2010 claim ECP compatible, some don't report their DMA
2011 conforming to ECP standards */
2012 p->dma = get_superio_dma(p);
2013 }
2014
2015 return p->dma;
2016}
2017
2018/* --- Initialisation code -------------------------------- */
2019
2020static LIST_HEAD(ports_list);
2021static DEFINE_SPINLOCK(ports_lock);
2022
2023struct parport *parport_pc_probe_port(unsigned long int base,
2024 unsigned long int base_hi,
2025 int irq, int dma,
2026 struct device *dev,
2027 int irqflags)
2028{
2029 struct parport_pc_private *priv;
2030 struct parport_operations *ops;
2031 struct parport *p;
2032 int probedirq = PARPORT_IRQ_NONE;
2033 struct resource *base_res;
2034 struct resource *ECR_res = NULL;
2035 struct resource *EPP_res = NULL;
2036 struct platform_device *pdev = NULL;
2037 int ret;
2038
2039 if (!dev) {
2040 /* We need a physical device to attach to, but none was
2041 * provided. Create our own. */
2042 pdev = platform_device_register_simple("parport_pc",
2043 base, NULL, 0);
2044 if (IS_ERR(pdev))
2045 return NULL;
2046 dev = &pdev->dev;
2047
2048 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(24));
2049 if (ret) {
2050 dev_err(dev, "Unable to set coherent dma mask: disabling DMA\n");
2051 dma = PARPORT_DMA_NONE;
2052 }
2053 }
2054
2055 ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL);
2056 if (!ops)
2057 goto out1;
2058
2059 priv = kmalloc(sizeof(struct parport_pc_private), GFP_KERNEL);
2060 if (!priv)
2061 goto out2;
2062
2063 /* a misnomer, actually - it's allocate and reserve parport number */
2064 p = parport_register_port(base, irq, dma, ops);
2065 if (!p)
2066 goto out3;
2067
2068 base_res = request_region(base, 3, p->name);
2069 if (!base_res)
2070 goto out4;
2071
2072 memcpy(ops, &parport_pc_ops, sizeof(struct parport_operations));
2073 priv->ctr = 0xc;
2074 priv->ctr_writable = ~0x10;
2075 priv->ecr = 0;
2076 priv->fifo_depth = 0;
2077 priv->dma_buf = NULL;
2078 priv->dma_handle = 0;
2079 INIT_LIST_HEAD(&priv->list);
2080 priv->port = p;
2081
2082 p->dev = dev;
2083 p->base_hi = base_hi;
2084 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
2085 p->private_data = priv;
2086
2087 if (base_hi) {
2088 ECR_res = request_region(base_hi, 3, p->name);
2089 if (ECR_res)
2090 parport_ECR_present(p);
2091 }
2092
2093 if (base != 0x3bc) {
2094 EPP_res = request_region(base+0x3, 5, p->name);
2095 if (EPP_res)
2096 if (!parport_EPP_supported(p))
2097 parport_ECPEPP_supported(p);
2098 }
2099 if (!parport_SPP_supported(p))
2100 /* No port. */
2101 goto out5;
2102 if (priv->ecr)
2103 parport_ECPPS2_supported(p);
2104 else
2105 parport_PS2_supported(p);
2106
2107 p->size = (p->modes & PARPORT_MODE_EPP) ? 8 : 3;
2108
2109 printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base);
2110 if (p->base_hi && priv->ecr)
2111 printk(KERN_CONT " (0x%lx)", p->base_hi);
2112 if (p->irq == PARPORT_IRQ_AUTO) {
2113 p->irq = PARPORT_IRQ_NONE;
2114 parport_irq_probe(p);
2115 } else if (p->irq == PARPORT_IRQ_PROBEONLY) {
2116 p->irq = PARPORT_IRQ_NONE;
2117 parport_irq_probe(p);
2118 probedirq = p->irq;
2119 p->irq = PARPORT_IRQ_NONE;
2120 }
2121 if (p->irq != PARPORT_IRQ_NONE) {
2122 printk(KERN_CONT ", irq %d", p->irq);
2123 priv->ctr_writable |= 0x10;
2124
2125 if (p->dma == PARPORT_DMA_AUTO) {
2126 p->dma = PARPORT_DMA_NONE;
2127 parport_dma_probe(p);
2128 }
2129 }
2130 if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq
2131 is mandatory (see above) */
2132 p->dma = PARPORT_DMA_NONE;
2133
2134#ifdef CONFIG_PARPORT_PC_FIFO
2135 if (parport_ECP_supported(p) &&
2136 p->dma != PARPORT_DMA_NOFIFO &&
2137 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) {
2138 p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT;
2139 p->ops->compat_write_data = parport_pc_compat_write_block_pio;
2140#ifdef CONFIG_PARPORT_1284
2141 p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
2142 /* currently broken, but working on it.. (FB) */
2143 /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */
2144#endif /* IEEE 1284 support */
2145 if (p->dma != PARPORT_DMA_NONE) {
2146 printk(KERN_CONT ", dma %d", p->dma);
2147 p->modes |= PARPORT_MODE_DMA;
2148 } else
2149 printk(KERN_CONT ", using FIFO");
2150 } else
2151 /* We can't use the DMA channel after all. */
2152 p->dma = PARPORT_DMA_NONE;
2153#endif /* Allowed to use FIFO/DMA */
2154
2155 printk(KERN_CONT " [");
2156
2157#define printmode(x) \
2158 {\
2159 if (p->modes & PARPORT_MODE_##x) {\
2160 printk(KERN_CONT "%s%s", f ? "," : "", #x);\
2161 f++;\
2162 } \
2163 }
2164
2165 {
2166 int f = 0;
2167 printmode(PCSPP);
2168 printmode(TRISTATE);
2169 printmode(COMPAT)
2170 printmode(EPP);
2171 printmode(ECP);
2172 printmode(DMA);
2173 }
2174#undef printmode
2175#ifndef CONFIG_PARPORT_1284
2176 printk(KERN_CONT "(,...)");
2177#endif /* CONFIG_PARPORT_1284 */
2178 printk(KERN_CONT "]\n");
2179 if (probedirq != PARPORT_IRQ_NONE)
2180 printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq);
2181
2182 /* If No ECP release the ports grabbed above. */
2183 if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) {
2184 release_region(base_hi, 3);
2185 ECR_res = NULL;
2186 }
2187 /* Likewise for EEP ports */
2188 if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) {
2189 release_region(base+3, 5);
2190 EPP_res = NULL;
2191 }
2192 if (p->irq != PARPORT_IRQ_NONE) {
2193 if (request_irq(p->irq, parport_irq_handler,
2194 irqflags, p->name, p)) {
2195 printk(KERN_WARNING "%s: irq %d in use, "
2196 "resorting to polled operation\n",
2197 p->name, p->irq);
2198 p->irq = PARPORT_IRQ_NONE;
2199 p->dma = PARPORT_DMA_NONE;
2200 }
2201
2202#ifdef CONFIG_PARPORT_PC_FIFO
2203#ifdef HAS_DMA
2204 if (p->dma != PARPORT_DMA_NONE) {
2205 if (request_dma(p->dma, p->name)) {
2206 printk(KERN_WARNING "%s: dma %d in use, "
2207 "resorting to PIO operation\n",
2208 p->name, p->dma);
2209 p->dma = PARPORT_DMA_NONE;
2210 } else {
2211 priv->dma_buf =
2212 dma_alloc_coherent(dev,
2213 PAGE_SIZE,
2214 &priv->dma_handle,
2215 GFP_KERNEL);
2216 if (!priv->dma_buf) {
2217 printk(KERN_WARNING "%s: "
2218 "cannot get buffer for DMA, "
2219 "resorting to PIO operation\n",
2220 p->name);
2221 free_dma(p->dma);
2222 p->dma = PARPORT_DMA_NONE;
2223 }
2224 }
2225 }
2226#endif
2227#endif
2228 }
2229
2230 /* Done probing. Now put the port into a sensible start-up state. */
2231 if (priv->ecr)
2232 /*
2233 * Put the ECP detected port in PS2 mode.
2234 * Do this also for ports that have ECR but don't do ECP.
2235 */
2236 ECR_WRITE(p, 0x34);
2237
2238 parport_pc_write_data(p, 0);
2239 parport_pc_data_forward(p);
2240
2241 /* Now that we've told the sharing engine about the port, and
2242 found out its characteristics, let the high-level drivers
2243 know about it. */
2244 spin_lock(&ports_lock);
2245 list_add(&priv->list, &ports_list);
2246 spin_unlock(&ports_lock);
2247 parport_announce_port(p);
2248
2249 return p;
2250
2251out5:
2252 if (ECR_res)
2253 release_region(base_hi, 3);
2254 if (EPP_res)
2255 release_region(base+0x3, 5);
2256 release_region(base, 3);
2257out4:
2258 parport_del_port(p);
2259out3:
2260 kfree(priv);
2261out2:
2262 kfree(ops);
2263out1:
2264 if (pdev)
2265 platform_device_unregister(pdev);
2266 return NULL;
2267}
2268EXPORT_SYMBOL(parport_pc_probe_port);
2269
2270void parport_pc_unregister_port(struct parport *p)
2271{
2272 struct parport_pc_private *priv = p->private_data;
2273 struct parport_operations *ops = p->ops;
2274
2275 parport_remove_port(p);
2276 spin_lock(&ports_lock);
2277 list_del_init(&priv->list);
2278 spin_unlock(&ports_lock);
2279#if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2280 if (p->dma != PARPORT_DMA_NONE)
2281 free_dma(p->dma);
2282#endif
2283 if (p->irq != PARPORT_IRQ_NONE)
2284 free_irq(p->irq, p);
2285 release_region(p->base, 3);
2286 if (p->size > 3)
2287 release_region(p->base + 3, p->size - 3);
2288 if (p->modes & PARPORT_MODE_ECP)
2289 release_region(p->base_hi, 3);
2290#if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2291 if (priv->dma_buf)
2292 dma_free_coherent(p->physport->dev, PAGE_SIZE,
2293 priv->dma_buf,
2294 priv->dma_handle);
2295#endif
2296 kfree(p->private_data);
2297 parport_del_port(p);
2298 kfree(ops); /* hope no-one cached it */
2299}
2300EXPORT_SYMBOL(parport_pc_unregister_port);
2301
2302#ifdef CONFIG_PCI
2303
2304/* ITE support maintained by Rich Liu <richliu@poorman.org> */
2305static int sio_ite_8872_probe(struct pci_dev *pdev, int autoirq, int autodma,
2306 const struct parport_pc_via_data *via)
2307{
2308 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 };
2309 u32 ite8872set;
2310 u32 ite8872_lpt, ite8872_lpthi;
2311 u8 ite8872_irq, type;
2312 int irq;
2313 int i;
2314
2315 DPRINTK(KERN_DEBUG "sio_ite_8872_probe()\n");
2316
2317 /* make sure which one chip */
2318 for (i = 0; i < 5; i++) {
2319 if (request_region(inta_addr[i], 32, "it887x")) {
2320 int test;
2321 pci_write_config_dword(pdev, 0x60,
2322 0xe5000000 | inta_addr[i]);
2323 pci_write_config_dword(pdev, 0x78,
2324 0x00000000 | inta_addr[i]);
2325 test = inb(inta_addr[i]);
2326 if (test != 0xff)
2327 break;
2328 release_region(inta_addr[i], 32);
2329 }
2330 }
2331 if (i >= 5) {
2332 printk(KERN_INFO "parport_pc: cannot find ITE8872 INTA\n");
2333 return 0;
2334 }
2335
2336 type = inb(inta_addr[i] + 0x18);
2337 type &= 0x0f;
2338
2339 switch (type) {
2340 case 0x2:
2341 printk(KERN_INFO "parport_pc: ITE8871 found (1P)\n");
2342 ite8872set = 0x64200000;
2343 break;
2344 case 0xa:
2345 printk(KERN_INFO "parport_pc: ITE8875 found (1P)\n");
2346 ite8872set = 0x64200000;
2347 break;
2348 case 0xe:
2349 printk(KERN_INFO "parport_pc: ITE8872 found (2S1P)\n");
2350 ite8872set = 0x64e00000;
2351 break;
2352 case 0x6:
2353 printk(KERN_INFO "parport_pc: ITE8873 found (1S)\n");
2354 release_region(inta_addr[i], 32);
2355 return 0;
2356 case 0x8:
2357 printk(KERN_INFO "parport_pc: ITE8874 found (2S)\n");
2358 release_region(inta_addr[i], 32);
2359 return 0;
2360 default:
2361 printk(KERN_INFO "parport_pc: unknown ITE887x\n");
2362 printk(KERN_INFO "parport_pc: please mail 'lspci -nvv' "
2363 "output to Rich.Liu@ite.com.tw\n");
2364 release_region(inta_addr[i], 32);
2365 return 0;
2366 }
2367
2368 pci_read_config_byte(pdev, 0x3c, &ite8872_irq);
2369 pci_read_config_dword(pdev, 0x1c, &ite8872_lpt);
2370 ite8872_lpt &= 0x0000ff00;
2371 pci_read_config_dword(pdev, 0x20, &ite8872_lpthi);
2372 ite8872_lpthi &= 0x0000ff00;
2373 pci_write_config_dword(pdev, 0x6c, 0xe3000000 | ite8872_lpt);
2374 pci_write_config_dword(pdev, 0x70, 0xe3000000 | ite8872_lpthi);
2375 pci_write_config_dword(pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt);
2376 /* SET SPP&EPP , Parallel Port NO DMA , Enable All Function */
2377 /* SET Parallel IRQ */
2378 pci_write_config_dword(pdev, 0x9c,
2379 ite8872set | (ite8872_irq * 0x11111));
2380
2381 DPRINTK(KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq);
2382 DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n",
2383 ite8872_lpt);
2384 DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n",
2385 ite8872_lpthi);
2386
2387 /* Let the user (or defaults) steer us away from interrupts */
2388 irq = ite8872_irq;
2389 if (autoirq != PARPORT_IRQ_AUTO)
2390 irq = PARPORT_IRQ_NONE;
2391
2392 /*
2393 * Release the resource so that parport_pc_probe_port can get it.
2394 */
2395 release_region(inta_addr[i], 32);
2396 if (parport_pc_probe_port(ite8872_lpt, ite8872_lpthi,
2397 irq, PARPORT_DMA_NONE, &pdev->dev, 0)) {
2398 printk(KERN_INFO
2399 "parport_pc: ITE 8872 parallel port: io=0x%X",
2400 ite8872_lpt);
2401 if (irq != PARPORT_IRQ_NONE)
2402 printk(", irq=%d", irq);
2403 printk("\n");
2404 return 1;
2405 }
2406
2407 return 0;
2408}
2409
2410/* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru>
2411 based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */
2412static int parport_init_mode;
2413
2414/* Data for two known VIA chips */
2415static struct parport_pc_via_data via_686a_data = {
2416 0x51,
2417 0x50,
2418 0x85,
2419 0x02,
2420 0xE2,
2421 0xF0,
2422 0xE6
2423};
2424static struct parport_pc_via_data via_8231_data = {
2425 0x45,
2426 0x44,
2427 0x50,
2428 0x04,
2429 0xF2,
2430 0xFA,
2431 0xF6
2432};
2433
2434static int sio_via_probe(struct pci_dev *pdev, int autoirq, int autodma,
2435 const struct parport_pc_via_data *via)
2436{
2437 u8 tmp, tmp2, siofunc;
2438 u8 ppcontrol = 0;
2439 int dma, irq;
2440 unsigned port1, port2;
2441 unsigned have_epp = 0;
2442
2443 printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n");
2444
2445 switch (parport_init_mode) {
2446 case 1:
2447 printk(KERN_DEBUG "parport_pc: setting SPP mode\n");
2448 siofunc = VIA_FUNCTION_PARPORT_SPP;
2449 break;
2450 case 2:
2451 printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n");
2452 siofunc = VIA_FUNCTION_PARPORT_SPP;
2453 ppcontrol = VIA_PARPORT_BIDIR;
2454 break;
2455 case 3:
2456 printk(KERN_DEBUG "parport_pc: setting EPP mode\n");
2457 siofunc = VIA_FUNCTION_PARPORT_EPP;
2458 ppcontrol = VIA_PARPORT_BIDIR;
2459 have_epp = 1;
2460 break;
2461 case 4:
2462 printk(KERN_DEBUG "parport_pc: setting ECP mode\n");
2463 siofunc = VIA_FUNCTION_PARPORT_ECP;
2464 ppcontrol = VIA_PARPORT_BIDIR;
2465 break;
2466 case 5:
2467 printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n");
2468 siofunc = VIA_FUNCTION_PARPORT_ECP;
2469 ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP;
2470 have_epp = 1;
2471 break;
2472 default:
2473 printk(KERN_DEBUG
2474 "parport_pc: probing current configuration\n");
2475 siofunc = VIA_FUNCTION_PROBE;
2476 break;
2477 }
2478 /*
2479 * unlock super i/o configuration
2480 */
2481 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2482 tmp |= via->via_pci_superio_config_data;
2483 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2484
2485 /* Bits 1-0: Parallel Port Mode / Enable */
2486 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2487 tmp = inb(VIA_CONFIG_DATA);
2488 /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */
2489 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2490 tmp2 = inb(VIA_CONFIG_DATA);
2491 if (siofunc == VIA_FUNCTION_PROBE) {
2492 siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE;
2493 ppcontrol = tmp2;
2494 } else {
2495 tmp &= ~VIA_FUNCTION_PARPORT_DISABLE;
2496 tmp |= siofunc;
2497 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2498 outb(tmp, VIA_CONFIG_DATA);
2499 tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP);
2500 tmp2 |= ppcontrol;
2501 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2502 outb(tmp2, VIA_CONFIG_DATA);
2503 }
2504
2505 /* Parallel Port I/O Base Address, bits 9-2 */
2506 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2507 port1 = inb(VIA_CONFIG_DATA) << 2;
2508
2509 printk(KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",
2510 port1);
2511 if (port1 == 0x3BC && have_epp) {
2512 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2513 outb((0x378 >> 2), VIA_CONFIG_DATA);
2514 printk(KERN_DEBUG
2515 "parport_pc: Parallel port base changed to 0x378\n");
2516 port1 = 0x378;
2517 }
2518
2519 /*
2520 * lock super i/o configuration
2521 */
2522 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2523 tmp &= ~via->via_pci_superio_config_data;
2524 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2525
2526 if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) {
2527 printk(KERN_INFO "parport_pc: VIA parallel port disabled in BIOS\n");
2528 return 0;
2529 }
2530
2531 /* Bits 7-4: PnP Routing for Parallel Port IRQ */
2532 pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp);
2533 irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4);
2534
2535 if (siofunc == VIA_FUNCTION_PARPORT_ECP) {
2536 /* Bits 3-2: PnP Routing for Parallel Port DMA */
2537 pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp);
2538 dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2);
2539 } else
2540 /* if ECP not enabled, DMA is not enabled, assumed
2541 bogus 'dma' value */
2542 dma = PARPORT_DMA_NONE;
2543
2544 /* Let the user (or defaults) steer us away from interrupts and DMA */
2545 if (autoirq == PARPORT_IRQ_NONE) {
2546 irq = PARPORT_IRQ_NONE;
2547 dma = PARPORT_DMA_NONE;
2548 }
2549 if (autodma == PARPORT_DMA_NONE)
2550 dma = PARPORT_DMA_NONE;
2551
2552 switch (port1) {
2553 case 0x3bc:
2554 port2 = 0x7bc; break;
2555 case 0x378:
2556 port2 = 0x778; break;
2557 case 0x278:
2558 port2 = 0x678; break;
2559 default:
2560 printk(KERN_INFO
2561 "parport_pc: Weird VIA parport base 0x%X, ignoring\n",
2562 port1);
2563 return 0;
2564 }
2565
2566 /* filter bogus IRQs */
2567 switch (irq) {
2568 case 0:
2569 case 2:
2570 case 8:
2571 case 13:
2572 irq = PARPORT_IRQ_NONE;
2573 break;
2574
2575 default: /* do nothing */
2576 break;
2577 }
2578
2579 /* finally, do the probe with values obtained */
2580 if (parport_pc_probe_port(port1, port2, irq, dma, &pdev->dev, 0)) {
2581 printk(KERN_INFO
2582 "parport_pc: VIA parallel port: io=0x%X", port1);
2583 if (irq != PARPORT_IRQ_NONE)
2584 printk(", irq=%d", irq);
2585 if (dma != PARPORT_DMA_NONE)
2586 printk(", dma=%d", dma);
2587 printk("\n");
2588 return 1;
2589 }
2590
2591 printk(KERN_WARNING "parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n",
2592 port1, irq, dma);
2593 return 0;
2594}
2595
2596
2597enum parport_pc_sio_types {
2598 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */
2599 sio_via_8231, /* Via VT8231 south bridge integrated Super IO */
2600 sio_ite_8872,
2601 last_sio
2602};
2603
2604/* each element directly indexed from enum list, above */
2605static struct parport_pc_superio {
2606 int (*probe) (struct pci_dev *pdev, int autoirq, int autodma,
2607 const struct parport_pc_via_data *via);
2608 const struct parport_pc_via_data *via;
2609} parport_pc_superio_info[] = {
2610 { sio_via_probe, &via_686a_data, },
2611 { sio_via_probe, &via_8231_data, },
2612 { sio_ite_8872_probe, NULL, },
2613};
2614
2615enum parport_pc_pci_cards {
2616 siig_1p_10x = last_sio,
2617 siig_2p_10x,
2618 siig_1p_20x,
2619 siig_2p_20x,
2620 lava_parallel,
2621 lava_parallel_dual_a,
2622 lava_parallel_dual_b,
2623 boca_ioppar,
2624 plx_9050,
2625 timedia_4006a,
2626 timedia_4014,
2627 timedia_4008a,
2628 timedia_4018,
2629 timedia_9018a,
2630 syba_2p_epp,
2631 syba_1p_ecp,
2632 titan_010l,
2633 avlab_1p,
2634 avlab_2p,
2635 oxsemi_952,
2636 oxsemi_954,
2637 oxsemi_840,
2638 oxsemi_pcie_pport,
2639 aks_0100,
2640 mobility_pp,
2641 netmos_9705,
2642 netmos_9715,
2643 netmos_9755,
2644 netmos_9805,
2645 netmos_9815,
2646 netmos_9901,
2647 netmos_9865,
2648 quatech_sppxp100,
2649};
2650
2651
2652/* each element directly indexed from enum list, above
2653 * (but offset by last_sio) */
2654static struct parport_pc_pci {
2655 int numports;
2656 struct { /* BAR (base address registers) numbers in the config
2657 space header */
2658 int lo;
2659 int hi;
2660 /* -1 if not there, >6 for offset-method (max BAR is 6) */
2661 } addr[4];
2662
2663 /* If set, this is called immediately after pci_enable_device.
2664 * If it returns non-zero, no probing will take place and the
2665 * ports will not be used. */
2666 int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma);
2667
2668 /* If set, this is called after probing for ports. If 'failed'
2669 * is non-zero we couldn't use any of the ports. */
2670 void (*postinit_hook) (struct pci_dev *pdev, int failed);
2671} cards[] = {
2672 /* siig_1p_10x */ { 1, { { 2, 3 }, } },
2673 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } },
2674 /* siig_1p_20x */ { 1, { { 0, 1 }, } },
2675 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
2676 /* lava_parallel */ { 1, { { 0, -1 }, } },
2677 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
2678 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
2679 /* boca_ioppar */ { 1, { { 0, -1 }, } },
2680 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } },
2681 /* timedia_4006a */ { 1, { { 0, -1 }, } },
2682 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2683 /* timedia_4008a */ { 1, { { 0, 1 }, } },
2684 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2685 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
2686 /* SYBA uses fixed offsets in
2687 a 1K io window */
2688 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
2689 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
2690 /* titan_010l */ { 1, { { 3, -1 }, } },
2691 /* avlab_1p */ { 1, { { 0, 1}, } },
2692 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
2693 /* The Oxford Semi cards are unusual: 954 doesn't support ECP,
2694 * and 840 locks up if you write 1 to bit 2! */
2695 /* oxsemi_952 */ { 1, { { 0, 1 }, } },
2696 /* oxsemi_954 */ { 1, { { 0, -1 }, } },
2697 /* oxsemi_840 */ { 1, { { 0, 1 }, } },
2698 /* oxsemi_pcie_pport */ { 1, { { 0, 1 }, } },
2699 /* aks_0100 */ { 1, { { 0, -1 }, } },
2700 /* mobility_pp */ { 1, { { 0, 1 }, } },
2701
2702 /* The netmos entries below are untested */
2703 /* netmos_9705 */ { 1, { { 0, -1 }, } },
2704 /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} },
2705 /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} },
2706 /* netmos_9805 */ { 1, { { 0, 1 }, } },
2707 /* netmos_9815 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2708 /* netmos_9901 */ { 1, { { 0, -1 }, } },
2709 /* netmos_9865 */ { 1, { { 0, -1 }, } },
2710 /* quatech_sppxp100 */ { 1, { { 0, 1 }, } },
2711};
2712
2713static const struct pci_device_id parport_pc_pci_tbl[] = {
2714 /* Super-IO onboard chips */
2715 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
2716 { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 },
2717 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2718 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 },
2719
2720 /* PCI cards */
2721 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x,
2722 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
2723 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x,
2724 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
2725 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x,
2726 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
2727 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x,
2728 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
2729 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL,
2730 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
2731 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A,
2732 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
2733 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B,
2734 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
2735 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR,
2736 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
2737 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2738 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0, 0, plx_9050 },
2739 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
2740 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
2741 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
2742 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
2743 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
2744 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
2745 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
2746 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
2747 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
2748 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
2749 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L,
2750 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
2751 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
2752 /* AFAVLAB_TK9902 */
2753 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p},
2754 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p},
2755 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952PP,
2756 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_952 },
2757 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP,
2758 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
2759 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
2760 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
2761 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840,
2762 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2763 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840_G,
2764 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2765 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0,
2766 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2767 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0_G,
2768 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2769 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1,
2770 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2771 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_G,
2772 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2773 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_U,
2774 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2775 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU,
2776 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2777 { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
2778 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
2779 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
2780 /* NetMos communication controllers */
2781 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705,
2782 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 },
2783 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715,
2784 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 },
2785 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755,
2786 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 },
2787 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805,
2788 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 },
2789 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815,
2790 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 },
2791 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
2792 0xA000, 0x2000, 0, 0, netmos_9901 },
2793 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
2794 0xA000, 0x1000, 0, 0, netmos_9865 },
2795 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
2796 0xA000, 0x2000, 0, 0, netmos_9865 },
2797 /* Quatech SPPXP-100 Parallel port PCI ExpressCard */
2798 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SPPXP_100,
2799 PCI_ANY_ID, PCI_ANY_ID, 0, 0, quatech_sppxp100 },
2800 { 0, } /* terminate list */
2801};
2802MODULE_DEVICE_TABLE(pci, parport_pc_pci_tbl);
2803
2804struct pci_parport_data {
2805 int num;
2806 struct parport *ports[2];
2807};
2808
2809static int parport_pc_pci_probe(struct pci_dev *dev,
2810 const struct pci_device_id *id)
2811{
2812 int err, count, n, i = id->driver_data;
2813 struct pci_parport_data *data;
2814
2815 if (i < last_sio)
2816 /* This is an onboard Super-IO and has already been probed */
2817 return 0;
2818
2819 /* This is a PCI card */
2820 i -= last_sio;
2821 count = 0;
2822 err = pci_enable_device(dev);
2823 if (err)
2824 return err;
2825
2826 data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL);
2827 if (!data)
2828 return -ENOMEM;
2829
2830 if (cards[i].preinit_hook &&
2831 cards[i].preinit_hook(dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) {
2832 kfree(data);
2833 return -ENODEV;
2834 }
2835
2836 for (n = 0; n < cards[i].numports; n++) {
2837 int lo = cards[i].addr[n].lo;
2838 int hi = cards[i].addr[n].hi;
2839 int irq;
2840 unsigned long io_lo, io_hi;
2841 io_lo = pci_resource_start(dev, lo);
2842 io_hi = 0;
2843 if ((hi >= 0) && (hi <= 6))
2844 io_hi = pci_resource_start(dev, hi);
2845 else if (hi > 6)
2846 io_lo += hi; /* Reinterpret the meaning of
2847 "hi" as an offset (see SYBA
2848 def.) */
2849 /* TODO: test if sharing interrupts works */
2850 irq = dev->irq;
2851 if (irq == IRQ_NONE) {
2852 printk(KERN_DEBUG
2853 "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n",
2854 id->vendor, id->device, io_lo, io_hi);
2855 irq = PARPORT_IRQ_NONE;
2856 } else {
2857 printk(KERN_DEBUG
2858 "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n",
2859 id->vendor, id->device, io_lo, io_hi, irq);
2860 }
2861 data->ports[count] =
2862 parport_pc_probe_port(io_lo, io_hi, irq,
2863 PARPORT_DMA_NONE, &dev->dev,
2864 IRQF_SHARED);
2865 if (data->ports[count])
2866 count++;
2867 }
2868
2869 data->num = count;
2870
2871 if (cards[i].postinit_hook)
2872 cards[i].postinit_hook(dev, count == 0);
2873
2874 if (count) {
2875 pci_set_drvdata(dev, data);
2876 return 0;
2877 }
2878
2879 kfree(data);
2880
2881 return -ENODEV;
2882}
2883
2884static void parport_pc_pci_remove(struct pci_dev *dev)
2885{
2886 struct pci_parport_data *data = pci_get_drvdata(dev);
2887 int i;
2888
2889 if (data) {
2890 for (i = data->num - 1; i >= 0; i--)
2891 parport_pc_unregister_port(data->ports[i]);
2892
2893 kfree(data);
2894 }
2895}
2896
2897static struct pci_driver parport_pc_pci_driver = {
2898 .name = "parport_pc",
2899 .id_table = parport_pc_pci_tbl,
2900 .probe = parport_pc_pci_probe,
2901 .remove = parport_pc_pci_remove,
2902};
2903
2904static int __init parport_pc_init_superio(int autoirq, int autodma)
2905{
2906 const struct pci_device_id *id;
2907 struct pci_dev *pdev = NULL;
2908 int ret = 0;
2909
2910 for_each_pci_dev(pdev) {
2911 id = pci_match_id(parport_pc_pci_tbl, pdev);
2912 if (id == NULL || id->driver_data >= last_sio)
2913 continue;
2914
2915 if (parport_pc_superio_info[id->driver_data].probe(
2916 pdev, autoirq, autodma,
2917 parport_pc_superio_info[id->driver_data].via)) {
2918 ret++;
2919 }
2920 }
2921
2922 return ret; /* number of devices found */
2923}
2924#else
2925static struct pci_driver parport_pc_pci_driver;
2926static int __init parport_pc_init_superio(int autoirq, int autodma)
2927{
2928 return 0;
2929}
2930#endif /* CONFIG_PCI */
2931
2932#ifdef CONFIG_PNP
2933
2934static const struct pnp_device_id parport_pc_pnp_tbl[] = {
2935 /* Standard LPT Printer Port */
2936 {.id = "PNP0400", .driver_data = 0},
2937 /* ECP Printer Port */
2938 {.id = "PNP0401", .driver_data = 0},
2939 { }
2940};
2941
2942MODULE_DEVICE_TABLE(pnp, parport_pc_pnp_tbl);
2943
2944static int parport_pc_pnp_probe(struct pnp_dev *dev,
2945 const struct pnp_device_id *id)
2946{
2947 struct parport *pdata;
2948 unsigned long io_lo, io_hi;
2949 int dma, irq;
2950
2951 if (pnp_port_valid(dev, 0) &&
2952 !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED)) {
2953 io_lo = pnp_port_start(dev, 0);
2954 } else
2955 return -EINVAL;
2956
2957 if (pnp_port_valid(dev, 1) &&
2958 !(pnp_port_flags(dev, 1) & IORESOURCE_DISABLED)) {
2959 io_hi = pnp_port_start(dev, 1);
2960 } else
2961 io_hi = 0;
2962
2963 if (pnp_irq_valid(dev, 0) &&
2964 !(pnp_irq_flags(dev, 0) & IORESOURCE_DISABLED)) {
2965 irq = pnp_irq(dev, 0);
2966 } else
2967 irq = PARPORT_IRQ_NONE;
2968
2969 if (pnp_dma_valid(dev, 0) &&
2970 !(pnp_dma_flags(dev, 0) & IORESOURCE_DISABLED)) {
2971 dma = pnp_dma(dev, 0);
2972 } else
2973 dma = PARPORT_DMA_NONE;
2974
2975 dev_info(&dev->dev, "reported by %s\n", dev->protocol->name);
2976 pdata = parport_pc_probe_port(io_lo, io_hi, irq, dma, &dev->dev, 0);
2977 if (pdata == NULL)
2978 return -ENODEV;
2979
2980 pnp_set_drvdata(dev, pdata);
2981 return 0;
2982}
2983
2984static void parport_pc_pnp_remove(struct pnp_dev *dev)
2985{
2986 struct parport *pdata = (struct parport *)pnp_get_drvdata(dev);
2987 if (!pdata)
2988 return;
2989
2990 parport_pc_unregister_port(pdata);
2991}
2992
2993/* we only need the pnp layer to activate the device, at least for now */
2994static struct pnp_driver parport_pc_pnp_driver = {
2995 .name = "parport_pc",
2996 .id_table = parport_pc_pnp_tbl,
2997 .probe = parport_pc_pnp_probe,
2998 .remove = parport_pc_pnp_remove,
2999};
3000
3001#else
3002static struct pnp_driver parport_pc_pnp_driver;
3003#endif /* CONFIG_PNP */
3004
3005static int parport_pc_platform_probe(struct platform_device *pdev)
3006{
3007 /* Always succeed, the actual probing is done in
3008 * parport_pc_probe_port(). */
3009 return 0;
3010}
3011
3012static struct platform_driver parport_pc_platform_driver = {
3013 .driver = {
3014 .name = "parport_pc",
3015 },
3016 .probe = parport_pc_platform_probe,
3017};
3018
3019/* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */
3020static int __attribute__((unused))
3021parport_pc_find_isa_ports(int autoirq, int autodma)
3022{
3023 int count = 0;
3024
3025 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL, 0))
3026 count++;
3027 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL, 0))
3028 count++;
3029 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL, 0))
3030 count++;
3031
3032 return count;
3033}
3034
3035/* This function is called by parport_pc_init if the user didn't
3036 * specify any ports to probe. Its job is to find some ports. Order
3037 * is important here -- we want ISA ports to be registered first,
3038 * followed by PCI cards (for least surprise), but before that we want
3039 * to do chipset-specific tests for some onboard ports that we know
3040 * about.
3041 *
3042 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY
3043 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO
3044 */
3045static void __init parport_pc_find_ports(int autoirq, int autodma)
3046{
3047 int count = 0, err;
3048
3049#ifdef CONFIG_PARPORT_PC_SUPERIO
3050 detect_and_report_it87();
3051 detect_and_report_winbond();
3052 detect_and_report_smsc();
3053#endif
3054
3055 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */
3056 count += parport_pc_init_superio(autoirq, autodma);
3057
3058 /* PnP ports, skip detection if SuperIO already found them */
3059 if (!count) {
3060 err = pnp_register_driver(&parport_pc_pnp_driver);
3061 if (!err)
3062 pnp_registered_parport = 1;
3063 }
3064
3065 /* ISA ports and whatever (see asm/parport.h). */
3066 parport_pc_find_nonpci_ports(autoirq, autodma);
3067
3068 err = pci_register_driver(&parport_pc_pci_driver);
3069 if (!err)
3070 pci_registered_parport = 1;
3071}
3072
3073/*
3074 * Piles of crap below pretend to be a parser for module and kernel
3075 * parameters. Say "thank you" to whoever had come up with that
3076 * syntax and keep in mind that code below is a cleaned up version.
3077 */
3078
3079static int __initdata io[PARPORT_PC_MAX_PORTS+1] = {
3080 [0 ... PARPORT_PC_MAX_PORTS] = 0
3081};
3082static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] = {
3083 [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO
3084};
3085static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = {
3086 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE
3087};
3088static int __initdata irqval[PARPORT_PC_MAX_PORTS] = {
3089 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY
3090};
3091
3092static int __init parport_parse_param(const char *s, int *val,
3093 int automatic, int none, int nofifo)
3094{
3095 if (!s)
3096 return 0;
3097 if (!strncmp(s, "auto", 4))
3098 *val = automatic;
3099 else if (!strncmp(s, "none", 4))
3100 *val = none;
3101 else if (nofifo && !strncmp(s, "nofifo", 6))
3102 *val = nofifo;
3103 else {
3104 char *ep;
3105 unsigned long r = simple_strtoul(s, &ep, 0);
3106 if (ep != s)
3107 *val = r;
3108 else {
3109 printk(KERN_ERR "parport: bad specifier `%s'\n", s);
3110 return -1;
3111 }
3112 }
3113 return 0;
3114}
3115
3116static int __init parport_parse_irq(const char *irqstr, int *val)
3117{
3118 return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO,
3119 PARPORT_IRQ_NONE, 0);
3120}
3121
3122static int __init parport_parse_dma(const char *dmastr, int *val)
3123{
3124 return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO,
3125 PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO);
3126}
3127
3128#ifdef CONFIG_PCI
3129static int __init parport_init_mode_setup(char *str)
3130{
3131 printk(KERN_DEBUG
3132 "parport_pc.c: Specified parameter parport_init_mode=%s\n", str);
3133
3134 if (!strcmp(str, "spp"))
3135 parport_init_mode = 1;
3136 if (!strcmp(str, "ps2"))
3137 parport_init_mode = 2;
3138 if (!strcmp(str, "epp"))
3139 parport_init_mode = 3;
3140 if (!strcmp(str, "ecp"))
3141 parport_init_mode = 4;
3142 if (!strcmp(str, "ecpepp"))
3143 parport_init_mode = 5;
3144 return 1;
3145}
3146#endif
3147
3148#ifdef MODULE
3149static char *irq[PARPORT_PC_MAX_PORTS];
3150static char *dma[PARPORT_PC_MAX_PORTS];
3151
3152MODULE_PARM_DESC(io, "Base I/O address (SPP regs)");
3153module_param_array(io, int, NULL, 0);
3154MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)");
3155module_param_array(io_hi, int, NULL, 0);
3156MODULE_PARM_DESC(irq, "IRQ line");
3157module_param_array(irq, charp, NULL, 0);
3158MODULE_PARM_DESC(dma, "DMA channel");
3159module_param_array(dma, charp, NULL, 0);
3160#if defined(CONFIG_PARPORT_PC_SUPERIO) || \
3161 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
3162MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation");
3163module_param(verbose_probing, int, 0644);
3164#endif
3165#ifdef CONFIG_PCI
3166static char *init_mode;
3167MODULE_PARM_DESC(init_mode,
3168 "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)");
3169module_param(init_mode, charp, 0);
3170#endif
3171
3172static int __init parse_parport_params(void)
3173{
3174 unsigned int i;
3175 int val;
3176
3177#ifdef CONFIG_PCI
3178 if (init_mode)
3179 parport_init_mode_setup(init_mode);
3180#endif
3181
3182 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) {
3183 if (parport_parse_irq(irq[i], &val))
3184 return 1;
3185 irqval[i] = val;
3186 if (parport_parse_dma(dma[i], &val))
3187 return 1;
3188 dmaval[i] = val;
3189 }
3190 if (!io[0]) {
3191 /* The user can make us use any IRQs or DMAs we find. */
3192 if (irq[0] && !parport_parse_irq(irq[0], &val))
3193 switch (val) {
3194 case PARPORT_IRQ_NONE:
3195 case PARPORT_IRQ_AUTO:
3196 irqval[0] = val;
3197 break;
3198 default:
3199 printk(KERN_WARNING
3200 "parport_pc: irq specified "
3201 "without base address. Use 'io=' "
3202 "to specify one\n");
3203 }
3204
3205 if (dma[0] && !parport_parse_dma(dma[0], &val))
3206 switch (val) {
3207 case PARPORT_DMA_NONE:
3208 case PARPORT_DMA_AUTO:
3209 dmaval[0] = val;
3210 break;
3211 default:
3212 printk(KERN_WARNING
3213 "parport_pc: dma specified "
3214 "without base address. Use 'io=' "
3215 "to specify one\n");
3216 }
3217 }
3218 return 0;
3219}
3220
3221#else
3222
3223static int parport_setup_ptr __initdata;
3224
3225/*
3226 * Acceptable parameters:
3227 *
3228 * parport=0
3229 * parport=auto
3230 * parport=0xBASE[,IRQ[,DMA]]
3231 *
3232 * IRQ/DMA may be numeric or 'auto' or 'none'
3233 */
3234static int __init parport_setup(char *str)
3235{
3236 char *endptr;
3237 char *sep;
3238 int val;
3239
3240 if (!str || !*str || (*str == '0' && !*(str+1))) {
3241 /* Disable parport if "parport=0" in cmdline */
3242 io[0] = PARPORT_DISABLE;
3243 return 1;
3244 }
3245
3246 if (!strncmp(str, "auto", 4)) {
3247 irqval[0] = PARPORT_IRQ_AUTO;
3248 dmaval[0] = PARPORT_DMA_AUTO;
3249 return 1;
3250 }
3251
3252 val = simple_strtoul(str, &endptr, 0);
3253 if (endptr == str) {
3254 printk(KERN_WARNING "parport=%s not understood\n", str);
3255 return 1;
3256 }
3257
3258 if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) {
3259 printk(KERN_ERR "parport=%s ignored, too many ports\n", str);
3260 return 1;
3261 }
3262
3263 io[parport_setup_ptr] = val;
3264 irqval[parport_setup_ptr] = PARPORT_IRQ_NONE;
3265 dmaval[parport_setup_ptr] = PARPORT_DMA_NONE;
3266
3267 sep = strchr(str, ',');
3268 if (sep++) {
3269 if (parport_parse_irq(sep, &val))
3270 return 1;
3271 irqval[parport_setup_ptr] = val;
3272 sep = strchr(sep, ',');
3273 if (sep++) {
3274 if (parport_parse_dma(sep, &val))
3275 return 1;
3276 dmaval[parport_setup_ptr] = val;
3277 }
3278 }
3279 parport_setup_ptr++;
3280 return 1;
3281}
3282
3283static int __init parse_parport_params(void)
3284{
3285 return io[0] == PARPORT_DISABLE;
3286}
3287
3288__setup("parport=", parport_setup);
3289
3290/*
3291 * Acceptable parameters:
3292 *
3293 * parport_init_mode=[spp|ps2|epp|ecp|ecpepp]
3294 */
3295#ifdef CONFIG_PCI
3296__setup("parport_init_mode=", parport_init_mode_setup);
3297#endif
3298#endif
3299
3300/* "Parser" ends here */
3301
3302static int __init parport_pc_init(void)
3303{
3304 int err;
3305
3306 if (parse_parport_params())
3307 return -EINVAL;
3308
3309 err = platform_driver_register(&parport_pc_platform_driver);
3310 if (err)
3311 return err;
3312
3313 if (io[0]) {
3314 int i;
3315 /* Only probe the ports we were given. */
3316 user_specified = 1;
3317 for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) {
3318 if (!io[i])
3319 break;
3320 if (io_hi[i] == PARPORT_IOHI_AUTO)
3321 io_hi[i] = 0x400 + io[i];
3322 parport_pc_probe_port(io[i], io_hi[i],
3323 irqval[i], dmaval[i], NULL, 0);
3324 }
3325 } else
3326 parport_pc_find_ports(irqval[0], dmaval[0]);
3327
3328 return 0;
3329}
3330
3331static void __exit parport_pc_exit(void)
3332{
3333 if (pci_registered_parport)
3334 pci_unregister_driver(&parport_pc_pci_driver);
3335 if (pnp_registered_parport)
3336 pnp_unregister_driver(&parport_pc_pnp_driver);
3337 platform_driver_unregister(&parport_pc_platform_driver);
3338
3339 while (!list_empty(&ports_list)) {
3340 struct parport_pc_private *priv;
3341 struct parport *port;
3342 struct device *dev;
3343 priv = list_entry(ports_list.next,
3344 struct parport_pc_private, list);
3345 port = priv->port;
3346 dev = port->dev;
3347 parport_pc_unregister_port(port);
3348 if (dev && dev->bus == &platform_bus_type)
3349 platform_device_unregister(to_platform_device(dev));
3350 }
3351}
3352
3353MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
3354MODULE_DESCRIPTION("PC-style parallel port driver");
3355MODULE_LICENSE("GPL");
3356module_init(parport_pc_init)
3357module_exit(parport_pc_exit)