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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Clause 45 PHY support
4 */
5#include <linux/ethtool.h>
6#include <linux/export.h>
7#include <linux/mdio.h>
8#include <linux/mii.h>
9#include <linux/phy.h>
10
11/**
12 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities
13 * @phydev: target phy_device struct
14 */
15static bool genphy_c45_baset1_able(struct phy_device *phydev)
16{
17 int val;
18
19 if (phydev->pma_extable == -ENODATA) {
20 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
21 if (val < 0)
22 return false;
23
24 phydev->pma_extable = val;
25 }
26
27 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1);
28}
29
30/**
31 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support
32 * @phydev: target phy_device struct
33 */
34static bool genphy_c45_pma_can_sleep(struct phy_device *phydev)
35{
36 int stat1;
37
38 stat1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1);
39 if (stat1 < 0)
40 return false;
41
42 return !!(stat1 & MDIO_STAT1_LPOWERABLE);
43}
44
45/**
46 * genphy_c45_pma_resume - wakes up the PMA module
47 * @phydev: target phy_device struct
48 */
49int genphy_c45_pma_resume(struct phy_device *phydev)
50{
51 if (!genphy_c45_pma_can_sleep(phydev))
52 return -EOPNOTSUPP;
53
54 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
55 MDIO_CTRL1_LPOWER);
56}
57EXPORT_SYMBOL_GPL(genphy_c45_pma_resume);
58
59/**
60 * genphy_c45_pma_suspend - suspends the PMA module
61 * @phydev: target phy_device struct
62 */
63int genphy_c45_pma_suspend(struct phy_device *phydev)
64{
65 if (!genphy_c45_pma_can_sleep(phydev))
66 return -EOPNOTSUPP;
67
68 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
69 MDIO_CTRL1_LPOWER);
70}
71EXPORT_SYMBOL_GPL(genphy_c45_pma_suspend);
72
73/**
74 * genphy_c45_pma_baset1_setup_master_slave - configures forced master/slave
75 * role of BaseT1 devices.
76 * @phydev: target phy_device struct
77 */
78int genphy_c45_pma_baset1_setup_master_slave(struct phy_device *phydev)
79{
80 int ctl = 0;
81
82 switch (phydev->master_slave_set) {
83 case MASTER_SLAVE_CFG_MASTER_PREFERRED:
84 case MASTER_SLAVE_CFG_MASTER_FORCE:
85 ctl = MDIO_PMA_PMD_BT1_CTRL_CFG_MST;
86 break;
87 case MASTER_SLAVE_CFG_SLAVE_FORCE:
88 case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
89 break;
90 case MASTER_SLAVE_CFG_UNKNOWN:
91 case MASTER_SLAVE_CFG_UNSUPPORTED:
92 return 0;
93 default:
94 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
95 return -EOPNOTSUPP;
96 }
97
98 return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,
99 MDIO_PMA_PMD_BT1_CTRL_CFG_MST, ctl);
100}
101EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_setup_master_slave);
102
103/**
104 * genphy_c45_pma_setup_forced - configures a forced speed
105 * @phydev: target phy_device struct
106 */
107int genphy_c45_pma_setup_forced(struct phy_device *phydev)
108{
109 int ctrl1, ctrl2, ret;
110
111 /* Half duplex is not supported */
112 if (phydev->duplex != DUPLEX_FULL)
113 return -EINVAL;
114
115 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
116 if (ctrl1 < 0)
117 return ctrl1;
118
119 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2);
120 if (ctrl2 < 0)
121 return ctrl2;
122
123 ctrl1 &= ~MDIO_CTRL1_SPEEDSEL;
124 /*
125 * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0. See 45.2.1.6.1
126 * in 802.3-2012 and 802.3-2015.
127 */
128 ctrl2 &= ~(MDIO_PMA_CTRL2_TYPE | 0x30);
129
130 switch (phydev->speed) {
131 case SPEED_10:
132 if (genphy_c45_baset1_able(phydev))
133 ctrl2 |= MDIO_PMA_CTRL2_BASET1;
134 else
135 ctrl2 |= MDIO_PMA_CTRL2_10BT;
136 break;
137 case SPEED_100:
138 ctrl1 |= MDIO_PMA_CTRL1_SPEED100;
139 ctrl2 |= MDIO_PMA_CTRL2_100BTX;
140 break;
141 case SPEED_1000:
142 ctrl1 |= MDIO_PMA_CTRL1_SPEED1000;
143 /* Assume 1000base-T */
144 ctrl2 |= MDIO_PMA_CTRL2_1000BT;
145 break;
146 case SPEED_2500:
147 ctrl1 |= MDIO_CTRL1_SPEED2_5G;
148 /* Assume 2.5Gbase-T */
149 ctrl2 |= MDIO_PMA_CTRL2_2_5GBT;
150 break;
151 case SPEED_5000:
152 ctrl1 |= MDIO_CTRL1_SPEED5G;
153 /* Assume 5Gbase-T */
154 ctrl2 |= MDIO_PMA_CTRL2_5GBT;
155 break;
156 case SPEED_10000:
157 ctrl1 |= MDIO_CTRL1_SPEED10G;
158 /* Assume 10Gbase-T */
159 ctrl2 |= MDIO_PMA_CTRL2_10GBT;
160 break;
161 default:
162 return -EINVAL;
163 }
164
165 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1);
166 if (ret < 0)
167 return ret;
168
169 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2);
170 if (ret < 0)
171 return ret;
172
173 if (genphy_c45_baset1_able(phydev)) {
174 ret = genphy_c45_pma_baset1_setup_master_slave(phydev);
175 if (ret < 0)
176 return ret;
177 }
178
179 return genphy_c45_an_disable_aneg(phydev);
180}
181EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced);
182
183/* Sets master/slave preference and supported technologies.
184 * The preference is set in the BIT(4) of BASE-T1 AN
185 * advertisement register 7.515 and whether the status
186 * is forced or not, it is set in the BIT(12) of BASE-T1
187 * AN advertisement register 7.514.
188 * Sets 10BASE-T1L Ability BIT(14) in BASE-T1 autonegotiation
189 * advertisement register [31:16] if supported.
190 */
191static int genphy_c45_baset1_an_config_aneg(struct phy_device *phydev)
192{
193 u16 adv_l_mask, adv_l = 0;
194 u16 adv_m_mask, adv_m = 0;
195 int changed = 0;
196 int ret;
197
198 adv_l_mask = MDIO_AN_T1_ADV_L_FORCE_MS | MDIO_AN_T1_ADV_L_PAUSE_CAP |
199 MDIO_AN_T1_ADV_L_PAUSE_ASYM;
200 adv_m_mask = MDIO_AN_T1_ADV_M_MST | MDIO_AN_T1_ADV_M_B10L;
201
202 switch (phydev->master_slave_set) {
203 case MASTER_SLAVE_CFG_MASTER_FORCE:
204 adv_m |= MDIO_AN_T1_ADV_M_MST;
205 fallthrough;
206 case MASTER_SLAVE_CFG_SLAVE_FORCE:
207 adv_l |= MDIO_AN_T1_ADV_L_FORCE_MS;
208 break;
209 case MASTER_SLAVE_CFG_MASTER_PREFERRED:
210 adv_m |= MDIO_AN_T1_ADV_M_MST;
211 fallthrough;
212 case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
213 break;
214 case MASTER_SLAVE_CFG_UNKNOWN:
215 case MASTER_SLAVE_CFG_UNSUPPORTED:
216 /* if master/slave role is not specified, do not overwrite it */
217 adv_l_mask &= ~MDIO_AN_T1_ADV_L_FORCE_MS;
218 adv_m_mask &= ~MDIO_AN_T1_ADV_M_MST;
219 break;
220 default:
221 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
222 return -EOPNOTSUPP;
223 }
224
225 adv_l |= linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising);
226
227 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L,
228 adv_l_mask, adv_l);
229 if (ret < 0)
230 return ret;
231 if (ret > 0)
232 changed = 1;
233
234 adv_m |= linkmode_adv_to_mii_t1_adv_m_t(phydev->advertising);
235
236 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M,
237 adv_m_mask, adv_m);
238 if (ret < 0)
239 return ret;
240 if (ret > 0)
241 changed = 1;
242
243 return changed;
244}
245
246/**
247 * genphy_c45_an_config_aneg - configure advertisement registers
248 * @phydev: target phy_device struct
249 *
250 * Configure advertisement registers based on modes set in phydev->advertising
251 *
252 * Returns negative errno code on failure, 0 if advertisement didn't change,
253 * or 1 if advertised modes changed.
254 */
255int genphy_c45_an_config_aneg(struct phy_device *phydev)
256{
257 int changed, ret;
258 u32 adv;
259
260 linkmode_and(phydev->advertising, phydev->advertising,
261 phydev->supported);
262
263 changed = genphy_config_eee_advert(phydev);
264
265 if (genphy_c45_baset1_able(phydev))
266 return genphy_c45_baset1_an_config_aneg(phydev);
267
268 adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
269
270 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
271 ADVERTISE_ALL | ADVERTISE_100BASE4 |
272 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
273 adv);
274 if (ret < 0)
275 return ret;
276 if (ret > 0)
277 changed = 1;
278
279 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
280
281 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
282 MDIO_AN_10GBT_CTRL_ADV10G |
283 MDIO_AN_10GBT_CTRL_ADV5G |
284 MDIO_AN_10GBT_CTRL_ADV2_5G, adv);
285 if (ret < 0)
286 return ret;
287 if (ret > 0)
288 changed = 1;
289
290 return changed;
291}
292EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg);
293
294/**
295 * genphy_c45_an_disable_aneg - disable auto-negotiation
296 * @phydev: target phy_device struct
297 *
298 * Disable auto-negotiation in the Clause 45 PHY. The link parameters
299 * are controlled through the PMA/PMD MMD registers.
300 *
301 * Returns zero on success, negative errno code on failure.
302 */
303int genphy_c45_an_disable_aneg(struct phy_device *phydev)
304{
305 u16 reg = MDIO_CTRL1;
306
307 if (genphy_c45_baset1_able(phydev))
308 reg = MDIO_AN_T1_CTRL;
309
310 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
311 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
312}
313EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg);
314
315/**
316 * genphy_c45_restart_aneg - Enable and restart auto-negotiation
317 * @phydev: target phy_device struct
318 *
319 * This assumes that the auto-negotiation MMD is present.
320 *
321 * Enable and restart auto-negotiation.
322 */
323int genphy_c45_restart_aneg(struct phy_device *phydev)
324{
325 u16 reg = MDIO_CTRL1;
326
327 if (genphy_c45_baset1_able(phydev))
328 reg = MDIO_AN_T1_CTRL;
329
330 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg,
331 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
332}
333EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg);
334
335/**
336 * genphy_c45_check_and_restart_aneg - Enable and restart auto-negotiation
337 * @phydev: target phy_device struct
338 * @restart: whether aneg restart is requested
339 *
340 * This assumes that the auto-negotiation MMD is present.
341 *
342 * Check, and restart auto-negotiation if needed.
343 */
344int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart)
345{
346 u16 reg = MDIO_CTRL1;
347 int ret;
348
349 if (genphy_c45_baset1_able(phydev))
350 reg = MDIO_AN_T1_CTRL;
351
352 if (!restart) {
353 /* Configure and restart aneg if it wasn't set before */
354 ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
355 if (ret < 0)
356 return ret;
357
358 if (!(ret & MDIO_AN_CTRL1_ENABLE))
359 restart = true;
360 }
361
362 if (restart)
363 return genphy_c45_restart_aneg(phydev);
364
365 return 0;
366}
367EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg);
368
369/**
370 * genphy_c45_aneg_done - return auto-negotiation complete status
371 * @phydev: target phy_device struct
372 *
373 * This assumes that the auto-negotiation MMD is present.
374 *
375 * Reads the status register from the auto-negotiation MMD, returning:
376 * - positive if auto-negotiation is complete
377 * - negative errno code on error
378 * - zero otherwise
379 */
380int genphy_c45_aneg_done(struct phy_device *phydev)
381{
382 int reg = MDIO_STAT1;
383 int val;
384
385 if (genphy_c45_baset1_able(phydev))
386 reg = MDIO_AN_T1_STAT;
387
388 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
389
390 return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0;
391}
392EXPORT_SYMBOL_GPL(genphy_c45_aneg_done);
393
394/**
395 * genphy_c45_read_link - read the overall link status from the MMDs
396 * @phydev: target phy_device struct
397 *
398 * Read the link status from the specified MMDs, and if they all indicate
399 * that the link is up, set phydev->link to 1. If an error is encountered,
400 * a negative errno will be returned, otherwise zero.
401 */
402int genphy_c45_read_link(struct phy_device *phydev)
403{
404 u32 mmd_mask = MDIO_DEVS_PMAPMD;
405 int val, devad;
406 bool link = true;
407
408 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) {
409 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
410 if (val < 0)
411 return val;
412
413 /* Autoneg is being started, therefore disregard current
414 * link status and report link as down.
415 */
416 if (val & MDIO_AN_CTRL1_RESTART) {
417 phydev->link = 0;
418 return 0;
419 }
420 }
421
422 while (mmd_mask && link) {
423 devad = __ffs(mmd_mask);
424 mmd_mask &= ~BIT(devad);
425
426 /* The link state is latched low so that momentary link
427 * drops can be detected. Do not double-read the status
428 * in polling mode to detect such short link drops except
429 * the link was already down.
430 */
431 if (!phy_polling_mode(phydev) || !phydev->link) {
432 val = phy_read_mmd(phydev, devad, MDIO_STAT1);
433 if (val < 0)
434 return val;
435 else if (val & MDIO_STAT1_LSTATUS)
436 continue;
437 }
438
439 val = phy_read_mmd(phydev, devad, MDIO_STAT1);
440 if (val < 0)
441 return val;
442
443 if (!(val & MDIO_STAT1_LSTATUS))
444 link = false;
445 }
446
447 phydev->link = link;
448
449 return 0;
450}
451EXPORT_SYMBOL_GPL(genphy_c45_read_link);
452
453/* Read the Clause 45 defined BASE-T1 AN (7.513) status register to check
454 * if autoneg is complete. If so read the BASE-T1 Autonegotiation
455 * Advertisement registers filling in the link partner advertisement,
456 * pause and asym_pause members in phydev.
457 */
458static int genphy_c45_baset1_read_lpa(struct phy_device *phydev)
459{
460 int val;
461
462 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);
463 if (val < 0)
464 return val;
465
466 if (!(val & MDIO_AN_STAT1_COMPLETE)) {
467 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising);
468 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, 0);
469 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, 0);
470
471 phydev->pause = 0;
472 phydev->asym_pause = 0;
473
474 return 0;
475 }
476
477 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 1);
478
479 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L);
480 if (val < 0)
481 return val;
482
483 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val);
484 phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP ? 1 : 0;
485 phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM ? 1 : 0;
486
487 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M);
488 if (val < 0)
489 return val;
490
491 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val);
492
493 return 0;
494}
495
496/**
497 * genphy_c45_read_lpa - read the link partner advertisement and pause
498 * @phydev: target phy_device struct
499 *
500 * Read the Clause 45 defined base (7.19) and 10G (7.33) status registers,
501 * filling in the link partner advertisement, pause and asym_pause members
502 * in @phydev. This assumes that the auto-negotiation MMD is present, and
503 * the backplane bit (7.48.0) is clear. Clause 45 PHY drivers are expected
504 * to fill in the remainder of the link partner advert from vendor registers.
505 */
506int genphy_c45_read_lpa(struct phy_device *phydev)
507{
508 int val;
509
510 if (genphy_c45_baset1_able(phydev))
511 return genphy_c45_baset1_read_lpa(phydev);
512
513 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
514 if (val < 0)
515 return val;
516
517 if (!(val & MDIO_AN_STAT1_COMPLETE)) {
518 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
519 phydev->lp_advertising);
520 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
521 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0);
522 phydev->pause = 0;
523 phydev->asym_pause = 0;
524
525 return 0;
526 }
527
528 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising,
529 val & MDIO_AN_STAT1_LPABLE);
530
531 /* Read the link partner's base page advertisement */
532 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
533 if (val < 0)
534 return val;
535
536 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val);
537 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0;
538 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0;
539
540 /* Read the link partner's 10G advertisement */
541 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
542 if (val < 0)
543 return val;
544
545 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val);
546
547 return 0;
548}
549EXPORT_SYMBOL_GPL(genphy_c45_read_lpa);
550
551/**
552 * genphy_c45_pma_baset1_read_master_slave - read forced master/slave
553 * configuration
554 * @phydev: target phy_device struct
555 */
556int genphy_c45_pma_baset1_read_master_slave(struct phy_device *phydev)
557{
558 int val;
559
560 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
561 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
562
563 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL);
564 if (val < 0)
565 return val;
566
567 if (val & MDIO_PMA_PMD_BT1_CTRL_CFG_MST) {
568 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
569 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
570 } else {
571 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
572 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
573 }
574
575 return 0;
576}
577EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_read_master_slave);
578
579/**
580 * genphy_c45_read_pma - read link speed etc from PMA
581 * @phydev: target phy_device struct
582 */
583int genphy_c45_read_pma(struct phy_device *phydev)
584{
585 int val;
586
587 linkmode_zero(phydev->lp_advertising);
588
589 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
590 if (val < 0)
591 return val;
592
593 switch (val & MDIO_CTRL1_SPEEDSEL) {
594 case 0:
595 phydev->speed = SPEED_10;
596 break;
597 case MDIO_PMA_CTRL1_SPEED100:
598 phydev->speed = SPEED_100;
599 break;
600 case MDIO_PMA_CTRL1_SPEED1000:
601 phydev->speed = SPEED_1000;
602 break;
603 case MDIO_CTRL1_SPEED2_5G:
604 phydev->speed = SPEED_2500;
605 break;
606 case MDIO_CTRL1_SPEED5G:
607 phydev->speed = SPEED_5000;
608 break;
609 case MDIO_CTRL1_SPEED10G:
610 phydev->speed = SPEED_10000;
611 break;
612 default:
613 phydev->speed = SPEED_UNKNOWN;
614 break;
615 }
616
617 phydev->duplex = DUPLEX_FULL;
618
619 if (genphy_c45_baset1_able(phydev)) {
620 val = genphy_c45_pma_baset1_read_master_slave(phydev);
621 if (val < 0)
622 return val;
623 }
624
625 return 0;
626}
627EXPORT_SYMBOL_GPL(genphy_c45_read_pma);
628
629/**
630 * genphy_c45_read_mdix - read mdix status from PMA
631 * @phydev: target phy_device struct
632 */
633int genphy_c45_read_mdix(struct phy_device *phydev)
634{
635 int val;
636
637 if (phydev->speed == SPEED_10000) {
638 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
639 MDIO_PMA_10GBT_SWAPPOL);
640 if (val < 0)
641 return val;
642
643 switch (val) {
644 case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX:
645 phydev->mdix = ETH_TP_MDI;
646 break;
647
648 case 0:
649 phydev->mdix = ETH_TP_MDI_X;
650 break;
651
652 default:
653 phydev->mdix = ETH_TP_MDI_INVALID;
654 break;
655 }
656 }
657
658 return 0;
659}
660EXPORT_SYMBOL_GPL(genphy_c45_read_mdix);
661
662/**
663 * genphy_c45_pma_read_abilities - read supported link modes from PMA
664 * @phydev: target phy_device struct
665 *
666 * Read the supported link modes from the PMA Status 2 (1.8) register. If bit
667 * 1.8.9 is set, the list of supported modes is build using the values in the
668 * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related
669 * modes. If bit 1.11.14 is set, then the list is also extended with the modes
670 * in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and
671 * 5GBASET are supported.
672 */
673int genphy_c45_pma_read_abilities(struct phy_device *phydev)
674{
675 int val;
676
677 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
678 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) {
679 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
680 if (val < 0)
681 return val;
682
683 if (val & MDIO_AN_STAT1_ABLE)
684 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
685 phydev->supported);
686 }
687
688 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2);
689 if (val < 0)
690 return val;
691
692 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
693 phydev->supported,
694 val & MDIO_PMA_STAT2_10GBSR);
695
696 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
697 phydev->supported,
698 val & MDIO_PMA_STAT2_10GBLR);
699
700 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
701 phydev->supported,
702 val & MDIO_PMA_STAT2_10GBER);
703
704 if (val & MDIO_PMA_STAT2_EXTABLE) {
705 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
706 if (val < 0)
707 return val;
708
709 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
710 phydev->supported,
711 val & MDIO_PMA_EXTABLE_10GBLRM);
712 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
713 phydev->supported,
714 val & MDIO_PMA_EXTABLE_10GBT);
715 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
716 phydev->supported,
717 val & MDIO_PMA_EXTABLE_10GBKX4);
718 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
719 phydev->supported,
720 val & MDIO_PMA_EXTABLE_10GBKR);
721 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
722 phydev->supported,
723 val & MDIO_PMA_EXTABLE_1000BT);
724 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
725 phydev->supported,
726 val & MDIO_PMA_EXTABLE_1000BKX);
727
728 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
729 phydev->supported,
730 val & MDIO_PMA_EXTABLE_100BTX);
731 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
732 phydev->supported,
733 val & MDIO_PMA_EXTABLE_100BTX);
734
735 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
736 phydev->supported,
737 val & MDIO_PMA_EXTABLE_10BT);
738 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
739 phydev->supported,
740 val & MDIO_PMA_EXTABLE_10BT);
741
742 if (val & MDIO_PMA_EXTABLE_NBT) {
743 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
744 MDIO_PMA_NG_EXTABLE);
745 if (val < 0)
746 return val;
747
748 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
749 phydev->supported,
750 val & MDIO_PMA_NG_EXTABLE_2_5GBT);
751
752 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
753 phydev->supported,
754 val & MDIO_PMA_NG_EXTABLE_5GBT);
755 }
756
757 if (val & MDIO_PMA_EXTABLE_BT1) {
758 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1);
759 if (val < 0)
760 return val;
761
762 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
763 phydev->supported,
764 val & MDIO_PMA_PMD_BT1_B10L_ABLE);
765
766 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);
767 if (val < 0)
768 return val;
769
770 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
771 phydev->supported,
772 val & MDIO_AN_STAT1_ABLE);
773 }
774 }
775
776 return 0;
777}
778EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities);
779
780/* Read master/slave preference from registers.
781 * The preference is read from the BIT(4) of BASE-T1 AN
782 * advertisement register 7.515 and whether the preference
783 * is forced or not, it is read from BASE-T1 AN advertisement
784 * register 7.514.
785 */
786int genphy_c45_baset1_read_status(struct phy_device *phydev)
787{
788 int ret;
789 int cfg;
790
791 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
792 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
793
794 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L);
795 if (ret < 0)
796 return ret;
797
798 cfg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M);
799 if (cfg < 0)
800 return cfg;
801
802 if (ret & MDIO_AN_T1_ADV_L_FORCE_MS) {
803 if (cfg & MDIO_AN_T1_ADV_M_MST)
804 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
805 else
806 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
807 } else {
808 if (cfg & MDIO_AN_T1_ADV_M_MST)
809 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED;
810 else
811 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED;
812 }
813
814 return 0;
815}
816EXPORT_SYMBOL_GPL(genphy_c45_baset1_read_status);
817
818/**
819 * genphy_c45_read_status - read PHY status
820 * @phydev: target phy_device struct
821 *
822 * Reads status from PHY and sets phy_device members accordingly.
823 */
824int genphy_c45_read_status(struct phy_device *phydev)
825{
826 int ret;
827
828 ret = genphy_c45_read_link(phydev);
829 if (ret)
830 return ret;
831
832 phydev->speed = SPEED_UNKNOWN;
833 phydev->duplex = DUPLEX_UNKNOWN;
834 phydev->pause = 0;
835 phydev->asym_pause = 0;
836
837 if (phydev->autoneg == AUTONEG_ENABLE) {
838 ret = genphy_c45_read_lpa(phydev);
839 if (ret)
840 return ret;
841
842 if (genphy_c45_baset1_able(phydev)) {
843 ret = genphy_c45_baset1_read_status(phydev);
844 if (ret < 0)
845 return ret;
846 }
847
848 phy_resolve_aneg_linkmode(phydev);
849 } else {
850 ret = genphy_c45_read_pma(phydev);
851 }
852
853 return ret;
854}
855EXPORT_SYMBOL_GPL(genphy_c45_read_status);
856
857/**
858 * genphy_c45_config_aneg - restart auto-negotiation or forced setup
859 * @phydev: target phy_device struct
860 *
861 * Description: If auto-negotiation is enabled, we configure the
862 * advertising, and then restart auto-negotiation. If it is not
863 * enabled, then we force a configuration.
864 */
865int genphy_c45_config_aneg(struct phy_device *phydev)
866{
867 bool changed = false;
868 int ret;
869
870 if (phydev->autoneg == AUTONEG_DISABLE)
871 return genphy_c45_pma_setup_forced(phydev);
872
873 ret = genphy_c45_an_config_aneg(phydev);
874 if (ret < 0)
875 return ret;
876 if (ret > 0)
877 changed = true;
878
879 return genphy_c45_check_and_restart_aneg(phydev, changed);
880}
881EXPORT_SYMBOL_GPL(genphy_c45_config_aneg);
882
883/* The gen10g_* functions are the old Clause 45 stub */
884
885int gen10g_config_aneg(struct phy_device *phydev)
886{
887 return 0;
888}
889EXPORT_SYMBOL_GPL(gen10g_config_aneg);
890
891int genphy_c45_loopback(struct phy_device *phydev, bool enable)
892{
893 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1,
894 MDIO_PCS_CTRL1_LOOPBACK,
895 enable ? MDIO_PCS_CTRL1_LOOPBACK : 0);
896}
897EXPORT_SYMBOL_GPL(genphy_c45_loopback);
898
899/**
900 * genphy_c45_fast_retrain - configure fast retrain registers
901 * @phydev: target phy_device struct
902 * @enable: enable fast retrain or not
903 *
904 * Description: If fast-retrain is enabled, we configure PHY as
905 * advertising fast retrain capable and THP Bypass Request, then
906 * enable fast retrain. If it is not enabled, we configure fast
907 * retrain disabled.
908 */
909int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable)
910{
911 int ret;
912
913 if (!enable)
914 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR,
915 MDIO_PMA_10GBR_FSRT_ENABLE);
916
917 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) {
918 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
919 MDIO_AN_10GBT_CTRL_ADVFSRT2_5G);
920 if (ret)
921 return ret;
922
923 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2,
924 MDIO_AN_THP_BP2_5GT);
925 if (ret)
926 return ret;
927 }
928
929 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR,
930 MDIO_PMA_10GBR_FSRT_ENABLE);
931}
932EXPORT_SYMBOL_GPL(genphy_c45_fast_retrain);
933
934struct phy_driver genphy_c45_driver = {
935 .phy_id = 0xffffffff,
936 .phy_id_mask = 0xffffffff,
937 .name = "Generic Clause 45 PHY",
938 .read_status = genphy_c45_read_status,
939};