Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Cadence MACB/GEM Ethernet Controller driver
4 *
5 * Copyright (C) 2004-2006 Atmel Corporation
6 */
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9#include <linux/clk.h>
10#include <linux/clk-provider.h>
11#include <linux/crc32.h>
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/circ_buf.h>
17#include <linux/slab.h>
18#include <linux/init.h>
19#include <linux/io.h>
20#include <linux/gpio.h>
21#include <linux/gpio/consumer.h>
22#include <linux/interrupt.h>
23#include <linux/netdevice.h>
24#include <linux/etherdevice.h>
25#include <linux/dma-mapping.h>
26#include <linux/platform_device.h>
27#include <linux/phylink.h>
28#include <linux/of.h>
29#include <linux/of_device.h>
30#include <linux/of_gpio.h>
31#include <linux/of_mdio.h>
32#include <linux/of_net.h>
33#include <linux/ip.h>
34#include <linux/udp.h>
35#include <linux/tcp.h>
36#include <linux/iopoll.h>
37#include <linux/phy/phy.h>
38#include <linux/pm_runtime.h>
39#include <linux/ptp_classify.h>
40#include <linux/reset.h>
41#include <linux/firmware/xlnx-zynqmp.h>
42#include "macb.h"
43
44/* This structure is only used for MACB on SiFive FU540 devices */
45struct sifive_fu540_macb_mgmt {
46 void __iomem *reg;
47 unsigned long rate;
48 struct clk_hw hw;
49};
50
51#define MACB_RX_BUFFER_SIZE 128
52#define RX_BUFFER_MULTIPLE 64 /* bytes */
53
54#define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
55#define MIN_RX_RING_SIZE 64
56#define MAX_RX_RING_SIZE 8192
57#define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
58 * (bp)->rx_ring_size)
59
60#define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
61#define MIN_TX_RING_SIZE 64
62#define MAX_TX_RING_SIZE 4096
63#define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
64 * (bp)->tx_ring_size)
65
66/* level of occupied TX descriptors under which we wake up TX process */
67#define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
68
69#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR))
70#define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
71 | MACB_BIT(ISR_RLE) \
72 | MACB_BIT(TXERR))
73#define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \
74 | MACB_BIT(TXUBR))
75
76/* Max length of transmit frame must be a multiple of 8 bytes */
77#define MACB_TX_LEN_ALIGN 8
78#define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
79/* Limit maximum TX length as per Cadence TSO errata. This is to avoid a
80 * false amba_error in TX path from the DMA assuming there is not enough
81 * space in the SRAM (16KB) even when there is.
82 */
83#define GEM_MAX_TX_LEN (unsigned int)(0x3FC0)
84
85#define GEM_MTU_MIN_SIZE ETH_MIN_MTU
86#define MACB_NETIF_LSO NETIF_F_TSO
87
88#define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
89#define MACB_WOL_ENABLED (0x1 << 1)
90
91#define HS_SPEED_10000M 4
92#define MACB_SERDES_RATE_10G 1
93
94/* Graceful stop timeouts in us. We should allow up to
95 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
96 */
97#define MACB_HALT_TIMEOUT 1230
98
99#define MACB_PM_TIMEOUT 100 /* ms */
100
101#define MACB_MDIO_TIMEOUT 1000000 /* in usecs */
102
103/* DMA buffer descriptor might be different size
104 * depends on hardware configuration:
105 *
106 * 1. dma address width 32 bits:
107 * word 1: 32 bit address of Data Buffer
108 * word 2: control
109 *
110 * 2. dma address width 64 bits:
111 * word 1: 32 bit address of Data Buffer
112 * word 2: control
113 * word 3: upper 32 bit address of Data Buffer
114 * word 4: unused
115 *
116 * 3. dma address width 32 bits with hardware timestamping:
117 * word 1: 32 bit address of Data Buffer
118 * word 2: control
119 * word 3: timestamp word 1
120 * word 4: timestamp word 2
121 *
122 * 4. dma address width 64 bits with hardware timestamping:
123 * word 1: 32 bit address of Data Buffer
124 * word 2: control
125 * word 3: upper 32 bit address of Data Buffer
126 * word 4: unused
127 * word 5: timestamp word 1
128 * word 6: timestamp word 2
129 */
130static unsigned int macb_dma_desc_get_size(struct macb *bp)
131{
132#ifdef MACB_EXT_DESC
133 unsigned int desc_size;
134
135 switch (bp->hw_dma_cap) {
136 case HW_DMA_CAP_64B:
137 desc_size = sizeof(struct macb_dma_desc)
138 + sizeof(struct macb_dma_desc_64);
139 break;
140 case HW_DMA_CAP_PTP:
141 desc_size = sizeof(struct macb_dma_desc)
142 + sizeof(struct macb_dma_desc_ptp);
143 break;
144 case HW_DMA_CAP_64B_PTP:
145 desc_size = sizeof(struct macb_dma_desc)
146 + sizeof(struct macb_dma_desc_64)
147 + sizeof(struct macb_dma_desc_ptp);
148 break;
149 default:
150 desc_size = sizeof(struct macb_dma_desc);
151 }
152 return desc_size;
153#endif
154 return sizeof(struct macb_dma_desc);
155}
156
157static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
158{
159#ifdef MACB_EXT_DESC
160 switch (bp->hw_dma_cap) {
161 case HW_DMA_CAP_64B:
162 case HW_DMA_CAP_PTP:
163 desc_idx <<= 1;
164 break;
165 case HW_DMA_CAP_64B_PTP:
166 desc_idx *= 3;
167 break;
168 default:
169 break;
170 }
171#endif
172 return desc_idx;
173}
174
175#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
176static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
177{
178 return (struct macb_dma_desc_64 *)((void *)desc
179 + sizeof(struct macb_dma_desc));
180}
181#endif
182
183/* Ring buffer accessors */
184static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
185{
186 return index & (bp->tx_ring_size - 1);
187}
188
189static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
190 unsigned int index)
191{
192 index = macb_tx_ring_wrap(queue->bp, index);
193 index = macb_adj_dma_desc_idx(queue->bp, index);
194 return &queue->tx_ring[index];
195}
196
197static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
198 unsigned int index)
199{
200 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
201}
202
203static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
204{
205 dma_addr_t offset;
206
207 offset = macb_tx_ring_wrap(queue->bp, index) *
208 macb_dma_desc_get_size(queue->bp);
209
210 return queue->tx_ring_dma + offset;
211}
212
213static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
214{
215 return index & (bp->rx_ring_size - 1);
216}
217
218static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
219{
220 index = macb_rx_ring_wrap(queue->bp, index);
221 index = macb_adj_dma_desc_idx(queue->bp, index);
222 return &queue->rx_ring[index];
223}
224
225static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
226{
227 return queue->rx_buffers + queue->bp->rx_buffer_size *
228 macb_rx_ring_wrap(queue->bp, index);
229}
230
231/* I/O accessors */
232static u32 hw_readl_native(struct macb *bp, int offset)
233{
234 return __raw_readl(bp->regs + offset);
235}
236
237static void hw_writel_native(struct macb *bp, int offset, u32 value)
238{
239 __raw_writel(value, bp->regs + offset);
240}
241
242static u32 hw_readl(struct macb *bp, int offset)
243{
244 return readl_relaxed(bp->regs + offset);
245}
246
247static void hw_writel(struct macb *bp, int offset, u32 value)
248{
249 writel_relaxed(value, bp->regs + offset);
250}
251
252/* Find the CPU endianness by using the loopback bit of NCR register. When the
253 * CPU is in big endian we need to program swapped mode for management
254 * descriptor access.
255 */
256static bool hw_is_native_io(void __iomem *addr)
257{
258 u32 value = MACB_BIT(LLB);
259
260 __raw_writel(value, addr + MACB_NCR);
261 value = __raw_readl(addr + MACB_NCR);
262
263 /* Write 0 back to disable everything */
264 __raw_writel(0, addr + MACB_NCR);
265
266 return value == MACB_BIT(LLB);
267}
268
269static bool hw_is_gem(void __iomem *addr, bool native_io)
270{
271 u32 id;
272
273 if (native_io)
274 id = __raw_readl(addr + MACB_MID);
275 else
276 id = readl_relaxed(addr + MACB_MID);
277
278 return MACB_BFEXT(IDNUM, id) >= 0x2;
279}
280
281static void macb_set_hwaddr(struct macb *bp)
282{
283 u32 bottom;
284 u16 top;
285
286 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
287 macb_or_gem_writel(bp, SA1B, bottom);
288 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
289 macb_or_gem_writel(bp, SA1T, top);
290
291 /* Clear unused address register sets */
292 macb_or_gem_writel(bp, SA2B, 0);
293 macb_or_gem_writel(bp, SA2T, 0);
294 macb_or_gem_writel(bp, SA3B, 0);
295 macb_or_gem_writel(bp, SA3T, 0);
296 macb_or_gem_writel(bp, SA4B, 0);
297 macb_or_gem_writel(bp, SA4T, 0);
298}
299
300static void macb_get_hwaddr(struct macb *bp)
301{
302 u32 bottom;
303 u16 top;
304 u8 addr[6];
305 int i;
306
307 /* Check all 4 address register for valid address */
308 for (i = 0; i < 4; i++) {
309 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
310 top = macb_or_gem_readl(bp, SA1T + i * 8);
311
312 addr[0] = bottom & 0xff;
313 addr[1] = (bottom >> 8) & 0xff;
314 addr[2] = (bottom >> 16) & 0xff;
315 addr[3] = (bottom >> 24) & 0xff;
316 addr[4] = top & 0xff;
317 addr[5] = (top >> 8) & 0xff;
318
319 if (is_valid_ether_addr(addr)) {
320 eth_hw_addr_set(bp->dev, addr);
321 return;
322 }
323 }
324
325 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
326 eth_hw_addr_random(bp->dev);
327}
328
329static int macb_mdio_wait_for_idle(struct macb *bp)
330{
331 u32 val;
332
333 return readx_poll_timeout(MACB_READ_NSR, bp, val, val & MACB_BIT(IDLE),
334 1, MACB_MDIO_TIMEOUT);
335}
336
337static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
338{
339 struct macb *bp = bus->priv;
340 int status;
341
342 status = pm_runtime_resume_and_get(&bp->pdev->dev);
343 if (status < 0)
344 goto mdio_pm_exit;
345
346 status = macb_mdio_wait_for_idle(bp);
347 if (status < 0)
348 goto mdio_read_exit;
349
350 if (regnum & MII_ADDR_C45) {
351 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
352 | MACB_BF(RW, MACB_MAN_C45_ADDR)
353 | MACB_BF(PHYA, mii_id)
354 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
355 | MACB_BF(DATA, regnum & 0xFFFF)
356 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
357
358 status = macb_mdio_wait_for_idle(bp);
359 if (status < 0)
360 goto mdio_read_exit;
361
362 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
363 | MACB_BF(RW, MACB_MAN_C45_READ)
364 | MACB_BF(PHYA, mii_id)
365 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
366 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
367 } else {
368 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
369 | MACB_BF(RW, MACB_MAN_C22_READ)
370 | MACB_BF(PHYA, mii_id)
371 | MACB_BF(REGA, regnum)
372 | MACB_BF(CODE, MACB_MAN_C22_CODE)));
373 }
374
375 status = macb_mdio_wait_for_idle(bp);
376 if (status < 0)
377 goto mdio_read_exit;
378
379 status = MACB_BFEXT(DATA, macb_readl(bp, MAN));
380
381mdio_read_exit:
382 pm_runtime_mark_last_busy(&bp->pdev->dev);
383 pm_runtime_put_autosuspend(&bp->pdev->dev);
384mdio_pm_exit:
385 return status;
386}
387
388static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
389 u16 value)
390{
391 struct macb *bp = bus->priv;
392 int status;
393
394 status = pm_runtime_resume_and_get(&bp->pdev->dev);
395 if (status < 0)
396 goto mdio_pm_exit;
397
398 status = macb_mdio_wait_for_idle(bp);
399 if (status < 0)
400 goto mdio_write_exit;
401
402 if (regnum & MII_ADDR_C45) {
403 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
404 | MACB_BF(RW, MACB_MAN_C45_ADDR)
405 | MACB_BF(PHYA, mii_id)
406 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
407 | MACB_BF(DATA, regnum & 0xFFFF)
408 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
409
410 status = macb_mdio_wait_for_idle(bp);
411 if (status < 0)
412 goto mdio_write_exit;
413
414 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
415 | MACB_BF(RW, MACB_MAN_C45_WRITE)
416 | MACB_BF(PHYA, mii_id)
417 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
418 | MACB_BF(CODE, MACB_MAN_C45_CODE)
419 | MACB_BF(DATA, value)));
420 } else {
421 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
422 | MACB_BF(RW, MACB_MAN_C22_WRITE)
423 | MACB_BF(PHYA, mii_id)
424 | MACB_BF(REGA, regnum)
425 | MACB_BF(CODE, MACB_MAN_C22_CODE)
426 | MACB_BF(DATA, value)));
427 }
428
429 status = macb_mdio_wait_for_idle(bp);
430 if (status < 0)
431 goto mdio_write_exit;
432
433mdio_write_exit:
434 pm_runtime_mark_last_busy(&bp->pdev->dev);
435 pm_runtime_put_autosuspend(&bp->pdev->dev);
436mdio_pm_exit:
437 return status;
438}
439
440static void macb_init_buffers(struct macb *bp)
441{
442 struct macb_queue *queue;
443 unsigned int q;
444
445 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
446 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
447#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
448 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
449 queue_writel(queue, RBQPH,
450 upper_32_bits(queue->rx_ring_dma));
451#endif
452 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
453#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
454 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
455 queue_writel(queue, TBQPH,
456 upper_32_bits(queue->tx_ring_dma));
457#endif
458 }
459}
460
461/**
462 * macb_set_tx_clk() - Set a clock to a new frequency
463 * @bp: pointer to struct macb
464 * @speed: New frequency in Hz
465 */
466static void macb_set_tx_clk(struct macb *bp, int speed)
467{
468 long ferr, rate, rate_rounded;
469
470 if (!bp->tx_clk || (bp->caps & MACB_CAPS_CLK_HW_CHG))
471 return;
472
473 /* In case of MII the PHY is the clock master */
474 if (bp->phy_interface == PHY_INTERFACE_MODE_MII)
475 return;
476
477 switch (speed) {
478 case SPEED_10:
479 rate = 2500000;
480 break;
481 case SPEED_100:
482 rate = 25000000;
483 break;
484 case SPEED_1000:
485 rate = 125000000;
486 break;
487 default:
488 return;
489 }
490
491 rate_rounded = clk_round_rate(bp->tx_clk, rate);
492 if (rate_rounded < 0)
493 return;
494
495 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
496 * is not satisfied.
497 */
498 ferr = abs(rate_rounded - rate);
499 ferr = DIV_ROUND_UP(ferr, rate / 100000);
500 if (ferr > 5)
501 netdev_warn(bp->dev,
502 "unable to generate target frequency: %ld Hz\n",
503 rate);
504
505 if (clk_set_rate(bp->tx_clk, rate_rounded))
506 netdev_err(bp->dev, "adjusting tx_clk failed.\n");
507}
508
509static void macb_usx_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
510 phy_interface_t interface, int speed,
511 int duplex)
512{
513 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
514 u32 config;
515
516 config = gem_readl(bp, USX_CONTROL);
517 config = GEM_BFINS(SERDES_RATE, MACB_SERDES_RATE_10G, config);
518 config = GEM_BFINS(USX_CTRL_SPEED, HS_SPEED_10000M, config);
519 config &= ~(GEM_BIT(TX_SCR_BYPASS) | GEM_BIT(RX_SCR_BYPASS));
520 config |= GEM_BIT(TX_EN);
521 gem_writel(bp, USX_CONTROL, config);
522}
523
524static void macb_usx_pcs_get_state(struct phylink_pcs *pcs,
525 struct phylink_link_state *state)
526{
527 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
528 u32 val;
529
530 state->speed = SPEED_10000;
531 state->duplex = 1;
532 state->an_complete = 1;
533
534 val = gem_readl(bp, USX_STATUS);
535 state->link = !!(val & GEM_BIT(USX_BLOCK_LOCK));
536 val = gem_readl(bp, NCFGR);
537 if (val & GEM_BIT(PAE))
538 state->pause = MLO_PAUSE_RX;
539}
540
541static int macb_usx_pcs_config(struct phylink_pcs *pcs,
542 unsigned int mode,
543 phy_interface_t interface,
544 const unsigned long *advertising,
545 bool permit_pause_to_mac)
546{
547 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
548
549 gem_writel(bp, USX_CONTROL, gem_readl(bp, USX_CONTROL) |
550 GEM_BIT(SIGNAL_OK));
551
552 return 0;
553}
554
555static void macb_pcs_get_state(struct phylink_pcs *pcs,
556 struct phylink_link_state *state)
557{
558 state->link = 0;
559}
560
561static void macb_pcs_an_restart(struct phylink_pcs *pcs)
562{
563 /* Not supported */
564}
565
566static int macb_pcs_config(struct phylink_pcs *pcs,
567 unsigned int mode,
568 phy_interface_t interface,
569 const unsigned long *advertising,
570 bool permit_pause_to_mac)
571{
572 return 0;
573}
574
575static const struct phylink_pcs_ops macb_phylink_usx_pcs_ops = {
576 .pcs_get_state = macb_usx_pcs_get_state,
577 .pcs_config = macb_usx_pcs_config,
578 .pcs_link_up = macb_usx_pcs_link_up,
579};
580
581static const struct phylink_pcs_ops macb_phylink_pcs_ops = {
582 .pcs_get_state = macb_pcs_get_state,
583 .pcs_an_restart = macb_pcs_an_restart,
584 .pcs_config = macb_pcs_config,
585};
586
587static void macb_mac_config(struct phylink_config *config, unsigned int mode,
588 const struct phylink_link_state *state)
589{
590 struct net_device *ndev = to_net_dev(config->dev);
591 struct macb *bp = netdev_priv(ndev);
592 unsigned long flags;
593 u32 old_ctrl, ctrl;
594 u32 old_ncr, ncr;
595
596 spin_lock_irqsave(&bp->lock, flags);
597
598 old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR);
599 old_ncr = ncr = macb_or_gem_readl(bp, NCR);
600
601 if (bp->caps & MACB_CAPS_MACB_IS_EMAC) {
602 if (state->interface == PHY_INTERFACE_MODE_RMII)
603 ctrl |= MACB_BIT(RM9200_RMII);
604 } else if (macb_is_gem(bp)) {
605 ctrl &= ~(GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL));
606 ncr &= ~GEM_BIT(ENABLE_HS_MAC);
607
608 if (state->interface == PHY_INTERFACE_MODE_SGMII) {
609 ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
610 } else if (state->interface == PHY_INTERFACE_MODE_10GBASER) {
611 ctrl |= GEM_BIT(PCSSEL);
612 ncr |= GEM_BIT(ENABLE_HS_MAC);
613 } else if (bp->caps & MACB_CAPS_MIIONRGMII &&
614 bp->phy_interface == PHY_INTERFACE_MODE_MII) {
615 ncr |= MACB_BIT(MIIONRGMII);
616 }
617 }
618
619 /* Apply the new configuration, if any */
620 if (old_ctrl ^ ctrl)
621 macb_or_gem_writel(bp, NCFGR, ctrl);
622
623 if (old_ncr ^ ncr)
624 macb_or_gem_writel(bp, NCR, ncr);
625
626 /* Disable AN for SGMII fixed link configuration, enable otherwise.
627 * Must be written after PCSSEL is set in NCFGR,
628 * otherwise writes will not take effect.
629 */
630 if (macb_is_gem(bp) && state->interface == PHY_INTERFACE_MODE_SGMII) {
631 u32 pcsctrl, old_pcsctrl;
632
633 old_pcsctrl = gem_readl(bp, PCSCNTRL);
634 if (mode == MLO_AN_FIXED)
635 pcsctrl = old_pcsctrl & ~GEM_BIT(PCSAUTONEG);
636 else
637 pcsctrl = old_pcsctrl | GEM_BIT(PCSAUTONEG);
638 if (old_pcsctrl != pcsctrl)
639 gem_writel(bp, PCSCNTRL, pcsctrl);
640 }
641
642 spin_unlock_irqrestore(&bp->lock, flags);
643}
644
645static void macb_mac_link_down(struct phylink_config *config, unsigned int mode,
646 phy_interface_t interface)
647{
648 struct net_device *ndev = to_net_dev(config->dev);
649 struct macb *bp = netdev_priv(ndev);
650 struct macb_queue *queue;
651 unsigned int q;
652 u32 ctrl;
653
654 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC))
655 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
656 queue_writel(queue, IDR,
657 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
658
659 /* Disable Rx and Tx */
660 ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE));
661 macb_writel(bp, NCR, ctrl);
662
663 netif_tx_stop_all_queues(ndev);
664}
665
666static void macb_mac_link_up(struct phylink_config *config,
667 struct phy_device *phy,
668 unsigned int mode, phy_interface_t interface,
669 int speed, int duplex,
670 bool tx_pause, bool rx_pause)
671{
672 struct net_device *ndev = to_net_dev(config->dev);
673 struct macb *bp = netdev_priv(ndev);
674 struct macb_queue *queue;
675 unsigned long flags;
676 unsigned int q;
677 u32 ctrl;
678
679 spin_lock_irqsave(&bp->lock, flags);
680
681 ctrl = macb_or_gem_readl(bp, NCFGR);
682
683 ctrl &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
684
685 if (speed == SPEED_100)
686 ctrl |= MACB_BIT(SPD);
687
688 if (duplex)
689 ctrl |= MACB_BIT(FD);
690
691 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) {
692 ctrl &= ~MACB_BIT(PAE);
693 if (macb_is_gem(bp)) {
694 ctrl &= ~GEM_BIT(GBE);
695
696 if (speed == SPEED_1000)
697 ctrl |= GEM_BIT(GBE);
698 }
699
700 if (rx_pause)
701 ctrl |= MACB_BIT(PAE);
702
703 macb_set_tx_clk(bp, speed);
704
705 /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
706 * cleared the pipeline and control registers.
707 */
708 bp->macbgem_ops.mog_init_rings(bp);
709 macb_init_buffers(bp);
710
711 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
712 queue_writel(queue, IER,
713 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
714 }
715
716 macb_or_gem_writel(bp, NCFGR, ctrl);
717
718 if (bp->phy_interface == PHY_INTERFACE_MODE_10GBASER)
719 gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_10000M,
720 gem_readl(bp, HS_MAC_CONFIG)));
721
722 spin_unlock_irqrestore(&bp->lock, flags);
723
724 /* Enable Rx and Tx */
725 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
726
727 netif_tx_wake_all_queues(ndev);
728}
729
730static struct phylink_pcs *macb_mac_select_pcs(struct phylink_config *config,
731 phy_interface_t interface)
732{
733 struct net_device *ndev = to_net_dev(config->dev);
734 struct macb *bp = netdev_priv(ndev);
735
736 if (interface == PHY_INTERFACE_MODE_10GBASER)
737 return &bp->phylink_usx_pcs;
738 else if (interface == PHY_INTERFACE_MODE_SGMII)
739 return &bp->phylink_sgmii_pcs;
740 else
741 return NULL;
742}
743
744static const struct phylink_mac_ops macb_phylink_ops = {
745 .mac_select_pcs = macb_mac_select_pcs,
746 .mac_config = macb_mac_config,
747 .mac_link_down = macb_mac_link_down,
748 .mac_link_up = macb_mac_link_up,
749};
750
751static bool macb_phy_handle_exists(struct device_node *dn)
752{
753 dn = of_parse_phandle(dn, "phy-handle", 0);
754 of_node_put(dn);
755 return dn != NULL;
756}
757
758static int macb_phylink_connect(struct macb *bp)
759{
760 struct device_node *dn = bp->pdev->dev.of_node;
761 struct net_device *dev = bp->dev;
762 struct phy_device *phydev;
763 int ret;
764
765 if (dn)
766 ret = phylink_of_phy_connect(bp->phylink, dn, 0);
767
768 if (!dn || (ret && !macb_phy_handle_exists(dn))) {
769 phydev = phy_find_first(bp->mii_bus);
770 if (!phydev) {
771 netdev_err(dev, "no PHY found\n");
772 return -ENXIO;
773 }
774
775 /* attach the mac to the phy */
776 ret = phylink_connect_phy(bp->phylink, phydev);
777 }
778
779 if (ret) {
780 netdev_err(dev, "Could not attach PHY (%d)\n", ret);
781 return ret;
782 }
783
784 phylink_start(bp->phylink);
785
786 return 0;
787}
788
789static void macb_get_pcs_fixed_state(struct phylink_config *config,
790 struct phylink_link_state *state)
791{
792 struct net_device *ndev = to_net_dev(config->dev);
793 struct macb *bp = netdev_priv(ndev);
794
795 state->link = (macb_readl(bp, NSR) & MACB_BIT(NSR_LINK)) != 0;
796}
797
798/* based on au1000_eth. c*/
799static int macb_mii_probe(struct net_device *dev)
800{
801 struct macb *bp = netdev_priv(dev);
802
803 bp->phylink_sgmii_pcs.ops = &macb_phylink_pcs_ops;
804 bp->phylink_usx_pcs.ops = &macb_phylink_usx_pcs_ops;
805
806 bp->phylink_config.dev = &dev->dev;
807 bp->phylink_config.type = PHYLINK_NETDEV;
808 bp->phylink_config.mac_managed_pm = true;
809
810 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
811 bp->phylink_config.poll_fixed_state = true;
812 bp->phylink_config.get_fixed_state = macb_get_pcs_fixed_state;
813 }
814
815 bp->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
816 MAC_10 | MAC_100;
817
818 __set_bit(PHY_INTERFACE_MODE_MII,
819 bp->phylink_config.supported_interfaces);
820 __set_bit(PHY_INTERFACE_MODE_RMII,
821 bp->phylink_config.supported_interfaces);
822
823 /* Determine what modes are supported */
824 if (macb_is_gem(bp) && (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)) {
825 bp->phylink_config.mac_capabilities |= MAC_1000FD;
826 if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF))
827 bp->phylink_config.mac_capabilities |= MAC_1000HD;
828
829 __set_bit(PHY_INTERFACE_MODE_GMII,
830 bp->phylink_config.supported_interfaces);
831 phy_interface_set_rgmii(bp->phylink_config.supported_interfaces);
832
833 if (bp->caps & MACB_CAPS_PCS)
834 __set_bit(PHY_INTERFACE_MODE_SGMII,
835 bp->phylink_config.supported_interfaces);
836
837 if (bp->caps & MACB_CAPS_HIGH_SPEED) {
838 __set_bit(PHY_INTERFACE_MODE_10GBASER,
839 bp->phylink_config.supported_interfaces);
840 bp->phylink_config.mac_capabilities |= MAC_10000FD;
841 }
842 }
843
844 bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode,
845 bp->phy_interface, &macb_phylink_ops);
846 if (IS_ERR(bp->phylink)) {
847 netdev_err(dev, "Could not create a phylink instance (%ld)\n",
848 PTR_ERR(bp->phylink));
849 return PTR_ERR(bp->phylink);
850 }
851
852 return 0;
853}
854
855static int macb_mdiobus_register(struct macb *bp)
856{
857 struct device_node *child, *np = bp->pdev->dev.of_node;
858
859 /* If we have a child named mdio, probe it instead of looking for PHYs
860 * directly under the MAC node
861 */
862 child = of_get_child_by_name(np, "mdio");
863 if (child) {
864 int ret = of_mdiobus_register(bp->mii_bus, child);
865
866 of_node_put(child);
867 return ret;
868 }
869
870 if (of_phy_is_fixed_link(np))
871 return mdiobus_register(bp->mii_bus);
872
873 /* Only create the PHY from the device tree if at least one PHY is
874 * described. Otherwise scan the entire MDIO bus. We do this to support
875 * old device tree that did not follow the best practices and did not
876 * describe their network PHYs.
877 */
878 for_each_available_child_of_node(np, child)
879 if (of_mdiobus_child_is_phy(child)) {
880 /* The loop increments the child refcount,
881 * decrement it before returning.
882 */
883 of_node_put(child);
884
885 return of_mdiobus_register(bp->mii_bus, np);
886 }
887
888 return mdiobus_register(bp->mii_bus);
889}
890
891static int macb_mii_init(struct macb *bp)
892{
893 int err = -ENXIO;
894
895 /* Enable management port */
896 macb_writel(bp, NCR, MACB_BIT(MPE));
897
898 bp->mii_bus = mdiobus_alloc();
899 if (!bp->mii_bus) {
900 err = -ENOMEM;
901 goto err_out;
902 }
903
904 bp->mii_bus->name = "MACB_mii_bus";
905 bp->mii_bus->read = &macb_mdio_read;
906 bp->mii_bus->write = &macb_mdio_write;
907 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
908 bp->pdev->name, bp->pdev->id);
909 bp->mii_bus->priv = bp;
910 bp->mii_bus->parent = &bp->pdev->dev;
911
912 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
913
914 err = macb_mdiobus_register(bp);
915 if (err)
916 goto err_out_free_mdiobus;
917
918 err = macb_mii_probe(bp->dev);
919 if (err)
920 goto err_out_unregister_bus;
921
922 return 0;
923
924err_out_unregister_bus:
925 mdiobus_unregister(bp->mii_bus);
926err_out_free_mdiobus:
927 mdiobus_free(bp->mii_bus);
928err_out:
929 return err;
930}
931
932static void macb_update_stats(struct macb *bp)
933{
934 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
935 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
936 int offset = MACB_PFR;
937
938 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
939
940 for (; p < end; p++, offset += 4)
941 *p += bp->macb_reg_readl(bp, offset);
942}
943
944static int macb_halt_tx(struct macb *bp)
945{
946 unsigned long halt_time, timeout;
947 u32 status;
948
949 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
950
951 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
952 do {
953 halt_time = jiffies;
954 status = macb_readl(bp, TSR);
955 if (!(status & MACB_BIT(TGO)))
956 return 0;
957
958 udelay(250);
959 } while (time_before(halt_time, timeout));
960
961 return -ETIMEDOUT;
962}
963
964static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb, int budget)
965{
966 if (tx_skb->mapping) {
967 if (tx_skb->mapped_as_page)
968 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
969 tx_skb->size, DMA_TO_DEVICE);
970 else
971 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
972 tx_skb->size, DMA_TO_DEVICE);
973 tx_skb->mapping = 0;
974 }
975
976 if (tx_skb->skb) {
977 napi_consume_skb(tx_skb->skb, budget);
978 tx_skb->skb = NULL;
979 }
980}
981
982static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
983{
984#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
985 struct macb_dma_desc_64 *desc_64;
986
987 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
988 desc_64 = macb_64b_desc(bp, desc);
989 desc_64->addrh = upper_32_bits(addr);
990 /* The low bits of RX address contain the RX_USED bit, clearing
991 * of which allows packet RX. Make sure the high bits are also
992 * visible to HW at that point.
993 */
994 dma_wmb();
995 }
996#endif
997 desc->addr = lower_32_bits(addr);
998}
999
1000static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
1001{
1002 dma_addr_t addr = 0;
1003#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1004 struct macb_dma_desc_64 *desc_64;
1005
1006 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
1007 desc_64 = macb_64b_desc(bp, desc);
1008 addr = ((u64)(desc_64->addrh) << 32);
1009 }
1010#endif
1011 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1012 return addr;
1013}
1014
1015static void macb_tx_error_task(struct work_struct *work)
1016{
1017 struct macb_queue *queue = container_of(work, struct macb_queue,
1018 tx_error_task);
1019 struct macb *bp = queue->bp;
1020 struct macb_tx_skb *tx_skb;
1021 struct macb_dma_desc *desc;
1022 struct sk_buff *skb;
1023 unsigned int tail;
1024 unsigned long flags;
1025
1026 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
1027 (unsigned int)(queue - bp->queues),
1028 queue->tx_tail, queue->tx_head);
1029
1030 /* Prevent the queue NAPI TX poll from running, as it calls
1031 * macb_tx_complete(), which in turn may call netif_wake_subqueue().
1032 * As explained below, we have to halt the transmission before updating
1033 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
1034 * network engine about the macb/gem being halted.
1035 */
1036 napi_disable(&queue->napi_tx);
1037 spin_lock_irqsave(&bp->lock, flags);
1038
1039 /* Make sure nobody is trying to queue up new packets */
1040 netif_tx_stop_all_queues(bp->dev);
1041
1042 /* Stop transmission now
1043 * (in case we have just queued new packets)
1044 * macb/gem must be halted to write TBQP register
1045 */
1046 if (macb_halt_tx(bp))
1047 /* Just complain for now, reinitializing TX path can be good */
1048 netdev_err(bp->dev, "BUG: halt tx timed out\n");
1049
1050 /* Treat frames in TX queue including the ones that caused the error.
1051 * Free transmit buffers in upper layer.
1052 */
1053 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
1054 u32 ctrl;
1055
1056 desc = macb_tx_desc(queue, tail);
1057 ctrl = desc->ctrl;
1058 tx_skb = macb_tx_skb(queue, tail);
1059 skb = tx_skb->skb;
1060
1061 if (ctrl & MACB_BIT(TX_USED)) {
1062 /* skb is set for the last buffer of the frame */
1063 while (!skb) {
1064 macb_tx_unmap(bp, tx_skb, 0);
1065 tail++;
1066 tx_skb = macb_tx_skb(queue, tail);
1067 skb = tx_skb->skb;
1068 }
1069
1070 /* ctrl still refers to the first buffer descriptor
1071 * since it's the only one written back by the hardware
1072 */
1073 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
1074 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
1075 macb_tx_ring_wrap(bp, tail),
1076 skb->data);
1077 bp->dev->stats.tx_packets++;
1078 queue->stats.tx_packets++;
1079 bp->dev->stats.tx_bytes += skb->len;
1080 queue->stats.tx_bytes += skb->len;
1081 }
1082 } else {
1083 /* "Buffers exhausted mid-frame" errors may only happen
1084 * if the driver is buggy, so complain loudly about
1085 * those. Statistics are updated by hardware.
1086 */
1087 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
1088 netdev_err(bp->dev,
1089 "BUG: TX buffers exhausted mid-frame\n");
1090
1091 desc->ctrl = ctrl | MACB_BIT(TX_USED);
1092 }
1093
1094 macb_tx_unmap(bp, tx_skb, 0);
1095 }
1096
1097 /* Set end of TX queue */
1098 desc = macb_tx_desc(queue, 0);
1099 macb_set_addr(bp, desc, 0);
1100 desc->ctrl = MACB_BIT(TX_USED);
1101
1102 /* Make descriptor updates visible to hardware */
1103 wmb();
1104
1105 /* Reinitialize the TX desc queue */
1106 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
1107#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1108 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1109 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
1110#endif
1111 /* Make TX ring reflect state of hardware */
1112 queue->tx_head = 0;
1113 queue->tx_tail = 0;
1114
1115 /* Housework before enabling TX IRQ */
1116 macb_writel(bp, TSR, macb_readl(bp, TSR));
1117 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
1118
1119 /* Now we are ready to start transmission again */
1120 netif_tx_start_all_queues(bp->dev);
1121 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1122
1123 spin_unlock_irqrestore(&bp->lock, flags);
1124 napi_enable(&queue->napi_tx);
1125}
1126
1127static bool ptp_one_step_sync(struct sk_buff *skb)
1128{
1129 struct ptp_header *hdr;
1130 unsigned int ptp_class;
1131 u8 msgtype;
1132
1133 /* No need to parse packet if PTP TS is not involved */
1134 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
1135 goto not_oss;
1136
1137 /* Identify and return whether PTP one step sync is being processed */
1138 ptp_class = ptp_classify_raw(skb);
1139 if (ptp_class == PTP_CLASS_NONE)
1140 goto not_oss;
1141
1142 hdr = ptp_parse_header(skb, ptp_class);
1143 if (!hdr)
1144 goto not_oss;
1145
1146 if (hdr->flag_field[0] & PTP_FLAG_TWOSTEP)
1147 goto not_oss;
1148
1149 msgtype = ptp_get_msgtype(hdr, ptp_class);
1150 if (msgtype == PTP_MSGTYPE_SYNC)
1151 return true;
1152
1153not_oss:
1154 return false;
1155}
1156
1157static int macb_tx_complete(struct macb_queue *queue, int budget)
1158{
1159 struct macb *bp = queue->bp;
1160 u16 queue_index = queue - bp->queues;
1161 unsigned int tail;
1162 unsigned int head;
1163 int packets = 0;
1164
1165 spin_lock(&queue->tx_ptr_lock);
1166 head = queue->tx_head;
1167 for (tail = queue->tx_tail; tail != head && packets < budget; tail++) {
1168 struct macb_tx_skb *tx_skb;
1169 struct sk_buff *skb;
1170 struct macb_dma_desc *desc;
1171 u32 ctrl;
1172
1173 desc = macb_tx_desc(queue, tail);
1174
1175 /* Make hw descriptor updates visible to CPU */
1176 rmb();
1177
1178 ctrl = desc->ctrl;
1179
1180 /* TX_USED bit is only set by hardware on the very first buffer
1181 * descriptor of the transmitted frame.
1182 */
1183 if (!(ctrl & MACB_BIT(TX_USED)))
1184 break;
1185
1186 /* Process all buffers of the current transmitted frame */
1187 for (;; tail++) {
1188 tx_skb = macb_tx_skb(queue, tail);
1189 skb = tx_skb->skb;
1190
1191 /* First, update TX stats if needed */
1192 if (skb) {
1193 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1194 !ptp_one_step_sync(skb) &&
1195 gem_ptp_do_txstamp(queue, skb, desc) == 0) {
1196 /* skb now belongs to timestamp buffer
1197 * and will be removed later
1198 */
1199 tx_skb->skb = NULL;
1200 }
1201 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
1202 macb_tx_ring_wrap(bp, tail),
1203 skb->data);
1204 bp->dev->stats.tx_packets++;
1205 queue->stats.tx_packets++;
1206 bp->dev->stats.tx_bytes += skb->len;
1207 queue->stats.tx_bytes += skb->len;
1208 packets++;
1209 }
1210
1211 /* Now we can safely release resources */
1212 macb_tx_unmap(bp, tx_skb, budget);
1213
1214 /* skb is set only for the last buffer of the frame.
1215 * WARNING: at this point skb has been freed by
1216 * macb_tx_unmap().
1217 */
1218 if (skb)
1219 break;
1220 }
1221 }
1222
1223 queue->tx_tail = tail;
1224 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
1225 CIRC_CNT(queue->tx_head, queue->tx_tail,
1226 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
1227 netif_wake_subqueue(bp->dev, queue_index);
1228 spin_unlock(&queue->tx_ptr_lock);
1229
1230 return packets;
1231}
1232
1233static void gem_rx_refill(struct macb_queue *queue)
1234{
1235 unsigned int entry;
1236 struct sk_buff *skb;
1237 dma_addr_t paddr;
1238 struct macb *bp = queue->bp;
1239 struct macb_dma_desc *desc;
1240
1241 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
1242 bp->rx_ring_size) > 0) {
1243 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head);
1244
1245 /* Make hw descriptor updates visible to CPU */
1246 rmb();
1247
1248 desc = macb_rx_desc(queue, entry);
1249
1250 if (!queue->rx_skbuff[entry]) {
1251 /* allocate sk_buff for this free entry in ring */
1252 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
1253 if (unlikely(!skb)) {
1254 netdev_err(bp->dev,
1255 "Unable to allocate sk_buff\n");
1256 break;
1257 }
1258
1259 /* now fill corresponding descriptor entry */
1260 paddr = dma_map_single(&bp->pdev->dev, skb->data,
1261 bp->rx_buffer_size,
1262 DMA_FROM_DEVICE);
1263 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
1264 dev_kfree_skb(skb);
1265 break;
1266 }
1267
1268 queue->rx_skbuff[entry] = skb;
1269
1270 if (entry == bp->rx_ring_size - 1)
1271 paddr |= MACB_BIT(RX_WRAP);
1272 desc->ctrl = 0;
1273 /* Setting addr clears RX_USED and allows reception,
1274 * make sure ctrl is cleared first to avoid a race.
1275 */
1276 dma_wmb();
1277 macb_set_addr(bp, desc, paddr);
1278
1279 /* properly align Ethernet header */
1280 skb_reserve(skb, NET_IP_ALIGN);
1281 } else {
1282 desc->ctrl = 0;
1283 dma_wmb();
1284 desc->addr &= ~MACB_BIT(RX_USED);
1285 }
1286 queue->rx_prepared_head++;
1287 }
1288
1289 /* Make descriptor updates visible to hardware */
1290 wmb();
1291
1292 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
1293 queue, queue->rx_prepared_head, queue->rx_tail);
1294}
1295
1296/* Mark DMA descriptors from begin up to and not including end as unused */
1297static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
1298 unsigned int end)
1299{
1300 unsigned int frag;
1301
1302 for (frag = begin; frag != end; frag++) {
1303 struct macb_dma_desc *desc = macb_rx_desc(queue, frag);
1304
1305 desc->addr &= ~MACB_BIT(RX_USED);
1306 }
1307
1308 /* Make descriptor updates visible to hardware */
1309 wmb();
1310
1311 /* When this happens, the hardware stats registers for
1312 * whatever caused this is updated, so we don't have to record
1313 * anything.
1314 */
1315}
1316
1317static int gem_rx(struct macb_queue *queue, struct napi_struct *napi,
1318 int budget)
1319{
1320 struct macb *bp = queue->bp;
1321 unsigned int len;
1322 unsigned int entry;
1323 struct sk_buff *skb;
1324 struct macb_dma_desc *desc;
1325 int count = 0;
1326
1327 while (count < budget) {
1328 u32 ctrl;
1329 dma_addr_t addr;
1330 bool rxused;
1331
1332 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1333 desc = macb_rx_desc(queue, entry);
1334
1335 /* Make hw descriptor updates visible to CPU */
1336 rmb();
1337
1338 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
1339 addr = macb_get_addr(bp, desc);
1340
1341 if (!rxused)
1342 break;
1343
1344 /* Ensure ctrl is at least as up-to-date as rxused */
1345 dma_rmb();
1346
1347 ctrl = desc->ctrl;
1348
1349 queue->rx_tail++;
1350 count++;
1351
1352 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1353 netdev_err(bp->dev,
1354 "not whole frame pointed by descriptor\n");
1355 bp->dev->stats.rx_dropped++;
1356 queue->stats.rx_dropped++;
1357 break;
1358 }
1359 skb = queue->rx_skbuff[entry];
1360 if (unlikely(!skb)) {
1361 netdev_err(bp->dev,
1362 "inconsistent Rx descriptor chain\n");
1363 bp->dev->stats.rx_dropped++;
1364 queue->stats.rx_dropped++;
1365 break;
1366 }
1367 /* now everything is ready for receiving packet */
1368 queue->rx_skbuff[entry] = NULL;
1369 len = ctrl & bp->rx_frm_len_mask;
1370
1371 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1372
1373 skb_put(skb, len);
1374 dma_unmap_single(&bp->pdev->dev, addr,
1375 bp->rx_buffer_size, DMA_FROM_DEVICE);
1376
1377 skb->protocol = eth_type_trans(skb, bp->dev);
1378 skb_checksum_none_assert(skb);
1379 if (bp->dev->features & NETIF_F_RXCSUM &&
1380 !(bp->dev->flags & IFF_PROMISC) &&
1381 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1382 skb->ip_summed = CHECKSUM_UNNECESSARY;
1383
1384 bp->dev->stats.rx_packets++;
1385 queue->stats.rx_packets++;
1386 bp->dev->stats.rx_bytes += skb->len;
1387 queue->stats.rx_bytes += skb->len;
1388
1389 gem_ptp_do_rxstamp(bp, skb, desc);
1390
1391#if defined(DEBUG) && defined(VERBOSE_DEBUG)
1392 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1393 skb->len, skb->csum);
1394 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1395 skb_mac_header(skb), 16, true);
1396 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1397 skb->data, 32, true);
1398#endif
1399
1400 napi_gro_receive(napi, skb);
1401 }
1402
1403 gem_rx_refill(queue);
1404
1405 return count;
1406}
1407
1408static int macb_rx_frame(struct macb_queue *queue, struct napi_struct *napi,
1409 unsigned int first_frag, unsigned int last_frag)
1410{
1411 unsigned int len;
1412 unsigned int frag;
1413 unsigned int offset;
1414 struct sk_buff *skb;
1415 struct macb_dma_desc *desc;
1416 struct macb *bp = queue->bp;
1417
1418 desc = macb_rx_desc(queue, last_frag);
1419 len = desc->ctrl & bp->rx_frm_len_mask;
1420
1421 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1422 macb_rx_ring_wrap(bp, first_frag),
1423 macb_rx_ring_wrap(bp, last_frag), len);
1424
1425 /* The ethernet header starts NET_IP_ALIGN bytes into the
1426 * first buffer. Since the header is 14 bytes, this makes the
1427 * payload word-aligned.
1428 *
1429 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1430 * the two padding bytes into the skb so that we avoid hitting
1431 * the slowpath in memcpy(), and pull them off afterwards.
1432 */
1433 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1434 if (!skb) {
1435 bp->dev->stats.rx_dropped++;
1436 for (frag = first_frag; ; frag++) {
1437 desc = macb_rx_desc(queue, frag);
1438 desc->addr &= ~MACB_BIT(RX_USED);
1439 if (frag == last_frag)
1440 break;
1441 }
1442
1443 /* Make descriptor updates visible to hardware */
1444 wmb();
1445
1446 return 1;
1447 }
1448
1449 offset = 0;
1450 len += NET_IP_ALIGN;
1451 skb_checksum_none_assert(skb);
1452 skb_put(skb, len);
1453
1454 for (frag = first_frag; ; frag++) {
1455 unsigned int frag_len = bp->rx_buffer_size;
1456
1457 if (offset + frag_len > len) {
1458 if (unlikely(frag != last_frag)) {
1459 dev_kfree_skb_any(skb);
1460 return -1;
1461 }
1462 frag_len = len - offset;
1463 }
1464 skb_copy_to_linear_data_offset(skb, offset,
1465 macb_rx_buffer(queue, frag),
1466 frag_len);
1467 offset += bp->rx_buffer_size;
1468 desc = macb_rx_desc(queue, frag);
1469 desc->addr &= ~MACB_BIT(RX_USED);
1470
1471 if (frag == last_frag)
1472 break;
1473 }
1474
1475 /* Make descriptor updates visible to hardware */
1476 wmb();
1477
1478 __skb_pull(skb, NET_IP_ALIGN);
1479 skb->protocol = eth_type_trans(skb, bp->dev);
1480
1481 bp->dev->stats.rx_packets++;
1482 bp->dev->stats.rx_bytes += skb->len;
1483 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1484 skb->len, skb->csum);
1485 napi_gro_receive(napi, skb);
1486
1487 return 0;
1488}
1489
1490static inline void macb_init_rx_ring(struct macb_queue *queue)
1491{
1492 struct macb *bp = queue->bp;
1493 dma_addr_t addr;
1494 struct macb_dma_desc *desc = NULL;
1495 int i;
1496
1497 addr = queue->rx_buffers_dma;
1498 for (i = 0; i < bp->rx_ring_size; i++) {
1499 desc = macb_rx_desc(queue, i);
1500 macb_set_addr(bp, desc, addr);
1501 desc->ctrl = 0;
1502 addr += bp->rx_buffer_size;
1503 }
1504 desc->addr |= MACB_BIT(RX_WRAP);
1505 queue->rx_tail = 0;
1506}
1507
1508static int macb_rx(struct macb_queue *queue, struct napi_struct *napi,
1509 int budget)
1510{
1511 struct macb *bp = queue->bp;
1512 bool reset_rx_queue = false;
1513 int received = 0;
1514 unsigned int tail;
1515 int first_frag = -1;
1516
1517 for (tail = queue->rx_tail; budget > 0; tail++) {
1518 struct macb_dma_desc *desc = macb_rx_desc(queue, tail);
1519 u32 ctrl;
1520
1521 /* Make hw descriptor updates visible to CPU */
1522 rmb();
1523
1524 if (!(desc->addr & MACB_BIT(RX_USED)))
1525 break;
1526
1527 /* Ensure ctrl is at least as up-to-date as addr */
1528 dma_rmb();
1529
1530 ctrl = desc->ctrl;
1531
1532 if (ctrl & MACB_BIT(RX_SOF)) {
1533 if (first_frag != -1)
1534 discard_partial_frame(queue, first_frag, tail);
1535 first_frag = tail;
1536 }
1537
1538 if (ctrl & MACB_BIT(RX_EOF)) {
1539 int dropped;
1540
1541 if (unlikely(first_frag == -1)) {
1542 reset_rx_queue = true;
1543 continue;
1544 }
1545
1546 dropped = macb_rx_frame(queue, napi, first_frag, tail);
1547 first_frag = -1;
1548 if (unlikely(dropped < 0)) {
1549 reset_rx_queue = true;
1550 continue;
1551 }
1552 if (!dropped) {
1553 received++;
1554 budget--;
1555 }
1556 }
1557 }
1558
1559 if (unlikely(reset_rx_queue)) {
1560 unsigned long flags;
1561 u32 ctrl;
1562
1563 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1564
1565 spin_lock_irqsave(&bp->lock, flags);
1566
1567 ctrl = macb_readl(bp, NCR);
1568 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1569
1570 macb_init_rx_ring(queue);
1571 queue_writel(queue, RBQP, queue->rx_ring_dma);
1572
1573 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1574
1575 spin_unlock_irqrestore(&bp->lock, flags);
1576 return received;
1577 }
1578
1579 if (first_frag != -1)
1580 queue->rx_tail = first_frag;
1581 else
1582 queue->rx_tail = tail;
1583
1584 return received;
1585}
1586
1587static bool macb_rx_pending(struct macb_queue *queue)
1588{
1589 struct macb *bp = queue->bp;
1590 unsigned int entry;
1591 struct macb_dma_desc *desc;
1592
1593 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1594 desc = macb_rx_desc(queue, entry);
1595
1596 /* Make hw descriptor updates visible to CPU */
1597 rmb();
1598
1599 return (desc->addr & MACB_BIT(RX_USED)) != 0;
1600}
1601
1602static int macb_rx_poll(struct napi_struct *napi, int budget)
1603{
1604 struct macb_queue *queue = container_of(napi, struct macb_queue, napi_rx);
1605 struct macb *bp = queue->bp;
1606 int work_done;
1607
1608 work_done = bp->macbgem_ops.mog_rx(queue, napi, budget);
1609
1610 netdev_vdbg(bp->dev, "RX poll: queue = %u, work_done = %d, budget = %d\n",
1611 (unsigned int)(queue - bp->queues), work_done, budget);
1612
1613 if (work_done < budget && napi_complete_done(napi, work_done)) {
1614 queue_writel(queue, IER, bp->rx_intr_mask);
1615
1616 /* Packet completions only seem to propagate to raise
1617 * interrupts when interrupts are enabled at the time, so if
1618 * packets were received while interrupts were disabled,
1619 * they will not cause another interrupt to be generated when
1620 * interrupts are re-enabled.
1621 * Check for this case here to avoid losing a wakeup. This can
1622 * potentially race with the interrupt handler doing the same
1623 * actions if an interrupt is raised just after enabling them,
1624 * but this should be harmless.
1625 */
1626 if (macb_rx_pending(queue)) {
1627 queue_writel(queue, IDR, bp->rx_intr_mask);
1628 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1629 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1630 netdev_vdbg(bp->dev, "poll: packets pending, reschedule\n");
1631 napi_schedule(napi);
1632 }
1633 }
1634
1635 /* TODO: Handle errors */
1636
1637 return work_done;
1638}
1639
1640static void macb_tx_restart(struct macb_queue *queue)
1641{
1642 struct macb *bp = queue->bp;
1643 unsigned int head_idx, tbqp;
1644
1645 spin_lock(&queue->tx_ptr_lock);
1646
1647 if (queue->tx_head == queue->tx_tail)
1648 goto out_tx_ptr_unlock;
1649
1650 tbqp = queue_readl(queue, TBQP) / macb_dma_desc_get_size(bp);
1651 tbqp = macb_adj_dma_desc_idx(bp, macb_tx_ring_wrap(bp, tbqp));
1652 head_idx = macb_adj_dma_desc_idx(bp, macb_tx_ring_wrap(bp, queue->tx_head));
1653
1654 if (tbqp == head_idx)
1655 goto out_tx_ptr_unlock;
1656
1657 spin_lock_irq(&bp->lock);
1658 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1659 spin_unlock_irq(&bp->lock);
1660
1661out_tx_ptr_unlock:
1662 spin_unlock(&queue->tx_ptr_lock);
1663}
1664
1665static bool macb_tx_complete_pending(struct macb_queue *queue)
1666{
1667 bool retval = false;
1668
1669 spin_lock(&queue->tx_ptr_lock);
1670 if (queue->tx_head != queue->tx_tail) {
1671 /* Make hw descriptor updates visible to CPU */
1672 rmb();
1673
1674 if (macb_tx_desc(queue, queue->tx_tail)->ctrl & MACB_BIT(TX_USED))
1675 retval = true;
1676 }
1677 spin_unlock(&queue->tx_ptr_lock);
1678 return retval;
1679}
1680
1681static int macb_tx_poll(struct napi_struct *napi, int budget)
1682{
1683 struct macb_queue *queue = container_of(napi, struct macb_queue, napi_tx);
1684 struct macb *bp = queue->bp;
1685 int work_done;
1686
1687 work_done = macb_tx_complete(queue, budget);
1688
1689 rmb(); // ensure txubr_pending is up to date
1690 if (queue->txubr_pending) {
1691 queue->txubr_pending = false;
1692 netdev_vdbg(bp->dev, "poll: tx restart\n");
1693 macb_tx_restart(queue);
1694 }
1695
1696 netdev_vdbg(bp->dev, "TX poll: queue = %u, work_done = %d, budget = %d\n",
1697 (unsigned int)(queue - bp->queues), work_done, budget);
1698
1699 if (work_done < budget && napi_complete_done(napi, work_done)) {
1700 queue_writel(queue, IER, MACB_BIT(TCOMP));
1701
1702 /* Packet completions only seem to propagate to raise
1703 * interrupts when interrupts are enabled at the time, so if
1704 * packets were sent while interrupts were disabled,
1705 * they will not cause another interrupt to be generated when
1706 * interrupts are re-enabled.
1707 * Check for this case here to avoid losing a wakeup. This can
1708 * potentially race with the interrupt handler doing the same
1709 * actions if an interrupt is raised just after enabling them,
1710 * but this should be harmless.
1711 */
1712 if (macb_tx_complete_pending(queue)) {
1713 queue_writel(queue, IDR, MACB_BIT(TCOMP));
1714 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1715 queue_writel(queue, ISR, MACB_BIT(TCOMP));
1716 netdev_vdbg(bp->dev, "TX poll: packets pending, reschedule\n");
1717 napi_schedule(napi);
1718 }
1719 }
1720
1721 return work_done;
1722}
1723
1724static void macb_hresp_error_task(struct tasklet_struct *t)
1725{
1726 struct macb *bp = from_tasklet(bp, t, hresp_err_tasklet);
1727 struct net_device *dev = bp->dev;
1728 struct macb_queue *queue;
1729 unsigned int q;
1730 u32 ctrl;
1731
1732 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1733 queue_writel(queue, IDR, bp->rx_intr_mask |
1734 MACB_TX_INT_FLAGS |
1735 MACB_BIT(HRESP));
1736 }
1737 ctrl = macb_readl(bp, NCR);
1738 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1739 macb_writel(bp, NCR, ctrl);
1740
1741 netif_tx_stop_all_queues(dev);
1742 netif_carrier_off(dev);
1743
1744 bp->macbgem_ops.mog_init_rings(bp);
1745
1746 /* Initialize TX and RX buffers */
1747 macb_init_buffers(bp);
1748
1749 /* Enable interrupts */
1750 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1751 queue_writel(queue, IER,
1752 bp->rx_intr_mask |
1753 MACB_TX_INT_FLAGS |
1754 MACB_BIT(HRESP));
1755
1756 ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1757 macb_writel(bp, NCR, ctrl);
1758
1759 netif_carrier_on(dev);
1760 netif_tx_start_all_queues(dev);
1761}
1762
1763static irqreturn_t macb_wol_interrupt(int irq, void *dev_id)
1764{
1765 struct macb_queue *queue = dev_id;
1766 struct macb *bp = queue->bp;
1767 u32 status;
1768
1769 status = queue_readl(queue, ISR);
1770
1771 if (unlikely(!status))
1772 return IRQ_NONE;
1773
1774 spin_lock(&bp->lock);
1775
1776 if (status & MACB_BIT(WOL)) {
1777 queue_writel(queue, IDR, MACB_BIT(WOL));
1778 macb_writel(bp, WOL, 0);
1779 netdev_vdbg(bp->dev, "MACB WoL: queue = %u, isr = 0x%08lx\n",
1780 (unsigned int)(queue - bp->queues),
1781 (unsigned long)status);
1782 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1783 queue_writel(queue, ISR, MACB_BIT(WOL));
1784 pm_wakeup_event(&bp->pdev->dev, 0);
1785 }
1786
1787 spin_unlock(&bp->lock);
1788
1789 return IRQ_HANDLED;
1790}
1791
1792static irqreturn_t gem_wol_interrupt(int irq, void *dev_id)
1793{
1794 struct macb_queue *queue = dev_id;
1795 struct macb *bp = queue->bp;
1796 u32 status;
1797
1798 status = queue_readl(queue, ISR);
1799
1800 if (unlikely(!status))
1801 return IRQ_NONE;
1802
1803 spin_lock(&bp->lock);
1804
1805 if (status & GEM_BIT(WOL)) {
1806 queue_writel(queue, IDR, GEM_BIT(WOL));
1807 gem_writel(bp, WOL, 0);
1808 netdev_vdbg(bp->dev, "GEM WoL: queue = %u, isr = 0x%08lx\n",
1809 (unsigned int)(queue - bp->queues),
1810 (unsigned long)status);
1811 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1812 queue_writel(queue, ISR, GEM_BIT(WOL));
1813 pm_wakeup_event(&bp->pdev->dev, 0);
1814 }
1815
1816 spin_unlock(&bp->lock);
1817
1818 return IRQ_HANDLED;
1819}
1820
1821static irqreturn_t macb_interrupt(int irq, void *dev_id)
1822{
1823 struct macb_queue *queue = dev_id;
1824 struct macb *bp = queue->bp;
1825 struct net_device *dev = bp->dev;
1826 u32 status, ctrl;
1827
1828 status = queue_readl(queue, ISR);
1829
1830 if (unlikely(!status))
1831 return IRQ_NONE;
1832
1833 spin_lock(&bp->lock);
1834
1835 while (status) {
1836 /* close possible race with dev_close */
1837 if (unlikely(!netif_running(dev))) {
1838 queue_writel(queue, IDR, -1);
1839 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1840 queue_writel(queue, ISR, -1);
1841 break;
1842 }
1843
1844 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1845 (unsigned int)(queue - bp->queues),
1846 (unsigned long)status);
1847
1848 if (status & bp->rx_intr_mask) {
1849 /* There's no point taking any more interrupts
1850 * until we have processed the buffers. The
1851 * scheduling call may fail if the poll routine
1852 * is already scheduled, so disable interrupts
1853 * now.
1854 */
1855 queue_writel(queue, IDR, bp->rx_intr_mask);
1856 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1857 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1858
1859 if (napi_schedule_prep(&queue->napi_rx)) {
1860 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1861 __napi_schedule(&queue->napi_rx);
1862 }
1863 }
1864
1865 if (status & (MACB_BIT(TCOMP) |
1866 MACB_BIT(TXUBR))) {
1867 queue_writel(queue, IDR, MACB_BIT(TCOMP));
1868 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1869 queue_writel(queue, ISR, MACB_BIT(TCOMP) |
1870 MACB_BIT(TXUBR));
1871
1872 if (status & MACB_BIT(TXUBR)) {
1873 queue->txubr_pending = true;
1874 wmb(); // ensure softirq can see update
1875 }
1876
1877 if (napi_schedule_prep(&queue->napi_tx)) {
1878 netdev_vdbg(bp->dev, "scheduling TX softirq\n");
1879 __napi_schedule(&queue->napi_tx);
1880 }
1881 }
1882
1883 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1884 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1885 schedule_work(&queue->tx_error_task);
1886
1887 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1888 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1889
1890 break;
1891 }
1892
1893 /* Link change detection isn't possible with RMII, so we'll
1894 * add that if/when we get our hands on a full-blown MII PHY.
1895 */
1896
1897 /* There is a hardware issue under heavy load where DMA can
1898 * stop, this causes endless "used buffer descriptor read"
1899 * interrupts but it can be cleared by re-enabling RX. See
1900 * the at91rm9200 manual, section 41.3.1 or the Zynq manual
1901 * section 16.7.4 for details. RXUBR is only enabled for
1902 * these two versions.
1903 */
1904 if (status & MACB_BIT(RXUBR)) {
1905 ctrl = macb_readl(bp, NCR);
1906 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1907 wmb();
1908 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1909
1910 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1911 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1912 }
1913
1914 if (status & MACB_BIT(ISR_ROVR)) {
1915 /* We missed at least one packet */
1916 if (macb_is_gem(bp))
1917 bp->hw_stats.gem.rx_overruns++;
1918 else
1919 bp->hw_stats.macb.rx_overruns++;
1920
1921 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1922 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1923 }
1924
1925 if (status & MACB_BIT(HRESP)) {
1926 tasklet_schedule(&bp->hresp_err_tasklet);
1927 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1928
1929 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1930 queue_writel(queue, ISR, MACB_BIT(HRESP));
1931 }
1932 status = queue_readl(queue, ISR);
1933 }
1934
1935 spin_unlock(&bp->lock);
1936
1937 return IRQ_HANDLED;
1938}
1939
1940#ifdef CONFIG_NET_POLL_CONTROLLER
1941/* Polling receive - used by netconsole and other diagnostic tools
1942 * to allow network i/o with interrupts disabled.
1943 */
1944static void macb_poll_controller(struct net_device *dev)
1945{
1946 struct macb *bp = netdev_priv(dev);
1947 struct macb_queue *queue;
1948 unsigned long flags;
1949 unsigned int q;
1950
1951 local_irq_save(flags);
1952 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1953 macb_interrupt(dev->irq, queue);
1954 local_irq_restore(flags);
1955}
1956#endif
1957
1958static unsigned int macb_tx_map(struct macb *bp,
1959 struct macb_queue *queue,
1960 struct sk_buff *skb,
1961 unsigned int hdrlen)
1962{
1963 dma_addr_t mapping;
1964 unsigned int len, entry, i, tx_head = queue->tx_head;
1965 struct macb_tx_skb *tx_skb = NULL;
1966 struct macb_dma_desc *desc;
1967 unsigned int offset, size, count = 0;
1968 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1969 unsigned int eof = 1, mss_mfs = 0;
1970 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
1971
1972 /* LSO */
1973 if (skb_shinfo(skb)->gso_size != 0) {
1974 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1975 /* UDP - UFO */
1976 lso_ctrl = MACB_LSO_UFO_ENABLE;
1977 else
1978 /* TCP - TSO */
1979 lso_ctrl = MACB_LSO_TSO_ENABLE;
1980 }
1981
1982 /* First, map non-paged data */
1983 len = skb_headlen(skb);
1984
1985 /* first buffer length */
1986 size = hdrlen;
1987
1988 offset = 0;
1989 while (len) {
1990 entry = macb_tx_ring_wrap(bp, tx_head);
1991 tx_skb = &queue->tx_skb[entry];
1992
1993 mapping = dma_map_single(&bp->pdev->dev,
1994 skb->data + offset,
1995 size, DMA_TO_DEVICE);
1996 if (dma_mapping_error(&bp->pdev->dev, mapping))
1997 goto dma_error;
1998
1999 /* Save info to properly release resources */
2000 tx_skb->skb = NULL;
2001 tx_skb->mapping = mapping;
2002 tx_skb->size = size;
2003 tx_skb->mapped_as_page = false;
2004
2005 len -= size;
2006 offset += size;
2007 count++;
2008 tx_head++;
2009
2010 size = min(len, bp->max_tx_length);
2011 }
2012
2013 /* Then, map paged data from fragments */
2014 for (f = 0; f < nr_frags; f++) {
2015 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
2016
2017 len = skb_frag_size(frag);
2018 offset = 0;
2019 while (len) {
2020 size = min(len, bp->max_tx_length);
2021 entry = macb_tx_ring_wrap(bp, tx_head);
2022 tx_skb = &queue->tx_skb[entry];
2023
2024 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
2025 offset, size, DMA_TO_DEVICE);
2026 if (dma_mapping_error(&bp->pdev->dev, mapping))
2027 goto dma_error;
2028
2029 /* Save info to properly release resources */
2030 tx_skb->skb = NULL;
2031 tx_skb->mapping = mapping;
2032 tx_skb->size = size;
2033 tx_skb->mapped_as_page = true;
2034
2035 len -= size;
2036 offset += size;
2037 count++;
2038 tx_head++;
2039 }
2040 }
2041
2042 /* Should never happen */
2043 if (unlikely(!tx_skb)) {
2044 netdev_err(bp->dev, "BUG! empty skb!\n");
2045 return 0;
2046 }
2047
2048 /* This is the last buffer of the frame: save socket buffer */
2049 tx_skb->skb = skb;
2050
2051 /* Update TX ring: update buffer descriptors in reverse order
2052 * to avoid race condition
2053 */
2054
2055 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
2056 * to set the end of TX queue
2057 */
2058 i = tx_head;
2059 entry = macb_tx_ring_wrap(bp, i);
2060 ctrl = MACB_BIT(TX_USED);
2061 desc = macb_tx_desc(queue, entry);
2062 desc->ctrl = ctrl;
2063
2064 if (lso_ctrl) {
2065 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
2066 /* include header and FCS in value given to h/w */
2067 mss_mfs = skb_shinfo(skb)->gso_size +
2068 skb_transport_offset(skb) +
2069 ETH_FCS_LEN;
2070 else /* TSO */ {
2071 mss_mfs = skb_shinfo(skb)->gso_size;
2072 /* TCP Sequence Number Source Select
2073 * can be set only for TSO
2074 */
2075 seq_ctrl = 0;
2076 }
2077 }
2078
2079 do {
2080 i--;
2081 entry = macb_tx_ring_wrap(bp, i);
2082 tx_skb = &queue->tx_skb[entry];
2083 desc = macb_tx_desc(queue, entry);
2084
2085 ctrl = (u32)tx_skb->size;
2086 if (eof) {
2087 ctrl |= MACB_BIT(TX_LAST);
2088 eof = 0;
2089 }
2090 if (unlikely(entry == (bp->tx_ring_size - 1)))
2091 ctrl |= MACB_BIT(TX_WRAP);
2092
2093 /* First descriptor is header descriptor */
2094 if (i == queue->tx_head) {
2095 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
2096 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
2097 if ((bp->dev->features & NETIF_F_HW_CSUM) &&
2098 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl &&
2099 !ptp_one_step_sync(skb))
2100 ctrl |= MACB_BIT(TX_NOCRC);
2101 } else
2102 /* Only set MSS/MFS on payload descriptors
2103 * (second or later descriptor)
2104 */
2105 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
2106
2107 /* Set TX buffer descriptor */
2108 macb_set_addr(bp, desc, tx_skb->mapping);
2109 /* desc->addr must be visible to hardware before clearing
2110 * 'TX_USED' bit in desc->ctrl.
2111 */
2112 wmb();
2113 desc->ctrl = ctrl;
2114 } while (i != queue->tx_head);
2115
2116 queue->tx_head = tx_head;
2117
2118 return count;
2119
2120dma_error:
2121 netdev_err(bp->dev, "TX DMA map failed\n");
2122
2123 for (i = queue->tx_head; i != tx_head; i++) {
2124 tx_skb = macb_tx_skb(queue, i);
2125
2126 macb_tx_unmap(bp, tx_skb, 0);
2127 }
2128
2129 return 0;
2130}
2131
2132static netdev_features_t macb_features_check(struct sk_buff *skb,
2133 struct net_device *dev,
2134 netdev_features_t features)
2135{
2136 unsigned int nr_frags, f;
2137 unsigned int hdrlen;
2138
2139 /* Validate LSO compatibility */
2140
2141 /* there is only one buffer or protocol is not UDP */
2142 if (!skb_is_nonlinear(skb) || (ip_hdr(skb)->protocol != IPPROTO_UDP))
2143 return features;
2144
2145 /* length of header */
2146 hdrlen = skb_transport_offset(skb);
2147
2148 /* For UFO only:
2149 * When software supplies two or more payload buffers all payload buffers
2150 * apart from the last must be a multiple of 8 bytes in size.
2151 */
2152 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
2153 return features & ~MACB_NETIF_LSO;
2154
2155 nr_frags = skb_shinfo(skb)->nr_frags;
2156 /* No need to check last fragment */
2157 nr_frags--;
2158 for (f = 0; f < nr_frags; f++) {
2159 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
2160
2161 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
2162 return features & ~MACB_NETIF_LSO;
2163 }
2164 return features;
2165}
2166
2167static inline int macb_clear_csum(struct sk_buff *skb)
2168{
2169 /* no change for packets without checksum offloading */
2170 if (skb->ip_summed != CHECKSUM_PARTIAL)
2171 return 0;
2172
2173 /* make sure we can modify the header */
2174 if (unlikely(skb_cow_head(skb, 0)))
2175 return -1;
2176
2177 /* initialize checksum field
2178 * This is required - at least for Zynq, which otherwise calculates
2179 * wrong UDP header checksums for UDP packets with UDP data len <=2
2180 */
2181 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
2182 return 0;
2183}
2184
2185static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
2186{
2187 bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb) ||
2188 skb_is_nonlinear(*skb);
2189 int padlen = ETH_ZLEN - (*skb)->len;
2190 int tailroom = skb_tailroom(*skb);
2191 struct sk_buff *nskb;
2192 u32 fcs;
2193
2194 if (!(ndev->features & NETIF_F_HW_CSUM) ||
2195 !((*skb)->ip_summed != CHECKSUM_PARTIAL) ||
2196 skb_shinfo(*skb)->gso_size || ptp_one_step_sync(*skb))
2197 return 0;
2198
2199 if (padlen <= 0) {
2200 /* FCS could be appeded to tailroom. */
2201 if (tailroom >= ETH_FCS_LEN)
2202 goto add_fcs;
2203 /* No room for FCS, need to reallocate skb. */
2204 else
2205 padlen = ETH_FCS_LEN;
2206 } else {
2207 /* Add room for FCS. */
2208 padlen += ETH_FCS_LEN;
2209 }
2210
2211 if (cloned || tailroom < padlen) {
2212 nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC);
2213 if (!nskb)
2214 return -ENOMEM;
2215
2216 dev_consume_skb_any(*skb);
2217 *skb = nskb;
2218 }
2219
2220 if (padlen > ETH_FCS_LEN)
2221 skb_put_zero(*skb, padlen - ETH_FCS_LEN);
2222
2223add_fcs:
2224 /* set FCS to packet */
2225 fcs = crc32_le(~0, (*skb)->data, (*skb)->len);
2226 fcs = ~fcs;
2227
2228 skb_put_u8(*skb, fcs & 0xff);
2229 skb_put_u8(*skb, (fcs >> 8) & 0xff);
2230 skb_put_u8(*skb, (fcs >> 16) & 0xff);
2231 skb_put_u8(*skb, (fcs >> 24) & 0xff);
2232
2233 return 0;
2234}
2235
2236static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
2237{
2238 u16 queue_index = skb_get_queue_mapping(skb);
2239 struct macb *bp = netdev_priv(dev);
2240 struct macb_queue *queue = &bp->queues[queue_index];
2241 unsigned int desc_cnt, nr_frags, frag_size, f;
2242 unsigned int hdrlen;
2243 bool is_lso;
2244 netdev_tx_t ret = NETDEV_TX_OK;
2245
2246 if (macb_clear_csum(skb)) {
2247 dev_kfree_skb_any(skb);
2248 return ret;
2249 }
2250
2251 if (macb_pad_and_fcs(&skb, dev)) {
2252 dev_kfree_skb_any(skb);
2253 return ret;
2254 }
2255
2256 is_lso = (skb_shinfo(skb)->gso_size != 0);
2257
2258 if (is_lso) {
2259 /* length of headers */
2260 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
2261 /* only queue eth + ip headers separately for UDP */
2262 hdrlen = skb_transport_offset(skb);
2263 else
2264 hdrlen = skb_tcp_all_headers(skb);
2265 if (skb_headlen(skb) < hdrlen) {
2266 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
2267 /* if this is required, would need to copy to single buffer */
2268 return NETDEV_TX_BUSY;
2269 }
2270 } else
2271 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
2272
2273#if defined(DEBUG) && defined(VERBOSE_DEBUG)
2274 netdev_vdbg(bp->dev,
2275 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
2276 queue_index, skb->len, skb->head, skb->data,
2277 skb_tail_pointer(skb), skb_end_pointer(skb));
2278 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
2279 skb->data, 16, true);
2280#endif
2281
2282 /* Count how many TX buffer descriptors are needed to send this
2283 * socket buffer: skb fragments of jumbo frames may need to be
2284 * split into many buffer descriptors.
2285 */
2286 if (is_lso && (skb_headlen(skb) > hdrlen))
2287 /* extra header descriptor if also payload in first buffer */
2288 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
2289 else
2290 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
2291 nr_frags = skb_shinfo(skb)->nr_frags;
2292 for (f = 0; f < nr_frags; f++) {
2293 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
2294 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
2295 }
2296
2297 spin_lock_bh(&queue->tx_ptr_lock);
2298
2299 /* This is a hard error, log it. */
2300 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
2301 bp->tx_ring_size) < desc_cnt) {
2302 netif_stop_subqueue(dev, queue_index);
2303 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
2304 queue->tx_head, queue->tx_tail);
2305 ret = NETDEV_TX_BUSY;
2306 goto unlock;
2307 }
2308
2309 /* Map socket buffer for DMA transfer */
2310 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
2311 dev_kfree_skb_any(skb);
2312 goto unlock;
2313 }
2314
2315 /* Make newly initialized descriptor visible to hardware */
2316 wmb();
2317 skb_tx_timestamp(skb);
2318
2319 spin_lock_irq(&bp->lock);
2320 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
2321 spin_unlock_irq(&bp->lock);
2322
2323 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
2324 netif_stop_subqueue(dev, queue_index);
2325
2326unlock:
2327 spin_unlock_bh(&queue->tx_ptr_lock);
2328
2329 return ret;
2330}
2331
2332static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
2333{
2334 if (!macb_is_gem(bp)) {
2335 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
2336 } else {
2337 bp->rx_buffer_size = size;
2338
2339 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
2340 netdev_dbg(bp->dev,
2341 "RX buffer must be multiple of %d bytes, expanding\n",
2342 RX_BUFFER_MULTIPLE);
2343 bp->rx_buffer_size =
2344 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
2345 }
2346 }
2347
2348 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
2349 bp->dev->mtu, bp->rx_buffer_size);
2350}
2351
2352static void gem_free_rx_buffers(struct macb *bp)
2353{
2354 struct sk_buff *skb;
2355 struct macb_dma_desc *desc;
2356 struct macb_queue *queue;
2357 dma_addr_t addr;
2358 unsigned int q;
2359 int i;
2360
2361 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2362 if (!queue->rx_skbuff)
2363 continue;
2364
2365 for (i = 0; i < bp->rx_ring_size; i++) {
2366 skb = queue->rx_skbuff[i];
2367
2368 if (!skb)
2369 continue;
2370
2371 desc = macb_rx_desc(queue, i);
2372 addr = macb_get_addr(bp, desc);
2373
2374 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
2375 DMA_FROM_DEVICE);
2376 dev_kfree_skb_any(skb);
2377 skb = NULL;
2378 }
2379
2380 kfree(queue->rx_skbuff);
2381 queue->rx_skbuff = NULL;
2382 }
2383}
2384
2385static void macb_free_rx_buffers(struct macb *bp)
2386{
2387 struct macb_queue *queue = &bp->queues[0];
2388
2389 if (queue->rx_buffers) {
2390 dma_free_coherent(&bp->pdev->dev,
2391 bp->rx_ring_size * bp->rx_buffer_size,
2392 queue->rx_buffers, queue->rx_buffers_dma);
2393 queue->rx_buffers = NULL;
2394 }
2395}
2396
2397static void macb_free_consistent(struct macb *bp)
2398{
2399 struct macb_queue *queue;
2400 unsigned int q;
2401 int size;
2402
2403 bp->macbgem_ops.mog_free_rx_buffers(bp);
2404
2405 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2406 kfree(queue->tx_skb);
2407 queue->tx_skb = NULL;
2408 if (queue->tx_ring) {
2409 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2410 dma_free_coherent(&bp->pdev->dev, size,
2411 queue->tx_ring, queue->tx_ring_dma);
2412 queue->tx_ring = NULL;
2413 }
2414 if (queue->rx_ring) {
2415 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2416 dma_free_coherent(&bp->pdev->dev, size,
2417 queue->rx_ring, queue->rx_ring_dma);
2418 queue->rx_ring = NULL;
2419 }
2420 }
2421}
2422
2423static int gem_alloc_rx_buffers(struct macb *bp)
2424{
2425 struct macb_queue *queue;
2426 unsigned int q;
2427 int size;
2428
2429 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2430 size = bp->rx_ring_size * sizeof(struct sk_buff *);
2431 queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
2432 if (!queue->rx_skbuff)
2433 return -ENOMEM;
2434 else
2435 netdev_dbg(bp->dev,
2436 "Allocated %d RX struct sk_buff entries at %p\n",
2437 bp->rx_ring_size, queue->rx_skbuff);
2438 }
2439 return 0;
2440}
2441
2442static int macb_alloc_rx_buffers(struct macb *bp)
2443{
2444 struct macb_queue *queue = &bp->queues[0];
2445 int size;
2446
2447 size = bp->rx_ring_size * bp->rx_buffer_size;
2448 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
2449 &queue->rx_buffers_dma, GFP_KERNEL);
2450 if (!queue->rx_buffers)
2451 return -ENOMEM;
2452
2453 netdev_dbg(bp->dev,
2454 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
2455 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
2456 return 0;
2457}
2458
2459static int macb_alloc_consistent(struct macb *bp)
2460{
2461 struct macb_queue *queue;
2462 unsigned int q;
2463 int size;
2464
2465 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2466 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2467 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2468 &queue->tx_ring_dma,
2469 GFP_KERNEL);
2470 if (!queue->tx_ring)
2471 goto out_err;
2472 netdev_dbg(bp->dev,
2473 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
2474 q, size, (unsigned long)queue->tx_ring_dma,
2475 queue->tx_ring);
2476
2477 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
2478 queue->tx_skb = kmalloc(size, GFP_KERNEL);
2479 if (!queue->tx_skb)
2480 goto out_err;
2481
2482 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2483 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2484 &queue->rx_ring_dma, GFP_KERNEL);
2485 if (!queue->rx_ring)
2486 goto out_err;
2487 netdev_dbg(bp->dev,
2488 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
2489 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
2490 }
2491 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
2492 goto out_err;
2493
2494 return 0;
2495
2496out_err:
2497 macb_free_consistent(bp);
2498 return -ENOMEM;
2499}
2500
2501static void gem_init_rings(struct macb *bp)
2502{
2503 struct macb_queue *queue;
2504 struct macb_dma_desc *desc = NULL;
2505 unsigned int q;
2506 int i;
2507
2508 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2509 for (i = 0; i < bp->tx_ring_size; i++) {
2510 desc = macb_tx_desc(queue, i);
2511 macb_set_addr(bp, desc, 0);
2512 desc->ctrl = MACB_BIT(TX_USED);
2513 }
2514 desc->ctrl |= MACB_BIT(TX_WRAP);
2515 queue->tx_head = 0;
2516 queue->tx_tail = 0;
2517
2518 queue->rx_tail = 0;
2519 queue->rx_prepared_head = 0;
2520
2521 gem_rx_refill(queue);
2522 }
2523
2524}
2525
2526static void macb_init_rings(struct macb *bp)
2527{
2528 int i;
2529 struct macb_dma_desc *desc = NULL;
2530
2531 macb_init_rx_ring(&bp->queues[0]);
2532
2533 for (i = 0; i < bp->tx_ring_size; i++) {
2534 desc = macb_tx_desc(&bp->queues[0], i);
2535 macb_set_addr(bp, desc, 0);
2536 desc->ctrl = MACB_BIT(TX_USED);
2537 }
2538 bp->queues[0].tx_head = 0;
2539 bp->queues[0].tx_tail = 0;
2540 desc->ctrl |= MACB_BIT(TX_WRAP);
2541}
2542
2543static void macb_reset_hw(struct macb *bp)
2544{
2545 struct macb_queue *queue;
2546 unsigned int q;
2547 u32 ctrl = macb_readl(bp, NCR);
2548
2549 /* Disable RX and TX (XXX: Should we halt the transmission
2550 * more gracefully?)
2551 */
2552 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
2553
2554 /* Clear the stats registers (XXX: Update stats first?) */
2555 ctrl |= MACB_BIT(CLRSTAT);
2556
2557 macb_writel(bp, NCR, ctrl);
2558
2559 /* Clear all status flags */
2560 macb_writel(bp, TSR, -1);
2561 macb_writel(bp, RSR, -1);
2562
2563 /* Disable all interrupts */
2564 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2565 queue_writel(queue, IDR, -1);
2566 queue_readl(queue, ISR);
2567 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2568 queue_writel(queue, ISR, -1);
2569 }
2570}
2571
2572static u32 gem_mdc_clk_div(struct macb *bp)
2573{
2574 u32 config;
2575 unsigned long pclk_hz = clk_get_rate(bp->pclk);
2576
2577 if (pclk_hz <= 20000000)
2578 config = GEM_BF(CLK, GEM_CLK_DIV8);
2579 else if (pclk_hz <= 40000000)
2580 config = GEM_BF(CLK, GEM_CLK_DIV16);
2581 else if (pclk_hz <= 80000000)
2582 config = GEM_BF(CLK, GEM_CLK_DIV32);
2583 else if (pclk_hz <= 120000000)
2584 config = GEM_BF(CLK, GEM_CLK_DIV48);
2585 else if (pclk_hz <= 160000000)
2586 config = GEM_BF(CLK, GEM_CLK_DIV64);
2587 else
2588 config = GEM_BF(CLK, GEM_CLK_DIV96);
2589
2590 return config;
2591}
2592
2593static u32 macb_mdc_clk_div(struct macb *bp)
2594{
2595 u32 config;
2596 unsigned long pclk_hz;
2597
2598 if (macb_is_gem(bp))
2599 return gem_mdc_clk_div(bp);
2600
2601 pclk_hz = clk_get_rate(bp->pclk);
2602 if (pclk_hz <= 20000000)
2603 config = MACB_BF(CLK, MACB_CLK_DIV8);
2604 else if (pclk_hz <= 40000000)
2605 config = MACB_BF(CLK, MACB_CLK_DIV16);
2606 else if (pclk_hz <= 80000000)
2607 config = MACB_BF(CLK, MACB_CLK_DIV32);
2608 else
2609 config = MACB_BF(CLK, MACB_CLK_DIV64);
2610
2611 return config;
2612}
2613
2614/* Get the DMA bus width field of the network configuration register that we
2615 * should program. We find the width from decoding the design configuration
2616 * register to find the maximum supported data bus width.
2617 */
2618static u32 macb_dbw(struct macb *bp)
2619{
2620 if (!macb_is_gem(bp))
2621 return 0;
2622
2623 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2624 case 4:
2625 return GEM_BF(DBW, GEM_DBW128);
2626 case 2:
2627 return GEM_BF(DBW, GEM_DBW64);
2628 case 1:
2629 default:
2630 return GEM_BF(DBW, GEM_DBW32);
2631 }
2632}
2633
2634/* Configure the receive DMA engine
2635 * - use the correct receive buffer size
2636 * - set best burst length for DMA operations
2637 * (if not supported by FIFO, it will fallback to default)
2638 * - set both rx/tx packet buffers to full memory size
2639 * These are configurable parameters for GEM.
2640 */
2641static void macb_configure_dma(struct macb *bp)
2642{
2643 struct macb_queue *queue;
2644 u32 buffer_size;
2645 unsigned int q;
2646 u32 dmacfg;
2647
2648 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2649 if (macb_is_gem(bp)) {
2650 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2651 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2652 if (q)
2653 queue_writel(queue, RBQS, buffer_size);
2654 else
2655 dmacfg |= GEM_BF(RXBS, buffer_size);
2656 }
2657 if (bp->dma_burst_length)
2658 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2659 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2660 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2661
2662 if (bp->native_io)
2663 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2664 else
2665 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2666
2667 if (bp->dev->features & NETIF_F_HW_CSUM)
2668 dmacfg |= GEM_BIT(TXCOEN);
2669 else
2670 dmacfg &= ~GEM_BIT(TXCOEN);
2671
2672 dmacfg &= ~GEM_BIT(ADDR64);
2673#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2674 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2675 dmacfg |= GEM_BIT(ADDR64);
2676#endif
2677#ifdef CONFIG_MACB_USE_HWSTAMP
2678 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2679 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2680#endif
2681 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2682 dmacfg);
2683 gem_writel(bp, DMACFG, dmacfg);
2684 }
2685}
2686
2687static void macb_init_hw(struct macb *bp)
2688{
2689 u32 config;
2690
2691 macb_reset_hw(bp);
2692 macb_set_hwaddr(bp);
2693
2694 config = macb_mdc_clk_div(bp);
2695 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2696 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2697 if (bp->caps & MACB_CAPS_JUMBO)
2698 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2699 else
2700 config |= MACB_BIT(BIG); /* Receive oversized frames */
2701 if (bp->dev->flags & IFF_PROMISC)
2702 config |= MACB_BIT(CAF); /* Copy All Frames */
2703 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2704 config |= GEM_BIT(RXCOEN);
2705 if (!(bp->dev->flags & IFF_BROADCAST))
2706 config |= MACB_BIT(NBC); /* No BroadCast */
2707 config |= macb_dbw(bp);
2708 macb_writel(bp, NCFGR, config);
2709 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2710 gem_writel(bp, JML, bp->jumbo_max_len);
2711 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2712 if (bp->caps & MACB_CAPS_JUMBO)
2713 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2714
2715 macb_configure_dma(bp);
2716}
2717
2718/* The hash address register is 64 bits long and takes up two
2719 * locations in the memory map. The least significant bits are stored
2720 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2721 *
2722 * The unicast hash enable and the multicast hash enable bits in the
2723 * network configuration register enable the reception of hash matched
2724 * frames. The destination address is reduced to a 6 bit index into
2725 * the 64 bit hash register using the following hash function. The
2726 * hash function is an exclusive or of every sixth bit of the
2727 * destination address.
2728 *
2729 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2730 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2731 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2732 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2733 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2734 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2735 *
2736 * da[0] represents the least significant bit of the first byte
2737 * received, that is, the multicast/unicast indicator, and da[47]
2738 * represents the most significant bit of the last byte received. If
2739 * the hash index, hi[n], points to a bit that is set in the hash
2740 * register then the frame will be matched according to whether the
2741 * frame is multicast or unicast. A multicast match will be signalled
2742 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2743 * index points to a bit set in the hash register. A unicast match
2744 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2745 * and the hash index points to a bit set in the hash register. To
2746 * receive all multicast frames, the hash register should be set with
2747 * all ones and the multicast hash enable bit should be set in the
2748 * network configuration register.
2749 */
2750
2751static inline int hash_bit_value(int bitnr, __u8 *addr)
2752{
2753 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2754 return 1;
2755 return 0;
2756}
2757
2758/* Return the hash index value for the specified address. */
2759static int hash_get_index(__u8 *addr)
2760{
2761 int i, j, bitval;
2762 int hash_index = 0;
2763
2764 for (j = 0; j < 6; j++) {
2765 for (i = 0, bitval = 0; i < 8; i++)
2766 bitval ^= hash_bit_value(i * 6 + j, addr);
2767
2768 hash_index |= (bitval << j);
2769 }
2770
2771 return hash_index;
2772}
2773
2774/* Add multicast addresses to the internal multicast-hash table. */
2775static void macb_sethashtable(struct net_device *dev)
2776{
2777 struct netdev_hw_addr *ha;
2778 unsigned long mc_filter[2];
2779 unsigned int bitnr;
2780 struct macb *bp = netdev_priv(dev);
2781
2782 mc_filter[0] = 0;
2783 mc_filter[1] = 0;
2784
2785 netdev_for_each_mc_addr(ha, dev) {
2786 bitnr = hash_get_index(ha->addr);
2787 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2788 }
2789
2790 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2791 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2792}
2793
2794/* Enable/Disable promiscuous and multicast modes. */
2795static void macb_set_rx_mode(struct net_device *dev)
2796{
2797 unsigned long cfg;
2798 struct macb *bp = netdev_priv(dev);
2799
2800 cfg = macb_readl(bp, NCFGR);
2801
2802 if (dev->flags & IFF_PROMISC) {
2803 /* Enable promiscuous mode */
2804 cfg |= MACB_BIT(CAF);
2805
2806 /* Disable RX checksum offload */
2807 if (macb_is_gem(bp))
2808 cfg &= ~GEM_BIT(RXCOEN);
2809 } else {
2810 /* Disable promiscuous mode */
2811 cfg &= ~MACB_BIT(CAF);
2812
2813 /* Enable RX checksum offload only if requested */
2814 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2815 cfg |= GEM_BIT(RXCOEN);
2816 }
2817
2818 if (dev->flags & IFF_ALLMULTI) {
2819 /* Enable all multicast mode */
2820 macb_or_gem_writel(bp, HRB, -1);
2821 macb_or_gem_writel(bp, HRT, -1);
2822 cfg |= MACB_BIT(NCFGR_MTI);
2823 } else if (!netdev_mc_empty(dev)) {
2824 /* Enable specific multicasts */
2825 macb_sethashtable(dev);
2826 cfg |= MACB_BIT(NCFGR_MTI);
2827 } else if (dev->flags & (~IFF_ALLMULTI)) {
2828 /* Disable all multicast mode */
2829 macb_or_gem_writel(bp, HRB, 0);
2830 macb_or_gem_writel(bp, HRT, 0);
2831 cfg &= ~MACB_BIT(NCFGR_MTI);
2832 }
2833
2834 macb_writel(bp, NCFGR, cfg);
2835}
2836
2837static int macb_open(struct net_device *dev)
2838{
2839 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2840 struct macb *bp = netdev_priv(dev);
2841 struct macb_queue *queue;
2842 unsigned int q;
2843 int err;
2844
2845 netdev_dbg(bp->dev, "open\n");
2846
2847 err = pm_runtime_resume_and_get(&bp->pdev->dev);
2848 if (err < 0)
2849 return err;
2850
2851 /* RX buffers initialization */
2852 macb_init_rx_buffer_size(bp, bufsz);
2853
2854 err = macb_alloc_consistent(bp);
2855 if (err) {
2856 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2857 err);
2858 goto pm_exit;
2859 }
2860
2861 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2862 napi_enable(&queue->napi_rx);
2863 napi_enable(&queue->napi_tx);
2864 }
2865
2866 macb_init_hw(bp);
2867
2868 err = phy_power_on(bp->sgmii_phy);
2869 if (err)
2870 goto reset_hw;
2871
2872 err = macb_phylink_connect(bp);
2873 if (err)
2874 goto phy_off;
2875
2876 netif_tx_start_all_queues(dev);
2877
2878 if (bp->ptp_info)
2879 bp->ptp_info->ptp_init(dev);
2880
2881 return 0;
2882
2883phy_off:
2884 phy_power_off(bp->sgmii_phy);
2885
2886reset_hw:
2887 macb_reset_hw(bp);
2888 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2889 napi_disable(&queue->napi_rx);
2890 napi_disable(&queue->napi_tx);
2891 }
2892 macb_free_consistent(bp);
2893pm_exit:
2894 pm_runtime_put_sync(&bp->pdev->dev);
2895 return err;
2896}
2897
2898static int macb_close(struct net_device *dev)
2899{
2900 struct macb *bp = netdev_priv(dev);
2901 struct macb_queue *queue;
2902 unsigned long flags;
2903 unsigned int q;
2904
2905 netif_tx_stop_all_queues(dev);
2906
2907 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2908 napi_disable(&queue->napi_rx);
2909 napi_disable(&queue->napi_tx);
2910 }
2911
2912 phylink_stop(bp->phylink);
2913 phylink_disconnect_phy(bp->phylink);
2914
2915 phy_power_off(bp->sgmii_phy);
2916
2917 spin_lock_irqsave(&bp->lock, flags);
2918 macb_reset_hw(bp);
2919 netif_carrier_off(dev);
2920 spin_unlock_irqrestore(&bp->lock, flags);
2921
2922 macb_free_consistent(bp);
2923
2924 if (bp->ptp_info)
2925 bp->ptp_info->ptp_remove(dev);
2926
2927 pm_runtime_put(&bp->pdev->dev);
2928
2929 return 0;
2930}
2931
2932static int macb_change_mtu(struct net_device *dev, int new_mtu)
2933{
2934 if (netif_running(dev))
2935 return -EBUSY;
2936
2937 dev->mtu = new_mtu;
2938
2939 return 0;
2940}
2941
2942static int macb_set_mac_addr(struct net_device *dev, void *addr)
2943{
2944 int err;
2945
2946 err = eth_mac_addr(dev, addr);
2947 if (err < 0)
2948 return err;
2949
2950 macb_set_hwaddr(netdev_priv(dev));
2951 return 0;
2952}
2953
2954static void gem_update_stats(struct macb *bp)
2955{
2956 struct macb_queue *queue;
2957 unsigned int i, q, idx;
2958 unsigned long *stat;
2959
2960 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2961
2962 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2963 u32 offset = gem_statistics[i].offset;
2964 u64 val = bp->macb_reg_readl(bp, offset);
2965
2966 bp->ethtool_stats[i] += val;
2967 *p += val;
2968
2969 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2970 /* Add GEM_OCTTXH, GEM_OCTRXH */
2971 val = bp->macb_reg_readl(bp, offset + 4);
2972 bp->ethtool_stats[i] += ((u64)val) << 32;
2973 *(++p) += val;
2974 }
2975 }
2976
2977 idx = GEM_STATS_LEN;
2978 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2979 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
2980 bp->ethtool_stats[idx++] = *stat;
2981}
2982
2983static struct net_device_stats *gem_get_stats(struct macb *bp)
2984{
2985 struct gem_stats *hwstat = &bp->hw_stats.gem;
2986 struct net_device_stats *nstat = &bp->dev->stats;
2987
2988 if (!netif_running(bp->dev))
2989 return nstat;
2990
2991 gem_update_stats(bp);
2992
2993 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2994 hwstat->rx_alignment_errors +
2995 hwstat->rx_resource_errors +
2996 hwstat->rx_overruns +
2997 hwstat->rx_oversize_frames +
2998 hwstat->rx_jabbers +
2999 hwstat->rx_undersized_frames +
3000 hwstat->rx_length_field_frame_errors);
3001 nstat->tx_errors = (hwstat->tx_late_collisions +
3002 hwstat->tx_excessive_collisions +
3003 hwstat->tx_underrun +
3004 hwstat->tx_carrier_sense_errors);
3005 nstat->multicast = hwstat->rx_multicast_frames;
3006 nstat->collisions = (hwstat->tx_single_collision_frames +
3007 hwstat->tx_multiple_collision_frames +
3008 hwstat->tx_excessive_collisions);
3009 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
3010 hwstat->rx_jabbers +
3011 hwstat->rx_undersized_frames +
3012 hwstat->rx_length_field_frame_errors);
3013 nstat->rx_over_errors = hwstat->rx_resource_errors;
3014 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
3015 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
3016 nstat->rx_fifo_errors = hwstat->rx_overruns;
3017 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
3018 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
3019 nstat->tx_fifo_errors = hwstat->tx_underrun;
3020
3021 return nstat;
3022}
3023
3024static void gem_get_ethtool_stats(struct net_device *dev,
3025 struct ethtool_stats *stats, u64 *data)
3026{
3027 struct macb *bp;
3028
3029 bp = netdev_priv(dev);
3030 gem_update_stats(bp);
3031 memcpy(data, &bp->ethtool_stats, sizeof(u64)
3032 * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
3033}
3034
3035static int gem_get_sset_count(struct net_device *dev, int sset)
3036{
3037 struct macb *bp = netdev_priv(dev);
3038
3039 switch (sset) {
3040 case ETH_SS_STATS:
3041 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
3042 default:
3043 return -EOPNOTSUPP;
3044 }
3045}
3046
3047static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
3048{
3049 char stat_string[ETH_GSTRING_LEN];
3050 struct macb *bp = netdev_priv(dev);
3051 struct macb_queue *queue;
3052 unsigned int i;
3053 unsigned int q;
3054
3055 switch (sset) {
3056 case ETH_SS_STATS:
3057 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
3058 memcpy(p, gem_statistics[i].stat_string,
3059 ETH_GSTRING_LEN);
3060
3061 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
3062 for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
3063 snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s",
3064 q, queue_statistics[i].stat_string);
3065 memcpy(p, stat_string, ETH_GSTRING_LEN);
3066 }
3067 }
3068 break;
3069 }
3070}
3071
3072static struct net_device_stats *macb_get_stats(struct net_device *dev)
3073{
3074 struct macb *bp = netdev_priv(dev);
3075 struct net_device_stats *nstat = &bp->dev->stats;
3076 struct macb_stats *hwstat = &bp->hw_stats.macb;
3077
3078 if (macb_is_gem(bp))
3079 return gem_get_stats(bp);
3080
3081 /* read stats from hardware */
3082 macb_update_stats(bp);
3083
3084 /* Convert HW stats into netdevice stats */
3085 nstat->rx_errors = (hwstat->rx_fcs_errors +
3086 hwstat->rx_align_errors +
3087 hwstat->rx_resource_errors +
3088 hwstat->rx_overruns +
3089 hwstat->rx_oversize_pkts +
3090 hwstat->rx_jabbers +
3091 hwstat->rx_undersize_pkts +
3092 hwstat->rx_length_mismatch);
3093 nstat->tx_errors = (hwstat->tx_late_cols +
3094 hwstat->tx_excessive_cols +
3095 hwstat->tx_underruns +
3096 hwstat->tx_carrier_errors +
3097 hwstat->sqe_test_errors);
3098 nstat->collisions = (hwstat->tx_single_cols +
3099 hwstat->tx_multiple_cols +
3100 hwstat->tx_excessive_cols);
3101 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
3102 hwstat->rx_jabbers +
3103 hwstat->rx_undersize_pkts +
3104 hwstat->rx_length_mismatch);
3105 nstat->rx_over_errors = hwstat->rx_resource_errors +
3106 hwstat->rx_overruns;
3107 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
3108 nstat->rx_frame_errors = hwstat->rx_align_errors;
3109 nstat->rx_fifo_errors = hwstat->rx_overruns;
3110 /* XXX: What does "missed" mean? */
3111 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
3112 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
3113 nstat->tx_fifo_errors = hwstat->tx_underruns;
3114 /* Don't know about heartbeat or window errors... */
3115
3116 return nstat;
3117}
3118
3119static int macb_get_regs_len(struct net_device *netdev)
3120{
3121 return MACB_GREGS_NBR * sizeof(u32);
3122}
3123
3124static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3125 void *p)
3126{
3127 struct macb *bp = netdev_priv(dev);
3128 unsigned int tail, head;
3129 u32 *regs_buff = p;
3130
3131 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
3132 | MACB_GREGS_VERSION;
3133
3134 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
3135 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
3136
3137 regs_buff[0] = macb_readl(bp, NCR);
3138 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
3139 regs_buff[2] = macb_readl(bp, NSR);
3140 regs_buff[3] = macb_readl(bp, TSR);
3141 regs_buff[4] = macb_readl(bp, RBQP);
3142 regs_buff[5] = macb_readl(bp, TBQP);
3143 regs_buff[6] = macb_readl(bp, RSR);
3144 regs_buff[7] = macb_readl(bp, IMR);
3145
3146 regs_buff[8] = tail;
3147 regs_buff[9] = head;
3148 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
3149 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
3150
3151 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
3152 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
3153 if (macb_is_gem(bp))
3154 regs_buff[13] = gem_readl(bp, DMACFG);
3155}
3156
3157static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
3158{
3159 struct macb *bp = netdev_priv(netdev);
3160
3161 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
3162 phylink_ethtool_get_wol(bp->phylink, wol);
3163 wol->supported |= WAKE_MAGIC;
3164
3165 if (bp->wol & MACB_WOL_ENABLED)
3166 wol->wolopts |= WAKE_MAGIC;
3167 }
3168}
3169
3170static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
3171{
3172 struct macb *bp = netdev_priv(netdev);
3173 int ret;
3174
3175 /* Pass the order to phylink layer */
3176 ret = phylink_ethtool_set_wol(bp->phylink, wol);
3177 /* Don't manage WoL on MAC if handled by the PHY
3178 * or if there's a failure in talking to the PHY
3179 */
3180 if (!ret || ret != -EOPNOTSUPP)
3181 return ret;
3182
3183 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
3184 (wol->wolopts & ~WAKE_MAGIC))
3185 return -EOPNOTSUPP;
3186
3187 if (wol->wolopts & WAKE_MAGIC)
3188 bp->wol |= MACB_WOL_ENABLED;
3189 else
3190 bp->wol &= ~MACB_WOL_ENABLED;
3191
3192 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
3193
3194 return 0;
3195}
3196
3197static int macb_get_link_ksettings(struct net_device *netdev,
3198 struct ethtool_link_ksettings *kset)
3199{
3200 struct macb *bp = netdev_priv(netdev);
3201
3202 return phylink_ethtool_ksettings_get(bp->phylink, kset);
3203}
3204
3205static int macb_set_link_ksettings(struct net_device *netdev,
3206 const struct ethtool_link_ksettings *kset)
3207{
3208 struct macb *bp = netdev_priv(netdev);
3209
3210 return phylink_ethtool_ksettings_set(bp->phylink, kset);
3211}
3212
3213static void macb_get_ringparam(struct net_device *netdev,
3214 struct ethtool_ringparam *ring,
3215 struct kernel_ethtool_ringparam *kernel_ring,
3216 struct netlink_ext_ack *extack)
3217{
3218 struct macb *bp = netdev_priv(netdev);
3219
3220 ring->rx_max_pending = MAX_RX_RING_SIZE;
3221 ring->tx_max_pending = MAX_TX_RING_SIZE;
3222
3223 ring->rx_pending = bp->rx_ring_size;
3224 ring->tx_pending = bp->tx_ring_size;
3225}
3226
3227static int macb_set_ringparam(struct net_device *netdev,
3228 struct ethtool_ringparam *ring,
3229 struct kernel_ethtool_ringparam *kernel_ring,
3230 struct netlink_ext_ack *extack)
3231{
3232 struct macb *bp = netdev_priv(netdev);
3233 u32 new_rx_size, new_tx_size;
3234 unsigned int reset = 0;
3235
3236 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
3237 return -EINVAL;
3238
3239 new_rx_size = clamp_t(u32, ring->rx_pending,
3240 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
3241 new_rx_size = roundup_pow_of_two(new_rx_size);
3242
3243 new_tx_size = clamp_t(u32, ring->tx_pending,
3244 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
3245 new_tx_size = roundup_pow_of_two(new_tx_size);
3246
3247 if ((new_tx_size == bp->tx_ring_size) &&
3248 (new_rx_size == bp->rx_ring_size)) {
3249 /* nothing to do */
3250 return 0;
3251 }
3252
3253 if (netif_running(bp->dev)) {
3254 reset = 1;
3255 macb_close(bp->dev);
3256 }
3257
3258 bp->rx_ring_size = new_rx_size;
3259 bp->tx_ring_size = new_tx_size;
3260
3261 if (reset)
3262 macb_open(bp->dev);
3263
3264 return 0;
3265}
3266
3267#ifdef CONFIG_MACB_USE_HWSTAMP
3268static unsigned int gem_get_tsu_rate(struct macb *bp)
3269{
3270 struct clk *tsu_clk;
3271 unsigned int tsu_rate;
3272
3273 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
3274 if (!IS_ERR(tsu_clk))
3275 tsu_rate = clk_get_rate(tsu_clk);
3276 /* try pclk instead */
3277 else if (!IS_ERR(bp->pclk)) {
3278 tsu_clk = bp->pclk;
3279 tsu_rate = clk_get_rate(tsu_clk);
3280 } else
3281 return -ENOTSUPP;
3282 return tsu_rate;
3283}
3284
3285static s32 gem_get_ptp_max_adj(void)
3286{
3287 return 64000000;
3288}
3289
3290static int gem_get_ts_info(struct net_device *dev,
3291 struct ethtool_ts_info *info)
3292{
3293 struct macb *bp = netdev_priv(dev);
3294
3295 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
3296 ethtool_op_get_ts_info(dev, info);
3297 return 0;
3298 }
3299
3300 info->so_timestamping =
3301 SOF_TIMESTAMPING_TX_SOFTWARE |
3302 SOF_TIMESTAMPING_RX_SOFTWARE |
3303 SOF_TIMESTAMPING_SOFTWARE |
3304 SOF_TIMESTAMPING_TX_HARDWARE |
3305 SOF_TIMESTAMPING_RX_HARDWARE |
3306 SOF_TIMESTAMPING_RAW_HARDWARE;
3307 info->tx_types =
3308 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
3309 (1 << HWTSTAMP_TX_OFF) |
3310 (1 << HWTSTAMP_TX_ON);
3311 info->rx_filters =
3312 (1 << HWTSTAMP_FILTER_NONE) |
3313 (1 << HWTSTAMP_FILTER_ALL);
3314
3315 info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
3316
3317 return 0;
3318}
3319
3320static struct macb_ptp_info gem_ptp_info = {
3321 .ptp_init = gem_ptp_init,
3322 .ptp_remove = gem_ptp_remove,
3323 .get_ptp_max_adj = gem_get_ptp_max_adj,
3324 .get_tsu_rate = gem_get_tsu_rate,
3325 .get_ts_info = gem_get_ts_info,
3326 .get_hwtst = gem_get_hwtst,
3327 .set_hwtst = gem_set_hwtst,
3328};
3329#endif
3330
3331static int macb_get_ts_info(struct net_device *netdev,
3332 struct ethtool_ts_info *info)
3333{
3334 struct macb *bp = netdev_priv(netdev);
3335
3336 if (bp->ptp_info)
3337 return bp->ptp_info->get_ts_info(netdev, info);
3338
3339 return ethtool_op_get_ts_info(netdev, info);
3340}
3341
3342static void gem_enable_flow_filters(struct macb *bp, bool enable)
3343{
3344 struct net_device *netdev = bp->dev;
3345 struct ethtool_rx_fs_item *item;
3346 u32 t2_scr;
3347 int num_t2_scr;
3348
3349 if (!(netdev->features & NETIF_F_NTUPLE))
3350 return;
3351
3352 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
3353
3354 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3355 struct ethtool_rx_flow_spec *fs = &item->fs;
3356 struct ethtool_tcpip4_spec *tp4sp_m;
3357
3358 if (fs->location >= num_t2_scr)
3359 continue;
3360
3361 t2_scr = gem_readl_n(bp, SCRT2, fs->location);
3362
3363 /* enable/disable screener regs for the flow entry */
3364 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
3365
3366 /* only enable fields with no masking */
3367 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3368
3369 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
3370 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
3371 else
3372 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
3373
3374 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
3375 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
3376 else
3377 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
3378
3379 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
3380 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
3381 else
3382 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
3383
3384 gem_writel_n(bp, SCRT2, fs->location, t2_scr);
3385 }
3386}
3387
3388static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
3389{
3390 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
3391 uint16_t index = fs->location;
3392 u32 w0, w1, t2_scr;
3393 bool cmp_a = false;
3394 bool cmp_b = false;
3395 bool cmp_c = false;
3396
3397 if (!macb_is_gem(bp))
3398 return;
3399
3400 tp4sp_v = &(fs->h_u.tcp_ip4_spec);
3401 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3402
3403 /* ignore field if any masking set */
3404 if (tp4sp_m->ip4src == 0xFFFFFFFF) {
3405 /* 1st compare reg - IP source address */
3406 w0 = 0;
3407 w1 = 0;
3408 w0 = tp4sp_v->ip4src;
3409 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3410 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3411 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
3412 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
3413 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
3414 cmp_a = true;
3415 }
3416
3417 /* ignore field if any masking set */
3418 if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
3419 /* 2nd compare reg - IP destination address */
3420 w0 = 0;
3421 w1 = 0;
3422 w0 = tp4sp_v->ip4dst;
3423 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3424 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3425 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
3426 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
3427 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
3428 cmp_b = true;
3429 }
3430
3431 /* ignore both port fields if masking set in both */
3432 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
3433 /* 3rd compare reg - source port, destination port */
3434 w0 = 0;
3435 w1 = 0;
3436 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
3437 if (tp4sp_m->psrc == tp4sp_m->pdst) {
3438 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
3439 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3440 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3441 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3442 } else {
3443 /* only one port definition */
3444 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
3445 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
3446 if (tp4sp_m->psrc == 0xFFFF) { /* src port */
3447 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
3448 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3449 } else { /* dst port */
3450 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3451 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
3452 }
3453 }
3454 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
3455 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
3456 cmp_c = true;
3457 }
3458
3459 t2_scr = 0;
3460 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
3461 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
3462 if (cmp_a)
3463 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
3464 if (cmp_b)
3465 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
3466 if (cmp_c)
3467 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
3468 gem_writel_n(bp, SCRT2, index, t2_scr);
3469}
3470
3471static int gem_add_flow_filter(struct net_device *netdev,
3472 struct ethtool_rxnfc *cmd)
3473{
3474 struct macb *bp = netdev_priv(netdev);
3475 struct ethtool_rx_flow_spec *fs = &cmd->fs;
3476 struct ethtool_rx_fs_item *item, *newfs;
3477 unsigned long flags;
3478 int ret = -EINVAL;
3479 bool added = false;
3480
3481 newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
3482 if (newfs == NULL)
3483 return -ENOMEM;
3484 memcpy(&newfs->fs, fs, sizeof(newfs->fs));
3485
3486 netdev_dbg(netdev,
3487 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3488 fs->flow_type, (int)fs->ring_cookie, fs->location,
3489 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3490 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3491 be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc),
3492 be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst));
3493
3494 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3495
3496 /* find correct place to add in list */
3497 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3498 if (item->fs.location > newfs->fs.location) {
3499 list_add_tail(&newfs->list, &item->list);
3500 added = true;
3501 break;
3502 } else if (item->fs.location == fs->location) {
3503 netdev_err(netdev, "Rule not added: location %d not free!\n",
3504 fs->location);
3505 ret = -EBUSY;
3506 goto err;
3507 }
3508 }
3509 if (!added)
3510 list_add_tail(&newfs->list, &bp->rx_fs_list.list);
3511
3512 gem_prog_cmp_regs(bp, fs);
3513 bp->rx_fs_list.count++;
3514 /* enable filtering if NTUPLE on */
3515 gem_enable_flow_filters(bp, 1);
3516
3517 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3518 return 0;
3519
3520err:
3521 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3522 kfree(newfs);
3523 return ret;
3524}
3525
3526static int gem_del_flow_filter(struct net_device *netdev,
3527 struct ethtool_rxnfc *cmd)
3528{
3529 struct macb *bp = netdev_priv(netdev);
3530 struct ethtool_rx_fs_item *item;
3531 struct ethtool_rx_flow_spec *fs;
3532 unsigned long flags;
3533
3534 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3535
3536 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3537 if (item->fs.location == cmd->fs.location) {
3538 /* disable screener regs for the flow entry */
3539 fs = &(item->fs);
3540 netdev_dbg(netdev,
3541 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3542 fs->flow_type, (int)fs->ring_cookie, fs->location,
3543 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3544 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3545 be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc),
3546 be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst));
3547
3548 gem_writel_n(bp, SCRT2, fs->location, 0);
3549
3550 list_del(&item->list);
3551 bp->rx_fs_list.count--;
3552 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3553 kfree(item);
3554 return 0;
3555 }
3556 }
3557
3558 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3559 return -EINVAL;
3560}
3561
3562static int gem_get_flow_entry(struct net_device *netdev,
3563 struct ethtool_rxnfc *cmd)
3564{
3565 struct macb *bp = netdev_priv(netdev);
3566 struct ethtool_rx_fs_item *item;
3567
3568 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3569 if (item->fs.location == cmd->fs.location) {
3570 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
3571 return 0;
3572 }
3573 }
3574 return -EINVAL;
3575}
3576
3577static int gem_get_all_flow_entries(struct net_device *netdev,
3578 struct ethtool_rxnfc *cmd, u32 *rule_locs)
3579{
3580 struct macb *bp = netdev_priv(netdev);
3581 struct ethtool_rx_fs_item *item;
3582 uint32_t cnt = 0;
3583
3584 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3585 if (cnt == cmd->rule_cnt)
3586 return -EMSGSIZE;
3587 rule_locs[cnt] = item->fs.location;
3588 cnt++;
3589 }
3590 cmd->data = bp->max_tuples;
3591 cmd->rule_cnt = cnt;
3592
3593 return 0;
3594}
3595
3596static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3597 u32 *rule_locs)
3598{
3599 struct macb *bp = netdev_priv(netdev);
3600 int ret = 0;
3601
3602 switch (cmd->cmd) {
3603 case ETHTOOL_GRXRINGS:
3604 cmd->data = bp->num_queues;
3605 break;
3606 case ETHTOOL_GRXCLSRLCNT:
3607 cmd->rule_cnt = bp->rx_fs_list.count;
3608 break;
3609 case ETHTOOL_GRXCLSRULE:
3610 ret = gem_get_flow_entry(netdev, cmd);
3611 break;
3612 case ETHTOOL_GRXCLSRLALL:
3613 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
3614 break;
3615 default:
3616 netdev_err(netdev,
3617 "Command parameter %d is not supported\n", cmd->cmd);
3618 ret = -EOPNOTSUPP;
3619 }
3620
3621 return ret;
3622}
3623
3624static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
3625{
3626 struct macb *bp = netdev_priv(netdev);
3627 int ret;
3628
3629 switch (cmd->cmd) {
3630 case ETHTOOL_SRXCLSRLINS:
3631 if ((cmd->fs.location >= bp->max_tuples)
3632 || (cmd->fs.ring_cookie >= bp->num_queues)) {
3633 ret = -EINVAL;
3634 break;
3635 }
3636 ret = gem_add_flow_filter(netdev, cmd);
3637 break;
3638 case ETHTOOL_SRXCLSRLDEL:
3639 ret = gem_del_flow_filter(netdev, cmd);
3640 break;
3641 default:
3642 netdev_err(netdev,
3643 "Command parameter %d is not supported\n", cmd->cmd);
3644 ret = -EOPNOTSUPP;
3645 }
3646
3647 return ret;
3648}
3649
3650static const struct ethtool_ops macb_ethtool_ops = {
3651 .get_regs_len = macb_get_regs_len,
3652 .get_regs = macb_get_regs,
3653 .get_link = ethtool_op_get_link,
3654 .get_ts_info = ethtool_op_get_ts_info,
3655 .get_wol = macb_get_wol,
3656 .set_wol = macb_set_wol,
3657 .get_link_ksettings = macb_get_link_ksettings,
3658 .set_link_ksettings = macb_set_link_ksettings,
3659 .get_ringparam = macb_get_ringparam,
3660 .set_ringparam = macb_set_ringparam,
3661};
3662
3663static const struct ethtool_ops gem_ethtool_ops = {
3664 .get_regs_len = macb_get_regs_len,
3665 .get_regs = macb_get_regs,
3666 .get_wol = macb_get_wol,
3667 .set_wol = macb_set_wol,
3668 .get_link = ethtool_op_get_link,
3669 .get_ts_info = macb_get_ts_info,
3670 .get_ethtool_stats = gem_get_ethtool_stats,
3671 .get_strings = gem_get_ethtool_strings,
3672 .get_sset_count = gem_get_sset_count,
3673 .get_link_ksettings = macb_get_link_ksettings,
3674 .set_link_ksettings = macb_set_link_ksettings,
3675 .get_ringparam = macb_get_ringparam,
3676 .set_ringparam = macb_set_ringparam,
3677 .get_rxnfc = gem_get_rxnfc,
3678 .set_rxnfc = gem_set_rxnfc,
3679};
3680
3681static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3682{
3683 struct macb *bp = netdev_priv(dev);
3684
3685 if (!netif_running(dev))
3686 return -EINVAL;
3687
3688 if (bp->ptp_info) {
3689 switch (cmd) {
3690 case SIOCSHWTSTAMP:
3691 return bp->ptp_info->set_hwtst(dev, rq, cmd);
3692 case SIOCGHWTSTAMP:
3693 return bp->ptp_info->get_hwtst(dev, rq);
3694 }
3695 }
3696
3697 return phylink_mii_ioctl(bp->phylink, rq, cmd);
3698}
3699
3700static inline void macb_set_txcsum_feature(struct macb *bp,
3701 netdev_features_t features)
3702{
3703 u32 val;
3704
3705 if (!macb_is_gem(bp))
3706 return;
3707
3708 val = gem_readl(bp, DMACFG);
3709 if (features & NETIF_F_HW_CSUM)
3710 val |= GEM_BIT(TXCOEN);
3711 else
3712 val &= ~GEM_BIT(TXCOEN);
3713
3714 gem_writel(bp, DMACFG, val);
3715}
3716
3717static inline void macb_set_rxcsum_feature(struct macb *bp,
3718 netdev_features_t features)
3719{
3720 struct net_device *netdev = bp->dev;
3721 u32 val;
3722
3723 if (!macb_is_gem(bp))
3724 return;
3725
3726 val = gem_readl(bp, NCFGR);
3727 if ((features & NETIF_F_RXCSUM) && !(netdev->flags & IFF_PROMISC))
3728 val |= GEM_BIT(RXCOEN);
3729 else
3730 val &= ~GEM_BIT(RXCOEN);
3731
3732 gem_writel(bp, NCFGR, val);
3733}
3734
3735static inline void macb_set_rxflow_feature(struct macb *bp,
3736 netdev_features_t features)
3737{
3738 if (!macb_is_gem(bp))
3739 return;
3740
3741 gem_enable_flow_filters(bp, !!(features & NETIF_F_NTUPLE));
3742}
3743
3744static int macb_set_features(struct net_device *netdev,
3745 netdev_features_t features)
3746{
3747 struct macb *bp = netdev_priv(netdev);
3748 netdev_features_t changed = features ^ netdev->features;
3749
3750 /* TX checksum offload */
3751 if (changed & NETIF_F_HW_CSUM)
3752 macb_set_txcsum_feature(bp, features);
3753
3754 /* RX checksum offload */
3755 if (changed & NETIF_F_RXCSUM)
3756 macb_set_rxcsum_feature(bp, features);
3757
3758 /* RX Flow Filters */
3759 if (changed & NETIF_F_NTUPLE)
3760 macb_set_rxflow_feature(bp, features);
3761
3762 return 0;
3763}
3764
3765static void macb_restore_features(struct macb *bp)
3766{
3767 struct net_device *netdev = bp->dev;
3768 netdev_features_t features = netdev->features;
3769 struct ethtool_rx_fs_item *item;
3770
3771 /* TX checksum offload */
3772 macb_set_txcsum_feature(bp, features);
3773
3774 /* RX checksum offload */
3775 macb_set_rxcsum_feature(bp, features);
3776
3777 /* RX Flow Filters */
3778 list_for_each_entry(item, &bp->rx_fs_list.list, list)
3779 gem_prog_cmp_regs(bp, &item->fs);
3780
3781 macb_set_rxflow_feature(bp, features);
3782}
3783
3784static const struct net_device_ops macb_netdev_ops = {
3785 .ndo_open = macb_open,
3786 .ndo_stop = macb_close,
3787 .ndo_start_xmit = macb_start_xmit,
3788 .ndo_set_rx_mode = macb_set_rx_mode,
3789 .ndo_get_stats = macb_get_stats,
3790 .ndo_eth_ioctl = macb_ioctl,
3791 .ndo_validate_addr = eth_validate_addr,
3792 .ndo_change_mtu = macb_change_mtu,
3793 .ndo_set_mac_address = macb_set_mac_addr,
3794#ifdef CONFIG_NET_POLL_CONTROLLER
3795 .ndo_poll_controller = macb_poll_controller,
3796#endif
3797 .ndo_set_features = macb_set_features,
3798 .ndo_features_check = macb_features_check,
3799};
3800
3801/* Configure peripheral capabilities according to device tree
3802 * and integration options used
3803 */
3804static void macb_configure_caps(struct macb *bp,
3805 const struct macb_config *dt_conf)
3806{
3807 u32 dcfg;
3808
3809 if (dt_conf)
3810 bp->caps = dt_conf->caps;
3811
3812 if (hw_is_gem(bp->regs, bp->native_io)) {
3813 bp->caps |= MACB_CAPS_MACB_IS_GEM;
3814
3815 dcfg = gem_readl(bp, DCFG1);
3816 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
3817 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
3818 if (GEM_BFEXT(NO_PCS, dcfg) == 0)
3819 bp->caps |= MACB_CAPS_PCS;
3820 dcfg = gem_readl(bp, DCFG12);
3821 if (GEM_BFEXT(HIGH_SPEED, dcfg) == 1)
3822 bp->caps |= MACB_CAPS_HIGH_SPEED;
3823 dcfg = gem_readl(bp, DCFG2);
3824 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
3825 bp->caps |= MACB_CAPS_FIFO_MODE;
3826#ifdef CONFIG_MACB_USE_HWSTAMP
3827 if (gem_has_ptp(bp)) {
3828 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
3829 dev_err(&bp->pdev->dev,
3830 "GEM doesn't support hardware ptp.\n");
3831 else {
3832 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
3833 bp->ptp_info = &gem_ptp_info;
3834 }
3835 }
3836#endif
3837 }
3838
3839 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
3840}
3841
3842static void macb_probe_queues(void __iomem *mem,
3843 bool native_io,
3844 unsigned int *queue_mask,
3845 unsigned int *num_queues)
3846{
3847 *queue_mask = 0x1;
3848 *num_queues = 1;
3849
3850 /* is it macb or gem ?
3851 *
3852 * We need to read directly from the hardware here because
3853 * we are early in the probe process and don't have the
3854 * MACB_CAPS_MACB_IS_GEM flag positioned
3855 */
3856 if (!hw_is_gem(mem, native_io))
3857 return;
3858
3859 /* bit 0 is never set but queue 0 always exists */
3860 *queue_mask |= readl_relaxed(mem + GEM_DCFG6) & 0xff;
3861 *num_queues = hweight32(*queue_mask);
3862}
3863
3864static void macb_clks_disable(struct clk *pclk, struct clk *hclk, struct clk *tx_clk,
3865 struct clk *rx_clk, struct clk *tsu_clk)
3866{
3867 struct clk_bulk_data clks[] = {
3868 { .clk = tsu_clk, },
3869 { .clk = rx_clk, },
3870 { .clk = pclk, },
3871 { .clk = hclk, },
3872 { .clk = tx_clk },
3873 };
3874
3875 clk_bulk_disable_unprepare(ARRAY_SIZE(clks), clks);
3876}
3877
3878static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
3879 struct clk **hclk, struct clk **tx_clk,
3880 struct clk **rx_clk, struct clk **tsu_clk)
3881{
3882 struct macb_platform_data *pdata;
3883 int err;
3884
3885 pdata = dev_get_platdata(&pdev->dev);
3886 if (pdata) {
3887 *pclk = pdata->pclk;
3888 *hclk = pdata->hclk;
3889 } else {
3890 *pclk = devm_clk_get(&pdev->dev, "pclk");
3891 *hclk = devm_clk_get(&pdev->dev, "hclk");
3892 }
3893
3894 if (IS_ERR_OR_NULL(*pclk))
3895 return dev_err_probe(&pdev->dev,
3896 IS_ERR(*pclk) ? PTR_ERR(*pclk) : -ENODEV,
3897 "failed to get pclk\n");
3898
3899 if (IS_ERR_OR_NULL(*hclk))
3900 return dev_err_probe(&pdev->dev,
3901 IS_ERR(*hclk) ? PTR_ERR(*hclk) : -ENODEV,
3902 "failed to get hclk\n");
3903
3904 *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk");
3905 if (IS_ERR(*tx_clk))
3906 return PTR_ERR(*tx_clk);
3907
3908 *rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk");
3909 if (IS_ERR(*rx_clk))
3910 return PTR_ERR(*rx_clk);
3911
3912 *tsu_clk = devm_clk_get_optional(&pdev->dev, "tsu_clk");
3913 if (IS_ERR(*tsu_clk))
3914 return PTR_ERR(*tsu_clk);
3915
3916 err = clk_prepare_enable(*pclk);
3917 if (err) {
3918 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
3919 return err;
3920 }
3921
3922 err = clk_prepare_enable(*hclk);
3923 if (err) {
3924 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
3925 goto err_disable_pclk;
3926 }
3927
3928 err = clk_prepare_enable(*tx_clk);
3929 if (err) {
3930 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
3931 goto err_disable_hclk;
3932 }
3933
3934 err = clk_prepare_enable(*rx_clk);
3935 if (err) {
3936 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
3937 goto err_disable_txclk;
3938 }
3939
3940 err = clk_prepare_enable(*tsu_clk);
3941 if (err) {
3942 dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err);
3943 goto err_disable_rxclk;
3944 }
3945
3946 return 0;
3947
3948err_disable_rxclk:
3949 clk_disable_unprepare(*rx_clk);
3950
3951err_disable_txclk:
3952 clk_disable_unprepare(*tx_clk);
3953
3954err_disable_hclk:
3955 clk_disable_unprepare(*hclk);
3956
3957err_disable_pclk:
3958 clk_disable_unprepare(*pclk);
3959
3960 return err;
3961}
3962
3963static int macb_init(struct platform_device *pdev)
3964{
3965 struct net_device *dev = platform_get_drvdata(pdev);
3966 unsigned int hw_q, q;
3967 struct macb *bp = netdev_priv(dev);
3968 struct macb_queue *queue;
3969 int err;
3970 u32 val, reg;
3971
3972 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
3973 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
3974
3975 /* set the queue register mapping once for all: queue0 has a special
3976 * register mapping but we don't want to test the queue index then
3977 * compute the corresponding register offset at run time.
3978 */
3979 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
3980 if (!(bp->queue_mask & (1 << hw_q)))
3981 continue;
3982
3983 queue = &bp->queues[q];
3984 queue->bp = bp;
3985 spin_lock_init(&queue->tx_ptr_lock);
3986 netif_napi_add(dev, &queue->napi_rx, macb_rx_poll);
3987 netif_napi_add(dev, &queue->napi_tx, macb_tx_poll);
3988 if (hw_q) {
3989 queue->ISR = GEM_ISR(hw_q - 1);
3990 queue->IER = GEM_IER(hw_q - 1);
3991 queue->IDR = GEM_IDR(hw_q - 1);
3992 queue->IMR = GEM_IMR(hw_q - 1);
3993 queue->TBQP = GEM_TBQP(hw_q - 1);
3994 queue->RBQP = GEM_RBQP(hw_q - 1);
3995 queue->RBQS = GEM_RBQS(hw_q - 1);
3996#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3997 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3998 queue->TBQPH = GEM_TBQPH(hw_q - 1);
3999 queue->RBQPH = GEM_RBQPH(hw_q - 1);
4000 }
4001#endif
4002 } else {
4003 /* queue0 uses legacy registers */
4004 queue->ISR = MACB_ISR;
4005 queue->IER = MACB_IER;
4006 queue->IDR = MACB_IDR;
4007 queue->IMR = MACB_IMR;
4008 queue->TBQP = MACB_TBQP;
4009 queue->RBQP = MACB_RBQP;
4010#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4011 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
4012 queue->TBQPH = MACB_TBQPH;
4013 queue->RBQPH = MACB_RBQPH;
4014 }
4015#endif
4016 }
4017
4018 /* get irq: here we use the linux queue index, not the hardware
4019 * queue index. the queue irq definitions in the device tree
4020 * must remove the optional gaps that could exist in the
4021 * hardware queue mask.
4022 */
4023 queue->irq = platform_get_irq(pdev, q);
4024 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
4025 IRQF_SHARED, dev->name, queue);
4026 if (err) {
4027 dev_err(&pdev->dev,
4028 "Unable to request IRQ %d (error %d)\n",
4029 queue->irq, err);
4030 return err;
4031 }
4032
4033 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
4034 q++;
4035 }
4036
4037 dev->netdev_ops = &macb_netdev_ops;
4038
4039 /* setup appropriated routines according to adapter type */
4040 if (macb_is_gem(bp)) {
4041 bp->max_tx_length = GEM_MAX_TX_LEN;
4042 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
4043 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
4044 bp->macbgem_ops.mog_init_rings = gem_init_rings;
4045 bp->macbgem_ops.mog_rx = gem_rx;
4046 dev->ethtool_ops = &gem_ethtool_ops;
4047 } else {
4048 bp->max_tx_length = MACB_MAX_TX_LEN;
4049 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
4050 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
4051 bp->macbgem_ops.mog_init_rings = macb_init_rings;
4052 bp->macbgem_ops.mog_rx = macb_rx;
4053 dev->ethtool_ops = &macb_ethtool_ops;
4054 }
4055
4056 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
4057
4058 /* Set features */
4059 dev->hw_features = NETIF_F_SG;
4060
4061 /* Check LSO capability */
4062 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
4063 dev->hw_features |= MACB_NETIF_LSO;
4064
4065 /* Checksum offload is only available on gem with packet buffer */
4066 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
4067 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
4068 if (bp->caps & MACB_CAPS_SG_DISABLED)
4069 dev->hw_features &= ~NETIF_F_SG;
4070 dev->features = dev->hw_features;
4071
4072 /* Check RX Flow Filters support.
4073 * Max Rx flows set by availability of screeners & compare regs:
4074 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
4075 */
4076 reg = gem_readl(bp, DCFG8);
4077 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
4078 GEM_BFEXT(T2SCR, reg));
4079 INIT_LIST_HEAD(&bp->rx_fs_list.list);
4080 if (bp->max_tuples > 0) {
4081 /* also needs one ethtype match to check IPv4 */
4082 if (GEM_BFEXT(SCR2ETH, reg) > 0) {
4083 /* program this reg now */
4084 reg = 0;
4085 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
4086 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
4087 /* Filtering is supported in hw but don't enable it in kernel now */
4088 dev->hw_features |= NETIF_F_NTUPLE;
4089 /* init Rx flow definitions */
4090 bp->rx_fs_list.count = 0;
4091 spin_lock_init(&bp->rx_fs_lock);
4092 } else
4093 bp->max_tuples = 0;
4094 }
4095
4096 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
4097 val = 0;
4098 if (phy_interface_mode_is_rgmii(bp->phy_interface))
4099 val = bp->usrio->rgmii;
4100 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
4101 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
4102 val = bp->usrio->rmii;
4103 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
4104 val = bp->usrio->mii;
4105
4106 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
4107 val |= bp->usrio->refclk;
4108
4109 macb_or_gem_writel(bp, USRIO, val);
4110 }
4111
4112 /* Set MII management clock divider */
4113 val = macb_mdc_clk_div(bp);
4114 val |= macb_dbw(bp);
4115 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
4116 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
4117 macb_writel(bp, NCFGR, val);
4118
4119 return 0;
4120}
4121
4122static const struct macb_usrio_config macb_default_usrio = {
4123 .mii = MACB_BIT(MII),
4124 .rmii = MACB_BIT(RMII),
4125 .rgmii = GEM_BIT(RGMII),
4126 .refclk = MACB_BIT(CLKEN),
4127};
4128
4129#if defined(CONFIG_OF)
4130/* 1518 rounded up */
4131#define AT91ETHER_MAX_RBUFF_SZ 0x600
4132/* max number of receive buffers */
4133#define AT91ETHER_MAX_RX_DESCR 9
4134
4135static struct sifive_fu540_macb_mgmt *mgmt;
4136
4137static int at91ether_alloc_coherent(struct macb *lp)
4138{
4139 struct macb_queue *q = &lp->queues[0];
4140
4141 q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
4142 (AT91ETHER_MAX_RX_DESCR *
4143 macb_dma_desc_get_size(lp)),
4144 &q->rx_ring_dma, GFP_KERNEL);
4145 if (!q->rx_ring)
4146 return -ENOMEM;
4147
4148 q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
4149 AT91ETHER_MAX_RX_DESCR *
4150 AT91ETHER_MAX_RBUFF_SZ,
4151 &q->rx_buffers_dma, GFP_KERNEL);
4152 if (!q->rx_buffers) {
4153 dma_free_coherent(&lp->pdev->dev,
4154 AT91ETHER_MAX_RX_DESCR *
4155 macb_dma_desc_get_size(lp),
4156 q->rx_ring, q->rx_ring_dma);
4157 q->rx_ring = NULL;
4158 return -ENOMEM;
4159 }
4160
4161 return 0;
4162}
4163
4164static void at91ether_free_coherent(struct macb *lp)
4165{
4166 struct macb_queue *q = &lp->queues[0];
4167
4168 if (q->rx_ring) {
4169 dma_free_coherent(&lp->pdev->dev,
4170 AT91ETHER_MAX_RX_DESCR *
4171 macb_dma_desc_get_size(lp),
4172 q->rx_ring, q->rx_ring_dma);
4173 q->rx_ring = NULL;
4174 }
4175
4176 if (q->rx_buffers) {
4177 dma_free_coherent(&lp->pdev->dev,
4178 AT91ETHER_MAX_RX_DESCR *
4179 AT91ETHER_MAX_RBUFF_SZ,
4180 q->rx_buffers, q->rx_buffers_dma);
4181 q->rx_buffers = NULL;
4182 }
4183}
4184
4185/* Initialize and start the Receiver and Transmit subsystems */
4186static int at91ether_start(struct macb *lp)
4187{
4188 struct macb_queue *q = &lp->queues[0];
4189 struct macb_dma_desc *desc;
4190 dma_addr_t addr;
4191 u32 ctl;
4192 int i, ret;
4193
4194 ret = at91ether_alloc_coherent(lp);
4195 if (ret)
4196 return ret;
4197
4198 addr = q->rx_buffers_dma;
4199 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
4200 desc = macb_rx_desc(q, i);
4201 macb_set_addr(lp, desc, addr);
4202 desc->ctrl = 0;
4203 addr += AT91ETHER_MAX_RBUFF_SZ;
4204 }
4205
4206 /* Set the Wrap bit on the last descriptor */
4207 desc->addr |= MACB_BIT(RX_WRAP);
4208
4209 /* Reset buffer index */
4210 q->rx_tail = 0;
4211
4212 /* Program address of descriptor list in Rx Buffer Queue register */
4213 macb_writel(lp, RBQP, q->rx_ring_dma);
4214
4215 /* Enable Receive and Transmit */
4216 ctl = macb_readl(lp, NCR);
4217 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
4218
4219 /* Enable MAC interrupts */
4220 macb_writel(lp, IER, MACB_BIT(RCOMP) |
4221 MACB_BIT(RXUBR) |
4222 MACB_BIT(ISR_TUND) |
4223 MACB_BIT(ISR_RLE) |
4224 MACB_BIT(TCOMP) |
4225 MACB_BIT(ISR_ROVR) |
4226 MACB_BIT(HRESP));
4227
4228 return 0;
4229}
4230
4231static void at91ether_stop(struct macb *lp)
4232{
4233 u32 ctl;
4234
4235 /* Disable MAC interrupts */
4236 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
4237 MACB_BIT(RXUBR) |
4238 MACB_BIT(ISR_TUND) |
4239 MACB_BIT(ISR_RLE) |
4240 MACB_BIT(TCOMP) |
4241 MACB_BIT(ISR_ROVR) |
4242 MACB_BIT(HRESP));
4243
4244 /* Disable Receiver and Transmitter */
4245 ctl = macb_readl(lp, NCR);
4246 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
4247
4248 /* Free resources. */
4249 at91ether_free_coherent(lp);
4250}
4251
4252/* Open the ethernet interface */
4253static int at91ether_open(struct net_device *dev)
4254{
4255 struct macb *lp = netdev_priv(dev);
4256 u32 ctl;
4257 int ret;
4258
4259 ret = pm_runtime_resume_and_get(&lp->pdev->dev);
4260 if (ret < 0)
4261 return ret;
4262
4263 /* Clear internal statistics */
4264 ctl = macb_readl(lp, NCR);
4265 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
4266
4267 macb_set_hwaddr(lp);
4268
4269 ret = at91ether_start(lp);
4270 if (ret)
4271 goto pm_exit;
4272
4273 ret = macb_phylink_connect(lp);
4274 if (ret)
4275 goto stop;
4276
4277 netif_start_queue(dev);
4278
4279 return 0;
4280
4281stop:
4282 at91ether_stop(lp);
4283pm_exit:
4284 pm_runtime_put_sync(&lp->pdev->dev);
4285 return ret;
4286}
4287
4288/* Close the interface */
4289static int at91ether_close(struct net_device *dev)
4290{
4291 struct macb *lp = netdev_priv(dev);
4292
4293 netif_stop_queue(dev);
4294
4295 phylink_stop(lp->phylink);
4296 phylink_disconnect_phy(lp->phylink);
4297
4298 at91ether_stop(lp);
4299
4300 return pm_runtime_put(&lp->pdev->dev);
4301}
4302
4303/* Transmit packet */
4304static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
4305 struct net_device *dev)
4306{
4307 struct macb *lp = netdev_priv(dev);
4308
4309 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
4310 int desc = 0;
4311
4312 netif_stop_queue(dev);
4313
4314 /* Store packet information (to free when Tx completed) */
4315 lp->rm9200_txq[desc].skb = skb;
4316 lp->rm9200_txq[desc].size = skb->len;
4317 lp->rm9200_txq[desc].mapping = dma_map_single(&lp->pdev->dev, skb->data,
4318 skb->len, DMA_TO_DEVICE);
4319 if (dma_mapping_error(&lp->pdev->dev, lp->rm9200_txq[desc].mapping)) {
4320 dev_kfree_skb_any(skb);
4321 dev->stats.tx_dropped++;
4322 netdev_err(dev, "%s: DMA mapping error\n", __func__);
4323 return NETDEV_TX_OK;
4324 }
4325
4326 /* Set address of the data in the Transmit Address register */
4327 macb_writel(lp, TAR, lp->rm9200_txq[desc].mapping);
4328 /* Set length of the packet in the Transmit Control register */
4329 macb_writel(lp, TCR, skb->len);
4330
4331 } else {
4332 netdev_err(dev, "%s called, but device is busy!\n", __func__);
4333 return NETDEV_TX_BUSY;
4334 }
4335
4336 return NETDEV_TX_OK;
4337}
4338
4339/* Extract received frame from buffer descriptors and sent to upper layers.
4340 * (Called from interrupt context)
4341 */
4342static void at91ether_rx(struct net_device *dev)
4343{
4344 struct macb *lp = netdev_priv(dev);
4345 struct macb_queue *q = &lp->queues[0];
4346 struct macb_dma_desc *desc;
4347 unsigned char *p_recv;
4348 struct sk_buff *skb;
4349 unsigned int pktlen;
4350
4351 desc = macb_rx_desc(q, q->rx_tail);
4352 while (desc->addr & MACB_BIT(RX_USED)) {
4353 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
4354 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
4355 skb = netdev_alloc_skb(dev, pktlen + 2);
4356 if (skb) {
4357 skb_reserve(skb, 2);
4358 skb_put_data(skb, p_recv, pktlen);
4359
4360 skb->protocol = eth_type_trans(skb, dev);
4361 dev->stats.rx_packets++;
4362 dev->stats.rx_bytes += pktlen;
4363 netif_rx(skb);
4364 } else {
4365 dev->stats.rx_dropped++;
4366 }
4367
4368 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
4369 dev->stats.multicast++;
4370
4371 /* reset ownership bit */
4372 desc->addr &= ~MACB_BIT(RX_USED);
4373
4374 /* wrap after last buffer */
4375 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
4376 q->rx_tail = 0;
4377 else
4378 q->rx_tail++;
4379
4380 desc = macb_rx_desc(q, q->rx_tail);
4381 }
4382}
4383
4384/* MAC interrupt handler */
4385static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
4386{
4387 struct net_device *dev = dev_id;
4388 struct macb *lp = netdev_priv(dev);
4389 u32 intstatus, ctl;
4390 unsigned int desc;
4391
4392 /* MAC Interrupt Status register indicates what interrupts are pending.
4393 * It is automatically cleared once read.
4394 */
4395 intstatus = macb_readl(lp, ISR);
4396
4397 /* Receive complete */
4398 if (intstatus & MACB_BIT(RCOMP))
4399 at91ether_rx(dev);
4400
4401 /* Transmit complete */
4402 if (intstatus & MACB_BIT(TCOMP)) {
4403 /* The TCOM bit is set even if the transmission failed */
4404 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
4405 dev->stats.tx_errors++;
4406
4407 desc = 0;
4408 if (lp->rm9200_txq[desc].skb) {
4409 dev_consume_skb_irq(lp->rm9200_txq[desc].skb);
4410 lp->rm9200_txq[desc].skb = NULL;
4411 dma_unmap_single(&lp->pdev->dev, lp->rm9200_txq[desc].mapping,
4412 lp->rm9200_txq[desc].size, DMA_TO_DEVICE);
4413 dev->stats.tx_packets++;
4414 dev->stats.tx_bytes += lp->rm9200_txq[desc].size;
4415 }
4416 netif_wake_queue(dev);
4417 }
4418
4419 /* Work-around for EMAC Errata section 41.3.1 */
4420 if (intstatus & MACB_BIT(RXUBR)) {
4421 ctl = macb_readl(lp, NCR);
4422 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
4423 wmb();
4424 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
4425 }
4426
4427 if (intstatus & MACB_BIT(ISR_ROVR))
4428 netdev_err(dev, "ROVR error\n");
4429
4430 return IRQ_HANDLED;
4431}
4432
4433#ifdef CONFIG_NET_POLL_CONTROLLER
4434static void at91ether_poll_controller(struct net_device *dev)
4435{
4436 unsigned long flags;
4437
4438 local_irq_save(flags);
4439 at91ether_interrupt(dev->irq, dev);
4440 local_irq_restore(flags);
4441}
4442#endif
4443
4444static const struct net_device_ops at91ether_netdev_ops = {
4445 .ndo_open = at91ether_open,
4446 .ndo_stop = at91ether_close,
4447 .ndo_start_xmit = at91ether_start_xmit,
4448 .ndo_get_stats = macb_get_stats,
4449 .ndo_set_rx_mode = macb_set_rx_mode,
4450 .ndo_set_mac_address = eth_mac_addr,
4451 .ndo_eth_ioctl = macb_ioctl,
4452 .ndo_validate_addr = eth_validate_addr,
4453#ifdef CONFIG_NET_POLL_CONTROLLER
4454 .ndo_poll_controller = at91ether_poll_controller,
4455#endif
4456};
4457
4458static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
4459 struct clk **hclk, struct clk **tx_clk,
4460 struct clk **rx_clk, struct clk **tsu_clk)
4461{
4462 int err;
4463
4464 *hclk = NULL;
4465 *tx_clk = NULL;
4466 *rx_clk = NULL;
4467 *tsu_clk = NULL;
4468
4469 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
4470 if (IS_ERR(*pclk))
4471 return PTR_ERR(*pclk);
4472
4473 err = clk_prepare_enable(*pclk);
4474 if (err) {
4475 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
4476 return err;
4477 }
4478
4479 return 0;
4480}
4481
4482static int at91ether_init(struct platform_device *pdev)
4483{
4484 struct net_device *dev = platform_get_drvdata(pdev);
4485 struct macb *bp = netdev_priv(dev);
4486 int err;
4487
4488 bp->queues[0].bp = bp;
4489
4490 dev->netdev_ops = &at91ether_netdev_ops;
4491 dev->ethtool_ops = &macb_ethtool_ops;
4492
4493 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
4494 0, dev->name, dev);
4495 if (err)
4496 return err;
4497
4498 macb_writel(bp, NCR, 0);
4499
4500 macb_writel(bp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG));
4501
4502 return 0;
4503}
4504
4505static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw,
4506 unsigned long parent_rate)
4507{
4508 return mgmt->rate;
4509}
4510
4511static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate,
4512 unsigned long *parent_rate)
4513{
4514 if (WARN_ON(rate < 2500000))
4515 return 2500000;
4516 else if (rate == 2500000)
4517 return 2500000;
4518 else if (WARN_ON(rate < 13750000))
4519 return 2500000;
4520 else if (WARN_ON(rate < 25000000))
4521 return 25000000;
4522 else if (rate == 25000000)
4523 return 25000000;
4524 else if (WARN_ON(rate < 75000000))
4525 return 25000000;
4526 else if (WARN_ON(rate < 125000000))
4527 return 125000000;
4528 else if (rate == 125000000)
4529 return 125000000;
4530
4531 WARN_ON(rate > 125000000);
4532
4533 return 125000000;
4534}
4535
4536static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
4537 unsigned long parent_rate)
4538{
4539 rate = fu540_macb_tx_round_rate(hw, rate, &parent_rate);
4540 if (rate != 125000000)
4541 iowrite32(1, mgmt->reg);
4542 else
4543 iowrite32(0, mgmt->reg);
4544 mgmt->rate = rate;
4545
4546 return 0;
4547}
4548
4549static const struct clk_ops fu540_c000_ops = {
4550 .recalc_rate = fu540_macb_tx_recalc_rate,
4551 .round_rate = fu540_macb_tx_round_rate,
4552 .set_rate = fu540_macb_tx_set_rate,
4553};
4554
4555static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
4556 struct clk **hclk, struct clk **tx_clk,
4557 struct clk **rx_clk, struct clk **tsu_clk)
4558{
4559 struct clk_init_data init;
4560 int err = 0;
4561
4562 err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk);
4563 if (err)
4564 return err;
4565
4566 mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL);
4567 if (!mgmt) {
4568 err = -ENOMEM;
4569 goto err_disable_clks;
4570 }
4571
4572 init.name = "sifive-gemgxl-mgmt";
4573 init.ops = &fu540_c000_ops;
4574 init.flags = 0;
4575 init.num_parents = 0;
4576
4577 mgmt->rate = 0;
4578 mgmt->hw.init = &init;
4579
4580 *tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw);
4581 if (IS_ERR(*tx_clk)) {
4582 err = PTR_ERR(*tx_clk);
4583 goto err_disable_clks;
4584 }
4585
4586 err = clk_prepare_enable(*tx_clk);
4587 if (err) {
4588 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
4589 *tx_clk = NULL;
4590 goto err_disable_clks;
4591 } else {
4592 dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name);
4593 }
4594
4595 return 0;
4596
4597err_disable_clks:
4598 macb_clks_disable(*pclk, *hclk, *tx_clk, *rx_clk, *tsu_clk);
4599
4600 return err;
4601}
4602
4603static int fu540_c000_init(struct platform_device *pdev)
4604{
4605 mgmt->reg = devm_platform_ioremap_resource(pdev, 1);
4606 if (IS_ERR(mgmt->reg))
4607 return PTR_ERR(mgmt->reg);
4608
4609 return macb_init(pdev);
4610}
4611
4612static int init_reset_optional(struct platform_device *pdev)
4613{
4614 struct net_device *dev = platform_get_drvdata(pdev);
4615 struct macb *bp = netdev_priv(dev);
4616 int ret;
4617
4618 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
4619 /* Ensure PHY device used in SGMII mode is ready */
4620 bp->sgmii_phy = devm_phy_optional_get(&pdev->dev, NULL);
4621
4622 if (IS_ERR(bp->sgmii_phy))
4623 return dev_err_probe(&pdev->dev, PTR_ERR(bp->sgmii_phy),
4624 "failed to get SGMII PHY\n");
4625
4626 ret = phy_init(bp->sgmii_phy);
4627 if (ret)
4628 return dev_err_probe(&pdev->dev, ret,
4629 "failed to init SGMII PHY\n");
4630
4631 ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_SET_GEM_CONFIG);
4632 if (!ret) {
4633 u32 pm_info[2];
4634
4635 ret = of_property_read_u32_array(pdev->dev.of_node, "power-domains",
4636 pm_info, ARRAY_SIZE(pm_info));
4637 if (ret) {
4638 dev_err(&pdev->dev, "Failed to read power management information\n");
4639 goto err_out_phy_exit;
4640 }
4641 ret = zynqmp_pm_set_gem_config(pm_info[1], GEM_CONFIG_FIXED, 0);
4642 if (ret)
4643 goto err_out_phy_exit;
4644
4645 ret = zynqmp_pm_set_gem_config(pm_info[1], GEM_CONFIG_SGMII_MODE, 1);
4646 if (ret)
4647 goto err_out_phy_exit;
4648 }
4649
4650 }
4651
4652 /* Fully reset controller at hardware level if mapped in device tree */
4653 ret = device_reset_optional(&pdev->dev);
4654 if (ret) {
4655 phy_exit(bp->sgmii_phy);
4656 return dev_err_probe(&pdev->dev, ret, "failed to reset controller");
4657 }
4658
4659 ret = macb_init(pdev);
4660
4661err_out_phy_exit:
4662 if (ret)
4663 phy_exit(bp->sgmii_phy);
4664
4665 return ret;
4666}
4667
4668static const struct macb_usrio_config sama7g5_usrio = {
4669 .mii = 0,
4670 .rmii = 1,
4671 .rgmii = 2,
4672 .refclk = BIT(2),
4673 .hdfctlen = BIT(6),
4674};
4675
4676static const struct macb_config fu540_c000_config = {
4677 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
4678 MACB_CAPS_GEM_HAS_PTP,
4679 .dma_burst_length = 16,
4680 .clk_init = fu540_c000_clk_init,
4681 .init = fu540_c000_init,
4682 .jumbo_max_len = 10240,
4683 .usrio = &macb_default_usrio,
4684};
4685
4686static const struct macb_config at91sam9260_config = {
4687 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4688 .clk_init = macb_clk_init,
4689 .init = macb_init,
4690 .usrio = &macb_default_usrio,
4691};
4692
4693static const struct macb_config sama5d3macb_config = {
4694 .caps = MACB_CAPS_SG_DISABLED |
4695 MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4696 .clk_init = macb_clk_init,
4697 .init = macb_init,
4698 .usrio = &macb_default_usrio,
4699};
4700
4701static const struct macb_config pc302gem_config = {
4702 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
4703 .dma_burst_length = 16,
4704 .clk_init = macb_clk_init,
4705 .init = macb_init,
4706 .usrio = &macb_default_usrio,
4707};
4708
4709static const struct macb_config sama5d2_config = {
4710 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4711 .dma_burst_length = 16,
4712 .clk_init = macb_clk_init,
4713 .init = macb_init,
4714 .usrio = &macb_default_usrio,
4715};
4716
4717static const struct macb_config sama5d29_config = {
4718 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_GEM_HAS_PTP,
4719 .dma_burst_length = 16,
4720 .clk_init = macb_clk_init,
4721 .init = macb_init,
4722 .usrio = &macb_default_usrio,
4723};
4724
4725static const struct macb_config sama5d3_config = {
4726 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4727 MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
4728 .dma_burst_length = 16,
4729 .clk_init = macb_clk_init,
4730 .init = macb_init,
4731 .jumbo_max_len = 10240,
4732 .usrio = &macb_default_usrio,
4733};
4734
4735static const struct macb_config sama5d4_config = {
4736 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4737 .dma_burst_length = 4,
4738 .clk_init = macb_clk_init,
4739 .init = macb_init,
4740 .usrio = &macb_default_usrio,
4741};
4742
4743static const struct macb_config emac_config = {
4744 .caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC,
4745 .clk_init = at91ether_clk_init,
4746 .init = at91ether_init,
4747 .usrio = &macb_default_usrio,
4748};
4749
4750static const struct macb_config np4_config = {
4751 .caps = MACB_CAPS_USRIO_DISABLED,
4752 .clk_init = macb_clk_init,
4753 .init = macb_init,
4754 .usrio = &macb_default_usrio,
4755};
4756
4757static const struct macb_config zynqmp_config = {
4758 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4759 MACB_CAPS_JUMBO |
4760 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
4761 .dma_burst_length = 16,
4762 .clk_init = macb_clk_init,
4763 .init = init_reset_optional,
4764 .jumbo_max_len = 10240,
4765 .usrio = &macb_default_usrio,
4766};
4767
4768static const struct macb_config zynq_config = {
4769 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF |
4770 MACB_CAPS_NEEDS_RSTONUBR,
4771 .dma_burst_length = 16,
4772 .clk_init = macb_clk_init,
4773 .init = macb_init,
4774 .usrio = &macb_default_usrio,
4775};
4776
4777static const struct macb_config mpfs_config = {
4778 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4779 MACB_CAPS_JUMBO |
4780 MACB_CAPS_GEM_HAS_PTP,
4781 .dma_burst_length = 16,
4782 .clk_init = macb_clk_init,
4783 .init = init_reset_optional,
4784 .usrio = &macb_default_usrio,
4785 .jumbo_max_len = 10240,
4786};
4787
4788static const struct macb_config sama7g5_gem_config = {
4789 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG |
4790 MACB_CAPS_MIIONRGMII,
4791 .dma_burst_length = 16,
4792 .clk_init = macb_clk_init,
4793 .init = macb_init,
4794 .usrio = &sama7g5_usrio,
4795};
4796
4797static const struct macb_config sama7g5_emac_config = {
4798 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII |
4799 MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_MIIONRGMII,
4800 .dma_burst_length = 16,
4801 .clk_init = macb_clk_init,
4802 .init = macb_init,
4803 .usrio = &sama7g5_usrio,
4804};
4805
4806static const struct macb_config versal_config = {
4807 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
4808 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH | MACB_CAPS_NEED_TSUCLK,
4809 .dma_burst_length = 16,
4810 .clk_init = macb_clk_init,
4811 .init = init_reset_optional,
4812 .jumbo_max_len = 10240,
4813 .usrio = &macb_default_usrio,
4814};
4815
4816static const struct of_device_id macb_dt_ids[] = {
4817 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
4818 { .compatible = "cdns,macb" },
4819 { .compatible = "cdns,np4-macb", .data = &np4_config },
4820 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
4821 { .compatible = "cdns,gem", .data = &pc302gem_config },
4822 { .compatible = "cdns,sam9x60-macb", .data = &at91sam9260_config },
4823 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
4824 { .compatible = "atmel,sama5d29-gem", .data = &sama5d29_config },
4825 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
4826 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
4827 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
4828 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
4829 { .compatible = "cdns,emac", .data = &emac_config },
4830 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config}, /* deprecated */
4831 { .compatible = "cdns,zynq-gem", .data = &zynq_config }, /* deprecated */
4832 { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
4833 { .compatible = "microchip,mpfs-macb", .data = &mpfs_config },
4834 { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
4835 { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config },
4836 { .compatible = "xlnx,zynqmp-gem", .data = &zynqmp_config},
4837 { .compatible = "xlnx,zynq-gem", .data = &zynq_config },
4838 { .compatible = "xlnx,versal-gem", .data = &versal_config},
4839 { /* sentinel */ }
4840};
4841MODULE_DEVICE_TABLE(of, macb_dt_ids);
4842#endif /* CONFIG_OF */
4843
4844static const struct macb_config default_gem_config = {
4845 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4846 MACB_CAPS_JUMBO |
4847 MACB_CAPS_GEM_HAS_PTP,
4848 .dma_burst_length = 16,
4849 .clk_init = macb_clk_init,
4850 .init = macb_init,
4851 .usrio = &macb_default_usrio,
4852 .jumbo_max_len = 10240,
4853};
4854
4855static int macb_probe(struct platform_device *pdev)
4856{
4857 const struct macb_config *macb_config = &default_gem_config;
4858 int (*clk_init)(struct platform_device *, struct clk **,
4859 struct clk **, struct clk **, struct clk **,
4860 struct clk **) = macb_config->clk_init;
4861 int (*init)(struct platform_device *) = macb_config->init;
4862 struct device_node *np = pdev->dev.of_node;
4863 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
4864 struct clk *tsu_clk = NULL;
4865 unsigned int queue_mask, num_queues;
4866 bool native_io;
4867 phy_interface_t interface;
4868 struct net_device *dev;
4869 struct resource *regs;
4870 void __iomem *mem;
4871 struct macb *bp;
4872 int err, val;
4873
4874 mem = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
4875 if (IS_ERR(mem))
4876 return PTR_ERR(mem);
4877
4878 if (np) {
4879 const struct of_device_id *match;
4880
4881 match = of_match_node(macb_dt_ids, np);
4882 if (match && match->data) {
4883 macb_config = match->data;
4884 clk_init = macb_config->clk_init;
4885 init = macb_config->init;
4886 }
4887 }
4888
4889 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk, &tsu_clk);
4890 if (err)
4891 return err;
4892
4893 pm_runtime_set_autosuspend_delay(&pdev->dev, MACB_PM_TIMEOUT);
4894 pm_runtime_use_autosuspend(&pdev->dev);
4895 pm_runtime_get_noresume(&pdev->dev);
4896 pm_runtime_set_active(&pdev->dev);
4897 pm_runtime_enable(&pdev->dev);
4898 native_io = hw_is_native_io(mem);
4899
4900 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
4901 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
4902 if (!dev) {
4903 err = -ENOMEM;
4904 goto err_disable_clocks;
4905 }
4906
4907 dev->base_addr = regs->start;
4908
4909 SET_NETDEV_DEV(dev, &pdev->dev);
4910
4911 bp = netdev_priv(dev);
4912 bp->pdev = pdev;
4913 bp->dev = dev;
4914 bp->regs = mem;
4915 bp->native_io = native_io;
4916 if (native_io) {
4917 bp->macb_reg_readl = hw_readl_native;
4918 bp->macb_reg_writel = hw_writel_native;
4919 } else {
4920 bp->macb_reg_readl = hw_readl;
4921 bp->macb_reg_writel = hw_writel;
4922 }
4923 bp->num_queues = num_queues;
4924 bp->queue_mask = queue_mask;
4925 if (macb_config)
4926 bp->dma_burst_length = macb_config->dma_burst_length;
4927 bp->pclk = pclk;
4928 bp->hclk = hclk;
4929 bp->tx_clk = tx_clk;
4930 bp->rx_clk = rx_clk;
4931 bp->tsu_clk = tsu_clk;
4932 if (macb_config)
4933 bp->jumbo_max_len = macb_config->jumbo_max_len;
4934
4935 bp->wol = 0;
4936 if (of_get_property(np, "magic-packet", NULL))
4937 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
4938 device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
4939
4940 bp->usrio = macb_config->usrio;
4941
4942 spin_lock_init(&bp->lock);
4943
4944 /* setup capabilities */
4945 macb_configure_caps(bp, macb_config);
4946
4947#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4948 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
4949 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
4950 bp->hw_dma_cap |= HW_DMA_CAP_64B;
4951 }
4952#endif
4953 platform_set_drvdata(pdev, dev);
4954
4955 dev->irq = platform_get_irq(pdev, 0);
4956 if (dev->irq < 0) {
4957 err = dev->irq;
4958 goto err_out_free_netdev;
4959 }
4960
4961 /* MTU range: 68 - 1500 or 10240 */
4962 dev->min_mtu = GEM_MTU_MIN_SIZE;
4963 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
4964 dev->max_mtu = bp->jumbo_max_len - ETH_HLEN - ETH_FCS_LEN;
4965 else
4966 dev->max_mtu = ETH_DATA_LEN;
4967
4968 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) {
4969 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10));
4970 if (val)
4971 bp->rx_bd_rd_prefetch = (2 << (val - 1)) *
4972 macb_dma_desc_get_size(bp);
4973
4974 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10));
4975 if (val)
4976 bp->tx_bd_rd_prefetch = (2 << (val - 1)) *
4977 macb_dma_desc_get_size(bp);
4978 }
4979
4980 bp->rx_intr_mask = MACB_RX_INT_FLAGS;
4981 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR)
4982 bp->rx_intr_mask |= MACB_BIT(RXUBR);
4983
4984 err = of_get_ethdev_address(np, bp->dev);
4985 if (err == -EPROBE_DEFER)
4986 goto err_out_free_netdev;
4987 else if (err)
4988 macb_get_hwaddr(bp);
4989
4990 err = of_get_phy_mode(np, &interface);
4991 if (err)
4992 /* not found in DT, MII by default */
4993 bp->phy_interface = PHY_INTERFACE_MODE_MII;
4994 else
4995 bp->phy_interface = interface;
4996
4997 /* IP specific init */
4998 err = init(pdev);
4999 if (err)
5000 goto err_out_free_netdev;
5001
5002 err = macb_mii_init(bp);
5003 if (err)
5004 goto err_out_phy_exit;
5005
5006 netif_carrier_off(dev);
5007
5008 err = register_netdev(dev);
5009 if (err) {
5010 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
5011 goto err_out_unregister_mdio;
5012 }
5013
5014 tasklet_setup(&bp->hresp_err_tasklet, macb_hresp_error_task);
5015
5016 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
5017 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
5018 dev->base_addr, dev->irq, dev->dev_addr);
5019
5020 pm_runtime_mark_last_busy(&bp->pdev->dev);
5021 pm_runtime_put_autosuspend(&bp->pdev->dev);
5022
5023 return 0;
5024
5025err_out_unregister_mdio:
5026 mdiobus_unregister(bp->mii_bus);
5027 mdiobus_free(bp->mii_bus);
5028
5029err_out_phy_exit:
5030 phy_exit(bp->sgmii_phy);
5031
5032err_out_free_netdev:
5033 free_netdev(dev);
5034
5035err_disable_clocks:
5036 macb_clks_disable(pclk, hclk, tx_clk, rx_clk, tsu_clk);
5037 pm_runtime_disable(&pdev->dev);
5038 pm_runtime_set_suspended(&pdev->dev);
5039 pm_runtime_dont_use_autosuspend(&pdev->dev);
5040
5041 return err;
5042}
5043
5044static int macb_remove(struct platform_device *pdev)
5045{
5046 struct net_device *dev;
5047 struct macb *bp;
5048
5049 dev = platform_get_drvdata(pdev);
5050
5051 if (dev) {
5052 bp = netdev_priv(dev);
5053 phy_exit(bp->sgmii_phy);
5054 mdiobus_unregister(bp->mii_bus);
5055 mdiobus_free(bp->mii_bus);
5056
5057 unregister_netdev(dev);
5058 tasklet_kill(&bp->hresp_err_tasklet);
5059 pm_runtime_disable(&pdev->dev);
5060 pm_runtime_dont_use_autosuspend(&pdev->dev);
5061 if (!pm_runtime_suspended(&pdev->dev)) {
5062 macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk,
5063 bp->rx_clk, bp->tsu_clk);
5064 pm_runtime_set_suspended(&pdev->dev);
5065 }
5066 phylink_destroy(bp->phylink);
5067 free_netdev(dev);
5068 }
5069
5070 return 0;
5071}
5072
5073static int __maybe_unused macb_suspend(struct device *dev)
5074{
5075 struct net_device *netdev = dev_get_drvdata(dev);
5076 struct macb *bp = netdev_priv(netdev);
5077 struct macb_queue *queue;
5078 unsigned long flags;
5079 unsigned int q;
5080 int err;
5081
5082 if (!netif_running(netdev))
5083 return 0;
5084
5085 if (bp->wol & MACB_WOL_ENABLED) {
5086 spin_lock_irqsave(&bp->lock, flags);
5087 /* Flush all status bits */
5088 macb_writel(bp, TSR, -1);
5089 macb_writel(bp, RSR, -1);
5090 for (q = 0, queue = bp->queues; q < bp->num_queues;
5091 ++q, ++queue) {
5092 /* Disable all interrupts */
5093 queue_writel(queue, IDR, -1);
5094 queue_readl(queue, ISR);
5095 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
5096 queue_writel(queue, ISR, -1);
5097 }
5098 /* Change interrupt handler and
5099 * Enable WoL IRQ on queue 0
5100 */
5101 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
5102 if (macb_is_gem(bp)) {
5103 err = devm_request_irq(dev, bp->queues[0].irq, gem_wol_interrupt,
5104 IRQF_SHARED, netdev->name, bp->queues);
5105 if (err) {
5106 dev_err(dev,
5107 "Unable to request IRQ %d (error %d)\n",
5108 bp->queues[0].irq, err);
5109 spin_unlock_irqrestore(&bp->lock, flags);
5110 return err;
5111 }
5112 queue_writel(bp->queues, IER, GEM_BIT(WOL));
5113 gem_writel(bp, WOL, MACB_BIT(MAG));
5114 } else {
5115 err = devm_request_irq(dev, bp->queues[0].irq, macb_wol_interrupt,
5116 IRQF_SHARED, netdev->name, bp->queues);
5117 if (err) {
5118 dev_err(dev,
5119 "Unable to request IRQ %d (error %d)\n",
5120 bp->queues[0].irq, err);
5121 spin_unlock_irqrestore(&bp->lock, flags);
5122 return err;
5123 }
5124 queue_writel(bp->queues, IER, MACB_BIT(WOL));
5125 macb_writel(bp, WOL, MACB_BIT(MAG));
5126 }
5127 spin_unlock_irqrestore(&bp->lock, flags);
5128
5129 enable_irq_wake(bp->queues[0].irq);
5130 }
5131
5132 netif_device_detach(netdev);
5133 for (q = 0, queue = bp->queues; q < bp->num_queues;
5134 ++q, ++queue) {
5135 napi_disable(&queue->napi_rx);
5136 napi_disable(&queue->napi_tx);
5137 }
5138
5139 if (!(bp->wol & MACB_WOL_ENABLED)) {
5140 rtnl_lock();
5141 phylink_stop(bp->phylink);
5142 phy_exit(bp->sgmii_phy);
5143 rtnl_unlock();
5144 spin_lock_irqsave(&bp->lock, flags);
5145 macb_reset_hw(bp);
5146 spin_unlock_irqrestore(&bp->lock, flags);
5147 }
5148
5149 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
5150 bp->pm_data.usrio = macb_or_gem_readl(bp, USRIO);
5151
5152 if (netdev->hw_features & NETIF_F_NTUPLE)
5153 bp->pm_data.scrt2 = gem_readl_n(bp, ETHT, SCRT2_ETHT);
5154
5155 if (bp->ptp_info)
5156 bp->ptp_info->ptp_remove(netdev);
5157 if (!device_may_wakeup(dev))
5158 pm_runtime_force_suspend(dev);
5159
5160 return 0;
5161}
5162
5163static int __maybe_unused macb_resume(struct device *dev)
5164{
5165 struct net_device *netdev = dev_get_drvdata(dev);
5166 struct macb *bp = netdev_priv(netdev);
5167 struct macb_queue *queue;
5168 unsigned long flags;
5169 unsigned int q;
5170 int err;
5171
5172 if (!netif_running(netdev))
5173 return 0;
5174
5175 if (!device_may_wakeup(dev))
5176 pm_runtime_force_resume(dev);
5177
5178 if (bp->wol & MACB_WOL_ENABLED) {
5179 spin_lock_irqsave(&bp->lock, flags);
5180 /* Disable WoL */
5181 if (macb_is_gem(bp)) {
5182 queue_writel(bp->queues, IDR, GEM_BIT(WOL));
5183 gem_writel(bp, WOL, 0);
5184 } else {
5185 queue_writel(bp->queues, IDR, MACB_BIT(WOL));
5186 macb_writel(bp, WOL, 0);
5187 }
5188 /* Clear ISR on queue 0 */
5189 queue_readl(bp->queues, ISR);
5190 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
5191 queue_writel(bp->queues, ISR, -1);
5192 /* Replace interrupt handler on queue 0 */
5193 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
5194 err = devm_request_irq(dev, bp->queues[0].irq, macb_interrupt,
5195 IRQF_SHARED, netdev->name, bp->queues);
5196 if (err) {
5197 dev_err(dev,
5198 "Unable to request IRQ %d (error %d)\n",
5199 bp->queues[0].irq, err);
5200 spin_unlock_irqrestore(&bp->lock, flags);
5201 return err;
5202 }
5203 spin_unlock_irqrestore(&bp->lock, flags);
5204
5205 disable_irq_wake(bp->queues[0].irq);
5206
5207 /* Now make sure we disable phy before moving
5208 * to common restore path
5209 */
5210 rtnl_lock();
5211 phylink_stop(bp->phylink);
5212 rtnl_unlock();
5213 }
5214
5215 for (q = 0, queue = bp->queues; q < bp->num_queues;
5216 ++q, ++queue) {
5217 napi_enable(&queue->napi_rx);
5218 napi_enable(&queue->napi_tx);
5219 }
5220
5221 if (netdev->hw_features & NETIF_F_NTUPLE)
5222 gem_writel_n(bp, ETHT, SCRT2_ETHT, bp->pm_data.scrt2);
5223
5224 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
5225 macb_or_gem_writel(bp, USRIO, bp->pm_data.usrio);
5226
5227 macb_writel(bp, NCR, MACB_BIT(MPE));
5228 macb_init_hw(bp);
5229 macb_set_rx_mode(netdev);
5230 macb_restore_features(bp);
5231 rtnl_lock();
5232 if (!device_may_wakeup(&bp->dev->dev))
5233 phy_init(bp->sgmii_phy);
5234
5235 phylink_start(bp->phylink);
5236 rtnl_unlock();
5237
5238 netif_device_attach(netdev);
5239 if (bp->ptp_info)
5240 bp->ptp_info->ptp_init(netdev);
5241
5242 return 0;
5243}
5244
5245static int __maybe_unused macb_runtime_suspend(struct device *dev)
5246{
5247 struct net_device *netdev = dev_get_drvdata(dev);
5248 struct macb *bp = netdev_priv(netdev);
5249
5250 if (!(device_may_wakeup(dev)))
5251 macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, bp->rx_clk, bp->tsu_clk);
5252 else if (!(bp->caps & MACB_CAPS_NEED_TSUCLK))
5253 macb_clks_disable(NULL, NULL, NULL, NULL, bp->tsu_clk);
5254
5255 return 0;
5256}
5257
5258static int __maybe_unused macb_runtime_resume(struct device *dev)
5259{
5260 struct net_device *netdev = dev_get_drvdata(dev);
5261 struct macb *bp = netdev_priv(netdev);
5262
5263 if (!(device_may_wakeup(dev))) {
5264 clk_prepare_enable(bp->pclk);
5265 clk_prepare_enable(bp->hclk);
5266 clk_prepare_enable(bp->tx_clk);
5267 clk_prepare_enable(bp->rx_clk);
5268 clk_prepare_enable(bp->tsu_clk);
5269 } else if (!(bp->caps & MACB_CAPS_NEED_TSUCLK)) {
5270 clk_prepare_enable(bp->tsu_clk);
5271 }
5272
5273 return 0;
5274}
5275
5276static const struct dev_pm_ops macb_pm_ops = {
5277 SET_SYSTEM_SLEEP_PM_OPS(macb_suspend, macb_resume)
5278 SET_RUNTIME_PM_OPS(macb_runtime_suspend, macb_runtime_resume, NULL)
5279};
5280
5281static struct platform_driver macb_driver = {
5282 .probe = macb_probe,
5283 .remove = macb_remove,
5284 .driver = {
5285 .name = "macb",
5286 .of_match_table = of_match_ptr(macb_dt_ids),
5287 .pm = &macb_pm_ops,
5288 },
5289};
5290
5291module_platform_driver(macb_driver);
5292
5293MODULE_LICENSE("GPL");
5294MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
5295MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
5296MODULE_ALIAS("platform:macb");