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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Cadence MACB/GEM Ethernet Controller driver
4 *
5 * Copyright (C) 2004-2006 Atmel Corporation
6 */
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9#include <linux/clk.h>
10#include <linux/clk-provider.h>
11#include <linux/crc32.h>
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/circ_buf.h>
17#include <linux/slab.h>
18#include <linux/init.h>
19#include <linux/io.h>
20#include <linux/gpio.h>
21#include <linux/gpio/consumer.h>
22#include <linux/interrupt.h>
23#include <linux/netdevice.h>
24#include <linux/etherdevice.h>
25#include <linux/dma-mapping.h>
26#include <linux/platform_data/macb.h>
27#include <linux/platform_device.h>
28#include <linux/phylink.h>
29#include <linux/of.h>
30#include <linux/of_device.h>
31#include <linux/of_gpio.h>
32#include <linux/of_mdio.h>
33#include <linux/of_net.h>
34#include <linux/ip.h>
35#include <linux/udp.h>
36#include <linux/tcp.h>
37#include <linux/iopoll.h>
38#include <linux/pm_runtime.h>
39#include "macb.h"
40
41/* This structure is only used for MACB on SiFive FU540 devices */
42struct sifive_fu540_macb_mgmt {
43 void __iomem *reg;
44 unsigned long rate;
45 struct clk_hw hw;
46};
47
48#define MACB_RX_BUFFER_SIZE 128
49#define RX_BUFFER_MULTIPLE 64 /* bytes */
50
51#define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
52#define MIN_RX_RING_SIZE 64
53#define MAX_RX_RING_SIZE 8192
54#define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
55 * (bp)->rx_ring_size)
56
57#define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
58#define MIN_TX_RING_SIZE 64
59#define MAX_TX_RING_SIZE 4096
60#define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
61 * (bp)->tx_ring_size)
62
63/* level of occupied TX descriptors under which we wake up TX process */
64#define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
65
66#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR))
67#define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
68 | MACB_BIT(ISR_RLE) \
69 | MACB_BIT(TXERR))
70#define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \
71 | MACB_BIT(TXUBR))
72
73/* Max length of transmit frame must be a multiple of 8 bytes */
74#define MACB_TX_LEN_ALIGN 8
75#define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
76/* Limit maximum TX length as per Cadence TSO errata. This is to avoid a
77 * false amba_error in TX path from the DMA assuming there is not enough
78 * space in the SRAM (16KB) even when there is.
79 */
80#define GEM_MAX_TX_LEN (unsigned int)(0x3FC0)
81
82#define GEM_MTU_MIN_SIZE ETH_MIN_MTU
83#define MACB_NETIF_LSO NETIF_F_TSO
84
85#define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
86#define MACB_WOL_ENABLED (0x1 << 1)
87
88/* Graceful stop timeouts in us. We should allow up to
89 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
90 */
91#define MACB_HALT_TIMEOUT 1230
92
93#define MACB_PM_TIMEOUT 100 /* ms */
94
95#define MACB_MDIO_TIMEOUT 1000000 /* in usecs */
96
97/* DMA buffer descriptor might be different size
98 * depends on hardware configuration:
99 *
100 * 1. dma address width 32 bits:
101 * word 1: 32 bit address of Data Buffer
102 * word 2: control
103 *
104 * 2. dma address width 64 bits:
105 * word 1: 32 bit address of Data Buffer
106 * word 2: control
107 * word 3: upper 32 bit address of Data Buffer
108 * word 4: unused
109 *
110 * 3. dma address width 32 bits with hardware timestamping:
111 * word 1: 32 bit address of Data Buffer
112 * word 2: control
113 * word 3: timestamp word 1
114 * word 4: timestamp word 2
115 *
116 * 4. dma address width 64 bits with hardware timestamping:
117 * word 1: 32 bit address of Data Buffer
118 * word 2: control
119 * word 3: upper 32 bit address of Data Buffer
120 * word 4: unused
121 * word 5: timestamp word 1
122 * word 6: timestamp word 2
123 */
124static unsigned int macb_dma_desc_get_size(struct macb *bp)
125{
126#ifdef MACB_EXT_DESC
127 unsigned int desc_size;
128
129 switch (bp->hw_dma_cap) {
130 case HW_DMA_CAP_64B:
131 desc_size = sizeof(struct macb_dma_desc)
132 + sizeof(struct macb_dma_desc_64);
133 break;
134 case HW_DMA_CAP_PTP:
135 desc_size = sizeof(struct macb_dma_desc)
136 + sizeof(struct macb_dma_desc_ptp);
137 break;
138 case HW_DMA_CAP_64B_PTP:
139 desc_size = sizeof(struct macb_dma_desc)
140 + sizeof(struct macb_dma_desc_64)
141 + sizeof(struct macb_dma_desc_ptp);
142 break;
143 default:
144 desc_size = sizeof(struct macb_dma_desc);
145 }
146 return desc_size;
147#endif
148 return sizeof(struct macb_dma_desc);
149}
150
151static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
152{
153#ifdef MACB_EXT_DESC
154 switch (bp->hw_dma_cap) {
155 case HW_DMA_CAP_64B:
156 case HW_DMA_CAP_PTP:
157 desc_idx <<= 1;
158 break;
159 case HW_DMA_CAP_64B_PTP:
160 desc_idx *= 3;
161 break;
162 default:
163 break;
164 }
165#endif
166 return desc_idx;
167}
168
169#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
170static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
171{
172 return (struct macb_dma_desc_64 *)((void *)desc
173 + sizeof(struct macb_dma_desc));
174}
175#endif
176
177/* Ring buffer accessors */
178static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
179{
180 return index & (bp->tx_ring_size - 1);
181}
182
183static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
184 unsigned int index)
185{
186 index = macb_tx_ring_wrap(queue->bp, index);
187 index = macb_adj_dma_desc_idx(queue->bp, index);
188 return &queue->tx_ring[index];
189}
190
191static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
192 unsigned int index)
193{
194 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
195}
196
197static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
198{
199 dma_addr_t offset;
200
201 offset = macb_tx_ring_wrap(queue->bp, index) *
202 macb_dma_desc_get_size(queue->bp);
203
204 return queue->tx_ring_dma + offset;
205}
206
207static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
208{
209 return index & (bp->rx_ring_size - 1);
210}
211
212static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
213{
214 index = macb_rx_ring_wrap(queue->bp, index);
215 index = macb_adj_dma_desc_idx(queue->bp, index);
216 return &queue->rx_ring[index];
217}
218
219static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
220{
221 return queue->rx_buffers + queue->bp->rx_buffer_size *
222 macb_rx_ring_wrap(queue->bp, index);
223}
224
225/* I/O accessors */
226static u32 hw_readl_native(struct macb *bp, int offset)
227{
228 return __raw_readl(bp->regs + offset);
229}
230
231static void hw_writel_native(struct macb *bp, int offset, u32 value)
232{
233 __raw_writel(value, bp->regs + offset);
234}
235
236static u32 hw_readl(struct macb *bp, int offset)
237{
238 return readl_relaxed(bp->regs + offset);
239}
240
241static void hw_writel(struct macb *bp, int offset, u32 value)
242{
243 writel_relaxed(value, bp->regs + offset);
244}
245
246/* Find the CPU endianness by using the loopback bit of NCR register. When the
247 * CPU is in big endian we need to program swapped mode for management
248 * descriptor access.
249 */
250static bool hw_is_native_io(void __iomem *addr)
251{
252 u32 value = MACB_BIT(LLB);
253
254 __raw_writel(value, addr + MACB_NCR);
255 value = __raw_readl(addr + MACB_NCR);
256
257 /* Write 0 back to disable everything */
258 __raw_writel(0, addr + MACB_NCR);
259
260 return value == MACB_BIT(LLB);
261}
262
263static bool hw_is_gem(void __iomem *addr, bool native_io)
264{
265 u32 id;
266
267 if (native_io)
268 id = __raw_readl(addr + MACB_MID);
269 else
270 id = readl_relaxed(addr + MACB_MID);
271
272 return MACB_BFEXT(IDNUM, id) >= 0x2;
273}
274
275static void macb_set_hwaddr(struct macb *bp)
276{
277 u32 bottom;
278 u16 top;
279
280 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
281 macb_or_gem_writel(bp, SA1B, bottom);
282 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
283 macb_or_gem_writel(bp, SA1T, top);
284
285 /* Clear unused address register sets */
286 macb_or_gem_writel(bp, SA2B, 0);
287 macb_or_gem_writel(bp, SA2T, 0);
288 macb_or_gem_writel(bp, SA3B, 0);
289 macb_or_gem_writel(bp, SA3T, 0);
290 macb_or_gem_writel(bp, SA4B, 0);
291 macb_or_gem_writel(bp, SA4T, 0);
292}
293
294static void macb_get_hwaddr(struct macb *bp)
295{
296 u32 bottom;
297 u16 top;
298 u8 addr[6];
299 int i;
300
301 /* Check all 4 address register for valid address */
302 for (i = 0; i < 4; i++) {
303 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
304 top = macb_or_gem_readl(bp, SA1T + i * 8);
305
306 addr[0] = bottom & 0xff;
307 addr[1] = (bottom >> 8) & 0xff;
308 addr[2] = (bottom >> 16) & 0xff;
309 addr[3] = (bottom >> 24) & 0xff;
310 addr[4] = top & 0xff;
311 addr[5] = (top >> 8) & 0xff;
312
313 if (is_valid_ether_addr(addr)) {
314 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
315 return;
316 }
317 }
318
319 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
320 eth_hw_addr_random(bp->dev);
321}
322
323static int macb_mdio_wait_for_idle(struct macb *bp)
324{
325 u32 val;
326
327 return readx_poll_timeout(MACB_READ_NSR, bp, val, val & MACB_BIT(IDLE),
328 1, MACB_MDIO_TIMEOUT);
329}
330
331static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
332{
333 struct macb *bp = bus->priv;
334 int status;
335
336 status = pm_runtime_get_sync(&bp->pdev->dev);
337 if (status < 0) {
338 pm_runtime_put_noidle(&bp->pdev->dev);
339 goto mdio_pm_exit;
340 }
341
342 status = macb_mdio_wait_for_idle(bp);
343 if (status < 0)
344 goto mdio_read_exit;
345
346 if (regnum & MII_ADDR_C45) {
347 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
348 | MACB_BF(RW, MACB_MAN_C45_ADDR)
349 | MACB_BF(PHYA, mii_id)
350 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
351 | MACB_BF(DATA, regnum & 0xFFFF)
352 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
353
354 status = macb_mdio_wait_for_idle(bp);
355 if (status < 0)
356 goto mdio_read_exit;
357
358 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
359 | MACB_BF(RW, MACB_MAN_C45_READ)
360 | MACB_BF(PHYA, mii_id)
361 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
362 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
363 } else {
364 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
365 | MACB_BF(RW, MACB_MAN_C22_READ)
366 | MACB_BF(PHYA, mii_id)
367 | MACB_BF(REGA, regnum)
368 | MACB_BF(CODE, MACB_MAN_C22_CODE)));
369 }
370
371 status = macb_mdio_wait_for_idle(bp);
372 if (status < 0)
373 goto mdio_read_exit;
374
375 status = MACB_BFEXT(DATA, macb_readl(bp, MAN));
376
377mdio_read_exit:
378 pm_runtime_mark_last_busy(&bp->pdev->dev);
379 pm_runtime_put_autosuspend(&bp->pdev->dev);
380mdio_pm_exit:
381 return status;
382}
383
384static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
385 u16 value)
386{
387 struct macb *bp = bus->priv;
388 int status;
389
390 status = pm_runtime_get_sync(&bp->pdev->dev);
391 if (status < 0) {
392 pm_runtime_put_noidle(&bp->pdev->dev);
393 goto mdio_pm_exit;
394 }
395
396 status = macb_mdio_wait_for_idle(bp);
397 if (status < 0)
398 goto mdio_write_exit;
399
400 if (regnum & MII_ADDR_C45) {
401 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
402 | MACB_BF(RW, MACB_MAN_C45_ADDR)
403 | MACB_BF(PHYA, mii_id)
404 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
405 | MACB_BF(DATA, regnum & 0xFFFF)
406 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
407
408 status = macb_mdio_wait_for_idle(bp);
409 if (status < 0)
410 goto mdio_write_exit;
411
412 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
413 | MACB_BF(RW, MACB_MAN_C45_WRITE)
414 | MACB_BF(PHYA, mii_id)
415 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
416 | MACB_BF(CODE, MACB_MAN_C45_CODE)
417 | MACB_BF(DATA, value)));
418 } else {
419 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
420 | MACB_BF(RW, MACB_MAN_C22_WRITE)
421 | MACB_BF(PHYA, mii_id)
422 | MACB_BF(REGA, regnum)
423 | MACB_BF(CODE, MACB_MAN_C22_CODE)
424 | MACB_BF(DATA, value)));
425 }
426
427 status = macb_mdio_wait_for_idle(bp);
428 if (status < 0)
429 goto mdio_write_exit;
430
431mdio_write_exit:
432 pm_runtime_mark_last_busy(&bp->pdev->dev);
433 pm_runtime_put_autosuspend(&bp->pdev->dev);
434mdio_pm_exit:
435 return status;
436}
437
438static void macb_init_buffers(struct macb *bp)
439{
440 struct macb_queue *queue;
441 unsigned int q;
442
443 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
444 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
445#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
446 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
447 queue_writel(queue, RBQPH,
448 upper_32_bits(queue->rx_ring_dma));
449#endif
450 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
451#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
452 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
453 queue_writel(queue, TBQPH,
454 upper_32_bits(queue->tx_ring_dma));
455#endif
456 }
457}
458
459/**
460 * macb_set_tx_clk() - Set a clock to a new frequency
461 * @clk Pointer to the clock to change
462 * @rate New frequency in Hz
463 * @dev Pointer to the struct net_device
464 */
465static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
466{
467 long ferr, rate, rate_rounded;
468
469 if (!clk)
470 return;
471
472 switch (speed) {
473 case SPEED_10:
474 rate = 2500000;
475 break;
476 case SPEED_100:
477 rate = 25000000;
478 break;
479 case SPEED_1000:
480 rate = 125000000;
481 break;
482 default:
483 return;
484 }
485
486 rate_rounded = clk_round_rate(clk, rate);
487 if (rate_rounded < 0)
488 return;
489
490 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
491 * is not satisfied.
492 */
493 ferr = abs(rate_rounded - rate);
494 ferr = DIV_ROUND_UP(ferr, rate / 100000);
495 if (ferr > 5)
496 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
497 rate);
498
499 if (clk_set_rate(clk, rate_rounded))
500 netdev_err(dev, "adjusting tx_clk failed.\n");
501}
502
503static void macb_validate(struct phylink_config *config,
504 unsigned long *supported,
505 struct phylink_link_state *state)
506{
507 struct net_device *ndev = to_net_dev(config->dev);
508 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
509 struct macb *bp = netdev_priv(ndev);
510
511 /* We only support MII, RMII, GMII, RGMII & SGMII. */
512 if (state->interface != PHY_INTERFACE_MODE_NA &&
513 state->interface != PHY_INTERFACE_MODE_MII &&
514 state->interface != PHY_INTERFACE_MODE_RMII &&
515 state->interface != PHY_INTERFACE_MODE_GMII &&
516 state->interface != PHY_INTERFACE_MODE_SGMII &&
517 !phy_interface_mode_is_rgmii(state->interface)) {
518 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
519 return;
520 }
521
522 if (!macb_is_gem(bp) &&
523 (state->interface == PHY_INTERFACE_MODE_GMII ||
524 phy_interface_mode_is_rgmii(state->interface))) {
525 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
526 return;
527 }
528
529 phylink_set_port_modes(mask);
530 phylink_set(mask, Autoneg);
531 phylink_set(mask, Asym_Pause);
532
533 phylink_set(mask, 10baseT_Half);
534 phylink_set(mask, 10baseT_Full);
535 phylink_set(mask, 100baseT_Half);
536 phylink_set(mask, 100baseT_Full);
537
538 if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE &&
539 (state->interface == PHY_INTERFACE_MODE_NA ||
540 state->interface == PHY_INTERFACE_MODE_GMII ||
541 state->interface == PHY_INTERFACE_MODE_SGMII ||
542 phy_interface_mode_is_rgmii(state->interface))) {
543 phylink_set(mask, 1000baseT_Full);
544 phylink_set(mask, 1000baseX_Full);
545
546 if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF))
547 phylink_set(mask, 1000baseT_Half);
548 }
549
550 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
551 bitmap_and(state->advertising, state->advertising, mask,
552 __ETHTOOL_LINK_MODE_MASK_NBITS);
553}
554
555static void macb_mac_pcs_get_state(struct phylink_config *config,
556 struct phylink_link_state *state)
557{
558 state->link = 0;
559}
560
561static void macb_mac_an_restart(struct phylink_config *config)
562{
563 /* Not supported */
564}
565
566static void macb_mac_config(struct phylink_config *config, unsigned int mode,
567 const struct phylink_link_state *state)
568{
569 struct net_device *ndev = to_net_dev(config->dev);
570 struct macb *bp = netdev_priv(ndev);
571 unsigned long flags;
572 u32 old_ctrl, ctrl;
573
574 spin_lock_irqsave(&bp->lock, flags);
575
576 old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR);
577
578 if (bp->caps & MACB_CAPS_MACB_IS_EMAC) {
579 if (state->interface == PHY_INTERFACE_MODE_RMII)
580 ctrl |= MACB_BIT(RM9200_RMII);
581 } else if (macb_is_gem(bp)) {
582 ctrl &= ~(GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL));
583
584 if (state->interface == PHY_INTERFACE_MODE_SGMII)
585 ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
586 }
587
588 /* Apply the new configuration, if any */
589 if (old_ctrl ^ ctrl)
590 macb_or_gem_writel(bp, NCFGR, ctrl);
591
592 spin_unlock_irqrestore(&bp->lock, flags);
593}
594
595static void macb_mac_link_down(struct phylink_config *config, unsigned int mode,
596 phy_interface_t interface)
597{
598 struct net_device *ndev = to_net_dev(config->dev);
599 struct macb *bp = netdev_priv(ndev);
600 struct macb_queue *queue;
601 unsigned int q;
602 u32 ctrl;
603
604 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC))
605 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
606 queue_writel(queue, IDR,
607 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
608
609 /* Disable Rx and Tx */
610 ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE));
611 macb_writel(bp, NCR, ctrl);
612
613 netif_tx_stop_all_queues(ndev);
614}
615
616static void macb_mac_link_up(struct phylink_config *config,
617 struct phy_device *phy,
618 unsigned int mode, phy_interface_t interface,
619 int speed, int duplex,
620 bool tx_pause, bool rx_pause)
621{
622 struct net_device *ndev = to_net_dev(config->dev);
623 struct macb *bp = netdev_priv(ndev);
624 struct macb_queue *queue;
625 unsigned long flags;
626 unsigned int q;
627 u32 ctrl;
628
629 spin_lock_irqsave(&bp->lock, flags);
630
631 ctrl = macb_or_gem_readl(bp, NCFGR);
632
633 ctrl &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
634
635 if (speed == SPEED_100)
636 ctrl |= MACB_BIT(SPD);
637
638 if (duplex)
639 ctrl |= MACB_BIT(FD);
640
641 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) {
642 ctrl &= ~MACB_BIT(PAE);
643 if (macb_is_gem(bp)) {
644 ctrl &= ~GEM_BIT(GBE);
645
646 if (speed == SPEED_1000)
647 ctrl |= GEM_BIT(GBE);
648 }
649
650 if (rx_pause)
651 ctrl |= MACB_BIT(PAE);
652
653 macb_set_tx_clk(bp->tx_clk, speed, ndev);
654
655 /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
656 * cleared the pipeline and control registers.
657 */
658 bp->macbgem_ops.mog_init_rings(bp);
659 macb_init_buffers(bp);
660
661 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
662 queue_writel(queue, IER,
663 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
664 }
665
666 macb_or_gem_writel(bp, NCFGR, ctrl);
667
668 spin_unlock_irqrestore(&bp->lock, flags);
669
670 /* Enable Rx and Tx */
671 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
672
673 netif_tx_wake_all_queues(ndev);
674}
675
676static const struct phylink_mac_ops macb_phylink_ops = {
677 .validate = macb_validate,
678 .mac_pcs_get_state = macb_mac_pcs_get_state,
679 .mac_an_restart = macb_mac_an_restart,
680 .mac_config = macb_mac_config,
681 .mac_link_down = macb_mac_link_down,
682 .mac_link_up = macb_mac_link_up,
683};
684
685static bool macb_phy_handle_exists(struct device_node *dn)
686{
687 dn = of_parse_phandle(dn, "phy-handle", 0);
688 of_node_put(dn);
689 return dn != NULL;
690}
691
692static int macb_phylink_connect(struct macb *bp)
693{
694 struct device_node *dn = bp->pdev->dev.of_node;
695 struct net_device *dev = bp->dev;
696 struct phy_device *phydev;
697 int ret;
698
699 if (dn)
700 ret = phylink_of_phy_connect(bp->phylink, dn, 0);
701
702 if (!dn || (ret && !macb_phy_handle_exists(dn))) {
703 phydev = phy_find_first(bp->mii_bus);
704 if (!phydev) {
705 netdev_err(dev, "no PHY found\n");
706 return -ENXIO;
707 }
708
709 /* attach the mac to the phy */
710 ret = phylink_connect_phy(bp->phylink, phydev);
711 }
712
713 if (ret) {
714 netdev_err(dev, "Could not attach PHY (%d)\n", ret);
715 return ret;
716 }
717
718 phylink_start(bp->phylink);
719
720 return 0;
721}
722
723/* based on au1000_eth. c*/
724static int macb_mii_probe(struct net_device *dev)
725{
726 struct macb *bp = netdev_priv(dev);
727
728 bp->phylink_config.dev = &dev->dev;
729 bp->phylink_config.type = PHYLINK_NETDEV;
730
731 bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode,
732 bp->phy_interface, &macb_phylink_ops);
733 if (IS_ERR(bp->phylink)) {
734 netdev_err(dev, "Could not create a phylink instance (%ld)\n",
735 PTR_ERR(bp->phylink));
736 return PTR_ERR(bp->phylink);
737 }
738
739 return 0;
740}
741
742static int macb_mdiobus_register(struct macb *bp)
743{
744 struct device_node *child, *np = bp->pdev->dev.of_node;
745
746 if (of_phy_is_fixed_link(np))
747 return mdiobus_register(bp->mii_bus);
748
749 /* Only create the PHY from the device tree if at least one PHY is
750 * described. Otherwise scan the entire MDIO bus. We do this to support
751 * old device tree that did not follow the best practices and did not
752 * describe their network PHYs.
753 */
754 for_each_available_child_of_node(np, child)
755 if (of_mdiobus_child_is_phy(child)) {
756 /* The loop increments the child refcount,
757 * decrement it before returning.
758 */
759 of_node_put(child);
760
761 return of_mdiobus_register(bp->mii_bus, np);
762 }
763
764 return mdiobus_register(bp->mii_bus);
765}
766
767static int macb_mii_init(struct macb *bp)
768{
769 int err = -ENXIO;
770
771 /* Enable management port */
772 macb_writel(bp, NCR, MACB_BIT(MPE));
773
774 bp->mii_bus = mdiobus_alloc();
775 if (!bp->mii_bus) {
776 err = -ENOMEM;
777 goto err_out;
778 }
779
780 bp->mii_bus->name = "MACB_mii_bus";
781 bp->mii_bus->read = &macb_mdio_read;
782 bp->mii_bus->write = &macb_mdio_write;
783 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
784 bp->pdev->name, bp->pdev->id);
785 bp->mii_bus->priv = bp;
786 bp->mii_bus->parent = &bp->pdev->dev;
787
788 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
789
790 err = macb_mdiobus_register(bp);
791 if (err)
792 goto err_out_free_mdiobus;
793
794 err = macb_mii_probe(bp->dev);
795 if (err)
796 goto err_out_unregister_bus;
797
798 return 0;
799
800err_out_unregister_bus:
801 mdiobus_unregister(bp->mii_bus);
802err_out_free_mdiobus:
803 mdiobus_free(bp->mii_bus);
804err_out:
805 return err;
806}
807
808static void macb_update_stats(struct macb *bp)
809{
810 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
811 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
812 int offset = MACB_PFR;
813
814 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
815
816 for (; p < end; p++, offset += 4)
817 *p += bp->macb_reg_readl(bp, offset);
818}
819
820static int macb_halt_tx(struct macb *bp)
821{
822 unsigned long halt_time, timeout;
823 u32 status;
824
825 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
826
827 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
828 do {
829 halt_time = jiffies;
830 status = macb_readl(bp, TSR);
831 if (!(status & MACB_BIT(TGO)))
832 return 0;
833
834 udelay(250);
835 } while (time_before(halt_time, timeout));
836
837 return -ETIMEDOUT;
838}
839
840static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
841{
842 if (tx_skb->mapping) {
843 if (tx_skb->mapped_as_page)
844 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
845 tx_skb->size, DMA_TO_DEVICE);
846 else
847 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
848 tx_skb->size, DMA_TO_DEVICE);
849 tx_skb->mapping = 0;
850 }
851
852 if (tx_skb->skb) {
853 dev_kfree_skb_any(tx_skb->skb);
854 tx_skb->skb = NULL;
855 }
856}
857
858static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
859{
860#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
861 struct macb_dma_desc_64 *desc_64;
862
863 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
864 desc_64 = macb_64b_desc(bp, desc);
865 desc_64->addrh = upper_32_bits(addr);
866 /* The low bits of RX address contain the RX_USED bit, clearing
867 * of which allows packet RX. Make sure the high bits are also
868 * visible to HW at that point.
869 */
870 dma_wmb();
871 }
872#endif
873 desc->addr = lower_32_bits(addr);
874}
875
876static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
877{
878 dma_addr_t addr = 0;
879#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
880 struct macb_dma_desc_64 *desc_64;
881
882 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
883 desc_64 = macb_64b_desc(bp, desc);
884 addr = ((u64)(desc_64->addrh) << 32);
885 }
886#endif
887 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
888 return addr;
889}
890
891static void macb_tx_error_task(struct work_struct *work)
892{
893 struct macb_queue *queue = container_of(work, struct macb_queue,
894 tx_error_task);
895 struct macb *bp = queue->bp;
896 struct macb_tx_skb *tx_skb;
897 struct macb_dma_desc *desc;
898 struct sk_buff *skb;
899 unsigned int tail;
900 unsigned long flags;
901
902 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
903 (unsigned int)(queue - bp->queues),
904 queue->tx_tail, queue->tx_head);
905
906 /* Prevent the queue IRQ handlers from running: each of them may call
907 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
908 * As explained below, we have to halt the transmission before updating
909 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
910 * network engine about the macb/gem being halted.
911 */
912 spin_lock_irqsave(&bp->lock, flags);
913
914 /* Make sure nobody is trying to queue up new packets */
915 netif_tx_stop_all_queues(bp->dev);
916
917 /* Stop transmission now
918 * (in case we have just queued new packets)
919 * macb/gem must be halted to write TBQP register
920 */
921 if (macb_halt_tx(bp))
922 /* Just complain for now, reinitializing TX path can be good */
923 netdev_err(bp->dev, "BUG: halt tx timed out\n");
924
925 /* Treat frames in TX queue including the ones that caused the error.
926 * Free transmit buffers in upper layer.
927 */
928 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
929 u32 ctrl;
930
931 desc = macb_tx_desc(queue, tail);
932 ctrl = desc->ctrl;
933 tx_skb = macb_tx_skb(queue, tail);
934 skb = tx_skb->skb;
935
936 if (ctrl & MACB_BIT(TX_USED)) {
937 /* skb is set for the last buffer of the frame */
938 while (!skb) {
939 macb_tx_unmap(bp, tx_skb);
940 tail++;
941 tx_skb = macb_tx_skb(queue, tail);
942 skb = tx_skb->skb;
943 }
944
945 /* ctrl still refers to the first buffer descriptor
946 * since it's the only one written back by the hardware
947 */
948 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
949 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
950 macb_tx_ring_wrap(bp, tail),
951 skb->data);
952 bp->dev->stats.tx_packets++;
953 queue->stats.tx_packets++;
954 bp->dev->stats.tx_bytes += skb->len;
955 queue->stats.tx_bytes += skb->len;
956 }
957 } else {
958 /* "Buffers exhausted mid-frame" errors may only happen
959 * if the driver is buggy, so complain loudly about
960 * those. Statistics are updated by hardware.
961 */
962 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
963 netdev_err(bp->dev,
964 "BUG: TX buffers exhausted mid-frame\n");
965
966 desc->ctrl = ctrl | MACB_BIT(TX_USED);
967 }
968
969 macb_tx_unmap(bp, tx_skb);
970 }
971
972 /* Set end of TX queue */
973 desc = macb_tx_desc(queue, 0);
974 macb_set_addr(bp, desc, 0);
975 desc->ctrl = MACB_BIT(TX_USED);
976
977 /* Make descriptor updates visible to hardware */
978 wmb();
979
980 /* Reinitialize the TX desc queue */
981 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
982#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
983 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
984 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
985#endif
986 /* Make TX ring reflect state of hardware */
987 queue->tx_head = 0;
988 queue->tx_tail = 0;
989
990 /* Housework before enabling TX IRQ */
991 macb_writel(bp, TSR, macb_readl(bp, TSR));
992 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
993
994 /* Now we are ready to start transmission again */
995 netif_tx_start_all_queues(bp->dev);
996 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
997
998 spin_unlock_irqrestore(&bp->lock, flags);
999}
1000
1001static void macb_tx_interrupt(struct macb_queue *queue)
1002{
1003 unsigned int tail;
1004 unsigned int head;
1005 u32 status;
1006 struct macb *bp = queue->bp;
1007 u16 queue_index = queue - bp->queues;
1008
1009 status = macb_readl(bp, TSR);
1010 macb_writel(bp, TSR, status);
1011
1012 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1013 queue_writel(queue, ISR, MACB_BIT(TCOMP));
1014
1015 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
1016 (unsigned long)status);
1017
1018 head = queue->tx_head;
1019 for (tail = queue->tx_tail; tail != head; tail++) {
1020 struct macb_tx_skb *tx_skb;
1021 struct sk_buff *skb;
1022 struct macb_dma_desc *desc;
1023 u32 ctrl;
1024
1025 desc = macb_tx_desc(queue, tail);
1026
1027 /* Make hw descriptor updates visible to CPU */
1028 rmb();
1029
1030 ctrl = desc->ctrl;
1031
1032 /* TX_USED bit is only set by hardware on the very first buffer
1033 * descriptor of the transmitted frame.
1034 */
1035 if (!(ctrl & MACB_BIT(TX_USED)))
1036 break;
1037
1038 /* Process all buffers of the current transmitted frame */
1039 for (;; tail++) {
1040 tx_skb = macb_tx_skb(queue, tail);
1041 skb = tx_skb->skb;
1042
1043 /* First, update TX stats if needed */
1044 if (skb) {
1045 if (unlikely(skb_shinfo(skb)->tx_flags &
1046 SKBTX_HW_TSTAMP) &&
1047 gem_ptp_do_txstamp(queue, skb, desc) == 0) {
1048 /* skb now belongs to timestamp buffer
1049 * and will be removed later
1050 */
1051 tx_skb->skb = NULL;
1052 }
1053 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
1054 macb_tx_ring_wrap(bp, tail),
1055 skb->data);
1056 bp->dev->stats.tx_packets++;
1057 queue->stats.tx_packets++;
1058 bp->dev->stats.tx_bytes += skb->len;
1059 queue->stats.tx_bytes += skb->len;
1060 }
1061
1062 /* Now we can safely release resources */
1063 macb_tx_unmap(bp, tx_skb);
1064
1065 /* skb is set only for the last buffer of the frame.
1066 * WARNING: at this point skb has been freed by
1067 * macb_tx_unmap().
1068 */
1069 if (skb)
1070 break;
1071 }
1072 }
1073
1074 queue->tx_tail = tail;
1075 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
1076 CIRC_CNT(queue->tx_head, queue->tx_tail,
1077 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
1078 netif_wake_subqueue(bp->dev, queue_index);
1079}
1080
1081static void gem_rx_refill(struct macb_queue *queue)
1082{
1083 unsigned int entry;
1084 struct sk_buff *skb;
1085 dma_addr_t paddr;
1086 struct macb *bp = queue->bp;
1087 struct macb_dma_desc *desc;
1088
1089 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
1090 bp->rx_ring_size) > 0) {
1091 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head);
1092
1093 /* Make hw descriptor updates visible to CPU */
1094 rmb();
1095
1096 queue->rx_prepared_head++;
1097 desc = macb_rx_desc(queue, entry);
1098
1099 if (!queue->rx_skbuff[entry]) {
1100 /* allocate sk_buff for this free entry in ring */
1101 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
1102 if (unlikely(!skb)) {
1103 netdev_err(bp->dev,
1104 "Unable to allocate sk_buff\n");
1105 break;
1106 }
1107
1108 /* now fill corresponding descriptor entry */
1109 paddr = dma_map_single(&bp->pdev->dev, skb->data,
1110 bp->rx_buffer_size,
1111 DMA_FROM_DEVICE);
1112 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
1113 dev_kfree_skb(skb);
1114 break;
1115 }
1116
1117 queue->rx_skbuff[entry] = skb;
1118
1119 if (entry == bp->rx_ring_size - 1)
1120 paddr |= MACB_BIT(RX_WRAP);
1121 desc->ctrl = 0;
1122 /* Setting addr clears RX_USED and allows reception,
1123 * make sure ctrl is cleared first to avoid a race.
1124 */
1125 dma_wmb();
1126 macb_set_addr(bp, desc, paddr);
1127
1128 /* properly align Ethernet header */
1129 skb_reserve(skb, NET_IP_ALIGN);
1130 } else {
1131 desc->ctrl = 0;
1132 dma_wmb();
1133 desc->addr &= ~MACB_BIT(RX_USED);
1134 }
1135 }
1136
1137 /* Make descriptor updates visible to hardware */
1138 wmb();
1139
1140 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
1141 queue, queue->rx_prepared_head, queue->rx_tail);
1142}
1143
1144/* Mark DMA descriptors from begin up to and not including end as unused */
1145static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
1146 unsigned int end)
1147{
1148 unsigned int frag;
1149
1150 for (frag = begin; frag != end; frag++) {
1151 struct macb_dma_desc *desc = macb_rx_desc(queue, frag);
1152
1153 desc->addr &= ~MACB_BIT(RX_USED);
1154 }
1155
1156 /* Make descriptor updates visible to hardware */
1157 wmb();
1158
1159 /* When this happens, the hardware stats registers for
1160 * whatever caused this is updated, so we don't have to record
1161 * anything.
1162 */
1163}
1164
1165static int gem_rx(struct macb_queue *queue, struct napi_struct *napi,
1166 int budget)
1167{
1168 struct macb *bp = queue->bp;
1169 unsigned int len;
1170 unsigned int entry;
1171 struct sk_buff *skb;
1172 struct macb_dma_desc *desc;
1173 int count = 0;
1174
1175 while (count < budget) {
1176 u32 ctrl;
1177 dma_addr_t addr;
1178 bool rxused;
1179
1180 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1181 desc = macb_rx_desc(queue, entry);
1182
1183 /* Make hw descriptor updates visible to CPU */
1184 rmb();
1185
1186 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
1187 addr = macb_get_addr(bp, desc);
1188
1189 if (!rxused)
1190 break;
1191
1192 /* Ensure ctrl is at least as up-to-date as rxused */
1193 dma_rmb();
1194
1195 ctrl = desc->ctrl;
1196
1197 queue->rx_tail++;
1198 count++;
1199
1200 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1201 netdev_err(bp->dev,
1202 "not whole frame pointed by descriptor\n");
1203 bp->dev->stats.rx_dropped++;
1204 queue->stats.rx_dropped++;
1205 break;
1206 }
1207 skb = queue->rx_skbuff[entry];
1208 if (unlikely(!skb)) {
1209 netdev_err(bp->dev,
1210 "inconsistent Rx descriptor chain\n");
1211 bp->dev->stats.rx_dropped++;
1212 queue->stats.rx_dropped++;
1213 break;
1214 }
1215 /* now everything is ready for receiving packet */
1216 queue->rx_skbuff[entry] = NULL;
1217 len = ctrl & bp->rx_frm_len_mask;
1218
1219 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1220
1221 skb_put(skb, len);
1222 dma_unmap_single(&bp->pdev->dev, addr,
1223 bp->rx_buffer_size, DMA_FROM_DEVICE);
1224
1225 skb->protocol = eth_type_trans(skb, bp->dev);
1226 skb_checksum_none_assert(skb);
1227 if (bp->dev->features & NETIF_F_RXCSUM &&
1228 !(bp->dev->flags & IFF_PROMISC) &&
1229 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1230 skb->ip_summed = CHECKSUM_UNNECESSARY;
1231
1232 bp->dev->stats.rx_packets++;
1233 queue->stats.rx_packets++;
1234 bp->dev->stats.rx_bytes += skb->len;
1235 queue->stats.rx_bytes += skb->len;
1236
1237 gem_ptp_do_rxstamp(bp, skb, desc);
1238
1239#if defined(DEBUG) && defined(VERBOSE_DEBUG)
1240 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1241 skb->len, skb->csum);
1242 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1243 skb_mac_header(skb), 16, true);
1244 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1245 skb->data, 32, true);
1246#endif
1247
1248 napi_gro_receive(napi, skb);
1249 }
1250
1251 gem_rx_refill(queue);
1252
1253 return count;
1254}
1255
1256static int macb_rx_frame(struct macb_queue *queue, struct napi_struct *napi,
1257 unsigned int first_frag, unsigned int last_frag)
1258{
1259 unsigned int len;
1260 unsigned int frag;
1261 unsigned int offset;
1262 struct sk_buff *skb;
1263 struct macb_dma_desc *desc;
1264 struct macb *bp = queue->bp;
1265
1266 desc = macb_rx_desc(queue, last_frag);
1267 len = desc->ctrl & bp->rx_frm_len_mask;
1268
1269 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1270 macb_rx_ring_wrap(bp, first_frag),
1271 macb_rx_ring_wrap(bp, last_frag), len);
1272
1273 /* The ethernet header starts NET_IP_ALIGN bytes into the
1274 * first buffer. Since the header is 14 bytes, this makes the
1275 * payload word-aligned.
1276 *
1277 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1278 * the two padding bytes into the skb so that we avoid hitting
1279 * the slowpath in memcpy(), and pull them off afterwards.
1280 */
1281 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1282 if (!skb) {
1283 bp->dev->stats.rx_dropped++;
1284 for (frag = first_frag; ; frag++) {
1285 desc = macb_rx_desc(queue, frag);
1286 desc->addr &= ~MACB_BIT(RX_USED);
1287 if (frag == last_frag)
1288 break;
1289 }
1290
1291 /* Make descriptor updates visible to hardware */
1292 wmb();
1293
1294 return 1;
1295 }
1296
1297 offset = 0;
1298 len += NET_IP_ALIGN;
1299 skb_checksum_none_assert(skb);
1300 skb_put(skb, len);
1301
1302 for (frag = first_frag; ; frag++) {
1303 unsigned int frag_len = bp->rx_buffer_size;
1304
1305 if (offset + frag_len > len) {
1306 if (unlikely(frag != last_frag)) {
1307 dev_kfree_skb_any(skb);
1308 return -1;
1309 }
1310 frag_len = len - offset;
1311 }
1312 skb_copy_to_linear_data_offset(skb, offset,
1313 macb_rx_buffer(queue, frag),
1314 frag_len);
1315 offset += bp->rx_buffer_size;
1316 desc = macb_rx_desc(queue, frag);
1317 desc->addr &= ~MACB_BIT(RX_USED);
1318
1319 if (frag == last_frag)
1320 break;
1321 }
1322
1323 /* Make descriptor updates visible to hardware */
1324 wmb();
1325
1326 __skb_pull(skb, NET_IP_ALIGN);
1327 skb->protocol = eth_type_trans(skb, bp->dev);
1328
1329 bp->dev->stats.rx_packets++;
1330 bp->dev->stats.rx_bytes += skb->len;
1331 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1332 skb->len, skb->csum);
1333 napi_gro_receive(napi, skb);
1334
1335 return 0;
1336}
1337
1338static inline void macb_init_rx_ring(struct macb_queue *queue)
1339{
1340 struct macb *bp = queue->bp;
1341 dma_addr_t addr;
1342 struct macb_dma_desc *desc = NULL;
1343 int i;
1344
1345 addr = queue->rx_buffers_dma;
1346 for (i = 0; i < bp->rx_ring_size; i++) {
1347 desc = macb_rx_desc(queue, i);
1348 macb_set_addr(bp, desc, addr);
1349 desc->ctrl = 0;
1350 addr += bp->rx_buffer_size;
1351 }
1352 desc->addr |= MACB_BIT(RX_WRAP);
1353 queue->rx_tail = 0;
1354}
1355
1356static int macb_rx(struct macb_queue *queue, struct napi_struct *napi,
1357 int budget)
1358{
1359 struct macb *bp = queue->bp;
1360 bool reset_rx_queue = false;
1361 int received = 0;
1362 unsigned int tail;
1363 int first_frag = -1;
1364
1365 for (tail = queue->rx_tail; budget > 0; tail++) {
1366 struct macb_dma_desc *desc = macb_rx_desc(queue, tail);
1367 u32 ctrl;
1368
1369 /* Make hw descriptor updates visible to CPU */
1370 rmb();
1371
1372 if (!(desc->addr & MACB_BIT(RX_USED)))
1373 break;
1374
1375 /* Ensure ctrl is at least as up-to-date as addr */
1376 dma_rmb();
1377
1378 ctrl = desc->ctrl;
1379
1380 if (ctrl & MACB_BIT(RX_SOF)) {
1381 if (first_frag != -1)
1382 discard_partial_frame(queue, first_frag, tail);
1383 first_frag = tail;
1384 }
1385
1386 if (ctrl & MACB_BIT(RX_EOF)) {
1387 int dropped;
1388
1389 if (unlikely(first_frag == -1)) {
1390 reset_rx_queue = true;
1391 continue;
1392 }
1393
1394 dropped = macb_rx_frame(queue, napi, first_frag, tail);
1395 first_frag = -1;
1396 if (unlikely(dropped < 0)) {
1397 reset_rx_queue = true;
1398 continue;
1399 }
1400 if (!dropped) {
1401 received++;
1402 budget--;
1403 }
1404 }
1405 }
1406
1407 if (unlikely(reset_rx_queue)) {
1408 unsigned long flags;
1409 u32 ctrl;
1410
1411 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1412
1413 spin_lock_irqsave(&bp->lock, flags);
1414
1415 ctrl = macb_readl(bp, NCR);
1416 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1417
1418 macb_init_rx_ring(queue);
1419 queue_writel(queue, RBQP, queue->rx_ring_dma);
1420
1421 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1422
1423 spin_unlock_irqrestore(&bp->lock, flags);
1424 return received;
1425 }
1426
1427 if (first_frag != -1)
1428 queue->rx_tail = first_frag;
1429 else
1430 queue->rx_tail = tail;
1431
1432 return received;
1433}
1434
1435static int macb_poll(struct napi_struct *napi, int budget)
1436{
1437 struct macb_queue *queue = container_of(napi, struct macb_queue, napi);
1438 struct macb *bp = queue->bp;
1439 int work_done;
1440 u32 status;
1441
1442 status = macb_readl(bp, RSR);
1443 macb_writel(bp, RSR, status);
1444
1445 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1446 (unsigned long)status, budget);
1447
1448 work_done = bp->macbgem_ops.mog_rx(queue, napi, budget);
1449 if (work_done < budget) {
1450 napi_complete_done(napi, work_done);
1451
1452 /* Packets received while interrupts were disabled */
1453 status = macb_readl(bp, RSR);
1454 if (status) {
1455 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1456 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1457 napi_reschedule(napi);
1458 } else {
1459 queue_writel(queue, IER, bp->rx_intr_mask);
1460 }
1461 }
1462
1463 /* TODO: Handle errors */
1464
1465 return work_done;
1466}
1467
1468static void macb_hresp_error_task(unsigned long data)
1469{
1470 struct macb *bp = (struct macb *)data;
1471 struct net_device *dev = bp->dev;
1472 struct macb_queue *queue;
1473 unsigned int q;
1474 u32 ctrl;
1475
1476 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1477 queue_writel(queue, IDR, bp->rx_intr_mask |
1478 MACB_TX_INT_FLAGS |
1479 MACB_BIT(HRESP));
1480 }
1481 ctrl = macb_readl(bp, NCR);
1482 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1483 macb_writel(bp, NCR, ctrl);
1484
1485 netif_tx_stop_all_queues(dev);
1486 netif_carrier_off(dev);
1487
1488 bp->macbgem_ops.mog_init_rings(bp);
1489
1490 /* Initialize TX and RX buffers */
1491 macb_init_buffers(bp);
1492
1493 /* Enable interrupts */
1494 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1495 queue_writel(queue, IER,
1496 bp->rx_intr_mask |
1497 MACB_TX_INT_FLAGS |
1498 MACB_BIT(HRESP));
1499
1500 ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1501 macb_writel(bp, NCR, ctrl);
1502
1503 netif_carrier_on(dev);
1504 netif_tx_start_all_queues(dev);
1505}
1506
1507static void macb_tx_restart(struct macb_queue *queue)
1508{
1509 unsigned int head = queue->tx_head;
1510 unsigned int tail = queue->tx_tail;
1511 struct macb *bp = queue->bp;
1512
1513 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1514 queue_writel(queue, ISR, MACB_BIT(TXUBR));
1515
1516 if (head == tail)
1517 return;
1518
1519 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1520}
1521
1522static irqreturn_t macb_wol_interrupt(int irq, void *dev_id)
1523{
1524 struct macb_queue *queue = dev_id;
1525 struct macb *bp = queue->bp;
1526 u32 status;
1527
1528 status = queue_readl(queue, ISR);
1529
1530 if (unlikely(!status))
1531 return IRQ_NONE;
1532
1533 spin_lock(&bp->lock);
1534
1535 if (status & MACB_BIT(WOL)) {
1536 queue_writel(queue, IDR, MACB_BIT(WOL));
1537 macb_writel(bp, WOL, 0);
1538 netdev_vdbg(bp->dev, "MACB WoL: queue = %u, isr = 0x%08lx\n",
1539 (unsigned int)(queue - bp->queues),
1540 (unsigned long)status);
1541 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1542 queue_writel(queue, ISR, MACB_BIT(WOL));
1543 pm_wakeup_event(&bp->pdev->dev, 0);
1544 }
1545
1546 spin_unlock(&bp->lock);
1547
1548 return IRQ_HANDLED;
1549}
1550
1551static irqreturn_t gem_wol_interrupt(int irq, void *dev_id)
1552{
1553 struct macb_queue *queue = dev_id;
1554 struct macb *bp = queue->bp;
1555 u32 status;
1556
1557 status = queue_readl(queue, ISR);
1558
1559 if (unlikely(!status))
1560 return IRQ_NONE;
1561
1562 spin_lock(&bp->lock);
1563
1564 if (status & GEM_BIT(WOL)) {
1565 queue_writel(queue, IDR, GEM_BIT(WOL));
1566 gem_writel(bp, WOL, 0);
1567 netdev_vdbg(bp->dev, "GEM WoL: queue = %u, isr = 0x%08lx\n",
1568 (unsigned int)(queue - bp->queues),
1569 (unsigned long)status);
1570 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1571 queue_writel(queue, ISR, GEM_BIT(WOL));
1572 pm_wakeup_event(&bp->pdev->dev, 0);
1573 }
1574
1575 spin_unlock(&bp->lock);
1576
1577 return IRQ_HANDLED;
1578}
1579
1580static irqreturn_t macb_interrupt(int irq, void *dev_id)
1581{
1582 struct macb_queue *queue = dev_id;
1583 struct macb *bp = queue->bp;
1584 struct net_device *dev = bp->dev;
1585 u32 status, ctrl;
1586
1587 status = queue_readl(queue, ISR);
1588
1589 if (unlikely(!status))
1590 return IRQ_NONE;
1591
1592 spin_lock(&bp->lock);
1593
1594 while (status) {
1595 /* close possible race with dev_close */
1596 if (unlikely(!netif_running(dev))) {
1597 queue_writel(queue, IDR, -1);
1598 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1599 queue_writel(queue, ISR, -1);
1600 break;
1601 }
1602
1603 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1604 (unsigned int)(queue - bp->queues),
1605 (unsigned long)status);
1606
1607 if (status & bp->rx_intr_mask) {
1608 /* There's no point taking any more interrupts
1609 * until we have processed the buffers. The
1610 * scheduling call may fail if the poll routine
1611 * is already scheduled, so disable interrupts
1612 * now.
1613 */
1614 queue_writel(queue, IDR, bp->rx_intr_mask);
1615 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1616 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1617
1618 if (napi_schedule_prep(&queue->napi)) {
1619 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1620 __napi_schedule(&queue->napi);
1621 }
1622 }
1623
1624 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1625 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1626 schedule_work(&queue->tx_error_task);
1627
1628 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1629 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1630
1631 break;
1632 }
1633
1634 if (status & MACB_BIT(TCOMP))
1635 macb_tx_interrupt(queue);
1636
1637 if (status & MACB_BIT(TXUBR))
1638 macb_tx_restart(queue);
1639
1640 /* Link change detection isn't possible with RMII, so we'll
1641 * add that if/when we get our hands on a full-blown MII PHY.
1642 */
1643
1644 /* There is a hardware issue under heavy load where DMA can
1645 * stop, this causes endless "used buffer descriptor read"
1646 * interrupts but it can be cleared by re-enabling RX. See
1647 * the at91rm9200 manual, section 41.3.1 or the Zynq manual
1648 * section 16.7.4 for details. RXUBR is only enabled for
1649 * these two versions.
1650 */
1651 if (status & MACB_BIT(RXUBR)) {
1652 ctrl = macb_readl(bp, NCR);
1653 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1654 wmb();
1655 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1656
1657 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1658 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1659 }
1660
1661 if (status & MACB_BIT(ISR_ROVR)) {
1662 /* We missed at least one packet */
1663 if (macb_is_gem(bp))
1664 bp->hw_stats.gem.rx_overruns++;
1665 else
1666 bp->hw_stats.macb.rx_overruns++;
1667
1668 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1669 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1670 }
1671
1672 if (status & MACB_BIT(HRESP)) {
1673 tasklet_schedule(&bp->hresp_err_tasklet);
1674 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1675
1676 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1677 queue_writel(queue, ISR, MACB_BIT(HRESP));
1678 }
1679 status = queue_readl(queue, ISR);
1680 }
1681
1682 spin_unlock(&bp->lock);
1683
1684 return IRQ_HANDLED;
1685}
1686
1687#ifdef CONFIG_NET_POLL_CONTROLLER
1688/* Polling receive - used by netconsole and other diagnostic tools
1689 * to allow network i/o with interrupts disabled.
1690 */
1691static void macb_poll_controller(struct net_device *dev)
1692{
1693 struct macb *bp = netdev_priv(dev);
1694 struct macb_queue *queue;
1695 unsigned long flags;
1696 unsigned int q;
1697
1698 local_irq_save(flags);
1699 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1700 macb_interrupt(dev->irq, queue);
1701 local_irq_restore(flags);
1702}
1703#endif
1704
1705static unsigned int macb_tx_map(struct macb *bp,
1706 struct macb_queue *queue,
1707 struct sk_buff *skb,
1708 unsigned int hdrlen)
1709{
1710 dma_addr_t mapping;
1711 unsigned int len, entry, i, tx_head = queue->tx_head;
1712 struct macb_tx_skb *tx_skb = NULL;
1713 struct macb_dma_desc *desc;
1714 unsigned int offset, size, count = 0;
1715 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1716 unsigned int eof = 1, mss_mfs = 0;
1717 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
1718
1719 /* LSO */
1720 if (skb_shinfo(skb)->gso_size != 0) {
1721 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1722 /* UDP - UFO */
1723 lso_ctrl = MACB_LSO_UFO_ENABLE;
1724 else
1725 /* TCP - TSO */
1726 lso_ctrl = MACB_LSO_TSO_ENABLE;
1727 }
1728
1729 /* First, map non-paged data */
1730 len = skb_headlen(skb);
1731
1732 /* first buffer length */
1733 size = hdrlen;
1734
1735 offset = 0;
1736 while (len) {
1737 entry = macb_tx_ring_wrap(bp, tx_head);
1738 tx_skb = &queue->tx_skb[entry];
1739
1740 mapping = dma_map_single(&bp->pdev->dev,
1741 skb->data + offset,
1742 size, DMA_TO_DEVICE);
1743 if (dma_mapping_error(&bp->pdev->dev, mapping))
1744 goto dma_error;
1745
1746 /* Save info to properly release resources */
1747 tx_skb->skb = NULL;
1748 tx_skb->mapping = mapping;
1749 tx_skb->size = size;
1750 tx_skb->mapped_as_page = false;
1751
1752 len -= size;
1753 offset += size;
1754 count++;
1755 tx_head++;
1756
1757 size = min(len, bp->max_tx_length);
1758 }
1759
1760 /* Then, map paged data from fragments */
1761 for (f = 0; f < nr_frags; f++) {
1762 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1763
1764 len = skb_frag_size(frag);
1765 offset = 0;
1766 while (len) {
1767 size = min(len, bp->max_tx_length);
1768 entry = macb_tx_ring_wrap(bp, tx_head);
1769 tx_skb = &queue->tx_skb[entry];
1770
1771 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1772 offset, size, DMA_TO_DEVICE);
1773 if (dma_mapping_error(&bp->pdev->dev, mapping))
1774 goto dma_error;
1775
1776 /* Save info to properly release resources */
1777 tx_skb->skb = NULL;
1778 tx_skb->mapping = mapping;
1779 tx_skb->size = size;
1780 tx_skb->mapped_as_page = true;
1781
1782 len -= size;
1783 offset += size;
1784 count++;
1785 tx_head++;
1786 }
1787 }
1788
1789 /* Should never happen */
1790 if (unlikely(!tx_skb)) {
1791 netdev_err(bp->dev, "BUG! empty skb!\n");
1792 return 0;
1793 }
1794
1795 /* This is the last buffer of the frame: save socket buffer */
1796 tx_skb->skb = skb;
1797
1798 /* Update TX ring: update buffer descriptors in reverse order
1799 * to avoid race condition
1800 */
1801
1802 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1803 * to set the end of TX queue
1804 */
1805 i = tx_head;
1806 entry = macb_tx_ring_wrap(bp, i);
1807 ctrl = MACB_BIT(TX_USED);
1808 desc = macb_tx_desc(queue, entry);
1809 desc->ctrl = ctrl;
1810
1811 if (lso_ctrl) {
1812 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
1813 /* include header and FCS in value given to h/w */
1814 mss_mfs = skb_shinfo(skb)->gso_size +
1815 skb_transport_offset(skb) +
1816 ETH_FCS_LEN;
1817 else /* TSO */ {
1818 mss_mfs = skb_shinfo(skb)->gso_size;
1819 /* TCP Sequence Number Source Select
1820 * can be set only for TSO
1821 */
1822 seq_ctrl = 0;
1823 }
1824 }
1825
1826 do {
1827 i--;
1828 entry = macb_tx_ring_wrap(bp, i);
1829 tx_skb = &queue->tx_skb[entry];
1830 desc = macb_tx_desc(queue, entry);
1831
1832 ctrl = (u32)tx_skb->size;
1833 if (eof) {
1834 ctrl |= MACB_BIT(TX_LAST);
1835 eof = 0;
1836 }
1837 if (unlikely(entry == (bp->tx_ring_size - 1)))
1838 ctrl |= MACB_BIT(TX_WRAP);
1839
1840 /* First descriptor is header descriptor */
1841 if (i == queue->tx_head) {
1842 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
1843 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
1844 if ((bp->dev->features & NETIF_F_HW_CSUM) &&
1845 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl)
1846 ctrl |= MACB_BIT(TX_NOCRC);
1847 } else
1848 /* Only set MSS/MFS on payload descriptors
1849 * (second or later descriptor)
1850 */
1851 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
1852
1853 /* Set TX buffer descriptor */
1854 macb_set_addr(bp, desc, tx_skb->mapping);
1855 /* desc->addr must be visible to hardware before clearing
1856 * 'TX_USED' bit in desc->ctrl.
1857 */
1858 wmb();
1859 desc->ctrl = ctrl;
1860 } while (i != queue->tx_head);
1861
1862 queue->tx_head = tx_head;
1863
1864 return count;
1865
1866dma_error:
1867 netdev_err(bp->dev, "TX DMA map failed\n");
1868
1869 for (i = queue->tx_head; i != tx_head; i++) {
1870 tx_skb = macb_tx_skb(queue, i);
1871
1872 macb_tx_unmap(bp, tx_skb);
1873 }
1874
1875 return 0;
1876}
1877
1878static netdev_features_t macb_features_check(struct sk_buff *skb,
1879 struct net_device *dev,
1880 netdev_features_t features)
1881{
1882 unsigned int nr_frags, f;
1883 unsigned int hdrlen;
1884
1885 /* Validate LSO compatibility */
1886
1887 /* there is only one buffer or protocol is not UDP */
1888 if (!skb_is_nonlinear(skb) || (ip_hdr(skb)->protocol != IPPROTO_UDP))
1889 return features;
1890
1891 /* length of header */
1892 hdrlen = skb_transport_offset(skb);
1893
1894 /* For UFO only:
1895 * When software supplies two or more payload buffers all payload buffers
1896 * apart from the last must be a multiple of 8 bytes in size.
1897 */
1898 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
1899 return features & ~MACB_NETIF_LSO;
1900
1901 nr_frags = skb_shinfo(skb)->nr_frags;
1902 /* No need to check last fragment */
1903 nr_frags--;
1904 for (f = 0; f < nr_frags; f++) {
1905 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1906
1907 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
1908 return features & ~MACB_NETIF_LSO;
1909 }
1910 return features;
1911}
1912
1913static inline int macb_clear_csum(struct sk_buff *skb)
1914{
1915 /* no change for packets without checksum offloading */
1916 if (skb->ip_summed != CHECKSUM_PARTIAL)
1917 return 0;
1918
1919 /* make sure we can modify the header */
1920 if (unlikely(skb_cow_head(skb, 0)))
1921 return -1;
1922
1923 /* initialize checksum field
1924 * This is required - at least for Zynq, which otherwise calculates
1925 * wrong UDP header checksums for UDP packets with UDP data len <=2
1926 */
1927 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
1928 return 0;
1929}
1930
1931static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
1932{
1933 bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb);
1934 int padlen = ETH_ZLEN - (*skb)->len;
1935 int headroom = skb_headroom(*skb);
1936 int tailroom = skb_tailroom(*skb);
1937 struct sk_buff *nskb;
1938 u32 fcs;
1939
1940 if (!(ndev->features & NETIF_F_HW_CSUM) ||
1941 !((*skb)->ip_summed != CHECKSUM_PARTIAL) ||
1942 skb_shinfo(*skb)->gso_size) /* Not available for GSO */
1943 return 0;
1944
1945 if (padlen <= 0) {
1946 /* FCS could be appeded to tailroom. */
1947 if (tailroom >= ETH_FCS_LEN)
1948 goto add_fcs;
1949 /* FCS could be appeded by moving data to headroom. */
1950 else if (!cloned && headroom + tailroom >= ETH_FCS_LEN)
1951 padlen = 0;
1952 /* No room for FCS, need to reallocate skb. */
1953 else
1954 padlen = ETH_FCS_LEN;
1955 } else {
1956 /* Add room for FCS. */
1957 padlen += ETH_FCS_LEN;
1958 }
1959
1960 if (!cloned && headroom + tailroom >= padlen) {
1961 (*skb)->data = memmove((*skb)->head, (*skb)->data, (*skb)->len);
1962 skb_set_tail_pointer(*skb, (*skb)->len);
1963 } else {
1964 nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC);
1965 if (!nskb)
1966 return -ENOMEM;
1967
1968 dev_consume_skb_any(*skb);
1969 *skb = nskb;
1970 }
1971
1972 if (padlen > ETH_FCS_LEN)
1973 skb_put_zero(*skb, padlen - ETH_FCS_LEN);
1974
1975add_fcs:
1976 /* set FCS to packet */
1977 fcs = crc32_le(~0, (*skb)->data, (*skb)->len);
1978 fcs = ~fcs;
1979
1980 skb_put_u8(*skb, fcs & 0xff);
1981 skb_put_u8(*skb, (fcs >> 8) & 0xff);
1982 skb_put_u8(*skb, (fcs >> 16) & 0xff);
1983 skb_put_u8(*skb, (fcs >> 24) & 0xff);
1984
1985 return 0;
1986}
1987
1988static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1989{
1990 u16 queue_index = skb_get_queue_mapping(skb);
1991 struct macb *bp = netdev_priv(dev);
1992 struct macb_queue *queue = &bp->queues[queue_index];
1993 unsigned long flags;
1994 unsigned int desc_cnt, nr_frags, frag_size, f;
1995 unsigned int hdrlen;
1996 bool is_lso;
1997 netdev_tx_t ret = NETDEV_TX_OK;
1998
1999 if (macb_clear_csum(skb)) {
2000 dev_kfree_skb_any(skb);
2001 return ret;
2002 }
2003
2004 if (macb_pad_and_fcs(&skb, dev)) {
2005 dev_kfree_skb_any(skb);
2006 return ret;
2007 }
2008
2009 is_lso = (skb_shinfo(skb)->gso_size != 0);
2010
2011 if (is_lso) {
2012 /* length of headers */
2013 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
2014 /* only queue eth + ip headers separately for UDP */
2015 hdrlen = skb_transport_offset(skb);
2016 else
2017 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
2018 if (skb_headlen(skb) < hdrlen) {
2019 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
2020 /* if this is required, would need to copy to single buffer */
2021 return NETDEV_TX_BUSY;
2022 }
2023 } else
2024 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
2025
2026#if defined(DEBUG) && defined(VERBOSE_DEBUG)
2027 netdev_vdbg(bp->dev,
2028 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
2029 queue_index, skb->len, skb->head, skb->data,
2030 skb_tail_pointer(skb), skb_end_pointer(skb));
2031 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
2032 skb->data, 16, true);
2033#endif
2034
2035 /* Count how many TX buffer descriptors are needed to send this
2036 * socket buffer: skb fragments of jumbo frames may need to be
2037 * split into many buffer descriptors.
2038 */
2039 if (is_lso && (skb_headlen(skb) > hdrlen))
2040 /* extra header descriptor if also payload in first buffer */
2041 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
2042 else
2043 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
2044 nr_frags = skb_shinfo(skb)->nr_frags;
2045 for (f = 0; f < nr_frags; f++) {
2046 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
2047 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
2048 }
2049
2050 spin_lock_irqsave(&bp->lock, flags);
2051
2052 /* This is a hard error, log it. */
2053 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
2054 bp->tx_ring_size) < desc_cnt) {
2055 netif_stop_subqueue(dev, queue_index);
2056 spin_unlock_irqrestore(&bp->lock, flags);
2057 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
2058 queue->tx_head, queue->tx_tail);
2059 return NETDEV_TX_BUSY;
2060 }
2061
2062 /* Map socket buffer for DMA transfer */
2063 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
2064 dev_kfree_skb_any(skb);
2065 goto unlock;
2066 }
2067
2068 /* Make newly initialized descriptor visible to hardware */
2069 wmb();
2070 skb_tx_timestamp(skb);
2071
2072 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
2073
2074 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
2075 netif_stop_subqueue(dev, queue_index);
2076
2077unlock:
2078 spin_unlock_irqrestore(&bp->lock, flags);
2079
2080 return ret;
2081}
2082
2083static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
2084{
2085 if (!macb_is_gem(bp)) {
2086 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
2087 } else {
2088 bp->rx_buffer_size = size;
2089
2090 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
2091 netdev_dbg(bp->dev,
2092 "RX buffer must be multiple of %d bytes, expanding\n",
2093 RX_BUFFER_MULTIPLE);
2094 bp->rx_buffer_size =
2095 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
2096 }
2097 }
2098
2099 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
2100 bp->dev->mtu, bp->rx_buffer_size);
2101}
2102
2103static void gem_free_rx_buffers(struct macb *bp)
2104{
2105 struct sk_buff *skb;
2106 struct macb_dma_desc *desc;
2107 struct macb_queue *queue;
2108 dma_addr_t addr;
2109 unsigned int q;
2110 int i;
2111
2112 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2113 if (!queue->rx_skbuff)
2114 continue;
2115
2116 for (i = 0; i < bp->rx_ring_size; i++) {
2117 skb = queue->rx_skbuff[i];
2118
2119 if (!skb)
2120 continue;
2121
2122 desc = macb_rx_desc(queue, i);
2123 addr = macb_get_addr(bp, desc);
2124
2125 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
2126 DMA_FROM_DEVICE);
2127 dev_kfree_skb_any(skb);
2128 skb = NULL;
2129 }
2130
2131 kfree(queue->rx_skbuff);
2132 queue->rx_skbuff = NULL;
2133 }
2134}
2135
2136static void macb_free_rx_buffers(struct macb *bp)
2137{
2138 struct macb_queue *queue = &bp->queues[0];
2139
2140 if (queue->rx_buffers) {
2141 dma_free_coherent(&bp->pdev->dev,
2142 bp->rx_ring_size * bp->rx_buffer_size,
2143 queue->rx_buffers, queue->rx_buffers_dma);
2144 queue->rx_buffers = NULL;
2145 }
2146}
2147
2148static void macb_free_consistent(struct macb *bp)
2149{
2150 struct macb_queue *queue;
2151 unsigned int q;
2152 int size;
2153
2154 bp->macbgem_ops.mog_free_rx_buffers(bp);
2155
2156 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2157 kfree(queue->tx_skb);
2158 queue->tx_skb = NULL;
2159 if (queue->tx_ring) {
2160 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2161 dma_free_coherent(&bp->pdev->dev, size,
2162 queue->tx_ring, queue->tx_ring_dma);
2163 queue->tx_ring = NULL;
2164 }
2165 if (queue->rx_ring) {
2166 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2167 dma_free_coherent(&bp->pdev->dev, size,
2168 queue->rx_ring, queue->rx_ring_dma);
2169 queue->rx_ring = NULL;
2170 }
2171 }
2172}
2173
2174static int gem_alloc_rx_buffers(struct macb *bp)
2175{
2176 struct macb_queue *queue;
2177 unsigned int q;
2178 int size;
2179
2180 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2181 size = bp->rx_ring_size * sizeof(struct sk_buff *);
2182 queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
2183 if (!queue->rx_skbuff)
2184 return -ENOMEM;
2185 else
2186 netdev_dbg(bp->dev,
2187 "Allocated %d RX struct sk_buff entries at %p\n",
2188 bp->rx_ring_size, queue->rx_skbuff);
2189 }
2190 return 0;
2191}
2192
2193static int macb_alloc_rx_buffers(struct macb *bp)
2194{
2195 struct macb_queue *queue = &bp->queues[0];
2196 int size;
2197
2198 size = bp->rx_ring_size * bp->rx_buffer_size;
2199 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
2200 &queue->rx_buffers_dma, GFP_KERNEL);
2201 if (!queue->rx_buffers)
2202 return -ENOMEM;
2203
2204 netdev_dbg(bp->dev,
2205 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
2206 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
2207 return 0;
2208}
2209
2210static int macb_alloc_consistent(struct macb *bp)
2211{
2212 struct macb_queue *queue;
2213 unsigned int q;
2214 int size;
2215
2216 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2217 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2218 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2219 &queue->tx_ring_dma,
2220 GFP_KERNEL);
2221 if (!queue->tx_ring)
2222 goto out_err;
2223 netdev_dbg(bp->dev,
2224 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
2225 q, size, (unsigned long)queue->tx_ring_dma,
2226 queue->tx_ring);
2227
2228 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
2229 queue->tx_skb = kmalloc(size, GFP_KERNEL);
2230 if (!queue->tx_skb)
2231 goto out_err;
2232
2233 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2234 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2235 &queue->rx_ring_dma, GFP_KERNEL);
2236 if (!queue->rx_ring)
2237 goto out_err;
2238 netdev_dbg(bp->dev,
2239 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
2240 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
2241 }
2242 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
2243 goto out_err;
2244
2245 return 0;
2246
2247out_err:
2248 macb_free_consistent(bp);
2249 return -ENOMEM;
2250}
2251
2252static void gem_init_rings(struct macb *bp)
2253{
2254 struct macb_queue *queue;
2255 struct macb_dma_desc *desc = NULL;
2256 unsigned int q;
2257 int i;
2258
2259 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2260 for (i = 0; i < bp->tx_ring_size; i++) {
2261 desc = macb_tx_desc(queue, i);
2262 macb_set_addr(bp, desc, 0);
2263 desc->ctrl = MACB_BIT(TX_USED);
2264 }
2265 desc->ctrl |= MACB_BIT(TX_WRAP);
2266 queue->tx_head = 0;
2267 queue->tx_tail = 0;
2268
2269 queue->rx_tail = 0;
2270 queue->rx_prepared_head = 0;
2271
2272 gem_rx_refill(queue);
2273 }
2274
2275}
2276
2277static void macb_init_rings(struct macb *bp)
2278{
2279 int i;
2280 struct macb_dma_desc *desc = NULL;
2281
2282 macb_init_rx_ring(&bp->queues[0]);
2283
2284 for (i = 0; i < bp->tx_ring_size; i++) {
2285 desc = macb_tx_desc(&bp->queues[0], i);
2286 macb_set_addr(bp, desc, 0);
2287 desc->ctrl = MACB_BIT(TX_USED);
2288 }
2289 bp->queues[0].tx_head = 0;
2290 bp->queues[0].tx_tail = 0;
2291 desc->ctrl |= MACB_BIT(TX_WRAP);
2292}
2293
2294static void macb_reset_hw(struct macb *bp)
2295{
2296 struct macb_queue *queue;
2297 unsigned int q;
2298 u32 ctrl = macb_readl(bp, NCR);
2299
2300 /* Disable RX and TX (XXX: Should we halt the transmission
2301 * more gracefully?)
2302 */
2303 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
2304
2305 /* Clear the stats registers (XXX: Update stats first?) */
2306 ctrl |= MACB_BIT(CLRSTAT);
2307
2308 macb_writel(bp, NCR, ctrl);
2309
2310 /* Clear all status flags */
2311 macb_writel(bp, TSR, -1);
2312 macb_writel(bp, RSR, -1);
2313
2314 /* Disable all interrupts */
2315 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2316 queue_writel(queue, IDR, -1);
2317 queue_readl(queue, ISR);
2318 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2319 queue_writel(queue, ISR, -1);
2320 }
2321}
2322
2323static u32 gem_mdc_clk_div(struct macb *bp)
2324{
2325 u32 config;
2326 unsigned long pclk_hz = clk_get_rate(bp->pclk);
2327
2328 if (pclk_hz <= 20000000)
2329 config = GEM_BF(CLK, GEM_CLK_DIV8);
2330 else if (pclk_hz <= 40000000)
2331 config = GEM_BF(CLK, GEM_CLK_DIV16);
2332 else if (pclk_hz <= 80000000)
2333 config = GEM_BF(CLK, GEM_CLK_DIV32);
2334 else if (pclk_hz <= 120000000)
2335 config = GEM_BF(CLK, GEM_CLK_DIV48);
2336 else if (pclk_hz <= 160000000)
2337 config = GEM_BF(CLK, GEM_CLK_DIV64);
2338 else
2339 config = GEM_BF(CLK, GEM_CLK_DIV96);
2340
2341 return config;
2342}
2343
2344static u32 macb_mdc_clk_div(struct macb *bp)
2345{
2346 u32 config;
2347 unsigned long pclk_hz;
2348
2349 if (macb_is_gem(bp))
2350 return gem_mdc_clk_div(bp);
2351
2352 pclk_hz = clk_get_rate(bp->pclk);
2353 if (pclk_hz <= 20000000)
2354 config = MACB_BF(CLK, MACB_CLK_DIV8);
2355 else if (pclk_hz <= 40000000)
2356 config = MACB_BF(CLK, MACB_CLK_DIV16);
2357 else if (pclk_hz <= 80000000)
2358 config = MACB_BF(CLK, MACB_CLK_DIV32);
2359 else
2360 config = MACB_BF(CLK, MACB_CLK_DIV64);
2361
2362 return config;
2363}
2364
2365/* Get the DMA bus width field of the network configuration register that we
2366 * should program. We find the width from decoding the design configuration
2367 * register to find the maximum supported data bus width.
2368 */
2369static u32 macb_dbw(struct macb *bp)
2370{
2371 if (!macb_is_gem(bp))
2372 return 0;
2373
2374 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2375 case 4:
2376 return GEM_BF(DBW, GEM_DBW128);
2377 case 2:
2378 return GEM_BF(DBW, GEM_DBW64);
2379 case 1:
2380 default:
2381 return GEM_BF(DBW, GEM_DBW32);
2382 }
2383}
2384
2385/* Configure the receive DMA engine
2386 * - use the correct receive buffer size
2387 * - set best burst length for DMA operations
2388 * (if not supported by FIFO, it will fallback to default)
2389 * - set both rx/tx packet buffers to full memory size
2390 * These are configurable parameters for GEM.
2391 */
2392static void macb_configure_dma(struct macb *bp)
2393{
2394 struct macb_queue *queue;
2395 u32 buffer_size;
2396 unsigned int q;
2397 u32 dmacfg;
2398
2399 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2400 if (macb_is_gem(bp)) {
2401 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2402 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2403 if (q)
2404 queue_writel(queue, RBQS, buffer_size);
2405 else
2406 dmacfg |= GEM_BF(RXBS, buffer_size);
2407 }
2408 if (bp->dma_burst_length)
2409 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2410 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2411 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2412
2413 if (bp->native_io)
2414 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2415 else
2416 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2417
2418 if (bp->dev->features & NETIF_F_HW_CSUM)
2419 dmacfg |= GEM_BIT(TXCOEN);
2420 else
2421 dmacfg &= ~GEM_BIT(TXCOEN);
2422
2423 dmacfg &= ~GEM_BIT(ADDR64);
2424#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2425 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2426 dmacfg |= GEM_BIT(ADDR64);
2427#endif
2428#ifdef CONFIG_MACB_USE_HWSTAMP
2429 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2430 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2431#endif
2432 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2433 dmacfg);
2434 gem_writel(bp, DMACFG, dmacfg);
2435 }
2436}
2437
2438static void macb_init_hw(struct macb *bp)
2439{
2440 u32 config;
2441
2442 macb_reset_hw(bp);
2443 macb_set_hwaddr(bp);
2444
2445 config = macb_mdc_clk_div(bp);
2446 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2447 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2448 if (bp->caps & MACB_CAPS_JUMBO)
2449 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2450 else
2451 config |= MACB_BIT(BIG); /* Receive oversized frames */
2452 if (bp->dev->flags & IFF_PROMISC)
2453 config |= MACB_BIT(CAF); /* Copy All Frames */
2454 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2455 config |= GEM_BIT(RXCOEN);
2456 if (!(bp->dev->flags & IFF_BROADCAST))
2457 config |= MACB_BIT(NBC); /* No BroadCast */
2458 config |= macb_dbw(bp);
2459 macb_writel(bp, NCFGR, config);
2460 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2461 gem_writel(bp, JML, bp->jumbo_max_len);
2462 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2463 if (bp->caps & MACB_CAPS_JUMBO)
2464 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2465
2466 macb_configure_dma(bp);
2467}
2468
2469/* The hash address register is 64 bits long and takes up two
2470 * locations in the memory map. The least significant bits are stored
2471 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2472 *
2473 * The unicast hash enable and the multicast hash enable bits in the
2474 * network configuration register enable the reception of hash matched
2475 * frames. The destination address is reduced to a 6 bit index into
2476 * the 64 bit hash register using the following hash function. The
2477 * hash function is an exclusive or of every sixth bit of the
2478 * destination address.
2479 *
2480 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2481 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2482 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2483 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2484 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2485 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2486 *
2487 * da[0] represents the least significant bit of the first byte
2488 * received, that is, the multicast/unicast indicator, and da[47]
2489 * represents the most significant bit of the last byte received. If
2490 * the hash index, hi[n], points to a bit that is set in the hash
2491 * register then the frame will be matched according to whether the
2492 * frame is multicast or unicast. A multicast match will be signalled
2493 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2494 * index points to a bit set in the hash register. A unicast match
2495 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2496 * and the hash index points to a bit set in the hash register. To
2497 * receive all multicast frames, the hash register should be set with
2498 * all ones and the multicast hash enable bit should be set in the
2499 * network configuration register.
2500 */
2501
2502static inline int hash_bit_value(int bitnr, __u8 *addr)
2503{
2504 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2505 return 1;
2506 return 0;
2507}
2508
2509/* Return the hash index value for the specified address. */
2510static int hash_get_index(__u8 *addr)
2511{
2512 int i, j, bitval;
2513 int hash_index = 0;
2514
2515 for (j = 0; j < 6; j++) {
2516 for (i = 0, bitval = 0; i < 8; i++)
2517 bitval ^= hash_bit_value(i * 6 + j, addr);
2518
2519 hash_index |= (bitval << j);
2520 }
2521
2522 return hash_index;
2523}
2524
2525/* Add multicast addresses to the internal multicast-hash table. */
2526static void macb_sethashtable(struct net_device *dev)
2527{
2528 struct netdev_hw_addr *ha;
2529 unsigned long mc_filter[2];
2530 unsigned int bitnr;
2531 struct macb *bp = netdev_priv(dev);
2532
2533 mc_filter[0] = 0;
2534 mc_filter[1] = 0;
2535
2536 netdev_for_each_mc_addr(ha, dev) {
2537 bitnr = hash_get_index(ha->addr);
2538 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2539 }
2540
2541 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2542 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2543}
2544
2545/* Enable/Disable promiscuous and multicast modes. */
2546static void macb_set_rx_mode(struct net_device *dev)
2547{
2548 unsigned long cfg;
2549 struct macb *bp = netdev_priv(dev);
2550
2551 cfg = macb_readl(bp, NCFGR);
2552
2553 if (dev->flags & IFF_PROMISC) {
2554 /* Enable promiscuous mode */
2555 cfg |= MACB_BIT(CAF);
2556
2557 /* Disable RX checksum offload */
2558 if (macb_is_gem(bp))
2559 cfg &= ~GEM_BIT(RXCOEN);
2560 } else {
2561 /* Disable promiscuous mode */
2562 cfg &= ~MACB_BIT(CAF);
2563
2564 /* Enable RX checksum offload only if requested */
2565 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2566 cfg |= GEM_BIT(RXCOEN);
2567 }
2568
2569 if (dev->flags & IFF_ALLMULTI) {
2570 /* Enable all multicast mode */
2571 macb_or_gem_writel(bp, HRB, -1);
2572 macb_or_gem_writel(bp, HRT, -1);
2573 cfg |= MACB_BIT(NCFGR_MTI);
2574 } else if (!netdev_mc_empty(dev)) {
2575 /* Enable specific multicasts */
2576 macb_sethashtable(dev);
2577 cfg |= MACB_BIT(NCFGR_MTI);
2578 } else if (dev->flags & (~IFF_ALLMULTI)) {
2579 /* Disable all multicast mode */
2580 macb_or_gem_writel(bp, HRB, 0);
2581 macb_or_gem_writel(bp, HRT, 0);
2582 cfg &= ~MACB_BIT(NCFGR_MTI);
2583 }
2584
2585 macb_writel(bp, NCFGR, cfg);
2586}
2587
2588static int macb_open(struct net_device *dev)
2589{
2590 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2591 struct macb *bp = netdev_priv(dev);
2592 struct macb_queue *queue;
2593 unsigned int q;
2594 int err;
2595
2596 netdev_dbg(bp->dev, "open\n");
2597
2598 err = pm_runtime_get_sync(&bp->pdev->dev);
2599 if (err < 0)
2600 goto pm_exit;
2601
2602 /* RX buffers initialization */
2603 macb_init_rx_buffer_size(bp, bufsz);
2604
2605 err = macb_alloc_consistent(bp);
2606 if (err) {
2607 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2608 err);
2609 goto pm_exit;
2610 }
2611
2612 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2613 napi_enable(&queue->napi);
2614
2615 macb_init_hw(bp);
2616
2617 err = macb_phylink_connect(bp);
2618 if (err)
2619 goto reset_hw;
2620
2621 netif_tx_start_all_queues(dev);
2622
2623 if (bp->ptp_info)
2624 bp->ptp_info->ptp_init(dev);
2625
2626 return 0;
2627
2628reset_hw:
2629 macb_reset_hw(bp);
2630 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2631 napi_disable(&queue->napi);
2632 macb_free_consistent(bp);
2633pm_exit:
2634 pm_runtime_put_sync(&bp->pdev->dev);
2635 return err;
2636}
2637
2638static int macb_close(struct net_device *dev)
2639{
2640 struct macb *bp = netdev_priv(dev);
2641 struct macb_queue *queue;
2642 unsigned long flags;
2643 unsigned int q;
2644
2645 netif_tx_stop_all_queues(dev);
2646
2647 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2648 napi_disable(&queue->napi);
2649
2650 phylink_stop(bp->phylink);
2651 phylink_disconnect_phy(bp->phylink);
2652
2653 spin_lock_irqsave(&bp->lock, flags);
2654 macb_reset_hw(bp);
2655 netif_carrier_off(dev);
2656 spin_unlock_irqrestore(&bp->lock, flags);
2657
2658 macb_free_consistent(bp);
2659
2660 if (bp->ptp_info)
2661 bp->ptp_info->ptp_remove(dev);
2662
2663 pm_runtime_put(&bp->pdev->dev);
2664
2665 return 0;
2666}
2667
2668static int macb_change_mtu(struct net_device *dev, int new_mtu)
2669{
2670 if (netif_running(dev))
2671 return -EBUSY;
2672
2673 dev->mtu = new_mtu;
2674
2675 return 0;
2676}
2677
2678static void gem_update_stats(struct macb *bp)
2679{
2680 struct macb_queue *queue;
2681 unsigned int i, q, idx;
2682 unsigned long *stat;
2683
2684 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2685
2686 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2687 u32 offset = gem_statistics[i].offset;
2688 u64 val = bp->macb_reg_readl(bp, offset);
2689
2690 bp->ethtool_stats[i] += val;
2691 *p += val;
2692
2693 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2694 /* Add GEM_OCTTXH, GEM_OCTRXH */
2695 val = bp->macb_reg_readl(bp, offset + 4);
2696 bp->ethtool_stats[i] += ((u64)val) << 32;
2697 *(++p) += val;
2698 }
2699 }
2700
2701 idx = GEM_STATS_LEN;
2702 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2703 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
2704 bp->ethtool_stats[idx++] = *stat;
2705}
2706
2707static struct net_device_stats *gem_get_stats(struct macb *bp)
2708{
2709 struct gem_stats *hwstat = &bp->hw_stats.gem;
2710 struct net_device_stats *nstat = &bp->dev->stats;
2711
2712 gem_update_stats(bp);
2713
2714 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2715 hwstat->rx_alignment_errors +
2716 hwstat->rx_resource_errors +
2717 hwstat->rx_overruns +
2718 hwstat->rx_oversize_frames +
2719 hwstat->rx_jabbers +
2720 hwstat->rx_undersized_frames +
2721 hwstat->rx_length_field_frame_errors);
2722 nstat->tx_errors = (hwstat->tx_late_collisions +
2723 hwstat->tx_excessive_collisions +
2724 hwstat->tx_underrun +
2725 hwstat->tx_carrier_sense_errors);
2726 nstat->multicast = hwstat->rx_multicast_frames;
2727 nstat->collisions = (hwstat->tx_single_collision_frames +
2728 hwstat->tx_multiple_collision_frames +
2729 hwstat->tx_excessive_collisions);
2730 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
2731 hwstat->rx_jabbers +
2732 hwstat->rx_undersized_frames +
2733 hwstat->rx_length_field_frame_errors);
2734 nstat->rx_over_errors = hwstat->rx_resource_errors;
2735 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
2736 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
2737 nstat->rx_fifo_errors = hwstat->rx_overruns;
2738 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
2739 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
2740 nstat->tx_fifo_errors = hwstat->tx_underrun;
2741
2742 return nstat;
2743}
2744
2745static void gem_get_ethtool_stats(struct net_device *dev,
2746 struct ethtool_stats *stats, u64 *data)
2747{
2748 struct macb *bp;
2749
2750 bp = netdev_priv(dev);
2751 gem_update_stats(bp);
2752 memcpy(data, &bp->ethtool_stats, sizeof(u64)
2753 * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
2754}
2755
2756static int gem_get_sset_count(struct net_device *dev, int sset)
2757{
2758 struct macb *bp = netdev_priv(dev);
2759
2760 switch (sset) {
2761 case ETH_SS_STATS:
2762 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
2763 default:
2764 return -EOPNOTSUPP;
2765 }
2766}
2767
2768static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2769{
2770 char stat_string[ETH_GSTRING_LEN];
2771 struct macb *bp = netdev_priv(dev);
2772 struct macb_queue *queue;
2773 unsigned int i;
2774 unsigned int q;
2775
2776 switch (sset) {
2777 case ETH_SS_STATS:
2778 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2779 memcpy(p, gem_statistics[i].stat_string,
2780 ETH_GSTRING_LEN);
2781
2782 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2783 for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
2784 snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s",
2785 q, queue_statistics[i].stat_string);
2786 memcpy(p, stat_string, ETH_GSTRING_LEN);
2787 }
2788 }
2789 break;
2790 }
2791}
2792
2793static struct net_device_stats *macb_get_stats(struct net_device *dev)
2794{
2795 struct macb *bp = netdev_priv(dev);
2796 struct net_device_stats *nstat = &bp->dev->stats;
2797 struct macb_stats *hwstat = &bp->hw_stats.macb;
2798
2799 if (macb_is_gem(bp))
2800 return gem_get_stats(bp);
2801
2802 /* read stats from hardware */
2803 macb_update_stats(bp);
2804
2805 /* Convert HW stats into netdevice stats */
2806 nstat->rx_errors = (hwstat->rx_fcs_errors +
2807 hwstat->rx_align_errors +
2808 hwstat->rx_resource_errors +
2809 hwstat->rx_overruns +
2810 hwstat->rx_oversize_pkts +
2811 hwstat->rx_jabbers +
2812 hwstat->rx_undersize_pkts +
2813 hwstat->rx_length_mismatch);
2814 nstat->tx_errors = (hwstat->tx_late_cols +
2815 hwstat->tx_excessive_cols +
2816 hwstat->tx_underruns +
2817 hwstat->tx_carrier_errors +
2818 hwstat->sqe_test_errors);
2819 nstat->collisions = (hwstat->tx_single_cols +
2820 hwstat->tx_multiple_cols +
2821 hwstat->tx_excessive_cols);
2822 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2823 hwstat->rx_jabbers +
2824 hwstat->rx_undersize_pkts +
2825 hwstat->rx_length_mismatch);
2826 nstat->rx_over_errors = hwstat->rx_resource_errors +
2827 hwstat->rx_overruns;
2828 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2829 nstat->rx_frame_errors = hwstat->rx_align_errors;
2830 nstat->rx_fifo_errors = hwstat->rx_overruns;
2831 /* XXX: What does "missed" mean? */
2832 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2833 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2834 nstat->tx_fifo_errors = hwstat->tx_underruns;
2835 /* Don't know about heartbeat or window errors... */
2836
2837 return nstat;
2838}
2839
2840static int macb_get_regs_len(struct net_device *netdev)
2841{
2842 return MACB_GREGS_NBR * sizeof(u32);
2843}
2844
2845static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2846 void *p)
2847{
2848 struct macb *bp = netdev_priv(dev);
2849 unsigned int tail, head;
2850 u32 *regs_buff = p;
2851
2852 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2853 | MACB_GREGS_VERSION;
2854
2855 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
2856 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
2857
2858 regs_buff[0] = macb_readl(bp, NCR);
2859 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2860 regs_buff[2] = macb_readl(bp, NSR);
2861 regs_buff[3] = macb_readl(bp, TSR);
2862 regs_buff[4] = macb_readl(bp, RBQP);
2863 regs_buff[5] = macb_readl(bp, TBQP);
2864 regs_buff[6] = macb_readl(bp, RSR);
2865 regs_buff[7] = macb_readl(bp, IMR);
2866
2867 regs_buff[8] = tail;
2868 regs_buff[9] = head;
2869 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2870 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2871
2872 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
2873 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
2874 if (macb_is_gem(bp))
2875 regs_buff[13] = gem_readl(bp, DMACFG);
2876}
2877
2878static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2879{
2880 struct macb *bp = netdev_priv(netdev);
2881
2882 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
2883 phylink_ethtool_get_wol(bp->phylink, wol);
2884 wol->supported |= WAKE_MAGIC;
2885
2886 if (bp->wol & MACB_WOL_ENABLED)
2887 wol->wolopts |= WAKE_MAGIC;
2888 }
2889}
2890
2891static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2892{
2893 struct macb *bp = netdev_priv(netdev);
2894 int ret;
2895
2896 /* Pass the order to phylink layer */
2897 ret = phylink_ethtool_set_wol(bp->phylink, wol);
2898 /* Don't manage WoL on MAC if handled by the PHY
2899 * or if there's a failure in talking to the PHY
2900 */
2901 if (!ret || ret != -EOPNOTSUPP)
2902 return ret;
2903
2904 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
2905 (wol->wolopts & ~WAKE_MAGIC))
2906 return -EOPNOTSUPP;
2907
2908 if (wol->wolopts & WAKE_MAGIC)
2909 bp->wol |= MACB_WOL_ENABLED;
2910 else
2911 bp->wol &= ~MACB_WOL_ENABLED;
2912
2913 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
2914
2915 return 0;
2916}
2917
2918static int macb_get_link_ksettings(struct net_device *netdev,
2919 struct ethtool_link_ksettings *kset)
2920{
2921 struct macb *bp = netdev_priv(netdev);
2922
2923 return phylink_ethtool_ksettings_get(bp->phylink, kset);
2924}
2925
2926static int macb_set_link_ksettings(struct net_device *netdev,
2927 const struct ethtool_link_ksettings *kset)
2928{
2929 struct macb *bp = netdev_priv(netdev);
2930
2931 return phylink_ethtool_ksettings_set(bp->phylink, kset);
2932}
2933
2934static void macb_get_ringparam(struct net_device *netdev,
2935 struct ethtool_ringparam *ring)
2936{
2937 struct macb *bp = netdev_priv(netdev);
2938
2939 ring->rx_max_pending = MAX_RX_RING_SIZE;
2940 ring->tx_max_pending = MAX_TX_RING_SIZE;
2941
2942 ring->rx_pending = bp->rx_ring_size;
2943 ring->tx_pending = bp->tx_ring_size;
2944}
2945
2946static int macb_set_ringparam(struct net_device *netdev,
2947 struct ethtool_ringparam *ring)
2948{
2949 struct macb *bp = netdev_priv(netdev);
2950 u32 new_rx_size, new_tx_size;
2951 unsigned int reset = 0;
2952
2953 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2954 return -EINVAL;
2955
2956 new_rx_size = clamp_t(u32, ring->rx_pending,
2957 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
2958 new_rx_size = roundup_pow_of_two(new_rx_size);
2959
2960 new_tx_size = clamp_t(u32, ring->tx_pending,
2961 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
2962 new_tx_size = roundup_pow_of_two(new_tx_size);
2963
2964 if ((new_tx_size == bp->tx_ring_size) &&
2965 (new_rx_size == bp->rx_ring_size)) {
2966 /* nothing to do */
2967 return 0;
2968 }
2969
2970 if (netif_running(bp->dev)) {
2971 reset = 1;
2972 macb_close(bp->dev);
2973 }
2974
2975 bp->rx_ring_size = new_rx_size;
2976 bp->tx_ring_size = new_tx_size;
2977
2978 if (reset)
2979 macb_open(bp->dev);
2980
2981 return 0;
2982}
2983
2984#ifdef CONFIG_MACB_USE_HWSTAMP
2985static unsigned int gem_get_tsu_rate(struct macb *bp)
2986{
2987 struct clk *tsu_clk;
2988 unsigned int tsu_rate;
2989
2990 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
2991 if (!IS_ERR(tsu_clk))
2992 tsu_rate = clk_get_rate(tsu_clk);
2993 /* try pclk instead */
2994 else if (!IS_ERR(bp->pclk)) {
2995 tsu_clk = bp->pclk;
2996 tsu_rate = clk_get_rate(tsu_clk);
2997 } else
2998 return -ENOTSUPP;
2999 return tsu_rate;
3000}
3001
3002static s32 gem_get_ptp_max_adj(void)
3003{
3004 return 64000000;
3005}
3006
3007static int gem_get_ts_info(struct net_device *dev,
3008 struct ethtool_ts_info *info)
3009{
3010 struct macb *bp = netdev_priv(dev);
3011
3012 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
3013 ethtool_op_get_ts_info(dev, info);
3014 return 0;
3015 }
3016
3017 info->so_timestamping =
3018 SOF_TIMESTAMPING_TX_SOFTWARE |
3019 SOF_TIMESTAMPING_RX_SOFTWARE |
3020 SOF_TIMESTAMPING_SOFTWARE |
3021 SOF_TIMESTAMPING_TX_HARDWARE |
3022 SOF_TIMESTAMPING_RX_HARDWARE |
3023 SOF_TIMESTAMPING_RAW_HARDWARE;
3024 info->tx_types =
3025 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
3026 (1 << HWTSTAMP_TX_OFF) |
3027 (1 << HWTSTAMP_TX_ON);
3028 info->rx_filters =
3029 (1 << HWTSTAMP_FILTER_NONE) |
3030 (1 << HWTSTAMP_FILTER_ALL);
3031
3032 info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
3033
3034 return 0;
3035}
3036
3037static struct macb_ptp_info gem_ptp_info = {
3038 .ptp_init = gem_ptp_init,
3039 .ptp_remove = gem_ptp_remove,
3040 .get_ptp_max_adj = gem_get_ptp_max_adj,
3041 .get_tsu_rate = gem_get_tsu_rate,
3042 .get_ts_info = gem_get_ts_info,
3043 .get_hwtst = gem_get_hwtst,
3044 .set_hwtst = gem_set_hwtst,
3045};
3046#endif
3047
3048static int macb_get_ts_info(struct net_device *netdev,
3049 struct ethtool_ts_info *info)
3050{
3051 struct macb *bp = netdev_priv(netdev);
3052
3053 if (bp->ptp_info)
3054 return bp->ptp_info->get_ts_info(netdev, info);
3055
3056 return ethtool_op_get_ts_info(netdev, info);
3057}
3058
3059static void gem_enable_flow_filters(struct macb *bp, bool enable)
3060{
3061 struct net_device *netdev = bp->dev;
3062 struct ethtool_rx_fs_item *item;
3063 u32 t2_scr;
3064 int num_t2_scr;
3065
3066 if (!(netdev->features & NETIF_F_NTUPLE))
3067 return;
3068
3069 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
3070
3071 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3072 struct ethtool_rx_flow_spec *fs = &item->fs;
3073 struct ethtool_tcpip4_spec *tp4sp_m;
3074
3075 if (fs->location >= num_t2_scr)
3076 continue;
3077
3078 t2_scr = gem_readl_n(bp, SCRT2, fs->location);
3079
3080 /* enable/disable screener regs for the flow entry */
3081 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
3082
3083 /* only enable fields with no masking */
3084 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3085
3086 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
3087 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
3088 else
3089 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
3090
3091 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
3092 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
3093 else
3094 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
3095
3096 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
3097 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
3098 else
3099 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
3100
3101 gem_writel_n(bp, SCRT2, fs->location, t2_scr);
3102 }
3103}
3104
3105static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
3106{
3107 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
3108 uint16_t index = fs->location;
3109 u32 w0, w1, t2_scr;
3110 bool cmp_a = false;
3111 bool cmp_b = false;
3112 bool cmp_c = false;
3113
3114 tp4sp_v = &(fs->h_u.tcp_ip4_spec);
3115 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3116
3117 /* ignore field if any masking set */
3118 if (tp4sp_m->ip4src == 0xFFFFFFFF) {
3119 /* 1st compare reg - IP source address */
3120 w0 = 0;
3121 w1 = 0;
3122 w0 = tp4sp_v->ip4src;
3123 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3124 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3125 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
3126 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
3127 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
3128 cmp_a = true;
3129 }
3130
3131 /* ignore field if any masking set */
3132 if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
3133 /* 2nd compare reg - IP destination address */
3134 w0 = 0;
3135 w1 = 0;
3136 w0 = tp4sp_v->ip4dst;
3137 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3138 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3139 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
3140 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
3141 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
3142 cmp_b = true;
3143 }
3144
3145 /* ignore both port fields if masking set in both */
3146 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
3147 /* 3rd compare reg - source port, destination port */
3148 w0 = 0;
3149 w1 = 0;
3150 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
3151 if (tp4sp_m->psrc == tp4sp_m->pdst) {
3152 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
3153 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3154 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3155 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3156 } else {
3157 /* only one port definition */
3158 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
3159 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
3160 if (tp4sp_m->psrc == 0xFFFF) { /* src port */
3161 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
3162 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3163 } else { /* dst port */
3164 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3165 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
3166 }
3167 }
3168 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
3169 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
3170 cmp_c = true;
3171 }
3172
3173 t2_scr = 0;
3174 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
3175 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
3176 if (cmp_a)
3177 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
3178 if (cmp_b)
3179 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
3180 if (cmp_c)
3181 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
3182 gem_writel_n(bp, SCRT2, index, t2_scr);
3183}
3184
3185static int gem_add_flow_filter(struct net_device *netdev,
3186 struct ethtool_rxnfc *cmd)
3187{
3188 struct macb *bp = netdev_priv(netdev);
3189 struct ethtool_rx_flow_spec *fs = &cmd->fs;
3190 struct ethtool_rx_fs_item *item, *newfs;
3191 unsigned long flags;
3192 int ret = -EINVAL;
3193 bool added = false;
3194
3195 newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
3196 if (newfs == NULL)
3197 return -ENOMEM;
3198 memcpy(&newfs->fs, fs, sizeof(newfs->fs));
3199
3200 netdev_dbg(netdev,
3201 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3202 fs->flow_type, (int)fs->ring_cookie, fs->location,
3203 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3204 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3205 htons(fs->h_u.tcp_ip4_spec.psrc), htons(fs->h_u.tcp_ip4_spec.pdst));
3206
3207 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3208
3209 /* find correct place to add in list */
3210 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3211 if (item->fs.location > newfs->fs.location) {
3212 list_add_tail(&newfs->list, &item->list);
3213 added = true;
3214 break;
3215 } else if (item->fs.location == fs->location) {
3216 netdev_err(netdev, "Rule not added: location %d not free!\n",
3217 fs->location);
3218 ret = -EBUSY;
3219 goto err;
3220 }
3221 }
3222 if (!added)
3223 list_add_tail(&newfs->list, &bp->rx_fs_list.list);
3224
3225 gem_prog_cmp_regs(bp, fs);
3226 bp->rx_fs_list.count++;
3227 /* enable filtering if NTUPLE on */
3228 gem_enable_flow_filters(bp, 1);
3229
3230 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3231 return 0;
3232
3233err:
3234 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3235 kfree(newfs);
3236 return ret;
3237}
3238
3239static int gem_del_flow_filter(struct net_device *netdev,
3240 struct ethtool_rxnfc *cmd)
3241{
3242 struct macb *bp = netdev_priv(netdev);
3243 struct ethtool_rx_fs_item *item;
3244 struct ethtool_rx_flow_spec *fs;
3245 unsigned long flags;
3246
3247 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3248
3249 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3250 if (item->fs.location == cmd->fs.location) {
3251 /* disable screener regs for the flow entry */
3252 fs = &(item->fs);
3253 netdev_dbg(netdev,
3254 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3255 fs->flow_type, (int)fs->ring_cookie, fs->location,
3256 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3257 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3258 htons(fs->h_u.tcp_ip4_spec.psrc),
3259 htons(fs->h_u.tcp_ip4_spec.pdst));
3260
3261 gem_writel_n(bp, SCRT2, fs->location, 0);
3262
3263 list_del(&item->list);
3264 bp->rx_fs_list.count--;
3265 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3266 kfree(item);
3267 return 0;
3268 }
3269 }
3270
3271 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3272 return -EINVAL;
3273}
3274
3275static int gem_get_flow_entry(struct net_device *netdev,
3276 struct ethtool_rxnfc *cmd)
3277{
3278 struct macb *bp = netdev_priv(netdev);
3279 struct ethtool_rx_fs_item *item;
3280
3281 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3282 if (item->fs.location == cmd->fs.location) {
3283 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
3284 return 0;
3285 }
3286 }
3287 return -EINVAL;
3288}
3289
3290static int gem_get_all_flow_entries(struct net_device *netdev,
3291 struct ethtool_rxnfc *cmd, u32 *rule_locs)
3292{
3293 struct macb *bp = netdev_priv(netdev);
3294 struct ethtool_rx_fs_item *item;
3295 uint32_t cnt = 0;
3296
3297 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3298 if (cnt == cmd->rule_cnt)
3299 return -EMSGSIZE;
3300 rule_locs[cnt] = item->fs.location;
3301 cnt++;
3302 }
3303 cmd->data = bp->max_tuples;
3304 cmd->rule_cnt = cnt;
3305
3306 return 0;
3307}
3308
3309static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3310 u32 *rule_locs)
3311{
3312 struct macb *bp = netdev_priv(netdev);
3313 int ret = 0;
3314
3315 switch (cmd->cmd) {
3316 case ETHTOOL_GRXRINGS:
3317 cmd->data = bp->num_queues;
3318 break;
3319 case ETHTOOL_GRXCLSRLCNT:
3320 cmd->rule_cnt = bp->rx_fs_list.count;
3321 break;
3322 case ETHTOOL_GRXCLSRULE:
3323 ret = gem_get_flow_entry(netdev, cmd);
3324 break;
3325 case ETHTOOL_GRXCLSRLALL:
3326 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
3327 break;
3328 default:
3329 netdev_err(netdev,
3330 "Command parameter %d is not supported\n", cmd->cmd);
3331 ret = -EOPNOTSUPP;
3332 }
3333
3334 return ret;
3335}
3336
3337static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
3338{
3339 struct macb *bp = netdev_priv(netdev);
3340 int ret;
3341
3342 switch (cmd->cmd) {
3343 case ETHTOOL_SRXCLSRLINS:
3344 if ((cmd->fs.location >= bp->max_tuples)
3345 || (cmd->fs.ring_cookie >= bp->num_queues)) {
3346 ret = -EINVAL;
3347 break;
3348 }
3349 ret = gem_add_flow_filter(netdev, cmd);
3350 break;
3351 case ETHTOOL_SRXCLSRLDEL:
3352 ret = gem_del_flow_filter(netdev, cmd);
3353 break;
3354 default:
3355 netdev_err(netdev,
3356 "Command parameter %d is not supported\n", cmd->cmd);
3357 ret = -EOPNOTSUPP;
3358 }
3359
3360 return ret;
3361}
3362
3363static const struct ethtool_ops macb_ethtool_ops = {
3364 .get_regs_len = macb_get_regs_len,
3365 .get_regs = macb_get_regs,
3366 .get_link = ethtool_op_get_link,
3367 .get_ts_info = ethtool_op_get_ts_info,
3368 .get_wol = macb_get_wol,
3369 .set_wol = macb_set_wol,
3370 .get_link_ksettings = macb_get_link_ksettings,
3371 .set_link_ksettings = macb_set_link_ksettings,
3372 .get_ringparam = macb_get_ringparam,
3373 .set_ringparam = macb_set_ringparam,
3374};
3375
3376static const struct ethtool_ops gem_ethtool_ops = {
3377 .get_regs_len = macb_get_regs_len,
3378 .get_regs = macb_get_regs,
3379 .get_wol = macb_get_wol,
3380 .set_wol = macb_set_wol,
3381 .get_link = ethtool_op_get_link,
3382 .get_ts_info = macb_get_ts_info,
3383 .get_ethtool_stats = gem_get_ethtool_stats,
3384 .get_strings = gem_get_ethtool_strings,
3385 .get_sset_count = gem_get_sset_count,
3386 .get_link_ksettings = macb_get_link_ksettings,
3387 .set_link_ksettings = macb_set_link_ksettings,
3388 .get_ringparam = macb_get_ringparam,
3389 .set_ringparam = macb_set_ringparam,
3390 .get_rxnfc = gem_get_rxnfc,
3391 .set_rxnfc = gem_set_rxnfc,
3392};
3393
3394static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3395{
3396 struct macb *bp = netdev_priv(dev);
3397
3398 if (!netif_running(dev))
3399 return -EINVAL;
3400
3401 if (bp->ptp_info) {
3402 switch (cmd) {
3403 case SIOCSHWTSTAMP:
3404 return bp->ptp_info->set_hwtst(dev, rq, cmd);
3405 case SIOCGHWTSTAMP:
3406 return bp->ptp_info->get_hwtst(dev, rq);
3407 }
3408 }
3409
3410 return phylink_mii_ioctl(bp->phylink, rq, cmd);
3411}
3412
3413static inline void macb_set_txcsum_feature(struct macb *bp,
3414 netdev_features_t features)
3415{
3416 u32 val;
3417
3418 if (!macb_is_gem(bp))
3419 return;
3420
3421 val = gem_readl(bp, DMACFG);
3422 if (features & NETIF_F_HW_CSUM)
3423 val |= GEM_BIT(TXCOEN);
3424 else
3425 val &= ~GEM_BIT(TXCOEN);
3426
3427 gem_writel(bp, DMACFG, val);
3428}
3429
3430static inline void macb_set_rxcsum_feature(struct macb *bp,
3431 netdev_features_t features)
3432{
3433 struct net_device *netdev = bp->dev;
3434 u32 val;
3435
3436 if (!macb_is_gem(bp))
3437 return;
3438
3439 val = gem_readl(bp, NCFGR);
3440 if ((features & NETIF_F_RXCSUM) && !(netdev->flags & IFF_PROMISC))
3441 val |= GEM_BIT(RXCOEN);
3442 else
3443 val &= ~GEM_BIT(RXCOEN);
3444
3445 gem_writel(bp, NCFGR, val);
3446}
3447
3448static inline void macb_set_rxflow_feature(struct macb *bp,
3449 netdev_features_t features)
3450{
3451 if (!macb_is_gem(bp))
3452 return;
3453
3454 gem_enable_flow_filters(bp, !!(features & NETIF_F_NTUPLE));
3455}
3456
3457static int macb_set_features(struct net_device *netdev,
3458 netdev_features_t features)
3459{
3460 struct macb *bp = netdev_priv(netdev);
3461 netdev_features_t changed = features ^ netdev->features;
3462
3463 /* TX checksum offload */
3464 if (changed & NETIF_F_HW_CSUM)
3465 macb_set_txcsum_feature(bp, features);
3466
3467 /* RX checksum offload */
3468 if (changed & NETIF_F_RXCSUM)
3469 macb_set_rxcsum_feature(bp, features);
3470
3471 /* RX Flow Filters */
3472 if (changed & NETIF_F_NTUPLE)
3473 macb_set_rxflow_feature(bp, features);
3474
3475 return 0;
3476}
3477
3478static void macb_restore_features(struct macb *bp)
3479{
3480 struct net_device *netdev = bp->dev;
3481 netdev_features_t features = netdev->features;
3482
3483 /* TX checksum offload */
3484 macb_set_txcsum_feature(bp, features);
3485
3486 /* RX checksum offload */
3487 macb_set_rxcsum_feature(bp, features);
3488
3489 /* RX Flow Filters */
3490 macb_set_rxflow_feature(bp, features);
3491}
3492
3493static const struct net_device_ops macb_netdev_ops = {
3494 .ndo_open = macb_open,
3495 .ndo_stop = macb_close,
3496 .ndo_start_xmit = macb_start_xmit,
3497 .ndo_set_rx_mode = macb_set_rx_mode,
3498 .ndo_get_stats = macb_get_stats,
3499 .ndo_do_ioctl = macb_ioctl,
3500 .ndo_validate_addr = eth_validate_addr,
3501 .ndo_change_mtu = macb_change_mtu,
3502 .ndo_set_mac_address = eth_mac_addr,
3503#ifdef CONFIG_NET_POLL_CONTROLLER
3504 .ndo_poll_controller = macb_poll_controller,
3505#endif
3506 .ndo_set_features = macb_set_features,
3507 .ndo_features_check = macb_features_check,
3508};
3509
3510/* Configure peripheral capabilities according to device tree
3511 * and integration options used
3512 */
3513static void macb_configure_caps(struct macb *bp,
3514 const struct macb_config *dt_conf)
3515{
3516 u32 dcfg;
3517
3518 if (dt_conf)
3519 bp->caps = dt_conf->caps;
3520
3521 if (hw_is_gem(bp->regs, bp->native_io)) {
3522 bp->caps |= MACB_CAPS_MACB_IS_GEM;
3523
3524 dcfg = gem_readl(bp, DCFG1);
3525 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
3526 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
3527 dcfg = gem_readl(bp, DCFG2);
3528 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
3529 bp->caps |= MACB_CAPS_FIFO_MODE;
3530#ifdef CONFIG_MACB_USE_HWSTAMP
3531 if (gem_has_ptp(bp)) {
3532 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
3533 dev_err(&bp->pdev->dev,
3534 "GEM doesn't support hardware ptp.\n");
3535 else {
3536 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
3537 bp->ptp_info = &gem_ptp_info;
3538 }
3539 }
3540#endif
3541 }
3542
3543 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
3544}
3545
3546static void macb_probe_queues(void __iomem *mem,
3547 bool native_io,
3548 unsigned int *queue_mask,
3549 unsigned int *num_queues)
3550{
3551 *queue_mask = 0x1;
3552 *num_queues = 1;
3553
3554 /* is it macb or gem ?
3555 *
3556 * We need to read directly from the hardware here because
3557 * we are early in the probe process and don't have the
3558 * MACB_CAPS_MACB_IS_GEM flag positioned
3559 */
3560 if (!hw_is_gem(mem, native_io))
3561 return;
3562
3563 /* bit 0 is never set but queue 0 always exists */
3564 *queue_mask |= readl_relaxed(mem + GEM_DCFG6) & 0xff;
3565 *num_queues = hweight32(*queue_mask);
3566}
3567
3568static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
3569 struct clk **hclk, struct clk **tx_clk,
3570 struct clk **rx_clk, struct clk **tsu_clk)
3571{
3572 struct macb_platform_data *pdata;
3573 int err;
3574
3575 pdata = dev_get_platdata(&pdev->dev);
3576 if (pdata) {
3577 *pclk = pdata->pclk;
3578 *hclk = pdata->hclk;
3579 } else {
3580 *pclk = devm_clk_get(&pdev->dev, "pclk");
3581 *hclk = devm_clk_get(&pdev->dev, "hclk");
3582 }
3583
3584 if (IS_ERR_OR_NULL(*pclk)) {
3585 err = PTR_ERR(*pclk);
3586 if (!err)
3587 err = -ENODEV;
3588
3589 dev_err(&pdev->dev, "failed to get macb_clk (%d)\n", err);
3590 return err;
3591 }
3592
3593 if (IS_ERR_OR_NULL(*hclk)) {
3594 err = PTR_ERR(*hclk);
3595 if (!err)
3596 err = -ENODEV;
3597
3598 dev_err(&pdev->dev, "failed to get hclk (%d)\n", err);
3599 return err;
3600 }
3601
3602 *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk");
3603 if (IS_ERR(*tx_clk))
3604 return PTR_ERR(*tx_clk);
3605
3606 *rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk");
3607 if (IS_ERR(*rx_clk))
3608 return PTR_ERR(*rx_clk);
3609
3610 *tsu_clk = devm_clk_get_optional(&pdev->dev, "tsu_clk");
3611 if (IS_ERR(*tsu_clk))
3612 return PTR_ERR(*tsu_clk);
3613
3614 err = clk_prepare_enable(*pclk);
3615 if (err) {
3616 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
3617 return err;
3618 }
3619
3620 err = clk_prepare_enable(*hclk);
3621 if (err) {
3622 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
3623 goto err_disable_pclk;
3624 }
3625
3626 err = clk_prepare_enable(*tx_clk);
3627 if (err) {
3628 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
3629 goto err_disable_hclk;
3630 }
3631
3632 err = clk_prepare_enable(*rx_clk);
3633 if (err) {
3634 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
3635 goto err_disable_txclk;
3636 }
3637
3638 err = clk_prepare_enable(*tsu_clk);
3639 if (err) {
3640 dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err);
3641 goto err_disable_rxclk;
3642 }
3643
3644 return 0;
3645
3646err_disable_rxclk:
3647 clk_disable_unprepare(*rx_clk);
3648
3649err_disable_txclk:
3650 clk_disable_unprepare(*tx_clk);
3651
3652err_disable_hclk:
3653 clk_disable_unprepare(*hclk);
3654
3655err_disable_pclk:
3656 clk_disable_unprepare(*pclk);
3657
3658 return err;
3659}
3660
3661static int macb_init(struct platform_device *pdev)
3662{
3663 struct net_device *dev = platform_get_drvdata(pdev);
3664 unsigned int hw_q, q;
3665 struct macb *bp = netdev_priv(dev);
3666 struct macb_queue *queue;
3667 int err;
3668 u32 val, reg;
3669
3670 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
3671 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
3672
3673 /* set the queue register mapping once for all: queue0 has a special
3674 * register mapping but we don't want to test the queue index then
3675 * compute the corresponding register offset at run time.
3676 */
3677 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
3678 if (!(bp->queue_mask & (1 << hw_q)))
3679 continue;
3680
3681 queue = &bp->queues[q];
3682 queue->bp = bp;
3683 netif_napi_add(dev, &queue->napi, macb_poll, NAPI_POLL_WEIGHT);
3684 if (hw_q) {
3685 queue->ISR = GEM_ISR(hw_q - 1);
3686 queue->IER = GEM_IER(hw_q - 1);
3687 queue->IDR = GEM_IDR(hw_q - 1);
3688 queue->IMR = GEM_IMR(hw_q - 1);
3689 queue->TBQP = GEM_TBQP(hw_q - 1);
3690 queue->RBQP = GEM_RBQP(hw_q - 1);
3691 queue->RBQS = GEM_RBQS(hw_q - 1);
3692#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3693 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3694 queue->TBQPH = GEM_TBQPH(hw_q - 1);
3695 queue->RBQPH = GEM_RBQPH(hw_q - 1);
3696 }
3697#endif
3698 } else {
3699 /* queue0 uses legacy registers */
3700 queue->ISR = MACB_ISR;
3701 queue->IER = MACB_IER;
3702 queue->IDR = MACB_IDR;
3703 queue->IMR = MACB_IMR;
3704 queue->TBQP = MACB_TBQP;
3705 queue->RBQP = MACB_RBQP;
3706#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3707 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3708 queue->TBQPH = MACB_TBQPH;
3709 queue->RBQPH = MACB_RBQPH;
3710 }
3711#endif
3712 }
3713
3714 /* get irq: here we use the linux queue index, not the hardware
3715 * queue index. the queue irq definitions in the device tree
3716 * must remove the optional gaps that could exist in the
3717 * hardware queue mask.
3718 */
3719 queue->irq = platform_get_irq(pdev, q);
3720 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
3721 IRQF_SHARED, dev->name, queue);
3722 if (err) {
3723 dev_err(&pdev->dev,
3724 "Unable to request IRQ %d (error %d)\n",
3725 queue->irq, err);
3726 return err;
3727 }
3728
3729 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
3730 q++;
3731 }
3732
3733 dev->netdev_ops = &macb_netdev_ops;
3734
3735 /* setup appropriated routines according to adapter type */
3736 if (macb_is_gem(bp)) {
3737 bp->max_tx_length = GEM_MAX_TX_LEN;
3738 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
3739 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
3740 bp->macbgem_ops.mog_init_rings = gem_init_rings;
3741 bp->macbgem_ops.mog_rx = gem_rx;
3742 dev->ethtool_ops = &gem_ethtool_ops;
3743 } else {
3744 bp->max_tx_length = MACB_MAX_TX_LEN;
3745 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
3746 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
3747 bp->macbgem_ops.mog_init_rings = macb_init_rings;
3748 bp->macbgem_ops.mog_rx = macb_rx;
3749 dev->ethtool_ops = &macb_ethtool_ops;
3750 }
3751
3752 /* Set features */
3753 dev->hw_features = NETIF_F_SG;
3754
3755 /* Check LSO capability */
3756 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
3757 dev->hw_features |= MACB_NETIF_LSO;
3758
3759 /* Checksum offload is only available on gem with packet buffer */
3760 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
3761 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
3762 if (bp->caps & MACB_CAPS_SG_DISABLED)
3763 dev->hw_features &= ~NETIF_F_SG;
3764 dev->features = dev->hw_features;
3765
3766 /* Check RX Flow Filters support.
3767 * Max Rx flows set by availability of screeners & compare regs:
3768 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
3769 */
3770 reg = gem_readl(bp, DCFG8);
3771 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
3772 GEM_BFEXT(T2SCR, reg));
3773 if (bp->max_tuples > 0) {
3774 /* also needs one ethtype match to check IPv4 */
3775 if (GEM_BFEXT(SCR2ETH, reg) > 0) {
3776 /* program this reg now */
3777 reg = 0;
3778 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
3779 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
3780 /* Filtering is supported in hw but don't enable it in kernel now */
3781 dev->hw_features |= NETIF_F_NTUPLE;
3782 /* init Rx flow definitions */
3783 INIT_LIST_HEAD(&bp->rx_fs_list.list);
3784 bp->rx_fs_list.count = 0;
3785 spin_lock_init(&bp->rx_fs_lock);
3786 } else
3787 bp->max_tuples = 0;
3788 }
3789
3790 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
3791 val = 0;
3792 if (phy_interface_mode_is_rgmii(bp->phy_interface))
3793 val = GEM_BIT(RGMII);
3794 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
3795 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3796 val = MACB_BIT(RMII);
3797 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3798 val = MACB_BIT(MII);
3799
3800 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
3801 val |= MACB_BIT(CLKEN);
3802
3803 macb_or_gem_writel(bp, USRIO, val);
3804 }
3805
3806 /* Set MII management clock divider */
3807 val = macb_mdc_clk_div(bp);
3808 val |= macb_dbw(bp);
3809 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
3810 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
3811 macb_writel(bp, NCFGR, val);
3812
3813 return 0;
3814}
3815
3816#if defined(CONFIG_OF)
3817/* 1518 rounded up */
3818#define AT91ETHER_MAX_RBUFF_SZ 0x600
3819/* max number of receive buffers */
3820#define AT91ETHER_MAX_RX_DESCR 9
3821
3822static struct sifive_fu540_macb_mgmt *mgmt;
3823
3824static int at91ether_alloc_coherent(struct macb *lp)
3825{
3826 struct macb_queue *q = &lp->queues[0];
3827
3828 q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
3829 (AT91ETHER_MAX_RX_DESCR *
3830 macb_dma_desc_get_size(lp)),
3831 &q->rx_ring_dma, GFP_KERNEL);
3832 if (!q->rx_ring)
3833 return -ENOMEM;
3834
3835 q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
3836 AT91ETHER_MAX_RX_DESCR *
3837 AT91ETHER_MAX_RBUFF_SZ,
3838 &q->rx_buffers_dma, GFP_KERNEL);
3839 if (!q->rx_buffers) {
3840 dma_free_coherent(&lp->pdev->dev,
3841 AT91ETHER_MAX_RX_DESCR *
3842 macb_dma_desc_get_size(lp),
3843 q->rx_ring, q->rx_ring_dma);
3844 q->rx_ring = NULL;
3845 return -ENOMEM;
3846 }
3847
3848 return 0;
3849}
3850
3851static void at91ether_free_coherent(struct macb *lp)
3852{
3853 struct macb_queue *q = &lp->queues[0];
3854
3855 if (q->rx_ring) {
3856 dma_free_coherent(&lp->pdev->dev,
3857 AT91ETHER_MAX_RX_DESCR *
3858 macb_dma_desc_get_size(lp),
3859 q->rx_ring, q->rx_ring_dma);
3860 q->rx_ring = NULL;
3861 }
3862
3863 if (q->rx_buffers) {
3864 dma_free_coherent(&lp->pdev->dev,
3865 AT91ETHER_MAX_RX_DESCR *
3866 AT91ETHER_MAX_RBUFF_SZ,
3867 q->rx_buffers, q->rx_buffers_dma);
3868 q->rx_buffers = NULL;
3869 }
3870}
3871
3872/* Initialize and start the Receiver and Transmit subsystems */
3873static int at91ether_start(struct macb *lp)
3874{
3875 struct macb_queue *q = &lp->queues[0];
3876 struct macb_dma_desc *desc;
3877 dma_addr_t addr;
3878 u32 ctl;
3879 int i, ret;
3880
3881 ret = at91ether_alloc_coherent(lp);
3882 if (ret)
3883 return ret;
3884
3885 addr = q->rx_buffers_dma;
3886 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
3887 desc = macb_rx_desc(q, i);
3888 macb_set_addr(lp, desc, addr);
3889 desc->ctrl = 0;
3890 addr += AT91ETHER_MAX_RBUFF_SZ;
3891 }
3892
3893 /* Set the Wrap bit on the last descriptor */
3894 desc->addr |= MACB_BIT(RX_WRAP);
3895
3896 /* Reset buffer index */
3897 q->rx_tail = 0;
3898
3899 /* Program address of descriptor list in Rx Buffer Queue register */
3900 macb_writel(lp, RBQP, q->rx_ring_dma);
3901
3902 /* Enable Receive and Transmit */
3903 ctl = macb_readl(lp, NCR);
3904 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
3905
3906 /* Enable MAC interrupts */
3907 macb_writel(lp, IER, MACB_BIT(RCOMP) |
3908 MACB_BIT(RXUBR) |
3909 MACB_BIT(ISR_TUND) |
3910 MACB_BIT(ISR_RLE) |
3911 MACB_BIT(TCOMP) |
3912 MACB_BIT(ISR_ROVR) |
3913 MACB_BIT(HRESP));
3914
3915 return 0;
3916}
3917
3918static void at91ether_stop(struct macb *lp)
3919{
3920 u32 ctl;
3921
3922 /* Disable MAC interrupts */
3923 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
3924 MACB_BIT(RXUBR) |
3925 MACB_BIT(ISR_TUND) |
3926 MACB_BIT(ISR_RLE) |
3927 MACB_BIT(TCOMP) |
3928 MACB_BIT(ISR_ROVR) |
3929 MACB_BIT(HRESP));
3930
3931 /* Disable Receiver and Transmitter */
3932 ctl = macb_readl(lp, NCR);
3933 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
3934
3935 /* Free resources. */
3936 at91ether_free_coherent(lp);
3937}
3938
3939/* Open the ethernet interface */
3940static int at91ether_open(struct net_device *dev)
3941{
3942 struct macb *lp = netdev_priv(dev);
3943 u32 ctl;
3944 int ret;
3945
3946 ret = pm_runtime_get_sync(&lp->pdev->dev);
3947 if (ret < 0) {
3948 pm_runtime_put_noidle(&lp->pdev->dev);
3949 return ret;
3950 }
3951
3952 /* Clear internal statistics */
3953 ctl = macb_readl(lp, NCR);
3954 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
3955
3956 macb_set_hwaddr(lp);
3957
3958 ret = at91ether_start(lp);
3959 if (ret)
3960 goto pm_exit;
3961
3962 ret = macb_phylink_connect(lp);
3963 if (ret)
3964 goto stop;
3965
3966 netif_start_queue(dev);
3967
3968 return 0;
3969
3970stop:
3971 at91ether_stop(lp);
3972pm_exit:
3973 pm_runtime_put_sync(&lp->pdev->dev);
3974 return ret;
3975}
3976
3977/* Close the interface */
3978static int at91ether_close(struct net_device *dev)
3979{
3980 struct macb *lp = netdev_priv(dev);
3981
3982 netif_stop_queue(dev);
3983
3984 phylink_stop(lp->phylink);
3985 phylink_disconnect_phy(lp->phylink);
3986
3987 at91ether_stop(lp);
3988
3989 return pm_runtime_put(&lp->pdev->dev);
3990}
3991
3992/* Transmit packet */
3993static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
3994 struct net_device *dev)
3995{
3996 struct macb *lp = netdev_priv(dev);
3997
3998 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
3999 netif_stop_queue(dev);
4000
4001 /* Store packet information (to free when Tx completed) */
4002 lp->skb = skb;
4003 lp->skb_length = skb->len;
4004 lp->skb_physaddr = dma_map_single(&lp->pdev->dev, skb->data,
4005 skb->len, DMA_TO_DEVICE);
4006 if (dma_mapping_error(&lp->pdev->dev, lp->skb_physaddr)) {
4007 dev_kfree_skb_any(skb);
4008 dev->stats.tx_dropped++;
4009 netdev_err(dev, "%s: DMA mapping error\n", __func__);
4010 return NETDEV_TX_OK;
4011 }
4012
4013 /* Set address of the data in the Transmit Address register */
4014 macb_writel(lp, TAR, lp->skb_physaddr);
4015 /* Set length of the packet in the Transmit Control register */
4016 macb_writel(lp, TCR, skb->len);
4017
4018 } else {
4019 netdev_err(dev, "%s called, but device is busy!\n", __func__);
4020 return NETDEV_TX_BUSY;
4021 }
4022
4023 return NETDEV_TX_OK;
4024}
4025
4026/* Extract received frame from buffer descriptors and sent to upper layers.
4027 * (Called from interrupt context)
4028 */
4029static void at91ether_rx(struct net_device *dev)
4030{
4031 struct macb *lp = netdev_priv(dev);
4032 struct macb_queue *q = &lp->queues[0];
4033 struct macb_dma_desc *desc;
4034 unsigned char *p_recv;
4035 struct sk_buff *skb;
4036 unsigned int pktlen;
4037
4038 desc = macb_rx_desc(q, q->rx_tail);
4039 while (desc->addr & MACB_BIT(RX_USED)) {
4040 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
4041 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
4042 skb = netdev_alloc_skb(dev, pktlen + 2);
4043 if (skb) {
4044 skb_reserve(skb, 2);
4045 skb_put_data(skb, p_recv, pktlen);
4046
4047 skb->protocol = eth_type_trans(skb, dev);
4048 dev->stats.rx_packets++;
4049 dev->stats.rx_bytes += pktlen;
4050 netif_rx(skb);
4051 } else {
4052 dev->stats.rx_dropped++;
4053 }
4054
4055 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
4056 dev->stats.multicast++;
4057
4058 /* reset ownership bit */
4059 desc->addr &= ~MACB_BIT(RX_USED);
4060
4061 /* wrap after last buffer */
4062 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
4063 q->rx_tail = 0;
4064 else
4065 q->rx_tail++;
4066
4067 desc = macb_rx_desc(q, q->rx_tail);
4068 }
4069}
4070
4071/* MAC interrupt handler */
4072static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
4073{
4074 struct net_device *dev = dev_id;
4075 struct macb *lp = netdev_priv(dev);
4076 u32 intstatus, ctl;
4077
4078 /* MAC Interrupt Status register indicates what interrupts are pending.
4079 * It is automatically cleared once read.
4080 */
4081 intstatus = macb_readl(lp, ISR);
4082
4083 /* Receive complete */
4084 if (intstatus & MACB_BIT(RCOMP))
4085 at91ether_rx(dev);
4086
4087 /* Transmit complete */
4088 if (intstatus & MACB_BIT(TCOMP)) {
4089 /* The TCOM bit is set even if the transmission failed */
4090 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
4091 dev->stats.tx_errors++;
4092
4093 if (lp->skb) {
4094 dev_consume_skb_irq(lp->skb);
4095 lp->skb = NULL;
4096 dma_unmap_single(&lp->pdev->dev, lp->skb_physaddr,
4097 lp->skb_length, DMA_TO_DEVICE);
4098 dev->stats.tx_packets++;
4099 dev->stats.tx_bytes += lp->skb_length;
4100 }
4101 netif_wake_queue(dev);
4102 }
4103
4104 /* Work-around for EMAC Errata section 41.3.1 */
4105 if (intstatus & MACB_BIT(RXUBR)) {
4106 ctl = macb_readl(lp, NCR);
4107 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
4108 wmb();
4109 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
4110 }
4111
4112 if (intstatus & MACB_BIT(ISR_ROVR))
4113 netdev_err(dev, "ROVR error\n");
4114
4115 return IRQ_HANDLED;
4116}
4117
4118#ifdef CONFIG_NET_POLL_CONTROLLER
4119static void at91ether_poll_controller(struct net_device *dev)
4120{
4121 unsigned long flags;
4122
4123 local_irq_save(flags);
4124 at91ether_interrupt(dev->irq, dev);
4125 local_irq_restore(flags);
4126}
4127#endif
4128
4129static const struct net_device_ops at91ether_netdev_ops = {
4130 .ndo_open = at91ether_open,
4131 .ndo_stop = at91ether_close,
4132 .ndo_start_xmit = at91ether_start_xmit,
4133 .ndo_get_stats = macb_get_stats,
4134 .ndo_set_rx_mode = macb_set_rx_mode,
4135 .ndo_set_mac_address = eth_mac_addr,
4136 .ndo_do_ioctl = macb_ioctl,
4137 .ndo_validate_addr = eth_validate_addr,
4138#ifdef CONFIG_NET_POLL_CONTROLLER
4139 .ndo_poll_controller = at91ether_poll_controller,
4140#endif
4141};
4142
4143static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
4144 struct clk **hclk, struct clk **tx_clk,
4145 struct clk **rx_clk, struct clk **tsu_clk)
4146{
4147 int err;
4148
4149 *hclk = NULL;
4150 *tx_clk = NULL;
4151 *rx_clk = NULL;
4152 *tsu_clk = NULL;
4153
4154 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
4155 if (IS_ERR(*pclk))
4156 return PTR_ERR(*pclk);
4157
4158 err = clk_prepare_enable(*pclk);
4159 if (err) {
4160 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
4161 return err;
4162 }
4163
4164 return 0;
4165}
4166
4167static int at91ether_init(struct platform_device *pdev)
4168{
4169 struct net_device *dev = platform_get_drvdata(pdev);
4170 struct macb *bp = netdev_priv(dev);
4171 int err;
4172
4173 bp->queues[0].bp = bp;
4174
4175 dev->netdev_ops = &at91ether_netdev_ops;
4176 dev->ethtool_ops = &macb_ethtool_ops;
4177
4178 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
4179 0, dev->name, dev);
4180 if (err)
4181 return err;
4182
4183 macb_writel(bp, NCR, 0);
4184
4185 macb_writel(bp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG));
4186
4187 return 0;
4188}
4189
4190static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw,
4191 unsigned long parent_rate)
4192{
4193 return mgmt->rate;
4194}
4195
4196static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate,
4197 unsigned long *parent_rate)
4198{
4199 if (WARN_ON(rate < 2500000))
4200 return 2500000;
4201 else if (rate == 2500000)
4202 return 2500000;
4203 else if (WARN_ON(rate < 13750000))
4204 return 2500000;
4205 else if (WARN_ON(rate < 25000000))
4206 return 25000000;
4207 else if (rate == 25000000)
4208 return 25000000;
4209 else if (WARN_ON(rate < 75000000))
4210 return 25000000;
4211 else if (WARN_ON(rate < 125000000))
4212 return 125000000;
4213 else if (rate == 125000000)
4214 return 125000000;
4215
4216 WARN_ON(rate > 125000000);
4217
4218 return 125000000;
4219}
4220
4221static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
4222 unsigned long parent_rate)
4223{
4224 rate = fu540_macb_tx_round_rate(hw, rate, &parent_rate);
4225 if (rate != 125000000)
4226 iowrite32(1, mgmt->reg);
4227 else
4228 iowrite32(0, mgmt->reg);
4229 mgmt->rate = rate;
4230
4231 return 0;
4232}
4233
4234static const struct clk_ops fu540_c000_ops = {
4235 .recalc_rate = fu540_macb_tx_recalc_rate,
4236 .round_rate = fu540_macb_tx_round_rate,
4237 .set_rate = fu540_macb_tx_set_rate,
4238};
4239
4240static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
4241 struct clk **hclk, struct clk **tx_clk,
4242 struct clk **rx_clk, struct clk **tsu_clk)
4243{
4244 struct clk_init_data init;
4245 int err = 0;
4246
4247 err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk);
4248 if (err)
4249 return err;
4250
4251 mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL);
4252 if (!mgmt)
4253 return -ENOMEM;
4254
4255 init.name = "sifive-gemgxl-mgmt";
4256 init.ops = &fu540_c000_ops;
4257 init.flags = 0;
4258 init.num_parents = 0;
4259
4260 mgmt->rate = 0;
4261 mgmt->hw.init = &init;
4262
4263 *tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw);
4264 if (IS_ERR(*tx_clk))
4265 return PTR_ERR(*tx_clk);
4266
4267 err = clk_prepare_enable(*tx_clk);
4268 if (err)
4269 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
4270 else
4271 dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name);
4272
4273 return 0;
4274}
4275
4276static int fu540_c000_init(struct platform_device *pdev)
4277{
4278 mgmt->reg = devm_platform_ioremap_resource(pdev, 1);
4279 if (IS_ERR(mgmt->reg))
4280 return PTR_ERR(mgmt->reg);
4281
4282 return macb_init(pdev);
4283}
4284
4285static const struct macb_config fu540_c000_config = {
4286 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
4287 MACB_CAPS_GEM_HAS_PTP,
4288 .dma_burst_length = 16,
4289 .clk_init = fu540_c000_clk_init,
4290 .init = fu540_c000_init,
4291 .jumbo_max_len = 10240,
4292};
4293
4294static const struct macb_config at91sam9260_config = {
4295 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4296 .clk_init = macb_clk_init,
4297 .init = macb_init,
4298};
4299
4300static const struct macb_config sama5d3macb_config = {
4301 .caps = MACB_CAPS_SG_DISABLED
4302 | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4303 .clk_init = macb_clk_init,
4304 .init = macb_init,
4305};
4306
4307static const struct macb_config pc302gem_config = {
4308 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
4309 .dma_burst_length = 16,
4310 .clk_init = macb_clk_init,
4311 .init = macb_init,
4312};
4313
4314static const struct macb_config sama5d2_config = {
4315 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4316 .dma_burst_length = 16,
4317 .clk_init = macb_clk_init,
4318 .init = macb_init,
4319};
4320
4321static const struct macb_config sama5d3_config = {
4322 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
4323 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
4324 .dma_burst_length = 16,
4325 .clk_init = macb_clk_init,
4326 .init = macb_init,
4327 .jumbo_max_len = 10240,
4328};
4329
4330static const struct macb_config sama5d4_config = {
4331 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4332 .dma_burst_length = 4,
4333 .clk_init = macb_clk_init,
4334 .init = macb_init,
4335};
4336
4337static const struct macb_config emac_config = {
4338 .caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC,
4339 .clk_init = at91ether_clk_init,
4340 .init = at91ether_init,
4341};
4342
4343static const struct macb_config np4_config = {
4344 .caps = MACB_CAPS_USRIO_DISABLED,
4345 .clk_init = macb_clk_init,
4346 .init = macb_init,
4347};
4348
4349static const struct macb_config zynqmp_config = {
4350 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4351 MACB_CAPS_JUMBO |
4352 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
4353 .dma_burst_length = 16,
4354 .clk_init = macb_clk_init,
4355 .init = macb_init,
4356 .jumbo_max_len = 10240,
4357};
4358
4359static const struct macb_config zynq_config = {
4360 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF |
4361 MACB_CAPS_NEEDS_RSTONUBR,
4362 .dma_burst_length = 16,
4363 .clk_init = macb_clk_init,
4364 .init = macb_init,
4365};
4366
4367static const struct of_device_id macb_dt_ids[] = {
4368 { .compatible = "cdns,at32ap7000-macb" },
4369 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
4370 { .compatible = "cdns,macb" },
4371 { .compatible = "cdns,np4-macb", .data = &np4_config },
4372 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
4373 { .compatible = "cdns,gem", .data = &pc302gem_config },
4374 { .compatible = "cdns,sam9x60-macb", .data = &at91sam9260_config },
4375 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
4376 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
4377 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
4378 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
4379 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
4380 { .compatible = "cdns,emac", .data = &emac_config },
4381 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
4382 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
4383 { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
4384 { /* sentinel */ }
4385};
4386MODULE_DEVICE_TABLE(of, macb_dt_ids);
4387#endif /* CONFIG_OF */
4388
4389static const struct macb_config default_gem_config = {
4390 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4391 MACB_CAPS_JUMBO |
4392 MACB_CAPS_GEM_HAS_PTP,
4393 .dma_burst_length = 16,
4394 .clk_init = macb_clk_init,
4395 .init = macb_init,
4396 .jumbo_max_len = 10240,
4397};
4398
4399static int macb_probe(struct platform_device *pdev)
4400{
4401 const struct macb_config *macb_config = &default_gem_config;
4402 int (*clk_init)(struct platform_device *, struct clk **,
4403 struct clk **, struct clk **, struct clk **,
4404 struct clk **) = macb_config->clk_init;
4405 int (*init)(struct platform_device *) = macb_config->init;
4406 struct device_node *np = pdev->dev.of_node;
4407 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
4408 struct clk *tsu_clk = NULL;
4409 unsigned int queue_mask, num_queues;
4410 bool native_io;
4411 phy_interface_t interface;
4412 struct net_device *dev;
4413 struct resource *regs;
4414 void __iomem *mem;
4415 const char *mac;
4416 struct macb *bp;
4417 int err, val;
4418
4419 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4420 mem = devm_ioremap_resource(&pdev->dev, regs);
4421 if (IS_ERR(mem))
4422 return PTR_ERR(mem);
4423
4424 if (np) {
4425 const struct of_device_id *match;
4426
4427 match = of_match_node(macb_dt_ids, np);
4428 if (match && match->data) {
4429 macb_config = match->data;
4430 clk_init = macb_config->clk_init;
4431 init = macb_config->init;
4432 }
4433 }
4434
4435 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk, &tsu_clk);
4436 if (err)
4437 return err;
4438
4439 pm_runtime_set_autosuspend_delay(&pdev->dev, MACB_PM_TIMEOUT);
4440 pm_runtime_use_autosuspend(&pdev->dev);
4441 pm_runtime_get_noresume(&pdev->dev);
4442 pm_runtime_set_active(&pdev->dev);
4443 pm_runtime_enable(&pdev->dev);
4444 native_io = hw_is_native_io(mem);
4445
4446 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
4447 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
4448 if (!dev) {
4449 err = -ENOMEM;
4450 goto err_disable_clocks;
4451 }
4452
4453 dev->base_addr = regs->start;
4454
4455 SET_NETDEV_DEV(dev, &pdev->dev);
4456
4457 bp = netdev_priv(dev);
4458 bp->pdev = pdev;
4459 bp->dev = dev;
4460 bp->regs = mem;
4461 bp->native_io = native_io;
4462 if (native_io) {
4463 bp->macb_reg_readl = hw_readl_native;
4464 bp->macb_reg_writel = hw_writel_native;
4465 } else {
4466 bp->macb_reg_readl = hw_readl;
4467 bp->macb_reg_writel = hw_writel;
4468 }
4469 bp->num_queues = num_queues;
4470 bp->queue_mask = queue_mask;
4471 if (macb_config)
4472 bp->dma_burst_length = macb_config->dma_burst_length;
4473 bp->pclk = pclk;
4474 bp->hclk = hclk;
4475 bp->tx_clk = tx_clk;
4476 bp->rx_clk = rx_clk;
4477 bp->tsu_clk = tsu_clk;
4478 if (macb_config)
4479 bp->jumbo_max_len = macb_config->jumbo_max_len;
4480
4481 bp->wol = 0;
4482 if (of_get_property(np, "magic-packet", NULL))
4483 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
4484 device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
4485
4486 spin_lock_init(&bp->lock);
4487
4488 /* setup capabilities */
4489 macb_configure_caps(bp, macb_config);
4490
4491#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4492 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
4493 dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
4494 bp->hw_dma_cap |= HW_DMA_CAP_64B;
4495 }
4496#endif
4497 platform_set_drvdata(pdev, dev);
4498
4499 dev->irq = platform_get_irq(pdev, 0);
4500 if (dev->irq < 0) {
4501 err = dev->irq;
4502 goto err_out_free_netdev;
4503 }
4504
4505 /* MTU range: 68 - 1500 or 10240 */
4506 dev->min_mtu = GEM_MTU_MIN_SIZE;
4507 if (bp->caps & MACB_CAPS_JUMBO)
4508 dev->max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
4509 else
4510 dev->max_mtu = ETH_DATA_LEN;
4511
4512 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) {
4513 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10));
4514 if (val)
4515 bp->rx_bd_rd_prefetch = (2 << (val - 1)) *
4516 macb_dma_desc_get_size(bp);
4517
4518 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10));
4519 if (val)
4520 bp->tx_bd_rd_prefetch = (2 << (val - 1)) *
4521 macb_dma_desc_get_size(bp);
4522 }
4523
4524 bp->rx_intr_mask = MACB_RX_INT_FLAGS;
4525 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR)
4526 bp->rx_intr_mask |= MACB_BIT(RXUBR);
4527
4528 mac = of_get_mac_address(np);
4529 if (PTR_ERR(mac) == -EPROBE_DEFER) {
4530 err = -EPROBE_DEFER;
4531 goto err_out_free_netdev;
4532 } else if (!IS_ERR_OR_NULL(mac)) {
4533 ether_addr_copy(bp->dev->dev_addr, mac);
4534 } else {
4535 macb_get_hwaddr(bp);
4536 }
4537
4538 err = of_get_phy_mode(np, &interface);
4539 if (err)
4540 /* not found in DT, MII by default */
4541 bp->phy_interface = PHY_INTERFACE_MODE_MII;
4542 else
4543 bp->phy_interface = interface;
4544
4545 /* IP specific init */
4546 err = init(pdev);
4547 if (err)
4548 goto err_out_free_netdev;
4549
4550 err = macb_mii_init(bp);
4551 if (err)
4552 goto err_out_free_netdev;
4553
4554 netif_carrier_off(dev);
4555
4556 err = register_netdev(dev);
4557 if (err) {
4558 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
4559 goto err_out_unregister_mdio;
4560 }
4561
4562 tasklet_init(&bp->hresp_err_tasklet, macb_hresp_error_task,
4563 (unsigned long)bp);
4564
4565 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
4566 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
4567 dev->base_addr, dev->irq, dev->dev_addr);
4568
4569 pm_runtime_mark_last_busy(&bp->pdev->dev);
4570 pm_runtime_put_autosuspend(&bp->pdev->dev);
4571
4572 return 0;
4573
4574err_out_unregister_mdio:
4575 mdiobus_unregister(bp->mii_bus);
4576 mdiobus_free(bp->mii_bus);
4577
4578err_out_free_netdev:
4579 free_netdev(dev);
4580
4581err_disable_clocks:
4582 clk_disable_unprepare(tx_clk);
4583 clk_disable_unprepare(hclk);
4584 clk_disable_unprepare(pclk);
4585 clk_disable_unprepare(rx_clk);
4586 clk_disable_unprepare(tsu_clk);
4587 pm_runtime_disable(&pdev->dev);
4588 pm_runtime_set_suspended(&pdev->dev);
4589 pm_runtime_dont_use_autosuspend(&pdev->dev);
4590
4591 return err;
4592}
4593
4594static int macb_remove(struct platform_device *pdev)
4595{
4596 struct net_device *dev;
4597 struct macb *bp;
4598
4599 dev = platform_get_drvdata(pdev);
4600
4601 if (dev) {
4602 bp = netdev_priv(dev);
4603 mdiobus_unregister(bp->mii_bus);
4604 mdiobus_free(bp->mii_bus);
4605
4606 unregister_netdev(dev);
4607 tasklet_kill(&bp->hresp_err_tasklet);
4608 pm_runtime_disable(&pdev->dev);
4609 pm_runtime_dont_use_autosuspend(&pdev->dev);
4610 if (!pm_runtime_suspended(&pdev->dev)) {
4611 clk_disable_unprepare(bp->tx_clk);
4612 clk_disable_unprepare(bp->hclk);
4613 clk_disable_unprepare(bp->pclk);
4614 clk_disable_unprepare(bp->rx_clk);
4615 clk_disable_unprepare(bp->tsu_clk);
4616 pm_runtime_set_suspended(&pdev->dev);
4617 }
4618 phylink_destroy(bp->phylink);
4619 free_netdev(dev);
4620 }
4621
4622 return 0;
4623}
4624
4625static int __maybe_unused macb_suspend(struct device *dev)
4626{
4627 struct net_device *netdev = dev_get_drvdata(dev);
4628 struct macb *bp = netdev_priv(netdev);
4629 struct macb_queue *queue = bp->queues;
4630 unsigned long flags;
4631 unsigned int q;
4632 int err;
4633
4634 if (!netif_running(netdev))
4635 return 0;
4636
4637 if (bp->wol & MACB_WOL_ENABLED) {
4638 spin_lock_irqsave(&bp->lock, flags);
4639 /* Flush all status bits */
4640 macb_writel(bp, TSR, -1);
4641 macb_writel(bp, RSR, -1);
4642 for (q = 0, queue = bp->queues; q < bp->num_queues;
4643 ++q, ++queue) {
4644 /* Disable all interrupts */
4645 queue_writel(queue, IDR, -1);
4646 queue_readl(queue, ISR);
4647 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
4648 queue_writel(queue, ISR, -1);
4649 }
4650 /* Change interrupt handler and
4651 * Enable WoL IRQ on queue 0
4652 */
4653 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
4654 if (macb_is_gem(bp)) {
4655 err = devm_request_irq(dev, bp->queues[0].irq, gem_wol_interrupt,
4656 IRQF_SHARED, netdev->name, bp->queues);
4657 if (err) {
4658 dev_err(dev,
4659 "Unable to request IRQ %d (error %d)\n",
4660 bp->queues[0].irq, err);
4661 spin_unlock_irqrestore(&bp->lock, flags);
4662 return err;
4663 }
4664 queue_writel(bp->queues, IER, GEM_BIT(WOL));
4665 gem_writel(bp, WOL, MACB_BIT(MAG));
4666 } else {
4667 err = devm_request_irq(dev, bp->queues[0].irq, macb_wol_interrupt,
4668 IRQF_SHARED, netdev->name, bp->queues);
4669 if (err) {
4670 dev_err(dev,
4671 "Unable to request IRQ %d (error %d)\n",
4672 bp->queues[0].irq, err);
4673 spin_unlock_irqrestore(&bp->lock, flags);
4674 return err;
4675 }
4676 queue_writel(bp->queues, IER, MACB_BIT(WOL));
4677 macb_writel(bp, WOL, MACB_BIT(MAG));
4678 }
4679 spin_unlock_irqrestore(&bp->lock, flags);
4680
4681 enable_irq_wake(bp->queues[0].irq);
4682 }
4683
4684 netif_device_detach(netdev);
4685 for (q = 0, queue = bp->queues; q < bp->num_queues;
4686 ++q, ++queue)
4687 napi_disable(&queue->napi);
4688
4689 if (!(bp->wol & MACB_WOL_ENABLED)) {
4690 rtnl_lock();
4691 phylink_stop(bp->phylink);
4692 rtnl_unlock();
4693 spin_lock_irqsave(&bp->lock, flags);
4694 macb_reset_hw(bp);
4695 spin_unlock_irqrestore(&bp->lock, flags);
4696 }
4697
4698 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
4699 bp->pm_data.usrio = macb_or_gem_readl(bp, USRIO);
4700
4701 if (netdev->hw_features & NETIF_F_NTUPLE)
4702 bp->pm_data.scrt2 = gem_readl_n(bp, ETHT, SCRT2_ETHT);
4703
4704 if (bp->ptp_info)
4705 bp->ptp_info->ptp_remove(netdev);
4706 if (!device_may_wakeup(dev))
4707 pm_runtime_force_suspend(dev);
4708
4709 return 0;
4710}
4711
4712static int __maybe_unused macb_resume(struct device *dev)
4713{
4714 struct net_device *netdev = dev_get_drvdata(dev);
4715 struct macb *bp = netdev_priv(netdev);
4716 struct macb_queue *queue = bp->queues;
4717 unsigned long flags;
4718 unsigned int q;
4719 int err;
4720
4721 if (!netif_running(netdev))
4722 return 0;
4723
4724 if (!device_may_wakeup(dev))
4725 pm_runtime_force_resume(dev);
4726
4727 if (bp->wol & MACB_WOL_ENABLED) {
4728 spin_lock_irqsave(&bp->lock, flags);
4729 /* Disable WoL */
4730 if (macb_is_gem(bp)) {
4731 queue_writel(bp->queues, IDR, GEM_BIT(WOL));
4732 gem_writel(bp, WOL, 0);
4733 } else {
4734 queue_writel(bp->queues, IDR, MACB_BIT(WOL));
4735 macb_writel(bp, WOL, 0);
4736 }
4737 /* Clear ISR on queue 0 */
4738 queue_readl(bp->queues, ISR);
4739 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
4740 queue_writel(bp->queues, ISR, -1);
4741 /* Replace interrupt handler on queue 0 */
4742 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
4743 err = devm_request_irq(dev, bp->queues[0].irq, macb_interrupt,
4744 IRQF_SHARED, netdev->name, bp->queues);
4745 if (err) {
4746 dev_err(dev,
4747 "Unable to request IRQ %d (error %d)\n",
4748 bp->queues[0].irq, err);
4749 spin_unlock_irqrestore(&bp->lock, flags);
4750 return err;
4751 }
4752 spin_unlock_irqrestore(&bp->lock, flags);
4753
4754 disable_irq_wake(bp->queues[0].irq);
4755
4756 /* Now make sure we disable phy before moving
4757 * to common restore path
4758 */
4759 rtnl_lock();
4760 phylink_stop(bp->phylink);
4761 rtnl_unlock();
4762 }
4763
4764 for (q = 0, queue = bp->queues; q < bp->num_queues;
4765 ++q, ++queue)
4766 napi_enable(&queue->napi);
4767
4768 if (netdev->hw_features & NETIF_F_NTUPLE)
4769 gem_writel_n(bp, ETHT, SCRT2_ETHT, bp->pm_data.scrt2);
4770
4771 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
4772 macb_or_gem_writel(bp, USRIO, bp->pm_data.usrio);
4773
4774 macb_writel(bp, NCR, MACB_BIT(MPE));
4775 macb_init_hw(bp);
4776 macb_set_rx_mode(netdev);
4777 macb_restore_features(bp);
4778 rtnl_lock();
4779 phylink_start(bp->phylink);
4780 rtnl_unlock();
4781
4782 netif_device_attach(netdev);
4783 if (bp->ptp_info)
4784 bp->ptp_info->ptp_init(netdev);
4785
4786 return 0;
4787}
4788
4789static int __maybe_unused macb_runtime_suspend(struct device *dev)
4790{
4791 struct net_device *netdev = dev_get_drvdata(dev);
4792 struct macb *bp = netdev_priv(netdev);
4793
4794 if (!(device_may_wakeup(dev))) {
4795 clk_disable_unprepare(bp->tx_clk);
4796 clk_disable_unprepare(bp->hclk);
4797 clk_disable_unprepare(bp->pclk);
4798 clk_disable_unprepare(bp->rx_clk);
4799 }
4800 clk_disable_unprepare(bp->tsu_clk);
4801
4802 return 0;
4803}
4804
4805static int __maybe_unused macb_runtime_resume(struct device *dev)
4806{
4807 struct net_device *netdev = dev_get_drvdata(dev);
4808 struct macb *bp = netdev_priv(netdev);
4809
4810 if (!(device_may_wakeup(dev))) {
4811 clk_prepare_enable(bp->pclk);
4812 clk_prepare_enable(bp->hclk);
4813 clk_prepare_enable(bp->tx_clk);
4814 clk_prepare_enable(bp->rx_clk);
4815 }
4816 clk_prepare_enable(bp->tsu_clk);
4817
4818 return 0;
4819}
4820
4821static const struct dev_pm_ops macb_pm_ops = {
4822 SET_SYSTEM_SLEEP_PM_OPS(macb_suspend, macb_resume)
4823 SET_RUNTIME_PM_OPS(macb_runtime_suspend, macb_runtime_resume, NULL)
4824};
4825
4826static struct platform_driver macb_driver = {
4827 .probe = macb_probe,
4828 .remove = macb_remove,
4829 .driver = {
4830 .name = "macb",
4831 .of_match_table = of_match_ptr(macb_dt_ids),
4832 .pm = &macb_pm_ops,
4833 },
4834};
4835
4836module_platform_driver(macb_driver);
4837
4838MODULE_LICENSE("GPL");
4839MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
4840MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
4841MODULE_ALIAS("platform:macb");