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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Avionic Design GmbH
4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 */
6
7#include <linux/clk.h>
8#include <linux/debugfs.h>
9#include <linux/delay.h>
10#include <linux/hdmi.h>
11#include <linux/math64.h>
12#include <linux/module.h>
13#include <linux/of_device.h>
14#include <linux/pm_opp.h>
15#include <linux/pm_runtime.h>
16#include <linux/regulator/consumer.h>
17#include <linux/reset.h>
18
19#include <soc/tegra/common.h>
20#include <sound/hdmi-codec.h>
21
22#include <drm/drm_atomic_helper.h>
23#include <drm/drm_crtc.h>
24#include <drm/drm_debugfs.h>
25#include <drm/drm_file.h>
26#include <drm/drm_fourcc.h>
27#include <drm/drm_probe_helper.h>
28#include <drm/drm_simple_kms_helper.h>
29
30#include "hda.h"
31#include "hdmi.h"
32#include "drm.h"
33#include "dc.h"
34#include "trace.h"
35
36#define HDMI_ELD_BUFFER_SIZE 96
37
38struct tmds_config {
39 unsigned int pclk;
40 u32 pll0;
41 u32 pll1;
42 u32 pe_current;
43 u32 drive_current;
44 u32 peak_current;
45};
46
47struct tegra_hdmi_config {
48 const struct tmds_config *tmds;
49 unsigned int num_tmds;
50
51 unsigned long fuse_override_offset;
52 u32 fuse_override_value;
53
54 bool has_sor_io_peak_current;
55 bool has_hda;
56 bool has_hbr;
57};
58
59struct tegra_hdmi {
60 struct host1x_client client;
61 struct tegra_output output;
62 struct device *dev;
63
64 struct regulator *hdmi;
65 struct regulator *pll;
66 struct regulator *vdd;
67
68 void __iomem *regs;
69 unsigned int irq;
70
71 struct clk *clk_parent;
72 struct clk *clk;
73 struct reset_control *rst;
74
75 const struct tegra_hdmi_config *config;
76
77 unsigned int audio_source;
78 struct tegra_hda_format format;
79
80 unsigned int pixel_clock;
81 bool stereo;
82 bool dvi;
83
84 struct drm_info_list *debugfs_files;
85
86 struct platform_device *audio_pdev;
87 struct mutex audio_lock;
88};
89
90static inline struct tegra_hdmi *
91host1x_client_to_hdmi(struct host1x_client *client)
92{
93 return container_of(client, struct tegra_hdmi, client);
94}
95
96static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
97{
98 return container_of(output, struct tegra_hdmi, output);
99}
100
101#define HDMI_AUDIOCLK_FREQ 216000000
102#define HDMI_REKEY_DEFAULT 56
103
104enum {
105 AUTO = 0,
106 SPDIF,
107 HDA,
108};
109
110static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi,
111 unsigned int offset)
112{
113 u32 value = readl(hdmi->regs + (offset << 2));
114
115 trace_hdmi_readl(hdmi->dev, offset, value);
116
117 return value;
118}
119
120static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value,
121 unsigned int offset)
122{
123 trace_hdmi_writel(hdmi->dev, offset, value);
124 writel(value, hdmi->regs + (offset << 2));
125}
126
127struct tegra_hdmi_audio_config {
128 unsigned int n;
129 unsigned int cts;
130 unsigned int aval;
131};
132
133static const struct tmds_config tegra20_tmds_config[] = {
134 { /* slow pixel clock modes */
135 .pclk = 27000000,
136 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
137 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
138 SOR_PLL_TX_REG_LOAD(3),
139 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
140 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
141 PE_CURRENT1(PE_CURRENT_0_0_mA) |
142 PE_CURRENT2(PE_CURRENT_0_0_mA) |
143 PE_CURRENT3(PE_CURRENT_0_0_mA),
144 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
145 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
146 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
147 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
148 },
149 { /* high pixel clock modes */
150 .pclk = UINT_MAX,
151 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
152 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
153 SOR_PLL_TX_REG_LOAD(3),
154 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
155 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
156 PE_CURRENT1(PE_CURRENT_6_0_mA) |
157 PE_CURRENT2(PE_CURRENT_6_0_mA) |
158 PE_CURRENT3(PE_CURRENT_6_0_mA),
159 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
160 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
161 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
162 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
163 },
164};
165
166static const struct tmds_config tegra30_tmds_config[] = {
167 { /* 480p modes */
168 .pclk = 27000000,
169 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
170 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
171 SOR_PLL_TX_REG_LOAD(0),
172 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
173 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
174 PE_CURRENT1(PE_CURRENT_0_0_mA) |
175 PE_CURRENT2(PE_CURRENT_0_0_mA) |
176 PE_CURRENT3(PE_CURRENT_0_0_mA),
177 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
178 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
179 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
180 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
181 }, { /* 720p modes */
182 .pclk = 74250000,
183 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
184 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
185 SOR_PLL_TX_REG_LOAD(0),
186 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
187 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
188 PE_CURRENT1(PE_CURRENT_5_0_mA) |
189 PE_CURRENT2(PE_CURRENT_5_0_mA) |
190 PE_CURRENT3(PE_CURRENT_5_0_mA),
191 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
192 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
193 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
194 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
195 }, { /* 1080p modes */
196 .pclk = UINT_MAX,
197 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
198 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
199 SOR_PLL_TX_REG_LOAD(0),
200 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
201 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
202 PE_CURRENT1(PE_CURRENT_5_0_mA) |
203 PE_CURRENT2(PE_CURRENT_5_0_mA) |
204 PE_CURRENT3(PE_CURRENT_5_0_mA),
205 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
206 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
207 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
208 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
209 },
210};
211
212static const struct tmds_config tegra114_tmds_config[] = {
213 { /* 480p/576p / 25.2MHz/27MHz modes */
214 .pclk = 27000000,
215 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
216 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
217 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
218 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
219 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
220 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
221 PE_CURRENT3(PE_CURRENT_0_mA_T114),
222 .drive_current =
223 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
224 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
225 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
226 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
227 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
228 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
229 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
230 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
231 }, { /* 720p / 74.25MHz modes */
232 .pclk = 74250000,
233 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
234 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
235 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
236 SOR_PLL_TMDS_TERMADJ(0),
237 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
238 PE_CURRENT1(PE_CURRENT_15_mA_T114) |
239 PE_CURRENT2(PE_CURRENT_15_mA_T114) |
240 PE_CURRENT3(PE_CURRENT_15_mA_T114),
241 .drive_current =
242 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
243 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
244 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
245 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
246 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
247 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
248 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
249 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
250 }, { /* 1080p / 148.5MHz modes */
251 .pclk = 148500000,
252 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
253 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
254 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
255 SOR_PLL_TMDS_TERMADJ(0),
256 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
257 PE_CURRENT1(PE_CURRENT_10_mA_T114) |
258 PE_CURRENT2(PE_CURRENT_10_mA_T114) |
259 PE_CURRENT3(PE_CURRENT_10_mA_T114),
260 .drive_current =
261 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
262 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
263 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
264 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
265 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
266 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
267 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
268 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
269 }, { /* 225/297MHz modes */
270 .pclk = UINT_MAX,
271 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
272 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
273 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
274 | SOR_PLL_TMDS_TERM_ENABLE,
275 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
276 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
277 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
278 PE_CURRENT3(PE_CURRENT_0_mA_T114),
279 .drive_current =
280 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
281 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
282 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
283 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
284 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
285 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
286 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
287 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
288 },
289};
290
291static const struct tmds_config tegra124_tmds_config[] = {
292 { /* 480p/576p / 25.2MHz/27MHz modes */
293 .pclk = 27000000,
294 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
295 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
296 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
297 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
298 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
299 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
300 PE_CURRENT3(PE_CURRENT_0_mA_T114),
301 .drive_current =
302 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
303 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
304 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
305 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
306 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
307 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
308 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
309 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
310 }, { /* 720p / 74.25MHz modes */
311 .pclk = 74250000,
312 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
313 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
314 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
315 SOR_PLL_TMDS_TERMADJ(0),
316 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
317 PE_CURRENT1(PE_CURRENT_15_mA_T114) |
318 PE_CURRENT2(PE_CURRENT_15_mA_T114) |
319 PE_CURRENT3(PE_CURRENT_15_mA_T114),
320 .drive_current =
321 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
322 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
323 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
324 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
325 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
326 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
327 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
328 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
329 }, { /* 1080p / 148.5MHz modes */
330 .pclk = 148500000,
331 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
332 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
333 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
334 SOR_PLL_TMDS_TERMADJ(0),
335 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
336 PE_CURRENT1(PE_CURRENT_10_mA_T114) |
337 PE_CURRENT2(PE_CURRENT_10_mA_T114) |
338 PE_CURRENT3(PE_CURRENT_10_mA_T114),
339 .drive_current =
340 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
341 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
342 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
343 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
344 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
345 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
346 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
347 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
348 }, { /* 225/297MHz modes */
349 .pclk = UINT_MAX,
350 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
351 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
352 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
353 | SOR_PLL_TMDS_TERM_ENABLE,
354 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
355 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
356 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
357 PE_CURRENT3(PE_CURRENT_0_mA_T114),
358 .drive_current =
359 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
360 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
361 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
362 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
363 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
364 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
365 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
366 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
367 },
368};
369
370static void tegra_hdmi_audio_lock(struct tegra_hdmi *hdmi)
371{
372 mutex_lock(&hdmi->audio_lock);
373 disable_irq(hdmi->irq);
374}
375
376static void tegra_hdmi_audio_unlock(struct tegra_hdmi *hdmi)
377{
378 enable_irq(hdmi->irq);
379 mutex_unlock(&hdmi->audio_lock);
380}
381
382static int
383tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pix_clock,
384 struct tegra_hdmi_audio_config *config)
385{
386 const unsigned int afreq = 128 * audio_freq;
387 const unsigned int min_n = afreq / 1500;
388 const unsigned int max_n = afreq / 300;
389 const unsigned int ideal_n = afreq / 1000;
390 int64_t min_err = (uint64_t)-1 >> 1;
391 unsigned int min_delta = -1;
392 int n;
393
394 memset(config, 0, sizeof(*config));
395 config->n = -1;
396
397 for (n = min_n; n <= max_n; n++) {
398 uint64_t cts_f, aval_f;
399 unsigned int delta;
400 int64_t cts, err;
401
402 /* compute aval in 48.16 fixed point */
403 aval_f = ((int64_t)24000000 << 16) * n;
404 do_div(aval_f, afreq);
405 /* It should round without any rest */
406 if (aval_f & 0xFFFF)
407 continue;
408
409 /* Compute cts in 48.16 fixed point */
410 cts_f = ((int64_t)pix_clock << 16) * n;
411 do_div(cts_f, afreq);
412 /* Round it to the nearest integer */
413 cts = (cts_f & ~0xFFFF) + ((cts_f & BIT(15)) << 1);
414
415 delta = abs(n - ideal_n);
416
417 /* Compute the absolute error */
418 err = abs((int64_t)cts_f - cts);
419 if (err < min_err || (err == min_err && delta < min_delta)) {
420 config->n = n;
421 config->cts = cts >> 16;
422 config->aval = aval_f >> 16;
423 min_delta = delta;
424 min_err = err;
425 }
426 }
427
428 return config->n != -1 ? 0 : -EINVAL;
429}
430
431static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
432{
433 const unsigned int freqs[] = {
434 32000, 44100, 48000, 88200, 96000, 176400, 192000
435 };
436 unsigned int i;
437
438 for (i = 0; i < ARRAY_SIZE(freqs); i++) {
439 unsigned int f = freqs[i];
440 unsigned int eight_half;
441 unsigned int delta;
442 u32 value;
443
444 if (f > 96000)
445 delta = 2;
446 else if (f > 48000)
447 delta = 6;
448 else
449 delta = 9;
450
451 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
452 value = AUDIO_FS_LOW(eight_half - delta) |
453 AUDIO_FS_HIGH(eight_half + delta);
454 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
455 }
456}
457
458static void tegra_hdmi_write_aval(struct tegra_hdmi *hdmi, u32 value)
459{
460 static const struct {
461 unsigned int sample_rate;
462 unsigned int offset;
463 } regs[] = {
464 { 32000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 },
465 { 44100, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 },
466 { 48000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 },
467 { 88200, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 },
468 { 96000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 },
469 { 176400, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 },
470 { 192000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 },
471 };
472 unsigned int i;
473
474 for (i = 0; i < ARRAY_SIZE(regs); i++) {
475 if (regs[i].sample_rate == hdmi->format.sample_rate) {
476 tegra_hdmi_writel(hdmi, value, regs[i].offset);
477 break;
478 }
479 }
480}
481
482static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi)
483{
484 struct tegra_hdmi_audio_config config;
485 u32 source, value;
486 int err;
487
488 switch (hdmi->audio_source) {
489 case HDA:
490 if (hdmi->config->has_hda)
491 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
492 else
493 return -EINVAL;
494
495 break;
496
497 case SPDIF:
498 if (hdmi->config->has_hda)
499 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
500 else
501 source = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
502 break;
503
504 default:
505 if (hdmi->config->has_hda)
506 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
507 else
508 source = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
509 break;
510 }
511
512 /*
513 * Tegra30 and later use a slightly modified version of the register
514 * layout to accomodate for changes related to supporting HDA as the
515 * audio input source for HDMI. The source select field has moved to
516 * the SOR_AUDIO_CNTRL0 register, but the error tolerance and frames
517 * per block fields remain in the AUDIO_CNTRL0 register.
518 */
519 if (hdmi->config->has_hda) {
520 /*
521 * Inject null samples into the audio FIFO for every frame in
522 * which the codec did not receive any samples. This applies
523 * to stereo LPCM only.
524 *
525 * XXX: This seems to be a remnant of MCP days when this was
526 * used to work around issues with monitors not being able to
527 * play back system startup sounds early. It is possibly not
528 * needed on Linux at all.
529 */
530 if (hdmi->format.channels == 2)
531 value = SOR_AUDIO_CNTRL0_INJECT_NULLSMPL;
532 else
533 value = 0;
534
535 value |= source;
536
537 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
538 }
539
540 /*
541 * On Tegra20, HDA is not a supported audio source and the source
542 * select field is part of the AUDIO_CNTRL0 register.
543 */
544 value = AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
545 AUDIO_CNTRL0_ERROR_TOLERANCE(6);
546
547 if (!hdmi->config->has_hda)
548 value |= source;
549
550 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
551
552 /*
553 * Advertise support for High Bit-Rate on Tegra114 and later.
554 */
555 if (hdmi->config->has_hbr) {
556 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
557 value |= SOR_AUDIO_SPARE0_HBR_ENABLE;
558 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
559 }
560
561 err = tegra_hdmi_get_audio_config(hdmi->format.sample_rate,
562 hdmi->pixel_clock, &config);
563 if (err < 0) {
564 dev_err(hdmi->dev,
565 "cannot set audio to %u Hz at %u Hz pixel clock\n",
566 hdmi->format.sample_rate, hdmi->pixel_clock);
567 return err;
568 }
569
570 dev_dbg(hdmi->dev, "audio: pixclk=%u, n=%u, cts=%u, aval=%u\n",
571 hdmi->pixel_clock, config.n, config.cts, config.aval);
572
573 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
574
575 value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
576 AUDIO_N_VALUE(config.n - 1);
577 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
578
579 tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config.n) | ACR_ENABLE,
580 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
581
582 tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config.cts),
583 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
584
585 value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
586 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
587
588 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
589 value &= ~AUDIO_N_RESETF;
590 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
591
592 if (hdmi->config->has_hda)
593 tegra_hdmi_write_aval(hdmi, config.aval);
594
595 tegra_hdmi_setup_audio_fs_tables(hdmi);
596
597 return 0;
598}
599
600static void tegra_hdmi_disable_audio(struct tegra_hdmi *hdmi)
601{
602 u32 value;
603
604 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
605 value &= ~GENERIC_CTRL_AUDIO;
606 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
607}
608
609static void tegra_hdmi_enable_audio(struct tegra_hdmi *hdmi)
610{
611 u32 value;
612
613 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
614 value |= GENERIC_CTRL_AUDIO;
615 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
616}
617
618static void tegra_hdmi_write_eld(struct tegra_hdmi *hdmi)
619{
620 size_t length = drm_eld_size(hdmi->output.connector.eld), i;
621 u32 value;
622
623 for (i = 0; i < length; i++)
624 tegra_hdmi_writel(hdmi, i << 8 | hdmi->output.connector.eld[i],
625 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
626
627 /*
628 * The HDA codec will always report an ELD buffer size of 96 bytes and
629 * the HDA codec driver will check that each byte read from the buffer
630 * is valid. Therefore every byte must be written, even if no 96 bytes
631 * were parsed from EDID.
632 */
633 for (i = length; i < HDMI_ELD_BUFFER_SIZE; i++)
634 tegra_hdmi_writel(hdmi, i << 8 | 0,
635 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
636
637 value = SOR_AUDIO_HDA_PRESENSE_VALID | SOR_AUDIO_HDA_PRESENSE_PRESENT;
638 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
639}
640
641static inline u32 tegra_hdmi_subpack(const u8 *ptr, size_t size)
642{
643 u32 value = 0;
644 size_t i;
645
646 for (i = size; i > 0; i--)
647 value = (value << 8) | ptr[i - 1];
648
649 return value;
650}
651
652static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
653 size_t size)
654{
655 const u8 *ptr = data;
656 unsigned long offset;
657 size_t i, j;
658 u32 value;
659
660 switch (ptr[0]) {
661 case HDMI_INFOFRAME_TYPE_AVI:
662 offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
663 break;
664
665 case HDMI_INFOFRAME_TYPE_AUDIO:
666 offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
667 break;
668
669 case HDMI_INFOFRAME_TYPE_VENDOR:
670 offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
671 break;
672
673 default:
674 dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
675 ptr[0]);
676 return;
677 }
678
679 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
680 INFOFRAME_HEADER_VERSION(ptr[1]) |
681 INFOFRAME_HEADER_LEN(ptr[2]);
682 tegra_hdmi_writel(hdmi, value, offset);
683 offset++;
684
685 /*
686 * Each subpack contains 7 bytes, divided into:
687 * - subpack_low: bytes 0 - 3
688 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
689 */
690 for (i = 3, j = 0; i < size; i += 7, j += 8) {
691 size_t rem = size - i, num = min_t(size_t, rem, 4);
692
693 value = tegra_hdmi_subpack(&ptr[i], num);
694 tegra_hdmi_writel(hdmi, value, offset++);
695
696 num = min_t(size_t, rem - num, 3);
697
698 value = tegra_hdmi_subpack(&ptr[i + 4], num);
699 tegra_hdmi_writel(hdmi, value, offset++);
700 }
701}
702
703static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
704 struct drm_display_mode *mode)
705{
706 struct hdmi_avi_infoframe frame;
707 u8 buffer[17];
708 ssize_t err;
709
710 err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
711 &hdmi->output.connector, mode);
712 if (err < 0) {
713 dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
714 return;
715 }
716
717 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
718 if (err < 0) {
719 dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
720 return;
721 }
722
723 tegra_hdmi_write_infopack(hdmi, buffer, err);
724}
725
726static void tegra_hdmi_disable_avi_infoframe(struct tegra_hdmi *hdmi)
727{
728 u32 value;
729
730 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
731 value &= ~INFOFRAME_CTRL_ENABLE;
732 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
733}
734
735static void tegra_hdmi_enable_avi_infoframe(struct tegra_hdmi *hdmi)
736{
737 u32 value;
738
739 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
740 value |= INFOFRAME_CTRL_ENABLE;
741 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
742}
743
744static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
745{
746 struct hdmi_audio_infoframe frame;
747 u8 buffer[14];
748 ssize_t err;
749
750 err = hdmi_audio_infoframe_init(&frame);
751 if (err < 0) {
752 dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n",
753 err);
754 return;
755 }
756
757 frame.channels = hdmi->format.channels;
758
759 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
760 if (err < 0) {
761 dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
762 err);
763 return;
764 }
765
766 /*
767 * The audio infoframe has only one set of subpack registers, so the
768 * infoframe needs to be truncated. One set of subpack registers can
769 * contain 7 bytes. Including the 3 byte header only the first 10
770 * bytes can be programmed.
771 */
772 tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err));
773}
774
775static void tegra_hdmi_disable_audio_infoframe(struct tegra_hdmi *hdmi)
776{
777 u32 value;
778
779 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
780 value &= ~INFOFRAME_CTRL_ENABLE;
781 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
782}
783
784static void tegra_hdmi_enable_audio_infoframe(struct tegra_hdmi *hdmi)
785{
786 u32 value;
787
788 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
789 value |= INFOFRAME_CTRL_ENABLE;
790 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
791}
792
793static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
794{
795 struct hdmi_vendor_infoframe frame;
796 u8 buffer[10];
797 ssize_t err;
798
799 hdmi_vendor_infoframe_init(&frame);
800 frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING;
801
802 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
803 if (err < 0) {
804 dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
805 err);
806 return;
807 }
808
809 tegra_hdmi_write_infopack(hdmi, buffer, err);
810}
811
812static void tegra_hdmi_disable_stereo_infoframe(struct tegra_hdmi *hdmi)
813{
814 u32 value;
815
816 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
817 value &= ~GENERIC_CTRL_ENABLE;
818 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
819}
820
821static void tegra_hdmi_enable_stereo_infoframe(struct tegra_hdmi *hdmi)
822{
823 u32 value;
824
825 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
826 value |= GENERIC_CTRL_ENABLE;
827 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
828}
829
830static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
831 const struct tmds_config *tmds)
832{
833 u32 value;
834
835 tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
836 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
837 tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
838
839 tegra_hdmi_writel(hdmi, tmds->drive_current,
840 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
841
842 value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset);
843 value |= hdmi->config->fuse_override_value;
844 tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset);
845
846 if (hdmi->config->has_sor_io_peak_current)
847 tegra_hdmi_writel(hdmi, tmds->peak_current,
848 HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
849}
850
851static int tegra_hdmi_reconfigure_audio(struct tegra_hdmi *hdmi)
852{
853 int err;
854
855 err = tegra_hdmi_setup_audio(hdmi);
856 if (err < 0) {
857 tegra_hdmi_disable_audio_infoframe(hdmi);
858 tegra_hdmi_disable_audio(hdmi);
859 } else {
860 tegra_hdmi_setup_audio_infoframe(hdmi);
861 tegra_hdmi_enable_audio_infoframe(hdmi);
862 tegra_hdmi_enable_audio(hdmi);
863 }
864
865 return err;
866}
867
868static bool tegra_output_is_hdmi(struct tegra_output *output)
869{
870 return output->connector.display_info.is_hdmi;
871}
872
873static enum drm_connector_status
874tegra_hdmi_connector_detect(struct drm_connector *connector, bool force)
875{
876 struct tegra_output *output = connector_to_output(connector);
877 struct tegra_hdmi *hdmi = to_hdmi(output);
878 enum drm_connector_status status;
879
880 status = tegra_output_connector_detect(connector, force);
881 if (status == connector_status_connected)
882 return status;
883
884 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
885 return status;
886}
887
888#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
889
890static const struct debugfs_reg32 tegra_hdmi_regs[] = {
891 DEBUGFS_REG32(HDMI_CTXSW),
892 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE0),
893 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE1),
894 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE2),
895 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_MSB),
896 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_LSB),
897 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_MSB),
898 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_LSB),
899 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB),
900 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB),
901 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB),
902 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB),
903 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB),
904 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB),
905 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB),
906 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB),
907 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CTRL),
908 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CMODE),
909 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB),
910 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB),
911 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB),
912 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2),
913 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1),
914 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_RI),
915 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_MSB),
916 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_LSB),
917 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU0),
918 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0),
919 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU1),
920 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU2),
921 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL),
922 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS),
923 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER),
924 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW),
925 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH),
926 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL),
927 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS),
928 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER),
929 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW),
930 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH),
931 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW),
932 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH),
933 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_CTRL),
934 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_STATUS),
935 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_HEADER),
936 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW),
937 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH),
938 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW),
939 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH),
940 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW),
941 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH),
942 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW),
943 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH),
944 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_CTRL),
945 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW),
946 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH),
947 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW),
948 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH),
949 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW),
950 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH),
951 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW),
952 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH),
953 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW),
954 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH),
955 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW),
956 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH),
957 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW),
958 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH),
959 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CTRL),
960 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT),
961 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW),
962 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_CTRL),
963 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_STATUS),
964 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_SUBPACK),
965 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1),
966 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2),
967 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU0),
968 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1),
969 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1_RDATA),
970 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPARE),
971 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1),
972 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2),
973 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL),
974 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CAP),
975 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PWR),
976 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TEST),
977 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL0),
978 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL1),
979 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL2),
980 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CSTM),
981 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LVDS),
982 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCA),
983 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCB),
984 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_BLANK),
985 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_CTL),
986 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(0)),
987 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(1)),
988 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(2)),
989 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(3)),
990 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(4)),
991 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(5)),
992 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(6)),
993 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(7)),
994 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(8)),
995 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(9)),
996 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(10)),
997 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(11)),
998 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(12)),
999 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(13)),
1000 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(14)),
1001 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(15)),
1002 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA0),
1003 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA1),
1004 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA0),
1005 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA1),
1006 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA0),
1007 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA1),
1008 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA0),
1009 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA1),
1010 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA0),
1011 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA1),
1012 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TRIG),
1013 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_MSCHECK),
1014 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT),
1015 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG0),
1016 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG1),
1017 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG2),
1018 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(0)),
1019 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(1)),
1020 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(2)),
1021 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(3)),
1022 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(4)),
1023 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(5)),
1024 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(6)),
1025 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH),
1026 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_THRESHOLD),
1027 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_CNTRL0),
1028 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_N),
1029 DEBUGFS_REG32(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING),
1030 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_REFCLK),
1031 DEBUGFS_REG32(HDMI_NV_PDISP_CRC_CONTROL),
1032 DEBUGFS_REG32(HDMI_NV_PDISP_INPUT_CONTROL),
1033 DEBUGFS_REG32(HDMI_NV_PDISP_SCRATCH),
1034 DEBUGFS_REG32(HDMI_NV_PDISP_PE_CURRENT),
1035 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_CTRL),
1036 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG0),
1037 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG1),
1038 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG2),
1039 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_0),
1040 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_1),
1041 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_2),
1042 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_3),
1043 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG),
1044 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_SKEY_INDEX),
1045 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0),
1046 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_SPARE0),
1047 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0),
1048 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1),
1049 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR),
1050 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE),
1051 DEBUGFS_REG32(HDMI_NV_PDISP_INT_STATUS),
1052 DEBUGFS_REG32(HDMI_NV_PDISP_INT_MASK),
1053 DEBUGFS_REG32(HDMI_NV_PDISP_INT_ENABLE),
1054 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT),
1055};
1056
1057static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
1058{
1059 struct drm_info_node *node = s->private;
1060 struct tegra_hdmi *hdmi = node->info_ent->data;
1061 struct drm_crtc *crtc = hdmi->output.encoder.crtc;
1062 struct drm_device *drm = node->minor->dev;
1063 unsigned int i;
1064 int err = 0;
1065
1066 drm_modeset_lock_all(drm);
1067
1068 if (!crtc || !crtc->state->active) {
1069 err = -EBUSY;
1070 goto unlock;
1071 }
1072
1073 for (i = 0; i < ARRAY_SIZE(tegra_hdmi_regs); i++) {
1074 unsigned int offset = tegra_hdmi_regs[i].offset;
1075
1076 seq_printf(s, "%-56s %#05x %08x\n", tegra_hdmi_regs[i].name,
1077 offset, tegra_hdmi_readl(hdmi, offset));
1078 }
1079
1080unlock:
1081 drm_modeset_unlock_all(drm);
1082 return err;
1083}
1084
1085static struct drm_info_list debugfs_files[] = {
1086 { "regs", tegra_hdmi_show_regs, 0, NULL },
1087};
1088
1089static int tegra_hdmi_late_register(struct drm_connector *connector)
1090{
1091 struct tegra_output *output = connector_to_output(connector);
1092 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1093 struct drm_minor *minor = connector->dev->primary;
1094 struct dentry *root = connector->debugfs_entry;
1095 struct tegra_hdmi *hdmi = to_hdmi(output);
1096
1097 hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1098 GFP_KERNEL);
1099 if (!hdmi->debugfs_files)
1100 return -ENOMEM;
1101
1102 for (i = 0; i < count; i++)
1103 hdmi->debugfs_files[i].data = hdmi;
1104
1105 drm_debugfs_create_files(hdmi->debugfs_files, count, root, minor);
1106
1107 return 0;
1108}
1109
1110static void tegra_hdmi_early_unregister(struct drm_connector *connector)
1111{
1112 struct tegra_output *output = connector_to_output(connector);
1113 struct drm_minor *minor = connector->dev->primary;
1114 unsigned int count = ARRAY_SIZE(debugfs_files);
1115 struct tegra_hdmi *hdmi = to_hdmi(output);
1116
1117 drm_debugfs_remove_files(hdmi->debugfs_files, count, minor);
1118 kfree(hdmi->debugfs_files);
1119 hdmi->debugfs_files = NULL;
1120}
1121
1122static const struct drm_connector_funcs tegra_hdmi_connector_funcs = {
1123 .reset = drm_atomic_helper_connector_reset,
1124 .detect = tegra_hdmi_connector_detect,
1125 .fill_modes = drm_helper_probe_single_connector_modes,
1126 .destroy = tegra_output_connector_destroy,
1127 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1128 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1129 .late_register = tegra_hdmi_late_register,
1130 .early_unregister = tegra_hdmi_early_unregister,
1131};
1132
1133static enum drm_mode_status
1134tegra_hdmi_connector_mode_valid(struct drm_connector *connector,
1135 struct drm_display_mode *mode)
1136{
1137 struct tegra_output *output = connector_to_output(connector);
1138 struct tegra_hdmi *hdmi = to_hdmi(output);
1139 unsigned long pclk = mode->clock * 1000;
1140 enum drm_mode_status status = MODE_OK;
1141 struct clk *parent;
1142 long err;
1143
1144 parent = clk_get_parent(hdmi->clk_parent);
1145
1146 err = clk_round_rate(parent, pclk * 4);
1147 if (err <= 0)
1148 status = MODE_NOCLOCK;
1149
1150 return status;
1151}
1152
1153static const struct drm_connector_helper_funcs
1154tegra_hdmi_connector_helper_funcs = {
1155 .get_modes = tegra_output_connector_get_modes,
1156 .mode_valid = tegra_hdmi_connector_mode_valid,
1157};
1158
1159static void tegra_hdmi_encoder_disable(struct drm_encoder *encoder)
1160{
1161 struct tegra_output *output = encoder_to_output(encoder);
1162 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1163 struct tegra_hdmi *hdmi = to_hdmi(output);
1164 u32 value;
1165 int err;
1166
1167 tegra_hdmi_audio_lock(hdmi);
1168
1169 /*
1170 * The following accesses registers of the display controller, so make
1171 * sure it's only executed when the output is attached to one.
1172 */
1173 if (dc) {
1174 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1175 value &= ~HDMI_ENABLE;
1176 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1177
1178 tegra_dc_commit(dc);
1179 }
1180
1181 if (!hdmi->dvi) {
1182 if (hdmi->stereo)
1183 tegra_hdmi_disable_stereo_infoframe(hdmi);
1184
1185 tegra_hdmi_disable_audio_infoframe(hdmi);
1186 tegra_hdmi_disable_avi_infoframe(hdmi);
1187 tegra_hdmi_disable_audio(hdmi);
1188 }
1189
1190 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_ENABLE);
1191 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_MASK);
1192
1193 hdmi->pixel_clock = 0;
1194
1195 tegra_hdmi_audio_unlock(hdmi);
1196
1197 err = host1x_client_suspend(&hdmi->client);
1198 if (err < 0)
1199 dev_err(hdmi->dev, "failed to suspend: %d\n", err);
1200}
1201
1202static void tegra_hdmi_encoder_enable(struct drm_encoder *encoder)
1203{
1204 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1205 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
1206 struct tegra_output *output = encoder_to_output(encoder);
1207 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1208 struct tegra_hdmi *hdmi = to_hdmi(output);
1209 unsigned int pulse_start, div82;
1210 int retries = 1000;
1211 u32 value;
1212 int err;
1213
1214 err = host1x_client_resume(&hdmi->client);
1215 if (err < 0) {
1216 dev_err(hdmi->dev, "failed to resume: %d\n", err);
1217 return;
1218 }
1219
1220 tegra_hdmi_audio_lock(hdmi);
1221
1222 /*
1223 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
1224 * is used for interoperability between the HDA codec driver and the
1225 * HDMI driver.
1226 */
1227 tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_ENABLE);
1228 tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_MASK);
1229
1230 hdmi->pixel_clock = mode->clock * 1000;
1231 h_sync_width = mode->hsync_end - mode->hsync_start;
1232 h_back_porch = mode->htotal - mode->hsync_end;
1233 h_front_porch = mode->hsync_start - mode->hdisplay;
1234
1235 err = dev_pm_opp_set_rate(hdmi->dev, hdmi->pixel_clock);
1236 if (err < 0) {
1237 dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n",
1238 err);
1239 }
1240
1241 DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk));
1242
1243 /* power up sequence */
1244 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1245 value &= ~SOR_PLL_PDBG;
1246 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1247
1248 usleep_range(10, 20);
1249
1250 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1251 value &= ~SOR_PLL_PWR;
1252 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1253
1254 tegra_dc_writel(dc, VSYNC_H_POSITION(1),
1255 DC_DISP_DISP_TIMING_OPTIONS);
1256 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
1257 DC_DISP_DISP_COLOR_CONTROL);
1258
1259 /* video_preamble uses h_pulse2 */
1260 pulse_start = 1 + h_sync_width + h_back_porch - 10;
1261
1262 tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1263
1264 value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
1265 PULSE_LAST_END_A;
1266 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
1267
1268 value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
1269 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
1270
1271 value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
1272 VSYNC_WINDOW_ENABLE;
1273 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1274
1275 if (dc->pipe)
1276 value = HDMI_SRC_DISPLAYB;
1277 else
1278 value = HDMI_SRC_DISPLAYA;
1279
1280 if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
1281 (mode->vdisplay == 576)))
1282 tegra_hdmi_writel(hdmi,
1283 value | ARM_VIDEO_RANGE_FULL,
1284 HDMI_NV_PDISP_INPUT_CONTROL);
1285 else
1286 tegra_hdmi_writel(hdmi,
1287 value | ARM_VIDEO_RANGE_LIMITED,
1288 HDMI_NV_PDISP_INPUT_CONTROL);
1289
1290 div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
1291 value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
1292 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
1293
1294 hdmi->dvi = !tegra_output_is_hdmi(output);
1295 if (!hdmi->dvi) {
1296 /*
1297 * Make sure that the audio format has been configured before
1298 * enabling audio, otherwise we may try to divide by zero.
1299 */
1300 if (hdmi->format.sample_rate > 0) {
1301 err = tegra_hdmi_setup_audio(hdmi);
1302 if (err < 0)
1303 hdmi->dvi = true;
1304 }
1305 }
1306
1307 if (hdmi->config->has_hda)
1308 tegra_hdmi_write_eld(hdmi);
1309
1310 rekey = HDMI_REKEY_DEFAULT;
1311 value = HDMI_CTRL_REKEY(rekey);
1312 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
1313 h_front_porch - rekey - 18) / 32);
1314
1315 if (!hdmi->dvi)
1316 value |= HDMI_CTRL_ENABLE;
1317
1318 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
1319
1320 if (!hdmi->dvi) {
1321 tegra_hdmi_setup_avi_infoframe(hdmi, mode);
1322 tegra_hdmi_setup_audio_infoframe(hdmi);
1323
1324 if (hdmi->stereo)
1325 tegra_hdmi_setup_stereo_infoframe(hdmi);
1326 }
1327
1328 /* TMDS CONFIG */
1329 for (i = 0; i < hdmi->config->num_tmds; i++) {
1330 if (hdmi->pixel_clock <= hdmi->config->tmds[i].pclk) {
1331 tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]);
1332 break;
1333 }
1334 }
1335
1336 tegra_hdmi_writel(hdmi,
1337 SOR_SEQ_PU_PC(0) |
1338 SOR_SEQ_PU_PC_ALT(0) |
1339 SOR_SEQ_PD_PC(8) |
1340 SOR_SEQ_PD_PC_ALT(8),
1341 HDMI_NV_PDISP_SOR_SEQ_CTL);
1342
1343 value = SOR_SEQ_INST_WAIT_TIME(1) |
1344 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
1345 SOR_SEQ_INST_HALT |
1346 SOR_SEQ_INST_PIN_A_LOW |
1347 SOR_SEQ_INST_PIN_B_LOW |
1348 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
1349
1350 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
1351 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
1352
1353 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM);
1354 value &= ~SOR_CSTM_ROTCLK(~0);
1355 value |= SOR_CSTM_ROTCLK(2);
1356 value |= SOR_CSTM_PLLDIV;
1357 value &= ~SOR_CSTM_LVDS_ENABLE;
1358 value &= ~SOR_CSTM_MODE_MASK;
1359 value |= SOR_CSTM_MODE_TMDS;
1360 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
1361
1362 /* start SOR */
1363 tegra_hdmi_writel(hdmi,
1364 SOR_PWR_NORMAL_STATE_PU |
1365 SOR_PWR_NORMAL_START_NORMAL |
1366 SOR_PWR_SAFE_STATE_PD |
1367 SOR_PWR_SETTING_NEW_TRIGGER,
1368 HDMI_NV_PDISP_SOR_PWR);
1369 tegra_hdmi_writel(hdmi,
1370 SOR_PWR_NORMAL_STATE_PU |
1371 SOR_PWR_NORMAL_START_NORMAL |
1372 SOR_PWR_SAFE_STATE_PD |
1373 SOR_PWR_SETTING_NEW_DONE,
1374 HDMI_NV_PDISP_SOR_PWR);
1375
1376 do {
1377 BUG_ON(--retries < 0);
1378 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
1379 } while (value & SOR_PWR_SETTING_NEW_PENDING);
1380
1381 value = SOR_STATE_ASY_CRCMODE_COMPLETE |
1382 SOR_STATE_ASY_OWNER_HEAD0 |
1383 SOR_STATE_ASY_SUBOWNER_BOTH |
1384 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
1385 SOR_STATE_ASY_DEPOL_POS;
1386
1387 /* setup sync polarities */
1388 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1389 value |= SOR_STATE_ASY_HSYNCPOL_POS;
1390
1391 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1392 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
1393
1394 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1395 value |= SOR_STATE_ASY_VSYNCPOL_POS;
1396
1397 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1398 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
1399
1400 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
1401
1402 value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
1403 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
1404
1405 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1406 tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
1407 tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
1408 HDMI_NV_PDISP_SOR_STATE1);
1409 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1410
1411 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1412 value |= HDMI_ENABLE;
1413 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1414
1415 tegra_dc_commit(dc);
1416
1417 if (!hdmi->dvi) {
1418 tegra_hdmi_enable_avi_infoframe(hdmi);
1419 tegra_hdmi_enable_audio_infoframe(hdmi);
1420 tegra_hdmi_enable_audio(hdmi);
1421
1422 if (hdmi->stereo)
1423 tegra_hdmi_enable_stereo_infoframe(hdmi);
1424 }
1425
1426 /* TODO: add HDCP support */
1427
1428 tegra_hdmi_audio_unlock(hdmi);
1429}
1430
1431static int
1432tegra_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1433 struct drm_crtc_state *crtc_state,
1434 struct drm_connector_state *conn_state)
1435{
1436 struct tegra_output *output = encoder_to_output(encoder);
1437 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1438 unsigned long pclk = crtc_state->mode.clock * 1000;
1439 struct tegra_hdmi *hdmi = to_hdmi(output);
1440 int err;
1441
1442 err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent,
1443 pclk, 0);
1444 if (err < 0) {
1445 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1446 return err;
1447 }
1448
1449 return err;
1450}
1451
1452static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = {
1453 .disable = tegra_hdmi_encoder_disable,
1454 .enable = tegra_hdmi_encoder_enable,
1455 .atomic_check = tegra_hdmi_encoder_atomic_check,
1456};
1457
1458static int tegra_hdmi_hw_params(struct device *dev, void *data,
1459 struct hdmi_codec_daifmt *fmt,
1460 struct hdmi_codec_params *hparms)
1461{
1462 struct tegra_hdmi *hdmi = data;
1463 int ret = 0;
1464
1465 tegra_hdmi_audio_lock(hdmi);
1466
1467 hdmi->format.sample_rate = hparms->sample_rate;
1468 hdmi->format.channels = hparms->channels;
1469
1470 if (hdmi->pixel_clock && !hdmi->dvi)
1471 ret = tegra_hdmi_reconfigure_audio(hdmi);
1472
1473 tegra_hdmi_audio_unlock(hdmi);
1474
1475 return ret;
1476}
1477
1478static int tegra_hdmi_audio_startup(struct device *dev, void *data)
1479{
1480 struct tegra_hdmi *hdmi = data;
1481 int ret;
1482
1483 ret = host1x_client_resume(&hdmi->client);
1484 if (ret < 0)
1485 dev_err(hdmi->dev, "failed to resume: %d\n", ret);
1486
1487 return ret;
1488}
1489
1490static void tegra_hdmi_audio_shutdown(struct device *dev, void *data)
1491{
1492 struct tegra_hdmi *hdmi = data;
1493 int ret;
1494
1495 tegra_hdmi_audio_lock(hdmi);
1496
1497 hdmi->format.sample_rate = 0;
1498 hdmi->format.channels = 0;
1499
1500 tegra_hdmi_audio_unlock(hdmi);
1501
1502 ret = host1x_client_suspend(&hdmi->client);
1503 if (ret < 0)
1504 dev_err(hdmi->dev, "failed to suspend: %d\n", ret);
1505}
1506
1507static const struct hdmi_codec_ops tegra_hdmi_codec_ops = {
1508 .hw_params = tegra_hdmi_hw_params,
1509 .audio_startup = tegra_hdmi_audio_startup,
1510 .audio_shutdown = tegra_hdmi_audio_shutdown,
1511};
1512
1513static int tegra_hdmi_codec_register(struct tegra_hdmi *hdmi)
1514{
1515 struct hdmi_codec_pdata codec_data = {};
1516
1517 if (hdmi->config->has_hda)
1518 return 0;
1519
1520 codec_data.ops = &tegra_hdmi_codec_ops;
1521 codec_data.data = hdmi;
1522 codec_data.spdif = 1;
1523
1524 hdmi->audio_pdev = platform_device_register_data(hdmi->dev,
1525 HDMI_CODEC_DRV_NAME,
1526 PLATFORM_DEVID_AUTO,
1527 &codec_data,
1528 sizeof(codec_data));
1529 if (IS_ERR(hdmi->audio_pdev))
1530 return PTR_ERR(hdmi->audio_pdev);
1531
1532 hdmi->format.channels = 2;
1533
1534 return 0;
1535}
1536
1537static void tegra_hdmi_codec_unregister(struct tegra_hdmi *hdmi)
1538{
1539 if (hdmi->audio_pdev)
1540 platform_device_unregister(hdmi->audio_pdev);
1541}
1542
1543static int tegra_hdmi_init(struct host1x_client *client)
1544{
1545 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1546 struct drm_device *drm = dev_get_drvdata(client->host);
1547 int err;
1548
1549 hdmi->output.dev = client->dev;
1550
1551 drm_connector_init_with_ddc(drm, &hdmi->output.connector,
1552 &tegra_hdmi_connector_funcs,
1553 DRM_MODE_CONNECTOR_HDMIA,
1554 hdmi->output.ddc);
1555 drm_connector_helper_add(&hdmi->output.connector,
1556 &tegra_hdmi_connector_helper_funcs);
1557 hdmi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1558
1559 drm_simple_encoder_init(drm, &hdmi->output.encoder,
1560 DRM_MODE_ENCODER_TMDS);
1561 drm_encoder_helper_add(&hdmi->output.encoder,
1562 &tegra_hdmi_encoder_helper_funcs);
1563
1564 drm_connector_attach_encoder(&hdmi->output.connector,
1565 &hdmi->output.encoder);
1566 drm_connector_register(&hdmi->output.connector);
1567
1568 err = tegra_output_init(drm, &hdmi->output);
1569 if (err < 0) {
1570 dev_err(client->dev, "failed to initialize output: %d\n", err);
1571 return err;
1572 }
1573
1574 hdmi->output.encoder.possible_crtcs = 0x3;
1575
1576 err = regulator_enable(hdmi->hdmi);
1577 if (err < 0) {
1578 dev_err(client->dev, "failed to enable HDMI regulator: %d\n",
1579 err);
1580 goto output_exit;
1581 }
1582
1583 err = regulator_enable(hdmi->pll);
1584 if (err < 0) {
1585 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
1586 goto disable_hdmi;
1587 }
1588
1589 err = regulator_enable(hdmi->vdd);
1590 if (err < 0) {
1591 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
1592 goto disable_pll;
1593 }
1594
1595 err = tegra_hdmi_codec_register(hdmi);
1596 if (err < 0) {
1597 dev_err(hdmi->dev, "failed to register audio codec: %d\n", err);
1598 goto disable_vdd;
1599 }
1600
1601 return 0;
1602
1603disable_vdd:
1604 regulator_disable(hdmi->vdd);
1605disable_pll:
1606 regulator_disable(hdmi->pll);
1607disable_hdmi:
1608 regulator_disable(hdmi->hdmi);
1609output_exit:
1610 tegra_output_exit(&hdmi->output);
1611
1612 return err;
1613}
1614
1615static int tegra_hdmi_exit(struct host1x_client *client)
1616{
1617 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1618
1619 tegra_hdmi_codec_unregister(hdmi);
1620
1621 tegra_output_exit(&hdmi->output);
1622
1623 regulator_disable(hdmi->vdd);
1624 regulator_disable(hdmi->pll);
1625 regulator_disable(hdmi->hdmi);
1626
1627 return 0;
1628}
1629
1630static int tegra_hdmi_runtime_suspend(struct host1x_client *client)
1631{
1632 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1633 struct device *dev = client->dev;
1634 int err;
1635
1636 err = reset_control_assert(hdmi->rst);
1637 if (err < 0) {
1638 dev_err(dev, "failed to assert reset: %d\n", err);
1639 return err;
1640 }
1641
1642 usleep_range(1000, 2000);
1643
1644 clk_disable_unprepare(hdmi->clk);
1645 pm_runtime_put_sync(dev);
1646
1647 return 0;
1648}
1649
1650static int tegra_hdmi_runtime_resume(struct host1x_client *client)
1651{
1652 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1653 struct device *dev = client->dev;
1654 int err;
1655
1656 err = pm_runtime_resume_and_get(dev);
1657 if (err < 0) {
1658 dev_err(dev, "failed to get runtime PM: %d\n", err);
1659 return err;
1660 }
1661
1662 err = clk_prepare_enable(hdmi->clk);
1663 if (err < 0) {
1664 dev_err(dev, "failed to enable clock: %d\n", err);
1665 goto put_rpm;
1666 }
1667
1668 usleep_range(1000, 2000);
1669
1670 err = reset_control_deassert(hdmi->rst);
1671 if (err < 0) {
1672 dev_err(dev, "failed to deassert reset: %d\n", err);
1673 goto disable_clk;
1674 }
1675
1676 return 0;
1677
1678disable_clk:
1679 clk_disable_unprepare(hdmi->clk);
1680put_rpm:
1681 pm_runtime_put_sync(dev);
1682 return err;
1683}
1684
1685static const struct host1x_client_ops hdmi_client_ops = {
1686 .init = tegra_hdmi_init,
1687 .exit = tegra_hdmi_exit,
1688 .suspend = tegra_hdmi_runtime_suspend,
1689 .resume = tegra_hdmi_runtime_resume,
1690};
1691
1692static const struct tegra_hdmi_config tegra20_hdmi_config = {
1693 .tmds = tegra20_tmds_config,
1694 .num_tmds = ARRAY_SIZE(tegra20_tmds_config),
1695 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1696 .fuse_override_value = 1 << 31,
1697 .has_sor_io_peak_current = false,
1698 .has_hda = false,
1699 .has_hbr = false,
1700};
1701
1702static const struct tegra_hdmi_config tegra30_hdmi_config = {
1703 .tmds = tegra30_tmds_config,
1704 .num_tmds = ARRAY_SIZE(tegra30_tmds_config),
1705 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1706 .fuse_override_value = 1 << 31,
1707 .has_sor_io_peak_current = false,
1708 .has_hda = true,
1709 .has_hbr = false,
1710};
1711
1712static const struct tegra_hdmi_config tegra114_hdmi_config = {
1713 .tmds = tegra114_tmds_config,
1714 .num_tmds = ARRAY_SIZE(tegra114_tmds_config),
1715 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1716 .fuse_override_value = 1 << 31,
1717 .has_sor_io_peak_current = true,
1718 .has_hda = true,
1719 .has_hbr = true,
1720};
1721
1722static const struct tegra_hdmi_config tegra124_hdmi_config = {
1723 .tmds = tegra124_tmds_config,
1724 .num_tmds = ARRAY_SIZE(tegra124_tmds_config),
1725 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1726 .fuse_override_value = 1 << 31,
1727 .has_sor_io_peak_current = true,
1728 .has_hda = true,
1729 .has_hbr = true,
1730};
1731
1732static const struct of_device_id tegra_hdmi_of_match[] = {
1733 { .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config },
1734 { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config },
1735 { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config },
1736 { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config },
1737 { },
1738};
1739MODULE_DEVICE_TABLE(of, tegra_hdmi_of_match);
1740
1741static irqreturn_t tegra_hdmi_irq(int irq, void *data)
1742{
1743 struct tegra_hdmi *hdmi = data;
1744 u32 value;
1745
1746 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_INT_STATUS);
1747 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_INT_STATUS);
1748
1749 if (value & INT_CODEC_SCRATCH0) {
1750 unsigned int format;
1751 u32 value;
1752
1753 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0);
1754
1755 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
1756 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
1757
1758 tegra_hda_parse_format(format, &hdmi->format);
1759 tegra_hdmi_reconfigure_audio(hdmi);
1760 } else {
1761 tegra_hdmi_disable_audio_infoframe(hdmi);
1762 tegra_hdmi_disable_audio(hdmi);
1763 }
1764 }
1765
1766 return IRQ_HANDLED;
1767}
1768
1769static int tegra_hdmi_probe(struct platform_device *pdev)
1770{
1771 struct tegra_hdmi *hdmi;
1772 struct resource *regs;
1773 int err;
1774
1775 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1776 if (!hdmi)
1777 return -ENOMEM;
1778
1779 hdmi->config = of_device_get_match_data(&pdev->dev);
1780 hdmi->dev = &pdev->dev;
1781
1782 hdmi->audio_source = AUTO;
1783 hdmi->stereo = false;
1784 hdmi->dvi = false;
1785
1786 mutex_init(&hdmi->audio_lock);
1787
1788 hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1789 if (IS_ERR(hdmi->clk)) {
1790 dev_err(&pdev->dev, "failed to get clock\n");
1791 return PTR_ERR(hdmi->clk);
1792 }
1793
1794 hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi");
1795 if (IS_ERR(hdmi->rst)) {
1796 dev_err(&pdev->dev, "failed to get reset\n");
1797 return PTR_ERR(hdmi->rst);
1798 }
1799
1800 hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1801 if (IS_ERR(hdmi->clk_parent))
1802 return PTR_ERR(hdmi->clk_parent);
1803
1804 err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1805 if (err < 0) {
1806 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1807 return err;
1808 }
1809
1810 hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi");
1811 err = PTR_ERR_OR_ZERO(hdmi->hdmi);
1812 if (err)
1813 return dev_err_probe(&pdev->dev, err,
1814 "failed to get HDMI regulator\n");
1815
1816 hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1817 err = PTR_ERR_OR_ZERO(hdmi->pll);
1818 if (err)
1819 return dev_err_probe(&pdev->dev, err,
1820 "failed to get PLL regulator\n");
1821
1822 hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1823 err = PTR_ERR_OR_ZERO(hdmi->vdd);
1824 if (err)
1825 return dev_err_probe(&pdev->dev, err,
1826 "failed to get VDD regulator\n");
1827
1828 hdmi->output.dev = &pdev->dev;
1829
1830 err = tegra_output_probe(&hdmi->output);
1831 if (err < 0)
1832 return err;
1833
1834 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1835 hdmi->regs = devm_ioremap_resource(&pdev->dev, regs);
1836 if (IS_ERR(hdmi->regs))
1837 return PTR_ERR(hdmi->regs);
1838
1839 err = platform_get_irq(pdev, 0);
1840 if (err < 0)
1841 return err;
1842
1843 hdmi->irq = err;
1844
1845 err = devm_request_irq(hdmi->dev, hdmi->irq, tegra_hdmi_irq, 0,
1846 dev_name(hdmi->dev), hdmi);
1847 if (err < 0) {
1848 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n",
1849 hdmi->irq, err);
1850 return err;
1851 }
1852
1853 platform_set_drvdata(pdev, hdmi);
1854
1855 err = devm_pm_runtime_enable(&pdev->dev);
1856 if (err)
1857 return err;
1858
1859 err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
1860 if (err)
1861 return err;
1862
1863 INIT_LIST_HEAD(&hdmi->client.list);
1864 hdmi->client.ops = &hdmi_client_ops;
1865 hdmi->client.dev = &pdev->dev;
1866
1867 err = host1x_client_register(&hdmi->client);
1868 if (err < 0) {
1869 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1870 err);
1871 return err;
1872 }
1873
1874 return 0;
1875}
1876
1877static int tegra_hdmi_remove(struct platform_device *pdev)
1878{
1879 struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1880 int err;
1881
1882 err = host1x_client_unregister(&hdmi->client);
1883 if (err < 0) {
1884 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1885 err);
1886 return err;
1887 }
1888
1889 tegra_output_remove(&hdmi->output);
1890
1891 return 0;
1892}
1893
1894struct platform_driver tegra_hdmi_driver = {
1895 .driver = {
1896 .name = "tegra-hdmi",
1897 .of_match_table = tegra_hdmi_of_match,
1898 },
1899 .probe = tegra_hdmi_probe,
1900 .remove = tegra_hdmi_remove,
1901};