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1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
11#include <linux/debugfs.h>
12#include <linux/gpio.h>
13#include <linux/hdmi.h>
14#include <linux/pm_runtime.h>
15#include <linux/regulator/consumer.h>
16#include <linux/reset.h>
17
18#include <drm/drm_atomic_helper.h>
19#include <drm/drm_crtc.h>
20#include <drm/drm_crtc_helper.h>
21
22#include <sound/hda_verbs.h>
23
24#include "hdmi.h"
25#include "drm.h"
26#include "dc.h"
27
28#define HDMI_ELD_BUFFER_SIZE 96
29
30struct tmds_config {
31 unsigned int pclk;
32 u32 pll0;
33 u32 pll1;
34 u32 pe_current;
35 u32 drive_current;
36 u32 peak_current;
37};
38
39struct tegra_hdmi_config {
40 const struct tmds_config *tmds;
41 unsigned int num_tmds;
42
43 unsigned long fuse_override_offset;
44 u32 fuse_override_value;
45
46 bool has_sor_io_peak_current;
47 bool has_hda;
48 bool has_hbr;
49};
50
51struct tegra_hdmi {
52 struct host1x_client client;
53 struct tegra_output output;
54 struct device *dev;
55
56 struct regulator *hdmi;
57 struct regulator *pll;
58 struct regulator *vdd;
59
60 void __iomem *regs;
61 unsigned int irq;
62
63 struct clk *clk_parent;
64 struct clk *clk;
65 struct reset_control *rst;
66
67 const struct tegra_hdmi_config *config;
68
69 unsigned int audio_source;
70 unsigned int audio_sample_rate;
71 unsigned int audio_channels;
72
73 unsigned int pixel_clock;
74 bool stereo;
75 bool dvi;
76
77 struct drm_info_list *debugfs_files;
78 struct drm_minor *minor;
79 struct dentry *debugfs;
80};
81
82static inline struct tegra_hdmi *
83host1x_client_to_hdmi(struct host1x_client *client)
84{
85 return container_of(client, struct tegra_hdmi, client);
86}
87
88static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
89{
90 return container_of(output, struct tegra_hdmi, output);
91}
92
93#define HDMI_AUDIOCLK_FREQ 216000000
94#define HDMI_REKEY_DEFAULT 56
95
96enum {
97 AUTO = 0,
98 SPDIF,
99 HDA,
100};
101
102static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi,
103 unsigned long offset)
104{
105 return readl(hdmi->regs + (offset << 2));
106}
107
108static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value,
109 unsigned long offset)
110{
111 writel(value, hdmi->regs + (offset << 2));
112}
113
114struct tegra_hdmi_audio_config {
115 unsigned int pclk;
116 unsigned int n;
117 unsigned int cts;
118 unsigned int aval;
119};
120
121static const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
122 { 25200000, 4096, 25200, 24000 },
123 { 27000000, 4096, 27000, 24000 },
124 { 74250000, 4096, 74250, 24000 },
125 { 148500000, 4096, 148500, 24000 },
126 { 0, 0, 0, 0 },
127};
128
129static const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
130 { 25200000, 5880, 26250, 25000 },
131 { 27000000, 5880, 28125, 25000 },
132 { 74250000, 4704, 61875, 20000 },
133 { 148500000, 4704, 123750, 20000 },
134 { 0, 0, 0, 0 },
135};
136
137static const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
138 { 25200000, 6144, 25200, 24000 },
139 { 27000000, 6144, 27000, 24000 },
140 { 74250000, 6144, 74250, 24000 },
141 { 148500000, 6144, 148500, 24000 },
142 { 0, 0, 0, 0 },
143};
144
145static const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
146 { 25200000, 11760, 26250, 25000 },
147 { 27000000, 11760, 28125, 25000 },
148 { 74250000, 9408, 61875, 20000 },
149 { 148500000, 9408, 123750, 20000 },
150 { 0, 0, 0, 0 },
151};
152
153static const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
154 { 25200000, 12288, 25200, 24000 },
155 { 27000000, 12288, 27000, 24000 },
156 { 74250000, 12288, 74250, 24000 },
157 { 148500000, 12288, 148500, 24000 },
158 { 0, 0, 0, 0 },
159};
160
161static const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
162 { 25200000, 23520, 26250, 25000 },
163 { 27000000, 23520, 28125, 25000 },
164 { 74250000, 18816, 61875, 20000 },
165 { 148500000, 18816, 123750, 20000 },
166 { 0, 0, 0, 0 },
167};
168
169static const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
170 { 25200000, 24576, 25200, 24000 },
171 { 27000000, 24576, 27000, 24000 },
172 { 74250000, 24576, 74250, 24000 },
173 { 148500000, 24576, 148500, 24000 },
174 { 0, 0, 0, 0 },
175};
176
177static const struct tmds_config tegra20_tmds_config[] = {
178 { /* slow pixel clock modes */
179 .pclk = 27000000,
180 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
181 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
182 SOR_PLL_TX_REG_LOAD(3),
183 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
184 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
185 PE_CURRENT1(PE_CURRENT_0_0_mA) |
186 PE_CURRENT2(PE_CURRENT_0_0_mA) |
187 PE_CURRENT3(PE_CURRENT_0_0_mA),
188 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
189 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
190 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
191 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
192 },
193 { /* high pixel clock modes */
194 .pclk = UINT_MAX,
195 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
196 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
197 SOR_PLL_TX_REG_LOAD(3),
198 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
199 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
200 PE_CURRENT1(PE_CURRENT_6_0_mA) |
201 PE_CURRENT2(PE_CURRENT_6_0_mA) |
202 PE_CURRENT3(PE_CURRENT_6_0_mA),
203 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
204 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
205 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
206 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
207 },
208};
209
210static const struct tmds_config tegra30_tmds_config[] = {
211 { /* 480p modes */
212 .pclk = 27000000,
213 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
214 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
215 SOR_PLL_TX_REG_LOAD(0),
216 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
217 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
218 PE_CURRENT1(PE_CURRENT_0_0_mA) |
219 PE_CURRENT2(PE_CURRENT_0_0_mA) |
220 PE_CURRENT3(PE_CURRENT_0_0_mA),
221 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
222 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
223 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
224 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
225 }, { /* 720p modes */
226 .pclk = 74250000,
227 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
228 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
229 SOR_PLL_TX_REG_LOAD(0),
230 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
231 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
232 PE_CURRENT1(PE_CURRENT_5_0_mA) |
233 PE_CURRENT2(PE_CURRENT_5_0_mA) |
234 PE_CURRENT3(PE_CURRENT_5_0_mA),
235 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
236 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
237 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
238 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
239 }, { /* 1080p modes */
240 .pclk = UINT_MAX,
241 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
242 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
243 SOR_PLL_TX_REG_LOAD(0),
244 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
245 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
246 PE_CURRENT1(PE_CURRENT_5_0_mA) |
247 PE_CURRENT2(PE_CURRENT_5_0_mA) |
248 PE_CURRENT3(PE_CURRENT_5_0_mA),
249 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
250 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
251 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
252 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
253 },
254};
255
256static const struct tmds_config tegra114_tmds_config[] = {
257 { /* 480p/576p / 25.2MHz/27MHz modes */
258 .pclk = 27000000,
259 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
260 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
261 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
262 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
263 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
264 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
265 PE_CURRENT3(PE_CURRENT_0_mA_T114),
266 .drive_current =
267 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
268 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
269 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
270 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
271 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
272 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
273 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
274 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
275 }, { /* 720p / 74.25MHz modes */
276 .pclk = 74250000,
277 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
278 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
279 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
280 SOR_PLL_TMDS_TERMADJ(0),
281 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
282 PE_CURRENT1(PE_CURRENT_15_mA_T114) |
283 PE_CURRENT2(PE_CURRENT_15_mA_T114) |
284 PE_CURRENT3(PE_CURRENT_15_mA_T114),
285 .drive_current =
286 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
287 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
288 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
289 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
290 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
291 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
292 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
293 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
294 }, { /* 1080p / 148.5MHz modes */
295 .pclk = 148500000,
296 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
297 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
298 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
299 SOR_PLL_TMDS_TERMADJ(0),
300 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
301 PE_CURRENT1(PE_CURRENT_10_mA_T114) |
302 PE_CURRENT2(PE_CURRENT_10_mA_T114) |
303 PE_CURRENT3(PE_CURRENT_10_mA_T114),
304 .drive_current =
305 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
306 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
307 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
308 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
309 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
310 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
311 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
312 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
313 }, { /* 225/297MHz modes */
314 .pclk = UINT_MAX,
315 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
316 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
317 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
318 | SOR_PLL_TMDS_TERM_ENABLE,
319 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
320 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
321 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
322 PE_CURRENT3(PE_CURRENT_0_mA_T114),
323 .drive_current =
324 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
325 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
326 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
327 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
328 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
329 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
330 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
331 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
332 },
333};
334
335static const struct tmds_config tegra124_tmds_config[] = {
336 { /* 480p/576p / 25.2MHz/27MHz modes */
337 .pclk = 27000000,
338 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
339 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
340 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
341 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
342 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
343 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
344 PE_CURRENT3(PE_CURRENT_0_mA_T114),
345 .drive_current =
346 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
347 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
348 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
349 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
350 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
351 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
352 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
353 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
354 }, { /* 720p / 74.25MHz modes */
355 .pclk = 74250000,
356 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
357 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
358 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
359 SOR_PLL_TMDS_TERMADJ(0),
360 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
361 PE_CURRENT1(PE_CURRENT_15_mA_T114) |
362 PE_CURRENT2(PE_CURRENT_15_mA_T114) |
363 PE_CURRENT3(PE_CURRENT_15_mA_T114),
364 .drive_current =
365 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
366 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
367 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
368 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
369 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
370 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
371 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
372 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
373 }, { /* 1080p / 148.5MHz modes */
374 .pclk = 148500000,
375 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
376 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
377 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
378 SOR_PLL_TMDS_TERMADJ(0),
379 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
380 PE_CURRENT1(PE_CURRENT_10_mA_T114) |
381 PE_CURRENT2(PE_CURRENT_10_mA_T114) |
382 PE_CURRENT3(PE_CURRENT_10_mA_T114),
383 .drive_current =
384 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
385 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
386 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
387 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
388 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
389 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
390 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
391 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
392 }, { /* 225/297MHz modes */
393 .pclk = UINT_MAX,
394 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
395 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
396 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
397 | SOR_PLL_TMDS_TERM_ENABLE,
398 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
399 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
400 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
401 PE_CURRENT3(PE_CURRENT_0_mA_T114),
402 .drive_current =
403 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
404 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
405 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
406 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
407 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
408 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
409 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
410 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
411 },
412};
413
414static const struct tegra_hdmi_audio_config *
415tegra_hdmi_get_audio_config(unsigned int sample_rate, unsigned int pclk)
416{
417 const struct tegra_hdmi_audio_config *table;
418
419 switch (sample_rate) {
420 case 32000:
421 table = tegra_hdmi_audio_32k;
422 break;
423
424 case 44100:
425 table = tegra_hdmi_audio_44_1k;
426 break;
427
428 case 48000:
429 table = tegra_hdmi_audio_48k;
430 break;
431
432 case 88200:
433 table = tegra_hdmi_audio_88_2k;
434 break;
435
436 case 96000:
437 table = tegra_hdmi_audio_96k;
438 break;
439
440 case 176400:
441 table = tegra_hdmi_audio_176_4k;
442 break;
443
444 case 192000:
445 table = tegra_hdmi_audio_192k;
446 break;
447
448 default:
449 return NULL;
450 }
451
452 while (table->pclk) {
453 if (table->pclk == pclk)
454 return table;
455
456 table++;
457 }
458
459 return NULL;
460}
461
462static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
463{
464 const unsigned int freqs[] = {
465 32000, 44100, 48000, 88200, 96000, 176400, 192000
466 };
467 unsigned int i;
468
469 for (i = 0; i < ARRAY_SIZE(freqs); i++) {
470 unsigned int f = freqs[i];
471 unsigned int eight_half;
472 unsigned int delta;
473 u32 value;
474
475 if (f > 96000)
476 delta = 2;
477 else if (f > 48000)
478 delta = 6;
479 else
480 delta = 9;
481
482 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
483 value = AUDIO_FS_LOW(eight_half - delta) |
484 AUDIO_FS_HIGH(eight_half + delta);
485 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
486 }
487}
488
489static void tegra_hdmi_write_aval(struct tegra_hdmi *hdmi, u32 value)
490{
491 static const struct {
492 unsigned int sample_rate;
493 unsigned int offset;
494 } regs[] = {
495 { 32000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 },
496 { 44100, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 },
497 { 48000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 },
498 { 88200, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 },
499 { 96000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 },
500 { 176400, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 },
501 { 192000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 },
502 };
503 unsigned int i;
504
505 for (i = 0; i < ARRAY_SIZE(regs); i++) {
506 if (regs[i].sample_rate == hdmi->audio_sample_rate) {
507 tegra_hdmi_writel(hdmi, value, regs[i].offset);
508 break;
509 }
510 }
511}
512
513static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi)
514{
515 const struct tegra_hdmi_audio_config *config;
516 u32 source, value;
517
518 switch (hdmi->audio_source) {
519 case HDA:
520 if (hdmi->config->has_hda)
521 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
522 else
523 return -EINVAL;
524
525 break;
526
527 case SPDIF:
528 if (hdmi->config->has_hda)
529 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
530 else
531 source = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
532 break;
533
534 default:
535 if (hdmi->config->has_hda)
536 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
537 else
538 source = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
539 break;
540 }
541
542 /*
543 * Tegra30 and later use a slightly modified version of the register
544 * layout to accomodate for changes related to supporting HDA as the
545 * audio input source for HDMI. The source select field has moved to
546 * the SOR_AUDIO_CNTRL0 register, but the error tolerance and frames
547 * per block fields remain in the AUDIO_CNTRL0 register.
548 */
549 if (hdmi->config->has_hda) {
550 /*
551 * Inject null samples into the audio FIFO for every frame in
552 * which the codec did not receive any samples. This applies
553 * to stereo LPCM only.
554 *
555 * XXX: This seems to be a remnant of MCP days when this was
556 * used to work around issues with monitors not being able to
557 * play back system startup sounds early. It is possibly not
558 * needed on Linux at all.
559 */
560 if (hdmi->audio_channels == 2)
561 value = SOR_AUDIO_CNTRL0_INJECT_NULLSMPL;
562 else
563 value = 0;
564
565 value |= source;
566
567 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
568 }
569
570 /*
571 * On Tegra20, HDA is not a supported audio source and the source
572 * select field is part of the AUDIO_CNTRL0 register.
573 */
574 value = AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
575 AUDIO_CNTRL0_ERROR_TOLERANCE(6);
576
577 if (!hdmi->config->has_hda)
578 value |= source;
579
580 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
581
582 /*
583 * Advertise support for High Bit-Rate on Tegra114 and later.
584 */
585 if (hdmi->config->has_hbr) {
586 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
587 value |= SOR_AUDIO_SPARE0_HBR_ENABLE;
588 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
589 }
590
591 config = tegra_hdmi_get_audio_config(hdmi->audio_sample_rate,
592 hdmi->pixel_clock);
593 if (!config) {
594 dev_err(hdmi->dev,
595 "cannot set audio to %u Hz at %u Hz pixel clock\n",
596 hdmi->audio_sample_rate, hdmi->pixel_clock);
597 return -EINVAL;
598 }
599
600 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
601
602 value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
603 AUDIO_N_VALUE(config->n - 1);
604 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
605
606 tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
607 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
608
609 tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config->cts),
610 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
611
612 value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
613 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
614
615 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
616 value &= ~AUDIO_N_RESETF;
617 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
618
619 if (hdmi->config->has_hda)
620 tegra_hdmi_write_aval(hdmi, config->aval);
621
622 tegra_hdmi_setup_audio_fs_tables(hdmi);
623
624 return 0;
625}
626
627static void tegra_hdmi_disable_audio(struct tegra_hdmi *hdmi)
628{
629 u32 value;
630
631 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
632 value &= ~GENERIC_CTRL_AUDIO;
633 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
634}
635
636static void tegra_hdmi_enable_audio(struct tegra_hdmi *hdmi)
637{
638 u32 value;
639
640 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
641 value |= GENERIC_CTRL_AUDIO;
642 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
643}
644
645static void tegra_hdmi_write_eld(struct tegra_hdmi *hdmi)
646{
647 size_t length = drm_eld_size(hdmi->output.connector.eld), i;
648 u32 value;
649
650 for (i = 0; i < length; i++)
651 tegra_hdmi_writel(hdmi, i << 8 | hdmi->output.connector.eld[i],
652 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
653
654 /*
655 * The HDA codec will always report an ELD buffer size of 96 bytes and
656 * the HDA codec driver will check that each byte read from the buffer
657 * is valid. Therefore every byte must be written, even if no 96 bytes
658 * were parsed from EDID.
659 */
660 for (i = length; i < HDMI_ELD_BUFFER_SIZE; i++)
661 tegra_hdmi_writel(hdmi, i << 8 | 0,
662 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
663
664 value = SOR_AUDIO_HDA_PRESENSE_VALID | SOR_AUDIO_HDA_PRESENSE_PRESENT;
665 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
666}
667
668static inline u32 tegra_hdmi_subpack(const u8 *ptr, size_t size)
669{
670 u32 value = 0;
671 size_t i;
672
673 for (i = size; i > 0; i--)
674 value = (value << 8) | ptr[i - 1];
675
676 return value;
677}
678
679static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
680 size_t size)
681{
682 const u8 *ptr = data;
683 unsigned long offset;
684 size_t i, j;
685 u32 value;
686
687 switch (ptr[0]) {
688 case HDMI_INFOFRAME_TYPE_AVI:
689 offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
690 break;
691
692 case HDMI_INFOFRAME_TYPE_AUDIO:
693 offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
694 break;
695
696 case HDMI_INFOFRAME_TYPE_VENDOR:
697 offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
698 break;
699
700 default:
701 dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
702 ptr[0]);
703 return;
704 }
705
706 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
707 INFOFRAME_HEADER_VERSION(ptr[1]) |
708 INFOFRAME_HEADER_LEN(ptr[2]);
709 tegra_hdmi_writel(hdmi, value, offset);
710 offset++;
711
712 /*
713 * Each subpack contains 7 bytes, divided into:
714 * - subpack_low: bytes 0 - 3
715 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
716 */
717 for (i = 3, j = 0; i < size; i += 7, j += 8) {
718 size_t rem = size - i, num = min_t(size_t, rem, 4);
719
720 value = tegra_hdmi_subpack(&ptr[i], num);
721 tegra_hdmi_writel(hdmi, value, offset++);
722
723 num = min_t(size_t, rem - num, 3);
724
725 value = tegra_hdmi_subpack(&ptr[i + 4], num);
726 tegra_hdmi_writel(hdmi, value, offset++);
727 }
728}
729
730static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
731 struct drm_display_mode *mode)
732{
733 struct hdmi_avi_infoframe frame;
734 u8 buffer[17];
735 ssize_t err;
736
737 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
738 if (err < 0) {
739 dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
740 return;
741 }
742
743 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
744 if (err < 0) {
745 dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
746 return;
747 }
748
749 tegra_hdmi_write_infopack(hdmi, buffer, err);
750}
751
752static void tegra_hdmi_disable_avi_infoframe(struct tegra_hdmi *hdmi)
753{
754 u32 value;
755
756 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
757 value &= ~INFOFRAME_CTRL_ENABLE;
758 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
759}
760
761static void tegra_hdmi_enable_avi_infoframe(struct tegra_hdmi *hdmi)
762{
763 u32 value;
764
765 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
766 value |= INFOFRAME_CTRL_ENABLE;
767 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
768}
769
770static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
771{
772 struct hdmi_audio_infoframe frame;
773 u8 buffer[14];
774 ssize_t err;
775
776 err = hdmi_audio_infoframe_init(&frame);
777 if (err < 0) {
778 dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n",
779 err);
780 return;
781 }
782
783 frame.channels = hdmi->audio_channels;
784
785 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
786 if (err < 0) {
787 dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
788 err);
789 return;
790 }
791
792 /*
793 * The audio infoframe has only one set of subpack registers, so the
794 * infoframe needs to be truncated. One set of subpack registers can
795 * contain 7 bytes. Including the 3 byte header only the first 10
796 * bytes can be programmed.
797 */
798 tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err));
799}
800
801static void tegra_hdmi_disable_audio_infoframe(struct tegra_hdmi *hdmi)
802{
803 u32 value;
804
805 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
806 value &= ~INFOFRAME_CTRL_ENABLE;
807 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
808}
809
810static void tegra_hdmi_enable_audio_infoframe(struct tegra_hdmi *hdmi)
811{
812 u32 value;
813
814 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
815 value |= INFOFRAME_CTRL_ENABLE;
816 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
817}
818
819static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
820{
821 struct hdmi_vendor_infoframe frame;
822 u8 buffer[10];
823 ssize_t err;
824
825 hdmi_vendor_infoframe_init(&frame);
826 frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING;
827
828 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
829 if (err < 0) {
830 dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
831 err);
832 return;
833 }
834
835 tegra_hdmi_write_infopack(hdmi, buffer, err);
836}
837
838static void tegra_hdmi_disable_stereo_infoframe(struct tegra_hdmi *hdmi)
839{
840 u32 value;
841
842 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
843 value &= ~GENERIC_CTRL_ENABLE;
844 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
845}
846
847static void tegra_hdmi_enable_stereo_infoframe(struct tegra_hdmi *hdmi)
848{
849 u32 value;
850
851 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
852 value |= GENERIC_CTRL_ENABLE;
853 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
854}
855
856static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
857 const struct tmds_config *tmds)
858{
859 u32 value;
860
861 tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
862 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
863 tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
864
865 tegra_hdmi_writel(hdmi, tmds->drive_current,
866 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
867
868 value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset);
869 value |= hdmi->config->fuse_override_value;
870 tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset);
871
872 if (hdmi->config->has_sor_io_peak_current)
873 tegra_hdmi_writel(hdmi, tmds->peak_current,
874 HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
875}
876
877static bool tegra_output_is_hdmi(struct tegra_output *output)
878{
879 struct edid *edid;
880
881 if (!output->connector.edid_blob_ptr)
882 return false;
883
884 edid = (struct edid *)output->connector.edid_blob_ptr->data;
885
886 return drm_detect_hdmi_monitor(edid);
887}
888
889static enum drm_connector_status
890tegra_hdmi_connector_detect(struct drm_connector *connector, bool force)
891{
892 struct tegra_output *output = connector_to_output(connector);
893 struct tegra_hdmi *hdmi = to_hdmi(output);
894 enum drm_connector_status status;
895
896 status = tegra_output_connector_detect(connector, force);
897 if (status == connector_status_connected)
898 return status;
899
900 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
901 return status;
902}
903
904static const struct drm_connector_funcs tegra_hdmi_connector_funcs = {
905 .dpms = drm_atomic_helper_connector_dpms,
906 .reset = drm_atomic_helper_connector_reset,
907 .detect = tegra_hdmi_connector_detect,
908 .fill_modes = drm_helper_probe_single_connector_modes,
909 .destroy = tegra_output_connector_destroy,
910 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
911 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
912};
913
914static enum drm_mode_status
915tegra_hdmi_connector_mode_valid(struct drm_connector *connector,
916 struct drm_display_mode *mode)
917{
918 struct tegra_output *output = connector_to_output(connector);
919 struct tegra_hdmi *hdmi = to_hdmi(output);
920 unsigned long pclk = mode->clock * 1000;
921 enum drm_mode_status status = MODE_OK;
922 struct clk *parent;
923 long err;
924
925 parent = clk_get_parent(hdmi->clk_parent);
926
927 err = clk_round_rate(parent, pclk * 4);
928 if (err <= 0)
929 status = MODE_NOCLOCK;
930
931 return status;
932}
933
934static const struct drm_connector_helper_funcs
935tegra_hdmi_connector_helper_funcs = {
936 .get_modes = tegra_output_connector_get_modes,
937 .mode_valid = tegra_hdmi_connector_mode_valid,
938};
939
940static const struct drm_encoder_funcs tegra_hdmi_encoder_funcs = {
941 .destroy = tegra_output_encoder_destroy,
942};
943
944static void tegra_hdmi_encoder_disable(struct drm_encoder *encoder)
945{
946 struct tegra_output *output = encoder_to_output(encoder);
947 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
948 struct tegra_hdmi *hdmi = to_hdmi(output);
949 u32 value;
950
951 /*
952 * The following accesses registers of the display controller, so make
953 * sure it's only executed when the output is attached to one.
954 */
955 if (dc) {
956 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
957 value &= ~HDMI_ENABLE;
958 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
959
960 tegra_dc_commit(dc);
961 }
962
963 if (!hdmi->dvi) {
964 if (hdmi->stereo)
965 tegra_hdmi_disable_stereo_infoframe(hdmi);
966
967 tegra_hdmi_disable_audio_infoframe(hdmi);
968 tegra_hdmi_disable_avi_infoframe(hdmi);
969 tegra_hdmi_disable_audio(hdmi);
970 }
971
972 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_ENABLE);
973 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_MASK);
974
975 pm_runtime_put(hdmi->dev);
976}
977
978static void tegra_hdmi_encoder_enable(struct drm_encoder *encoder)
979{
980 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
981 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
982 struct tegra_output *output = encoder_to_output(encoder);
983 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
984 struct tegra_hdmi *hdmi = to_hdmi(output);
985 unsigned int pulse_start, div82;
986 int retries = 1000;
987 u32 value;
988 int err;
989
990 pm_runtime_get_sync(hdmi->dev);
991
992 /*
993 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
994 * is used for interoperability between the HDA codec driver and the
995 * HDMI driver.
996 */
997 tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_ENABLE);
998 tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_MASK);
999
1000 hdmi->pixel_clock = mode->clock * 1000;
1001 h_sync_width = mode->hsync_end - mode->hsync_start;
1002 h_back_porch = mode->htotal - mode->hsync_end;
1003 h_front_porch = mode->hsync_start - mode->hdisplay;
1004
1005 err = clk_set_rate(hdmi->clk, hdmi->pixel_clock);
1006 if (err < 0) {
1007 dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n",
1008 err);
1009 }
1010
1011 DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk));
1012
1013 /* power up sequence */
1014 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1015 value &= ~SOR_PLL_PDBG;
1016 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1017
1018 usleep_range(10, 20);
1019
1020 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1021 value &= ~SOR_PLL_PWR;
1022 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1023
1024 tegra_dc_writel(dc, VSYNC_H_POSITION(1),
1025 DC_DISP_DISP_TIMING_OPTIONS);
1026 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
1027 DC_DISP_DISP_COLOR_CONTROL);
1028
1029 /* video_preamble uses h_pulse2 */
1030 pulse_start = 1 + h_sync_width + h_back_porch - 10;
1031
1032 tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1033
1034 value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
1035 PULSE_LAST_END_A;
1036 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
1037
1038 value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
1039 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
1040
1041 value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
1042 VSYNC_WINDOW_ENABLE;
1043 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1044
1045 if (dc->pipe)
1046 value = HDMI_SRC_DISPLAYB;
1047 else
1048 value = HDMI_SRC_DISPLAYA;
1049
1050 if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
1051 (mode->vdisplay == 576)))
1052 tegra_hdmi_writel(hdmi,
1053 value | ARM_VIDEO_RANGE_FULL,
1054 HDMI_NV_PDISP_INPUT_CONTROL);
1055 else
1056 tegra_hdmi_writel(hdmi,
1057 value | ARM_VIDEO_RANGE_LIMITED,
1058 HDMI_NV_PDISP_INPUT_CONTROL);
1059
1060 div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
1061 value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
1062 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
1063
1064 hdmi->dvi = !tegra_output_is_hdmi(output);
1065 if (!hdmi->dvi) {
1066 err = tegra_hdmi_setup_audio(hdmi);
1067 if (err < 0)
1068 hdmi->dvi = true;
1069 }
1070
1071 if (hdmi->config->has_hda)
1072 tegra_hdmi_write_eld(hdmi);
1073
1074 rekey = HDMI_REKEY_DEFAULT;
1075 value = HDMI_CTRL_REKEY(rekey);
1076 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
1077 h_front_porch - rekey - 18) / 32);
1078
1079 if (!hdmi->dvi)
1080 value |= HDMI_CTRL_ENABLE;
1081
1082 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
1083
1084 if (!hdmi->dvi) {
1085 tegra_hdmi_setup_avi_infoframe(hdmi, mode);
1086 tegra_hdmi_setup_audio_infoframe(hdmi);
1087
1088 if (hdmi->stereo)
1089 tegra_hdmi_setup_stereo_infoframe(hdmi);
1090 }
1091
1092 /* TMDS CONFIG */
1093 for (i = 0; i < hdmi->config->num_tmds; i++) {
1094 if (hdmi->pixel_clock <= hdmi->config->tmds[i].pclk) {
1095 tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]);
1096 break;
1097 }
1098 }
1099
1100 tegra_hdmi_writel(hdmi,
1101 SOR_SEQ_PU_PC(0) |
1102 SOR_SEQ_PU_PC_ALT(0) |
1103 SOR_SEQ_PD_PC(8) |
1104 SOR_SEQ_PD_PC_ALT(8),
1105 HDMI_NV_PDISP_SOR_SEQ_CTL);
1106
1107 value = SOR_SEQ_INST_WAIT_TIME(1) |
1108 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
1109 SOR_SEQ_INST_HALT |
1110 SOR_SEQ_INST_PIN_A_LOW |
1111 SOR_SEQ_INST_PIN_B_LOW |
1112 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
1113
1114 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
1115 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
1116
1117 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM);
1118 value &= ~SOR_CSTM_ROTCLK(~0);
1119 value |= SOR_CSTM_ROTCLK(2);
1120 value |= SOR_CSTM_PLLDIV;
1121 value &= ~SOR_CSTM_LVDS_ENABLE;
1122 value &= ~SOR_CSTM_MODE_MASK;
1123 value |= SOR_CSTM_MODE_TMDS;
1124 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
1125
1126 /* start SOR */
1127 tegra_hdmi_writel(hdmi,
1128 SOR_PWR_NORMAL_STATE_PU |
1129 SOR_PWR_NORMAL_START_NORMAL |
1130 SOR_PWR_SAFE_STATE_PD |
1131 SOR_PWR_SETTING_NEW_TRIGGER,
1132 HDMI_NV_PDISP_SOR_PWR);
1133 tegra_hdmi_writel(hdmi,
1134 SOR_PWR_NORMAL_STATE_PU |
1135 SOR_PWR_NORMAL_START_NORMAL |
1136 SOR_PWR_SAFE_STATE_PD |
1137 SOR_PWR_SETTING_NEW_DONE,
1138 HDMI_NV_PDISP_SOR_PWR);
1139
1140 do {
1141 BUG_ON(--retries < 0);
1142 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
1143 } while (value & SOR_PWR_SETTING_NEW_PENDING);
1144
1145 value = SOR_STATE_ASY_CRCMODE_COMPLETE |
1146 SOR_STATE_ASY_OWNER_HEAD0 |
1147 SOR_STATE_ASY_SUBOWNER_BOTH |
1148 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
1149 SOR_STATE_ASY_DEPOL_POS;
1150
1151 /* setup sync polarities */
1152 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1153 value |= SOR_STATE_ASY_HSYNCPOL_POS;
1154
1155 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1156 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
1157
1158 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1159 value |= SOR_STATE_ASY_VSYNCPOL_POS;
1160
1161 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1162 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
1163
1164 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
1165
1166 value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
1167 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
1168
1169 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1170 tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
1171 tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
1172 HDMI_NV_PDISP_SOR_STATE1);
1173 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1174
1175 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1176 value |= HDMI_ENABLE;
1177 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1178
1179 tegra_dc_commit(dc);
1180
1181 if (!hdmi->dvi) {
1182 tegra_hdmi_enable_avi_infoframe(hdmi);
1183 tegra_hdmi_enable_audio_infoframe(hdmi);
1184 tegra_hdmi_enable_audio(hdmi);
1185
1186 if (hdmi->stereo)
1187 tegra_hdmi_enable_stereo_infoframe(hdmi);
1188 }
1189
1190 /* TODO: add HDCP support */
1191}
1192
1193static int
1194tegra_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1195 struct drm_crtc_state *crtc_state,
1196 struct drm_connector_state *conn_state)
1197{
1198 struct tegra_output *output = encoder_to_output(encoder);
1199 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1200 unsigned long pclk = crtc_state->mode.clock * 1000;
1201 struct tegra_hdmi *hdmi = to_hdmi(output);
1202 int err;
1203
1204 err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent,
1205 pclk, 0);
1206 if (err < 0) {
1207 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1208 return err;
1209 }
1210
1211 return err;
1212}
1213
1214static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = {
1215 .disable = tegra_hdmi_encoder_disable,
1216 .enable = tegra_hdmi_encoder_enable,
1217 .atomic_check = tegra_hdmi_encoder_atomic_check,
1218};
1219
1220static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
1221{
1222 struct drm_info_node *node = s->private;
1223 struct tegra_hdmi *hdmi = node->info_ent->data;
1224 struct drm_crtc *crtc = hdmi->output.encoder.crtc;
1225 struct drm_device *drm = node->minor->dev;
1226 int err = 0;
1227
1228 drm_modeset_lock_all(drm);
1229
1230 if (!crtc || !crtc->state->active) {
1231 err = -EBUSY;
1232 goto unlock;
1233 }
1234
1235#define DUMP_REG(name) \
1236 seq_printf(s, "%-56s %#05x %08x\n", #name, name, \
1237 tegra_hdmi_readl(hdmi, name))
1238
1239 DUMP_REG(HDMI_CTXSW);
1240 DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
1241 DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
1242 DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
1243 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
1244 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
1245 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
1246 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
1247 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
1248 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
1249 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
1250 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
1251 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
1252 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
1253 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
1254 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
1255 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
1256 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
1257 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
1258 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
1259 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
1260 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
1261 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
1262 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
1263 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
1264 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
1265 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
1266 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
1267 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
1268 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
1269 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
1270 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
1271 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
1272 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
1273 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
1274 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
1275 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
1276 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
1277 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
1278 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
1279 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
1280 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
1281 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1282 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
1283 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
1284 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
1285 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
1286 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
1287 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
1288 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
1289 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
1290 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
1291 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
1292 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
1293 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
1294 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
1295 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
1296 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
1297 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
1298 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
1299 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
1300 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
1301 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
1302 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
1303 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
1304 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
1305 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
1306 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
1307 DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
1308 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
1309 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1310 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
1311 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
1312 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
1313 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
1314 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
1315 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
1316 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
1317 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
1318 DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
1319 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
1320 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
1321 DUMP_REG(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL);
1322 DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
1323 DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
1324 DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
1325 DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
1326 DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
1327 DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
1328 DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
1329 DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
1330 DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
1331 DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
1332 DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
1333 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
1334 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(0));
1335 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(1));
1336 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(2));
1337 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(3));
1338 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(4));
1339 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(5));
1340 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(6));
1341 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(7));
1342 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(8));
1343 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(9));
1344 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(10));
1345 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(11));
1346 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(12));
1347 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(13));
1348 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(14));
1349 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(15));
1350 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
1351 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
1352 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
1353 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
1354 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
1355 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
1356 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
1357 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
1358 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
1359 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
1360 DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
1361 DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
1362 DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1363 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
1364 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
1365 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
1366 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
1367 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
1368 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
1369 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
1370 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
1371 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
1372 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
1373 DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
1374 DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
1375 DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
1376 DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
1377 DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
1378 DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
1379 DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
1380 DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
1381 DUMP_REG(HDMI_NV_PDISP_SCRATCH);
1382 DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
1383 DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
1384 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
1385 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
1386 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
1387 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
1388 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
1389 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
1390 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
1391 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
1392 DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
1393 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
1394 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
1395 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0);
1396 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1);
1397 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
1398 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
1399 DUMP_REG(HDMI_NV_PDISP_INT_STATUS);
1400 DUMP_REG(HDMI_NV_PDISP_INT_MASK);
1401 DUMP_REG(HDMI_NV_PDISP_INT_ENABLE);
1402 DUMP_REG(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
1403
1404#undef DUMP_REG
1405
1406unlock:
1407 drm_modeset_unlock_all(drm);
1408 return err;
1409}
1410
1411static struct drm_info_list debugfs_files[] = {
1412 { "regs", tegra_hdmi_show_regs, 0, NULL },
1413};
1414
1415static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi,
1416 struct drm_minor *minor)
1417{
1418 unsigned int i;
1419 int err;
1420
1421 hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root);
1422 if (!hdmi->debugfs)
1423 return -ENOMEM;
1424
1425 hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1426 GFP_KERNEL);
1427 if (!hdmi->debugfs_files) {
1428 err = -ENOMEM;
1429 goto remove;
1430 }
1431
1432 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1433 hdmi->debugfs_files[i].data = hdmi;
1434
1435 err = drm_debugfs_create_files(hdmi->debugfs_files,
1436 ARRAY_SIZE(debugfs_files),
1437 hdmi->debugfs, minor);
1438 if (err < 0)
1439 goto free;
1440
1441 hdmi->minor = minor;
1442
1443 return 0;
1444
1445free:
1446 kfree(hdmi->debugfs_files);
1447 hdmi->debugfs_files = NULL;
1448remove:
1449 debugfs_remove(hdmi->debugfs);
1450 hdmi->debugfs = NULL;
1451
1452 return err;
1453}
1454
1455static void tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi)
1456{
1457 drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files),
1458 hdmi->minor);
1459 hdmi->minor = NULL;
1460
1461 kfree(hdmi->debugfs_files);
1462 hdmi->debugfs_files = NULL;
1463
1464 debugfs_remove(hdmi->debugfs);
1465 hdmi->debugfs = NULL;
1466}
1467
1468static int tegra_hdmi_init(struct host1x_client *client)
1469{
1470 struct drm_device *drm = dev_get_drvdata(client->parent);
1471 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1472 int err;
1473
1474 hdmi->output.dev = client->dev;
1475
1476 drm_connector_init(drm, &hdmi->output.connector,
1477 &tegra_hdmi_connector_funcs,
1478 DRM_MODE_CONNECTOR_HDMIA);
1479 drm_connector_helper_add(&hdmi->output.connector,
1480 &tegra_hdmi_connector_helper_funcs);
1481 hdmi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1482
1483 drm_encoder_init(drm, &hdmi->output.encoder, &tegra_hdmi_encoder_funcs,
1484 DRM_MODE_ENCODER_TMDS, NULL);
1485 drm_encoder_helper_add(&hdmi->output.encoder,
1486 &tegra_hdmi_encoder_helper_funcs);
1487
1488 drm_mode_connector_attach_encoder(&hdmi->output.connector,
1489 &hdmi->output.encoder);
1490 drm_connector_register(&hdmi->output.connector);
1491
1492 err = tegra_output_init(drm, &hdmi->output);
1493 if (err < 0) {
1494 dev_err(client->dev, "failed to initialize output: %d\n", err);
1495 return err;
1496 }
1497
1498 hdmi->output.encoder.possible_crtcs = 0x3;
1499
1500 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1501 err = tegra_hdmi_debugfs_init(hdmi, drm->primary);
1502 if (err < 0)
1503 dev_err(client->dev, "debugfs setup failed: %d\n", err);
1504 }
1505
1506 err = regulator_enable(hdmi->hdmi);
1507 if (err < 0) {
1508 dev_err(client->dev, "failed to enable HDMI regulator: %d\n",
1509 err);
1510 return err;
1511 }
1512
1513 err = regulator_enable(hdmi->pll);
1514 if (err < 0) {
1515 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
1516 return err;
1517 }
1518
1519 err = regulator_enable(hdmi->vdd);
1520 if (err < 0) {
1521 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
1522 return err;
1523 }
1524
1525 return 0;
1526}
1527
1528static int tegra_hdmi_exit(struct host1x_client *client)
1529{
1530 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1531
1532 tegra_output_exit(&hdmi->output);
1533
1534 regulator_disable(hdmi->vdd);
1535 regulator_disable(hdmi->pll);
1536 regulator_disable(hdmi->hdmi);
1537
1538 if (IS_ENABLED(CONFIG_DEBUG_FS))
1539 tegra_hdmi_debugfs_exit(hdmi);
1540
1541 return 0;
1542}
1543
1544static const struct host1x_client_ops hdmi_client_ops = {
1545 .init = tegra_hdmi_init,
1546 .exit = tegra_hdmi_exit,
1547};
1548
1549static const struct tegra_hdmi_config tegra20_hdmi_config = {
1550 .tmds = tegra20_tmds_config,
1551 .num_tmds = ARRAY_SIZE(tegra20_tmds_config),
1552 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1553 .fuse_override_value = 1 << 31,
1554 .has_sor_io_peak_current = false,
1555 .has_hda = false,
1556 .has_hbr = false,
1557};
1558
1559static const struct tegra_hdmi_config tegra30_hdmi_config = {
1560 .tmds = tegra30_tmds_config,
1561 .num_tmds = ARRAY_SIZE(tegra30_tmds_config),
1562 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1563 .fuse_override_value = 1 << 31,
1564 .has_sor_io_peak_current = false,
1565 .has_hda = true,
1566 .has_hbr = false,
1567};
1568
1569static const struct tegra_hdmi_config tegra114_hdmi_config = {
1570 .tmds = tegra114_tmds_config,
1571 .num_tmds = ARRAY_SIZE(tegra114_tmds_config),
1572 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1573 .fuse_override_value = 1 << 31,
1574 .has_sor_io_peak_current = true,
1575 .has_hda = true,
1576 .has_hbr = true,
1577};
1578
1579static const struct tegra_hdmi_config tegra124_hdmi_config = {
1580 .tmds = tegra124_tmds_config,
1581 .num_tmds = ARRAY_SIZE(tegra124_tmds_config),
1582 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1583 .fuse_override_value = 1 << 31,
1584 .has_sor_io_peak_current = true,
1585 .has_hda = true,
1586 .has_hbr = true,
1587};
1588
1589static const struct of_device_id tegra_hdmi_of_match[] = {
1590 { .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config },
1591 { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config },
1592 { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config },
1593 { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config },
1594 { },
1595};
1596MODULE_DEVICE_TABLE(of, tegra_hdmi_of_match);
1597
1598static void hda_format_parse(unsigned int format, unsigned int *rate,
1599 unsigned int *channels)
1600{
1601 unsigned int mul, div;
1602
1603 if (format & AC_FMT_BASE_44K)
1604 *rate = 44100;
1605 else
1606 *rate = 48000;
1607
1608 mul = (format & AC_FMT_MULT_MASK) >> AC_FMT_MULT_SHIFT;
1609 div = (format & AC_FMT_DIV_MASK) >> AC_FMT_DIV_SHIFT;
1610
1611 *rate = *rate * (mul + 1) / (div + 1);
1612
1613 *channels = (format & AC_FMT_CHAN_MASK) >> AC_FMT_CHAN_SHIFT;
1614}
1615
1616static irqreturn_t tegra_hdmi_irq(int irq, void *data)
1617{
1618 struct tegra_hdmi *hdmi = data;
1619 u32 value;
1620 int err;
1621
1622 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_INT_STATUS);
1623 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_INT_STATUS);
1624
1625 if (value & INT_CODEC_SCRATCH0) {
1626 unsigned int format;
1627 u32 value;
1628
1629 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0);
1630
1631 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
1632 unsigned int sample_rate, channels;
1633
1634 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
1635
1636 hda_format_parse(format, &sample_rate, &channels);
1637
1638 hdmi->audio_sample_rate = sample_rate;
1639 hdmi->audio_channels = channels;
1640
1641 err = tegra_hdmi_setup_audio(hdmi);
1642 if (err < 0) {
1643 tegra_hdmi_disable_audio_infoframe(hdmi);
1644 tegra_hdmi_disable_audio(hdmi);
1645 } else {
1646 tegra_hdmi_setup_audio_infoframe(hdmi);
1647 tegra_hdmi_enable_audio_infoframe(hdmi);
1648 tegra_hdmi_enable_audio(hdmi);
1649 }
1650 } else {
1651 tegra_hdmi_disable_audio_infoframe(hdmi);
1652 tegra_hdmi_disable_audio(hdmi);
1653 }
1654 }
1655
1656 return IRQ_HANDLED;
1657}
1658
1659static int tegra_hdmi_probe(struct platform_device *pdev)
1660{
1661 const struct of_device_id *match;
1662 struct tegra_hdmi *hdmi;
1663 struct resource *regs;
1664 int err;
1665
1666 match = of_match_node(tegra_hdmi_of_match, pdev->dev.of_node);
1667 if (!match)
1668 return -ENODEV;
1669
1670 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1671 if (!hdmi)
1672 return -ENOMEM;
1673
1674 hdmi->config = match->data;
1675 hdmi->dev = &pdev->dev;
1676
1677 hdmi->audio_source = AUTO;
1678 hdmi->audio_sample_rate = 48000;
1679 hdmi->audio_channels = 2;
1680 hdmi->stereo = false;
1681 hdmi->dvi = false;
1682
1683 hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1684 if (IS_ERR(hdmi->clk)) {
1685 dev_err(&pdev->dev, "failed to get clock\n");
1686 return PTR_ERR(hdmi->clk);
1687 }
1688
1689 hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi");
1690 if (IS_ERR(hdmi->rst)) {
1691 dev_err(&pdev->dev, "failed to get reset\n");
1692 return PTR_ERR(hdmi->rst);
1693 }
1694
1695 hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1696 if (IS_ERR(hdmi->clk_parent))
1697 return PTR_ERR(hdmi->clk_parent);
1698
1699 err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1700 if (err < 0) {
1701 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1702 return err;
1703 }
1704
1705 hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi");
1706 if (IS_ERR(hdmi->hdmi)) {
1707 dev_err(&pdev->dev, "failed to get HDMI regulator\n");
1708 return PTR_ERR(hdmi->hdmi);
1709 }
1710
1711 hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1712 if (IS_ERR(hdmi->pll)) {
1713 dev_err(&pdev->dev, "failed to get PLL regulator\n");
1714 return PTR_ERR(hdmi->pll);
1715 }
1716
1717 hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1718 if (IS_ERR(hdmi->vdd)) {
1719 dev_err(&pdev->dev, "failed to get VDD regulator\n");
1720 return PTR_ERR(hdmi->vdd);
1721 }
1722
1723 hdmi->output.dev = &pdev->dev;
1724
1725 err = tegra_output_probe(&hdmi->output);
1726 if (err < 0)
1727 return err;
1728
1729 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1730 hdmi->regs = devm_ioremap_resource(&pdev->dev, regs);
1731 if (IS_ERR(hdmi->regs))
1732 return PTR_ERR(hdmi->regs);
1733
1734 err = platform_get_irq(pdev, 0);
1735 if (err < 0)
1736 return err;
1737
1738 hdmi->irq = err;
1739
1740 err = devm_request_irq(hdmi->dev, hdmi->irq, tegra_hdmi_irq, 0,
1741 dev_name(hdmi->dev), hdmi);
1742 if (err < 0) {
1743 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n",
1744 hdmi->irq, err);
1745 return err;
1746 }
1747
1748 platform_set_drvdata(pdev, hdmi);
1749 pm_runtime_enable(&pdev->dev);
1750
1751 INIT_LIST_HEAD(&hdmi->client.list);
1752 hdmi->client.ops = &hdmi_client_ops;
1753 hdmi->client.dev = &pdev->dev;
1754
1755 err = host1x_client_register(&hdmi->client);
1756 if (err < 0) {
1757 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1758 err);
1759 return err;
1760 }
1761
1762 return 0;
1763}
1764
1765static int tegra_hdmi_remove(struct platform_device *pdev)
1766{
1767 struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1768 int err;
1769
1770 pm_runtime_disable(&pdev->dev);
1771
1772 err = host1x_client_unregister(&hdmi->client);
1773 if (err < 0) {
1774 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1775 err);
1776 return err;
1777 }
1778
1779 tegra_output_remove(&hdmi->output);
1780
1781 return 0;
1782}
1783
1784#ifdef CONFIG_PM
1785static int tegra_hdmi_suspend(struct device *dev)
1786{
1787 struct tegra_hdmi *hdmi = dev_get_drvdata(dev);
1788 int err;
1789
1790 err = reset_control_assert(hdmi->rst);
1791 if (err < 0) {
1792 dev_err(dev, "failed to assert reset: %d\n", err);
1793 return err;
1794 }
1795
1796 usleep_range(1000, 2000);
1797
1798 clk_disable_unprepare(hdmi->clk);
1799
1800 return 0;
1801}
1802
1803static int tegra_hdmi_resume(struct device *dev)
1804{
1805 struct tegra_hdmi *hdmi = dev_get_drvdata(dev);
1806 int err;
1807
1808 err = clk_prepare_enable(hdmi->clk);
1809 if (err < 0) {
1810 dev_err(dev, "failed to enable clock: %d\n", err);
1811 return err;
1812 }
1813
1814 usleep_range(1000, 2000);
1815
1816 err = reset_control_deassert(hdmi->rst);
1817 if (err < 0) {
1818 dev_err(dev, "failed to deassert reset: %d\n", err);
1819 clk_disable_unprepare(hdmi->clk);
1820 return err;
1821 }
1822
1823 return 0;
1824}
1825#endif
1826
1827static const struct dev_pm_ops tegra_hdmi_pm_ops = {
1828 SET_RUNTIME_PM_OPS(tegra_hdmi_suspend, tegra_hdmi_resume, NULL)
1829};
1830
1831struct platform_driver tegra_hdmi_driver = {
1832 .driver = {
1833 .name = "tegra-hdmi",
1834 .of_match_table = tegra_hdmi_of_match,
1835 .pm = &tegra_hdmi_pm_ops,
1836 },
1837 .probe = tegra_hdmi_probe,
1838 .remove = tegra_hdmi_remove,
1839};