1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4 * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved.
  5 */
  6
  7#ifndef __DPU_ENCODER_PHYS_H__
  8#define __DPU_ENCODER_PHYS_H__
  9
 10#include <drm/drm_writeback.h>
 11#include <linux/jiffies.h>
 12
 13#include "dpu_kms.h"
 14#include "dpu_hw_intf.h"
 15#include "dpu_hw_wb.h"
 16#include "dpu_hw_pingpong.h"
 17#include "dpu_hw_ctl.h"
 18#include "dpu_hw_top.h"
 19#include "dpu_encoder.h"
 20#include "dpu_crtc.h"
 21
 22#define DPU_ENCODER_NAME_MAX	16
 23
 24/* wait for at most 2 vsync for lowest refresh rate (24hz) */
 25#define KICKOFF_TIMEOUT_MS		84
 26#define KICKOFF_TIMEOUT_JIFFIES		msecs_to_jiffies(KICKOFF_TIMEOUT_MS)
 27
 28/**
 29 * enum dpu_enc_split_role - Role this physical encoder will play in a
 30 *	split-panel configuration, where one panel is master, and others slaves.
 31 *	Masters have extra responsibilities, like managing the VBLANK IRQ.
 32 * @ENC_ROLE_SOLO:	This is the one and only panel. This encoder is master.
 33 * @ENC_ROLE_MASTER:	This encoder is the master of a split panel config.
 34 * @ENC_ROLE_SLAVE:	This encoder is not the master of a split panel config.
 35 */
 36enum dpu_enc_split_role {
 37	ENC_ROLE_SOLO,
 38	ENC_ROLE_MASTER,
 39	ENC_ROLE_SLAVE,
 40};
 41
 42/**
 43 * enum dpu_enc_enable_state - current enabled state of the physical encoder
 44 * @DPU_ENC_DISABLING:	Encoder transitioning to disable state
 45 *			Events bounding transition are encoder type specific
 46 * @DPU_ENC_DISABLED:	Encoder is disabled
 47 * @DPU_ENC_ENABLING:	Encoder transitioning to enabled
 48 *			Events bounding transition are encoder type specific
 49 * @DPU_ENC_ENABLED:	Encoder is enabled
 50 * @DPU_ENC_ERR_NEEDS_HW_RESET:	Encoder is enabled, but requires a hw_reset
 51 *				to recover from a previous error
 52 */
 53enum dpu_enc_enable_state {
 54	DPU_ENC_DISABLING,
 55	DPU_ENC_DISABLED,
 56	DPU_ENC_ENABLING,
 57	DPU_ENC_ENABLED,
 58	DPU_ENC_ERR_NEEDS_HW_RESET
 59};
 60
 61struct dpu_encoder_phys;
 62
 63/**
 64 * struct dpu_encoder_virt_ops - Interface the containing virtual encoder
 65 *	provides for the physical encoders to use to callback.
 66 * @handle_vblank_virt:	Notify virtual encoder of vblank IRQ reception
 67 *			Note: This is called from IRQ handler context.
 68 * @handle_underrun_virt: Notify virtual encoder of underrun IRQ reception
 69 *			Note: This is called from IRQ handler context.
 70 * @handle_frame_done:	Notify virtual encoder that this phys encoder
 71 *			completes last request frame.
 72 */
 73struct dpu_encoder_virt_ops {
 74	void (*handle_vblank_virt)(struct drm_encoder *,
 75			struct dpu_encoder_phys *phys);
 76	void (*handle_underrun_virt)(struct drm_encoder *,
 77			struct dpu_encoder_phys *phys);
 78	void (*handle_frame_done)(struct drm_encoder *,
 79			struct dpu_encoder_phys *phys, u32 event);
 80};
 81
 82/**
 83 * struct dpu_encoder_phys_ops - Interface the physical encoders provide to
 84 *	the containing virtual encoder.
 85 * @late_register:		DRM Call. Add Userspace interfaces, debugfs.
 86 * @prepare_commit:		MSM Atomic Call, start of atomic commit sequence
 87 * @is_master:			Whether this phys_enc is the current master
 88 *				encoder. Can be switched at enable time. Based
 89 *				on split_role and current mode (CMD/VID).
 90 * @atomic_mode_set:		DRM Call. Set a DRM mode.
 91 *				This likely caches the mode, for use at enable.
 92 * @enable:			DRM Call. Enable a DRM mode.
 93 * @disable:			DRM Call. Disable mode.
 94 * @atomic_check:		DRM Call. Atomic check new DRM state.
 95 * @destroy:			DRM Call. Destroy and release resources.
 96 * @control_vblank_irq		Register/Deregister for VBLANK IRQ
 97 * @wait_for_commit_done:	Wait for hardware to have flushed the
 98 *				current pending frames to hardware
 99 * @wait_for_tx_complete:	Wait for hardware to transfer the pixels
100 *				to the panel
101 * @wait_for_vblank:		Wait for VBLANK, for sub-driver internal use
102 * @prepare_for_kickoff:	Do any work necessary prior to a kickoff
103 *				For CMD encoder, may wait for previous tx done
104 * @handle_post_kickoff:	Do any work necessary post-kickoff work
105 * @trigger_start:		Process start event on physical encoder
106 * @needs_single_flush:		Whether encoder slaves need to be flushed
107 * @irq_control:		Handler to enable/disable all the encoder IRQs
108 * @prepare_idle_pc:		phys encoder can update the vsync_enable status
109 *                              on idle power collapse prepare
110 * @restore:			Restore all the encoder configs.
111 * @get_line_count:		Obtain current vertical line count
112 */
113
114struct dpu_encoder_phys_ops {
115	int (*late_register)(struct dpu_encoder_phys *encoder,
116			struct dentry *debugfs_root);
117	void (*prepare_commit)(struct dpu_encoder_phys *encoder);
118	bool (*is_master)(struct dpu_encoder_phys *encoder);
119	void (*atomic_mode_set)(struct dpu_encoder_phys *encoder,
120			struct drm_crtc_state *crtc_state,
121			struct drm_connector_state *conn_state);
122	void (*enable)(struct dpu_encoder_phys *encoder);
123	void (*disable)(struct dpu_encoder_phys *encoder);
124	int (*atomic_check)(struct dpu_encoder_phys *encoder,
125			    struct drm_crtc_state *crtc_state,
126			    struct drm_connector_state *conn_state);
127	void (*destroy)(struct dpu_encoder_phys *encoder);
128	int (*control_vblank_irq)(struct dpu_encoder_phys *enc, bool enable);
129	int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc);
130	int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc);
131	int (*wait_for_vblank)(struct dpu_encoder_phys *phys_enc);
132	void (*prepare_for_kickoff)(struct dpu_encoder_phys *phys_enc);
133	void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc);
134	void (*trigger_start)(struct dpu_encoder_phys *phys_enc);
135	bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc);
136	void (*irq_control)(struct dpu_encoder_phys *phys, bool enable);
137	void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);
138	void (*restore)(struct dpu_encoder_phys *phys);
139	int (*get_line_count)(struct dpu_encoder_phys *phys);
140	int (*get_frame_count)(struct dpu_encoder_phys *phys);
141	void (*prepare_wb_job)(struct dpu_encoder_phys *phys_enc,
142			struct drm_writeback_job *job);
143	void (*cleanup_wb_job)(struct dpu_encoder_phys *phys_enc,
144			struct drm_writeback_job *job);
145	bool (*is_valid_for_commit)(struct dpu_encoder_phys *phys_enc);
146};
147
148/**
149 * enum dpu_intr_idx - dpu encoder interrupt index
150 * @INTR_IDX_VSYNC:    Vsync interrupt for video mode panel
151 * @INTR_IDX_PINGPONG: Pingpong done unterrupt for cmd mode panel
152 * @INTR_IDX_UNDERRUN: Underrun unterrupt for video and cmd mode panel
153 * @INTR_IDX_RDPTR:    Readpointer done unterrupt for cmd mode panel
154 * @INTR_IDX_WB_DONE:  Writeback fone interrupt for virtual connector
155 */
156enum dpu_intr_idx {
157	INTR_IDX_VSYNC,
158	INTR_IDX_PINGPONG,
159	INTR_IDX_UNDERRUN,
160	INTR_IDX_CTL_START,
161	INTR_IDX_RDPTR,
162	INTR_IDX_WB_DONE,
163	INTR_IDX_MAX,
164};
165
166/**
167 * struct dpu_encoder_phys - physical encoder that drives a single INTF block
168 *	tied to a specific panel / sub-panel. Abstract type, sub-classed by
169 *	phys_vid or phys_cmd for video mode or command mode encs respectively.
170 * @parent:		Pointer to the containing virtual encoder
171 * @ops:		Operations exposed to the virtual encoder
172 * @parent_ops:		Callbacks exposed by the parent to the phys_enc
173 * @hw_mdptop:		Hardware interface to the top registers
174 * @hw_ctl:		Hardware interface to the ctl registers
175 * @hw_pp:		Hardware interface to the ping pong registers
176 * @hw_intf:		Hardware interface to the intf registers
177 * @hw_wb:		Hardware interface to the wb registers
178 * @dpu_kms:		Pointer to the dpu_kms top level
179 * @cached_mode:	DRM mode cached at mode_set time, acted on in enable
180 * @enabled:		Whether the encoder has enabled and running a mode
181 * @split_role:		Role to play in a split-panel configuration
182 * @intf_mode:		Interface mode
183 * @intf_idx:		Interface index on dpu hardware
184 * @wb_idx:			Writeback index on dpu hardware
185 * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
186 * @enable_state:	Enable state tracking
187 * @vblank_refcount:	Reference count of vblank request
188 * @vsync_cnt:		Vsync count for the physical encoder
189 * @underrun_cnt:	Underrun count for the physical encoder
190 * @pending_kickoff_cnt:	Atomic counter tracking the number of kickoffs
191 *				vs. the number of done/vblank irqs. Should hover
192 *				between 0-2 Incremented when a new kickoff is
193 *				scheduled. Decremented in irq handler
194 * @pending_ctlstart_cnt:	Atomic counter tracking the number of ctl start
195 *                              pending.
196 * @pending_kickoff_wq:		Wait queue for blocking until kickoff completes
197 * @irq:			IRQ indices
198 */
199struct dpu_encoder_phys {
200	struct drm_encoder *parent;
201	struct dpu_encoder_phys_ops ops;
202	const struct dpu_encoder_virt_ops *parent_ops;
203	struct dpu_hw_mdp *hw_mdptop;
204	struct dpu_hw_ctl *hw_ctl;
205	struct dpu_hw_pingpong *hw_pp;
206	struct dpu_hw_intf *hw_intf;
207	struct dpu_hw_wb *hw_wb;
208	struct dpu_kms *dpu_kms;
209	struct drm_display_mode cached_mode;
210	enum dpu_enc_split_role split_role;
211	enum dpu_intf_mode intf_mode;
212	enum dpu_intf intf_idx;
213	enum dpu_wb wb_idx;
214	spinlock_t *enc_spinlock;
215	enum dpu_enc_enable_state enable_state;
216	atomic_t vblank_refcount;
217	atomic_t vsync_cnt;
218	atomic_t underrun_cnt;
219	atomic_t pending_ctlstart_cnt;
220	atomic_t pending_kickoff_cnt;
221	wait_queue_head_t pending_kickoff_wq;
222	int irq[INTR_IDX_MAX];
223};
224
225static inline int dpu_encoder_phys_inc_pending(struct dpu_encoder_phys *phys)
226{
227	atomic_inc_return(&phys->pending_ctlstart_cnt);
228	return atomic_inc_return(&phys->pending_kickoff_cnt);
229}
230
231/**
232 * struct dpu_encoder_phys_wb - sub-class of dpu_encoder_phys to handle command
233 *	mode specific operations
234 * @base:	Baseclass physical encoder structure
235 * @wbirq_refcount:     Reference count of writeback interrupt
236 * @wb_done_timeout_cnt: number of wb done irq timeout errors
237 * @wb_cfg:  writeback block config to store fb related details
238 * @wb_conn: backpointer to writeback connector
239 * @wb_job: backpointer to current writeback job
240 * @dest:   dpu buffer layout for current writeback output buffer
241 */
242struct dpu_encoder_phys_wb {
243	struct dpu_encoder_phys base;
244	atomic_t wbirq_refcount;
245	int wb_done_timeout_cnt;
246	struct dpu_hw_wb_cfg wb_cfg;
247	struct drm_writeback_connector *wb_conn;
248	struct drm_writeback_job *wb_job;
249	struct dpu_hw_fmt_layout dest;
250};
251
252/**
253 * struct dpu_encoder_phys_cmd - sub-class of dpu_encoder_phys to handle command
254 *	mode specific operations
255 * @base:	Baseclass physical encoder structure
256 * @intf_idx:	Intf Block index used by this phys encoder
257 * @stream_sel:	Stream selection for multi-stream interfaces
258 * @serialize_wait4pp:	serialize wait4pp feature waits for pp_done interrupt
259 *			after ctl_start instead of before next frame kickoff
260 * @pp_timeout_report_cnt: number of pingpong done irq timeout errors
261 * @pending_vblank_cnt: Atomic counter tracking pending wait for VBLANK
262 * @pending_vblank_wq: Wait queue for blocking until VBLANK received
263 */
264struct dpu_encoder_phys_cmd {
265	struct dpu_encoder_phys base;
266	int stream_sel;
267	bool serialize_wait4pp;
268	int pp_timeout_report_cnt;
269	atomic_t pending_vblank_cnt;
270	wait_queue_head_t pending_vblank_wq;
271};
272
273/**
274 * struct dpu_enc_phys_init_params - initialization parameters for phys encs
275 * @dpu_kms:		Pointer to the dpu_kms top level
276 * @parent:		Pointer to the containing virtual encoder
277 * @parent_ops:		Callbacks exposed by the parent to the phys_enc
278 * @split_role:		Role to play in a split-panel configuration
279 * @intf_idx:		Interface index this phys_enc will control
280 * @wb_idx:			Writeback index this phys_enc will control
281 * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
282 */
283struct dpu_enc_phys_init_params {
284	struct dpu_kms *dpu_kms;
285	struct drm_encoder *parent;
286	const struct dpu_encoder_virt_ops *parent_ops;
287	enum dpu_enc_split_role split_role;
288	enum dpu_intf intf_idx;
289	enum dpu_wb wb_idx;
290	spinlock_t *enc_spinlock;
291};
292
293/**
294 * dpu_encoder_wait_info - container for passing arguments to irq wait functions
295 * @wq: wait queue structure
296 * @atomic_cnt: wait until atomic_cnt equals zero
297 * @timeout_ms: timeout value in milliseconds
298 */
299struct dpu_encoder_wait_info {
300	wait_queue_head_t *wq;
301	atomic_t *atomic_cnt;
302	s64 timeout_ms;
303};
304
305/**
306 * dpu_encoder_phys_vid_init - Construct a new video mode physical encoder
307 * @p:	Pointer to init params structure
308 * Return: Error code or newly allocated encoder
309 */
310struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
311		struct dpu_enc_phys_init_params *p);
312
313/**
314 * dpu_encoder_phys_cmd_init - Construct a new command mode physical encoder
315 * @p:	Pointer to init params structure
316 * Return: Error code or newly allocated encoder
317 */
318struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
319		struct dpu_enc_phys_init_params *p);
320
321/**
322 * dpu_encoder_phys_wb_init - initialize writeback encoder
323 * @init:	Pointer to init info structure with initialization params
324 */
325struct dpu_encoder_phys *dpu_encoder_phys_wb_init(
326		struct dpu_enc_phys_init_params *p);
327
328/**
329 * dpu_encoder_helper_trigger_start - control start helper function
330 *	This helper function may be optionally specified by physical
331 *	encoders if they require ctl_start triggering.
332 * @phys_enc: Pointer to physical encoder structure
333 */
334void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc);
335
336static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
337		struct dpu_encoder_phys *phys_enc)
338{
339	struct dpu_crtc_state *dpu_cstate;
340
341	if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
342		return BLEND_3D_NONE;
343
344	dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
345
346	/* Use merge_3d unless DSC MERGE topology is used */
347	if (phys_enc->split_role == ENC_ROLE_SOLO &&
348	    dpu_cstate->num_mixers == CRTC_DUAL_MIXERS &&
349	    !dpu_encoder_use_dsc_merge(phys_enc->parent))
350		return BLEND_3D_H_ROW_INT;
351
352	return BLEND_3D_NONE;
353}
354
355/**
356 * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder
357 *   This helper function is used by physical encoder to get DSC blocks mask
358 *   used for this encoder.
359 * @phys_enc: Pointer to physical encoder structure
360 */
361unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc);
362
363/**
364 * dpu_encoder_helper_split_config - split display configuration helper function
365 *	This helper function may be used by physical encoders to configure
366 *	the split display related registers.
367 * @phys_enc: Pointer to physical encoder structure
368 * @interface: enum dpu_intf setting
369 */
370void dpu_encoder_helper_split_config(
371		struct dpu_encoder_phys *phys_enc,
372		enum dpu_intf interface);
373
374/**
375 * dpu_encoder_helper_report_irq_timeout - utility to report error that irq has
376 *	timed out, including reporting frame error event to crtc and debug dump
377 * @phys_enc: Pointer to physical encoder structure
378 * @intr_idx: Failing interrupt index
379 */
380void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
381		enum dpu_intr_idx intr_idx);
382
383/**
384 * dpu_encoder_helper_wait_for_irq - utility to wait on an irq.
385 *	note: will call dpu_encoder_helper_wait_for_irq on timeout
386 * @phys_enc: Pointer to physical encoder structure
387 * @irq: IRQ index
388 * @func: IRQ callback to be called in case of timeout
389 * @wait_info: wait info struct
390 * @Return: 0 or -ERROR
391 */
392int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
393		int irq,
394		void (*func)(void *arg, int irq_idx),
395		struct dpu_encoder_wait_info *wait_info);
396
397/**
398 * dpu_encoder_helper_phys_cleanup - helper to cleanup dpu pipeline
399 * @phys_enc: Pointer to physical encoder structure
400 */
401void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc);
402
403#endif /* __dpu_encoder_phys_H__ */