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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 */
5
6#include <drm/drm_blend.h>
7#include <drm/drm_fourcc.h>
8#include <drm/drm_framebuffer.h>
9
10#include <linux/clk.h>
11#include <linux/component.h>
12#include <linux/module.h>
13#include <linux/of_device.h>
14#include <linux/of_irq.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/soc/mediatek/mtk-cmdq.h>
18
19#include "mtk_disp_drv.h"
20#include "mtk_drm_crtc.h"
21#include "mtk_drm_ddp_comp.h"
22
23#define DISP_REG_OVL_INTEN 0x0004
24#define OVL_FME_CPL_INT BIT(1)
25#define DISP_REG_OVL_INTSTA 0x0008
26#define DISP_REG_OVL_EN 0x000c
27#define DISP_REG_OVL_RST 0x0014
28#define DISP_REG_OVL_ROI_SIZE 0x0020
29#define DISP_REG_OVL_DATAPATH_CON 0x0024
30#define OVL_LAYER_SMI_ID_EN BIT(0)
31#define OVL_BGCLR_SEL_IN BIT(2)
32#define OVL_LAYER_AFBC_EN(n) BIT(4+n)
33#define DISP_REG_OVL_ROI_BGCLR 0x0028
34#define DISP_REG_OVL_SRC_CON 0x002c
35#define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n))
36#define DISP_REG_OVL_SRC_SIZE(n) (0x0038 + 0x20 * (n))
37#define DISP_REG_OVL_OFFSET(n) (0x003c + 0x20 * (n))
38#define DISP_REG_OVL_PITCH_MSB(n) (0x0040 + 0x20 * (n))
39#define OVL_PITCH_MSB_2ND_SUBBUF BIT(16)
40#define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n))
41#define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n))
42#define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n))
43#define DISP_REG_OVL_ADDR_MT2701 0x0040
44#define DISP_REG_OVL_ADDR_MT8173 0x0f40
45#define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n))
46#define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x04)
47#define DISP_REG_OVL_HDR_PITCH(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x08)
48
49#define GMC_THRESHOLD_BITS 16
50#define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4)
51#define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8)
52
53#define OVL_CON_BYTE_SWAP BIT(24)
54#define OVL_CON_MTX_YUV_TO_RGB (6 << 16)
55#define OVL_CON_CLRFMT_RGB (1 << 12)
56#define OVL_CON_CLRFMT_RGBA8888 (2 << 12)
57#define OVL_CON_CLRFMT_ARGB8888 (3 << 12)
58#define OVL_CON_CLRFMT_UYVY (4 << 12)
59#define OVL_CON_CLRFMT_YUYV (5 << 12)
60#define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \
61 0 : OVL_CON_CLRFMT_RGB)
62#define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \
63 OVL_CON_CLRFMT_RGB : 0)
64#define OVL_CON_AEN BIT(8)
65#define OVL_CON_ALPHA 0xff
66#define OVL_CON_VIRT_FLIP BIT(9)
67#define OVL_CON_HORZ_FLIP BIT(10)
68
69struct mtk_disp_ovl_data {
70 unsigned int addr;
71 unsigned int gmc_bits;
72 unsigned int layer_nr;
73 bool fmt_rgb565_is_0;
74 bool smi_id_en;
75 bool supports_afbc;
76};
77
78/*
79 * struct mtk_disp_ovl - DISP_OVL driver structure
80 * @crtc: associated crtc to report vblank events to
81 * @data: platform data
82 */
83struct mtk_disp_ovl {
84 struct drm_crtc *crtc;
85 struct clk *clk;
86 void __iomem *regs;
87 struct cmdq_client_reg cmdq_reg;
88 const struct mtk_disp_ovl_data *data;
89 void (*vblank_cb)(void *data);
90 void *vblank_cb_data;
91};
92
93static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id)
94{
95 struct mtk_disp_ovl *priv = dev_id;
96
97 /* Clear frame completion interrupt */
98 writel(0x0, priv->regs + DISP_REG_OVL_INTSTA);
99
100 if (!priv->vblank_cb)
101 return IRQ_NONE;
102
103 priv->vblank_cb(priv->vblank_cb_data);
104
105 return IRQ_HANDLED;
106}
107
108void mtk_ovl_register_vblank_cb(struct device *dev,
109 void (*vblank_cb)(void *),
110 void *vblank_cb_data)
111{
112 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
113
114 ovl->vblank_cb = vblank_cb;
115 ovl->vblank_cb_data = vblank_cb_data;
116}
117
118void mtk_ovl_unregister_vblank_cb(struct device *dev)
119{
120 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
121
122 ovl->vblank_cb = NULL;
123 ovl->vblank_cb_data = NULL;
124}
125
126void mtk_ovl_enable_vblank(struct device *dev)
127{
128 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
129
130 writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA);
131 writel_relaxed(OVL_FME_CPL_INT, ovl->regs + DISP_REG_OVL_INTEN);
132}
133
134void mtk_ovl_disable_vblank(struct device *dev)
135{
136 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
137
138 writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN);
139}
140
141int mtk_ovl_clk_enable(struct device *dev)
142{
143 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
144
145 return clk_prepare_enable(ovl->clk);
146}
147
148void mtk_ovl_clk_disable(struct device *dev)
149{
150 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
151
152 clk_disable_unprepare(ovl->clk);
153}
154
155void mtk_ovl_start(struct device *dev)
156{
157 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
158
159 if (ovl->data->smi_id_en) {
160 unsigned int reg;
161
162 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
163 reg = reg | OVL_LAYER_SMI_ID_EN;
164 writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
165 }
166 writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN);
167}
168
169void mtk_ovl_stop(struct device *dev)
170{
171 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
172
173 writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN);
174 if (ovl->data->smi_id_en) {
175 unsigned int reg;
176
177 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
178 reg = reg & ~OVL_LAYER_SMI_ID_EN;
179 writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
180 }
181}
182
183static void mtk_ovl_set_afbc(struct mtk_disp_ovl *ovl, struct cmdq_pkt *cmdq_pkt,
184 int idx, bool enabled)
185{
186 mtk_ddp_write_mask(cmdq_pkt, enabled ? OVL_LAYER_AFBC_EN(idx) : 0,
187 &ovl->cmdq_reg, ovl->regs,
188 DISP_REG_OVL_DATAPATH_CON, OVL_LAYER_AFBC_EN(idx));
189}
190
191void mtk_ovl_config(struct device *dev, unsigned int w,
192 unsigned int h, unsigned int vrefresh,
193 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
194{
195 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
196
197 if (w != 0 && h != 0)
198 mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs,
199 DISP_REG_OVL_ROI_SIZE);
200 mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ROI_BGCLR);
201
202 mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);
203 mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);
204}
205
206unsigned int mtk_ovl_layer_nr(struct device *dev)
207{
208 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
209
210 return ovl->data->layer_nr;
211}
212
213unsigned int mtk_ovl_supported_rotations(struct device *dev)
214{
215 return DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
216 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
217}
218
219int mtk_ovl_layer_check(struct device *dev, unsigned int idx,
220 struct mtk_plane_state *mtk_state)
221{
222 struct drm_plane_state *state = &mtk_state->base;
223 unsigned int rotation = 0;
224
225 rotation = drm_rotation_simplify(state->rotation,
226 DRM_MODE_ROTATE_0 |
227 DRM_MODE_REFLECT_X |
228 DRM_MODE_REFLECT_Y);
229 rotation &= ~DRM_MODE_ROTATE_0;
230
231 /* We can only do reflection, not rotation */
232 if ((rotation & DRM_MODE_ROTATE_MASK) != 0)
233 return -EINVAL;
234
235 /*
236 * TODO: Rotating/reflecting YUV buffers is not supported at this time.
237 * Only RGB[AX] variants are supported.
238 */
239 if (state->fb->format->is_yuv && rotation != 0)
240 return -EINVAL;
241
242 state->rotation = rotation;
243
244 return 0;
245}
246
247void mtk_ovl_layer_on(struct device *dev, unsigned int idx,
248 struct cmdq_pkt *cmdq_pkt)
249{
250 unsigned int gmc_thrshd_l;
251 unsigned int gmc_thrshd_h;
252 unsigned int gmc_value;
253 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
254
255 mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs,
256 DISP_REG_OVL_RDMA_CTRL(idx));
257 gmc_thrshd_l = GMC_THRESHOLD_LOW >>
258 (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
259 gmc_thrshd_h = GMC_THRESHOLD_HIGH >>
260 (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
261 if (ovl->data->gmc_bits == 10)
262 gmc_value = gmc_thrshd_h | gmc_thrshd_h << 16;
263 else
264 gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 |
265 gmc_thrshd_h << 16 | gmc_thrshd_h << 24;
266 mtk_ddp_write(cmdq_pkt, gmc_value,
267 &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx));
268 mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs,
269 DISP_REG_OVL_SRC_CON, BIT(idx));
270}
271
272void mtk_ovl_layer_off(struct device *dev, unsigned int idx,
273 struct cmdq_pkt *cmdq_pkt)
274{
275 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
276
277 mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,
278 DISP_REG_OVL_SRC_CON, BIT(idx));
279 mtk_ddp_write(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,
280 DISP_REG_OVL_RDMA_CTRL(idx));
281}
282
283static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
284{
285 /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
286 * is defined in mediatek HW data sheet.
287 * The alphabet order in XXX is no relation to data
288 * arrangement in memory.
289 */
290 switch (fmt) {
291 default:
292 case DRM_FORMAT_RGB565:
293 return OVL_CON_CLRFMT_RGB565(ovl);
294 case DRM_FORMAT_BGR565:
295 return OVL_CON_CLRFMT_RGB565(ovl) | OVL_CON_BYTE_SWAP;
296 case DRM_FORMAT_RGB888:
297 return OVL_CON_CLRFMT_RGB888(ovl);
298 case DRM_FORMAT_BGR888:
299 return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP;
300 case DRM_FORMAT_RGBX8888:
301 case DRM_FORMAT_RGBA8888:
302 return OVL_CON_CLRFMT_ARGB8888;
303 case DRM_FORMAT_BGRX8888:
304 case DRM_FORMAT_BGRA8888:
305 return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP;
306 case DRM_FORMAT_XRGB8888:
307 case DRM_FORMAT_ARGB8888:
308 return OVL_CON_CLRFMT_RGBA8888;
309 case DRM_FORMAT_XBGR8888:
310 case DRM_FORMAT_ABGR8888:
311 return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP;
312 case DRM_FORMAT_UYVY:
313 return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB;
314 case DRM_FORMAT_YUYV:
315 return OVL_CON_CLRFMT_YUYV | OVL_CON_MTX_YUV_TO_RGB;
316 }
317}
318
319void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
320 struct mtk_plane_state *state,
321 struct cmdq_pkt *cmdq_pkt)
322{
323 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
324 struct mtk_plane_pending_state *pending = &state->pending;
325 unsigned int addr = pending->addr;
326 unsigned int hdr_addr = pending->hdr_addr;
327 unsigned int pitch = pending->pitch;
328 unsigned int hdr_pitch = pending->hdr_pitch;
329 unsigned int fmt = pending->format;
330 unsigned int offset = (pending->y << 16) | pending->x;
331 unsigned int src_size = (pending->height << 16) | pending->width;
332 unsigned int con;
333 bool is_afbc = pending->modifier != DRM_FORMAT_MOD_LINEAR;
334 union overlay_pitch {
335 struct split_pitch {
336 u16 lsb;
337 u16 msb;
338 } split_pitch;
339 u32 pitch;
340 } overlay_pitch;
341
342 overlay_pitch.pitch = pitch;
343
344 if (!pending->enable) {
345 mtk_ovl_layer_off(dev, idx, cmdq_pkt);
346 return;
347 }
348
349 con = ovl_fmt_convert(ovl, fmt);
350 if (state->base.fb && state->base.fb->format->has_alpha)
351 con |= OVL_CON_AEN | OVL_CON_ALPHA;
352
353 if (pending->rotation & DRM_MODE_REFLECT_Y) {
354 con |= OVL_CON_VIRT_FLIP;
355 addr += (pending->height - 1) * pending->pitch;
356 }
357
358 if (pending->rotation & DRM_MODE_REFLECT_X) {
359 con |= OVL_CON_HORZ_FLIP;
360 addr += pending->pitch - 1;
361 }
362
363 if (ovl->data->supports_afbc)
364 mtk_ovl_set_afbc(ovl, cmdq_pkt, idx, is_afbc);
365
366 mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,
367 DISP_REG_OVL_CON(idx));
368 mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb, &ovl->cmdq_reg, ovl->regs,
369 DISP_REG_OVL_PITCH(idx));
370 mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs,
371 DISP_REG_OVL_SRC_SIZE(idx));
372 mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs,
373 DISP_REG_OVL_OFFSET(idx));
374 mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs,
375 DISP_REG_OVL_ADDR(ovl, idx));
376
377 if (is_afbc) {
378 mtk_ddp_write_relaxed(cmdq_pkt, hdr_addr, &ovl->cmdq_reg, ovl->regs,
379 DISP_REG_OVL_HDR_ADDR(ovl, idx));
380 mtk_ddp_write_relaxed(cmdq_pkt,
381 OVL_PITCH_MSB_2ND_SUBBUF | overlay_pitch.split_pitch.msb,
382 &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx));
383 mtk_ddp_write_relaxed(cmdq_pkt, hdr_pitch, &ovl->cmdq_reg, ovl->regs,
384 DISP_REG_OVL_HDR_PITCH(ovl, idx));
385 } else {
386 mtk_ddp_write_relaxed(cmdq_pkt,
387 overlay_pitch.split_pitch.msb,
388 &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx));
389 }
390
391 mtk_ovl_layer_on(dev, idx, cmdq_pkt);
392}
393
394void mtk_ovl_bgclr_in_on(struct device *dev)
395{
396 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
397 unsigned int reg;
398
399 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
400 reg = reg | OVL_BGCLR_SEL_IN;
401 writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
402}
403
404void mtk_ovl_bgclr_in_off(struct device *dev)
405{
406 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
407 unsigned int reg;
408
409 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
410 reg = reg & ~OVL_BGCLR_SEL_IN;
411 writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
412}
413
414static int mtk_disp_ovl_bind(struct device *dev, struct device *master,
415 void *data)
416{
417 return 0;
418}
419
420static void mtk_disp_ovl_unbind(struct device *dev, struct device *master,
421 void *data)
422{
423}
424
425static const struct component_ops mtk_disp_ovl_component_ops = {
426 .bind = mtk_disp_ovl_bind,
427 .unbind = mtk_disp_ovl_unbind,
428};
429
430static int mtk_disp_ovl_probe(struct platform_device *pdev)
431{
432 struct device *dev = &pdev->dev;
433 struct mtk_disp_ovl *priv;
434 struct resource *res;
435 int irq;
436 int ret;
437
438 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
439 if (!priv)
440 return -ENOMEM;
441
442 irq = platform_get_irq(pdev, 0);
443 if (irq < 0)
444 return irq;
445
446 priv->clk = devm_clk_get(dev, NULL);
447 if (IS_ERR(priv->clk)) {
448 dev_err(dev, "failed to get ovl clk\n");
449 return PTR_ERR(priv->clk);
450 }
451
452 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
453 priv->regs = devm_ioremap_resource(dev, res);
454 if (IS_ERR(priv->regs)) {
455 dev_err(dev, "failed to ioremap ovl\n");
456 return PTR_ERR(priv->regs);
457 }
458#if IS_REACHABLE(CONFIG_MTK_CMDQ)
459 ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
460 if (ret)
461 dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
462#endif
463
464 priv->data = of_device_get_match_data(dev);
465 platform_set_drvdata(pdev, priv);
466
467 ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler,
468 IRQF_TRIGGER_NONE, dev_name(dev), priv);
469 if (ret < 0) {
470 dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
471 return ret;
472 }
473
474 pm_runtime_enable(dev);
475
476 ret = component_add(dev, &mtk_disp_ovl_component_ops);
477 if (ret) {
478 pm_runtime_disable(dev);
479 dev_err(dev, "Failed to add component: %d\n", ret);
480 }
481
482 return ret;
483}
484
485static int mtk_disp_ovl_remove(struct platform_device *pdev)
486{
487 component_del(&pdev->dev, &mtk_disp_ovl_component_ops);
488 pm_runtime_disable(&pdev->dev);
489
490 return 0;
491}
492
493static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = {
494 .addr = DISP_REG_OVL_ADDR_MT2701,
495 .gmc_bits = 8,
496 .layer_nr = 4,
497 .fmt_rgb565_is_0 = false,
498};
499
500static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
501 .addr = DISP_REG_OVL_ADDR_MT8173,
502 .gmc_bits = 8,
503 .layer_nr = 4,
504 .fmt_rgb565_is_0 = true,
505};
506
507static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {
508 .addr = DISP_REG_OVL_ADDR_MT8173,
509 .gmc_bits = 10,
510 .layer_nr = 4,
511 .fmt_rgb565_is_0 = true,
512};
513
514static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
515 .addr = DISP_REG_OVL_ADDR_MT8173,
516 .gmc_bits = 10,
517 .layer_nr = 2,
518 .fmt_rgb565_is_0 = true,
519};
520
521static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {
522 .addr = DISP_REG_OVL_ADDR_MT8173,
523 .gmc_bits = 10,
524 .layer_nr = 4,
525 .fmt_rgb565_is_0 = true,
526 .smi_id_en = true,
527};
528
529static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {
530 .addr = DISP_REG_OVL_ADDR_MT8173,
531 .gmc_bits = 10,
532 .layer_nr = 2,
533 .fmt_rgb565_is_0 = true,
534 .smi_id_en = true,
535};
536
537static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = {
538 .addr = DISP_REG_OVL_ADDR_MT8173,
539 .gmc_bits = 10,
540 .layer_nr = 4,
541 .fmt_rgb565_is_0 = true,
542 .smi_id_en = true,
543 .supports_afbc = true,
544};
545
546static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
547 { .compatible = "mediatek,mt2701-disp-ovl",
548 .data = &mt2701_ovl_driver_data},
549 { .compatible = "mediatek,mt8173-disp-ovl",
550 .data = &mt8173_ovl_driver_data},
551 { .compatible = "mediatek,mt8183-disp-ovl",
552 .data = &mt8183_ovl_driver_data},
553 { .compatible = "mediatek,mt8183-disp-ovl-2l",
554 .data = &mt8183_ovl_2l_driver_data},
555 { .compatible = "mediatek,mt8192-disp-ovl",
556 .data = &mt8192_ovl_driver_data},
557 { .compatible = "mediatek,mt8192-disp-ovl-2l",
558 .data = &mt8192_ovl_2l_driver_data},
559 { .compatible = "mediatek,mt8195-disp-ovl",
560 .data = &mt8195_ovl_driver_data},
561 {},
562};
563MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
564
565struct platform_driver mtk_disp_ovl_driver = {
566 .probe = mtk_disp_ovl_probe,
567 .remove = mtk_disp_ovl_remove,
568 .driver = {
569 .name = "mediatek-disp-ovl",
570 .owner = THIS_MODULE,
571 .of_match_table = mtk_disp_ovl_driver_dt_match,
572 },
573};