1/*
  2 * Copyright (c) 2015 MediaTek Inc.
  3 *
  4 * This program is free software; you can redistribute it and/or modify
  5 * it under the terms of the GNU General Public License version 2 as
  6 * published by the Free Software Foundation.
  7 *
  8 * This program is distributed in the hope that it will be useful,
  9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 11 * GNU General Public License for more details.
 12 */
 13
 14#include <drm/drmP.h>
 15#include <linux/clk.h>
 16#include <linux/component.h>
 17#include <linux/of_device.h>
 18#include <linux/of_irq.h>
 19#include <linux/platform_device.h>
 20
 21#include "mtk_drm_crtc.h"
 22#include "mtk_drm_ddp_comp.h"
 23
 24#define DISP_REG_OVL_INTEN			0x0004
 25#define OVL_FME_CPL_INT					BIT(1)
 26#define DISP_REG_OVL_INTSTA			0x0008
 27#define DISP_REG_OVL_EN				0x000c
 28#define DISP_REG_OVL_RST			0x0014
 29#define DISP_REG_OVL_ROI_SIZE			0x0020
 30#define DISP_REG_OVL_ROI_BGCLR			0x0028
 31#define DISP_REG_OVL_SRC_CON			0x002c
 32#define DISP_REG_OVL_CON(n)			(0x0030 + 0x20 * (n))
 33#define DISP_REG_OVL_SRC_SIZE(n)		(0x0038 + 0x20 * (n))
 34#define DISP_REG_OVL_OFFSET(n)			(0x003c + 0x20 * (n))
 35#define DISP_REG_OVL_PITCH(n)			(0x0044 + 0x20 * (n))
 36#define DISP_REG_OVL_RDMA_CTRL(n)		(0x00c0 + 0x20 * (n))
 37#define DISP_REG_OVL_RDMA_GMC(n)		(0x00c8 + 0x20 * (n))
 38#define DISP_REG_OVL_ADDR(n)			(0x0f40 + 0x20 * (n))
 39
 40#define	OVL_RDMA_MEM_GMC	0x40402020
 41
 42#define OVL_CON_BYTE_SWAP	BIT(24)
 43#define OVL_CON_CLRFMT_RGB565	(0 << 12)
 44#define OVL_CON_CLRFMT_RGB888	(1 << 12)
 45#define OVL_CON_CLRFMT_RGBA8888	(2 << 12)
 46#define OVL_CON_CLRFMT_ARGB8888	(3 << 12)
 47#define	OVL_CON_AEN		BIT(8)
 48#define	OVL_CON_ALPHA		0xff
 49
 50/**
 51 * struct mtk_disp_ovl - DISP_OVL driver structure
 52 * @ddp_comp - structure containing type enum and hardware resources
 53 * @crtc - associated crtc to report vblank events to
 54 */
 55struct mtk_disp_ovl {
 56	struct mtk_ddp_comp		ddp_comp;
 57	struct drm_crtc			*crtc;
 58};
 59
 60static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id)
 61{
 62	struct mtk_disp_ovl *priv = dev_id;
 63	struct mtk_ddp_comp *ovl = &priv->ddp_comp;
 64
 65	/* Clear frame completion interrupt */
 66	writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA);
 67
 68	if (!priv->crtc)
 69		return IRQ_NONE;
 70
 71	mtk_crtc_ddp_irq(priv->crtc, ovl);
 72
 73	return IRQ_HANDLED;
 74}
 75
 76static void mtk_ovl_enable_vblank(struct mtk_ddp_comp *comp,
 77				  struct drm_crtc *crtc)
 78{
 79	struct mtk_disp_ovl *priv = container_of(comp, struct mtk_disp_ovl,
 80						 ddp_comp);
 81
 82	priv->crtc = crtc;
 83	writel(0x0, comp->regs + DISP_REG_OVL_INTSTA);
 84	writel_relaxed(OVL_FME_CPL_INT, comp->regs + DISP_REG_OVL_INTEN);
 85}
 86
 87static void mtk_ovl_disable_vblank(struct mtk_ddp_comp *comp)
 88{
 89	struct mtk_disp_ovl *priv = container_of(comp, struct mtk_disp_ovl,
 90						 ddp_comp);
 91
 92	priv->crtc = NULL;
 93	writel_relaxed(0x0, comp->regs + DISP_REG_OVL_INTEN);
 94}
 95
 96static void mtk_ovl_start(struct mtk_ddp_comp *comp)
 97{
 98	writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN);
 99}
100
101static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
102{
103	writel_relaxed(0x0, comp->regs + DISP_REG_OVL_EN);
104}
105
106static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w,
107			   unsigned int h, unsigned int vrefresh,
108			   unsigned int bpc)
109{
110	if (w != 0 && h != 0)
111		writel_relaxed(h << 16 | w, comp->regs + DISP_REG_OVL_ROI_SIZE);
112	writel_relaxed(0x0, comp->regs + DISP_REG_OVL_ROI_BGCLR);
113
114	writel(0x1, comp->regs + DISP_REG_OVL_RST);
115	writel(0x0, comp->regs + DISP_REG_OVL_RST);
116}
117
118static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx)
119{
120	unsigned int reg;
121
122	writel(0x1, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
123	writel(OVL_RDMA_MEM_GMC, comp->regs + DISP_REG_OVL_RDMA_GMC(idx));
124
125	reg = readl(comp->regs + DISP_REG_OVL_SRC_CON);
126	reg = reg | BIT(idx);
127	writel(reg, comp->regs + DISP_REG_OVL_SRC_CON);
128}
129
130static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx)
131{
132	unsigned int reg;
133
134	reg = readl(comp->regs + DISP_REG_OVL_SRC_CON);
135	reg = reg & ~BIT(idx);
136	writel(reg, comp->regs + DISP_REG_OVL_SRC_CON);
137
138	writel(0x0, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
139}
140
141static unsigned int ovl_fmt_convert(unsigned int fmt)
142{
143	switch (fmt) {
144	default:
145	case DRM_FORMAT_RGB565:
146		return OVL_CON_CLRFMT_RGB565;
147	case DRM_FORMAT_BGR565:
148		return OVL_CON_CLRFMT_RGB565 | OVL_CON_BYTE_SWAP;
149	case DRM_FORMAT_RGB888:
150		return OVL_CON_CLRFMT_RGB888;
151	case DRM_FORMAT_BGR888:
152		return OVL_CON_CLRFMT_RGB888 | OVL_CON_BYTE_SWAP;
153	case DRM_FORMAT_RGBX8888:
154	case DRM_FORMAT_RGBA8888:
155		return OVL_CON_CLRFMT_ARGB8888;
156	case DRM_FORMAT_BGRX8888:
157	case DRM_FORMAT_BGRA8888:
158		return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP;
159	case DRM_FORMAT_XRGB8888:
160	case DRM_FORMAT_ARGB8888:
161		return OVL_CON_CLRFMT_RGBA8888;
162	case DRM_FORMAT_XBGR8888:
163	case DRM_FORMAT_ABGR8888:
164		return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP;
165	}
166}
167
168static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
169				 struct mtk_plane_state *state)
170{
171	struct mtk_plane_pending_state *pending = &state->pending;
172	unsigned int addr = pending->addr;
173	unsigned int pitch = pending->pitch & 0xffff;
174	unsigned int fmt = pending->format;
175	unsigned int offset = (pending->y << 16) | pending->x;
176	unsigned int src_size = (pending->height << 16) | pending->width;
177	unsigned int con;
178
179	if (!pending->enable)
180		mtk_ovl_layer_off(comp, idx);
181
182	con = ovl_fmt_convert(fmt);
183	if (idx != 0)
184		con |= OVL_CON_AEN | OVL_CON_ALPHA;
185
186	writel_relaxed(con, comp->regs + DISP_REG_OVL_CON(idx));
187	writel_relaxed(pitch, comp->regs + DISP_REG_OVL_PITCH(idx));
188	writel_relaxed(src_size, comp->regs + DISP_REG_OVL_SRC_SIZE(idx));
189	writel_relaxed(offset, comp->regs + DISP_REG_OVL_OFFSET(idx));
190	writel_relaxed(addr, comp->regs + DISP_REG_OVL_ADDR(idx));
191
192	if (pending->enable)
193		mtk_ovl_layer_on(comp, idx);
194}
195
196static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = {
197	.config = mtk_ovl_config,
198	.start = mtk_ovl_start,
199	.stop = mtk_ovl_stop,
200	.enable_vblank = mtk_ovl_enable_vblank,
201	.disable_vblank = mtk_ovl_disable_vblank,
202	.layer_on = mtk_ovl_layer_on,
203	.layer_off = mtk_ovl_layer_off,
204	.layer_config = mtk_ovl_layer_config,
205};
206
207static int mtk_disp_ovl_bind(struct device *dev, struct device *master,
208			     void *data)
209{
210	struct mtk_disp_ovl *priv = dev_get_drvdata(dev);
211	struct drm_device *drm_dev = data;
212	int ret;
213
214	ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp);
215	if (ret < 0) {
216		dev_err(dev, "Failed to register component %s: %d\n",
217			dev->of_node->full_name, ret);
218		return ret;
219	}
220
221	return 0;
222}
223
224static void mtk_disp_ovl_unbind(struct device *dev, struct device *master,
225				void *data)
226{
227	struct mtk_disp_ovl *priv = dev_get_drvdata(dev);
228	struct drm_device *drm_dev = data;
229
230	mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp);
231}
232
233static const struct component_ops mtk_disp_ovl_component_ops = {
234	.bind	= mtk_disp_ovl_bind,
235	.unbind = mtk_disp_ovl_unbind,
236};
237
238static int mtk_disp_ovl_probe(struct platform_device *pdev)
239{
240	struct device *dev = &pdev->dev;
241	struct mtk_disp_ovl *priv;
242	int comp_id;
243	int irq;
244	int ret;
245
246	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
247	if (!priv)
248		return -ENOMEM;
249
250	irq = platform_get_irq(pdev, 0);
251	if (irq < 0)
252		return irq;
253
254	comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_OVL);
255	if (comp_id < 0) {
256		dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
257		return comp_id;
258	}
259
260	ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
261				&mtk_disp_ovl_funcs);
262	if (ret) {
263		dev_err(dev, "Failed to initialize component: %d\n", ret);
264		return ret;
265	}
266
267	platform_set_drvdata(pdev, priv);
268
269	ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler,
270			       IRQF_TRIGGER_NONE, dev_name(dev), priv);
271	if (ret < 0) {
272		dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
273		return ret;
274	}
275
276	ret = component_add(dev, &mtk_disp_ovl_component_ops);
277	if (ret)
278		dev_err(dev, "Failed to add component: %d\n", ret);
279
280	return ret;
281}
282
283static int mtk_disp_ovl_remove(struct platform_device *pdev)
284{
285	component_del(&pdev->dev, &mtk_disp_ovl_component_ops);
286
287	return 0;
288}
289
290static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
291	{ .compatible = "mediatek,mt8173-disp-ovl", },
292	{},
293};
294MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
295
296struct platform_driver mtk_disp_ovl_driver = {
297	.probe		= mtk_disp_ovl_probe,
298	.remove		= mtk_disp_ovl_remove,
299	.driver		= {
300		.name	= "mediatek-disp-ovl",
301		.owner	= THIS_MODULE,
302		.of_match_table = mtk_disp_ovl_driver_dt_match,
303	},
304};