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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright © 2006-2011 Intel Corporation
4 *
5 * Authors:
6 * Eric Anholt <eric@anholt.net>
7 */
8
9#include <linux/delay.h>
10#include <linux/i2c.h>
11
12#include "framebuffer.h"
13#include "gem.h"
14#include "gma_display.h"
15#include "power.h"
16#include "psb_drv.h"
17#include "psb_intel_drv.h"
18#include "psb_intel_reg.h"
19
20#define INTEL_LIMIT_I9XX_SDVO_DAC 0
21#define INTEL_LIMIT_I9XX_LVDS 1
22
23static const struct gma_limit_t psb_intel_limits[] = {
24 { /* INTEL_LIMIT_I9XX_SDVO_DAC */
25 .dot = {.min = 20000, .max = 400000},
26 .vco = {.min = 1400000, .max = 2800000},
27 .n = {.min = 1, .max = 6},
28 .m = {.min = 70, .max = 120},
29 .m1 = {.min = 8, .max = 18},
30 .m2 = {.min = 3, .max = 7},
31 .p = {.min = 5, .max = 80},
32 .p1 = {.min = 1, .max = 8},
33 .p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 5},
34 .find_pll = gma_find_best_pll,
35 },
36 { /* INTEL_LIMIT_I9XX_LVDS */
37 .dot = {.min = 20000, .max = 400000},
38 .vco = {.min = 1400000, .max = 2800000},
39 .n = {.min = 1, .max = 6},
40 .m = {.min = 70, .max = 120},
41 .m1 = {.min = 8, .max = 18},
42 .m2 = {.min = 3, .max = 7},
43 .p = {.min = 7, .max = 98},
44 .p1 = {.min = 1, .max = 8},
45 /* The single-channel range is 25-112Mhz, and dual-channel
46 * is 80-224Mhz. Prefer single channel as much as possible.
47 */
48 .p2 = {.dot_limit = 112000, .p2_slow = 14, .p2_fast = 7},
49 .find_pll = gma_find_best_pll,
50 },
51};
52
53static const struct gma_limit_t *psb_intel_limit(struct drm_crtc *crtc,
54 int refclk)
55{
56 const struct gma_limit_t *limit;
57
58 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
59 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS];
60 else
61 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
62 return limit;
63}
64
65static void psb_intel_clock(int refclk, struct gma_clock_t *clock)
66{
67 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
68 clock->p = clock->p1 * clock->p2;
69 clock->vco = refclk * clock->m / (clock->n + 2);
70 clock->dot = clock->vco / clock->p;
71}
72
73/*
74 * Return the pipe currently connected to the panel fitter,
75 * or -1 if the panel fitter is not present or not in use
76 */
77static int psb_intel_panel_fitter_pipe(struct drm_device *dev)
78{
79 u32 pfit_control;
80
81 pfit_control = REG_READ(PFIT_CONTROL);
82
83 /* See if the panel fitter is in use */
84 if ((pfit_control & PFIT_ENABLE) == 0)
85 return -1;
86 /* Must be on PIPE 1 for PSB */
87 return 1;
88}
89
90static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
91 struct drm_display_mode *mode,
92 struct drm_display_mode *adjusted_mode,
93 int x, int y,
94 struct drm_framebuffer *old_fb)
95{
96 struct drm_device *dev = crtc->dev;
97 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
98 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
99 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
100 int pipe = gma_crtc->pipe;
101 const struct psb_offset *map = &dev_priv->regmap[pipe];
102 int refclk;
103 struct gma_clock_t clock;
104 u32 dpll = 0, fp = 0, dspcntr, pipeconf;
105 bool ok, is_sdvo = false;
106 bool is_lvds = false, is_tv = false;
107 struct drm_connector_list_iter conn_iter;
108 struct drm_connector *connector;
109 const struct gma_limit_t *limit;
110
111 /* No scan out no play */
112 if (crtc->primary->fb == NULL) {
113 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
114 return 0;
115 }
116
117 drm_connector_list_iter_begin(dev, &conn_iter);
118 drm_for_each_connector_iter(connector, &conn_iter) {
119 struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
120
121 if (!connector->encoder
122 || connector->encoder->crtc != crtc)
123 continue;
124
125 switch (gma_encoder->type) {
126 case INTEL_OUTPUT_LVDS:
127 is_lvds = true;
128 break;
129 case INTEL_OUTPUT_SDVO:
130 is_sdvo = true;
131 break;
132 case INTEL_OUTPUT_TVOUT:
133 is_tv = true;
134 break;
135 }
136
137 break;
138 }
139 drm_connector_list_iter_end(&conn_iter);
140
141 refclk = 96000;
142
143 limit = gma_crtc->clock_funcs->limit(crtc, refclk);
144
145 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
146 &clock);
147 if (!ok) {
148 DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
149 adjusted_mode->clock, clock.dot);
150 return 0;
151 }
152
153 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
154
155 dpll = DPLL_VGA_MODE_DIS;
156 if (is_lvds) {
157 dpll |= DPLLB_MODE_LVDS;
158 dpll |= DPLL_DVO_HIGH_SPEED;
159 } else
160 dpll |= DPLLB_MODE_DAC_SERIAL;
161 if (is_sdvo) {
162 int sdvo_pixel_multiply =
163 adjusted_mode->clock / mode->clock;
164 dpll |= DPLL_DVO_HIGH_SPEED;
165 dpll |=
166 (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
167 }
168
169 /* compute bitmask from p1 value */
170 dpll |= (1 << (clock.p1 - 1)) << 16;
171 switch (clock.p2) {
172 case 5:
173 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
174 break;
175 case 7:
176 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
177 break;
178 case 10:
179 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
180 break;
181 case 14:
182 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
183 break;
184 }
185
186 if (is_tv) {
187 /* XXX: just matching BIOS for now */
188/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
189 dpll |= 3;
190 }
191 dpll |= PLL_REF_INPUT_DREFCLK;
192
193 /* setup pipeconf */
194 pipeconf = REG_READ(map->conf);
195
196 /* Set up the display plane register */
197 dspcntr = DISPPLANE_GAMMA_ENABLE;
198
199 if (pipe == 0)
200 dspcntr |= DISPPLANE_SEL_PIPE_A;
201 else
202 dspcntr |= DISPPLANE_SEL_PIPE_B;
203
204 dspcntr |= DISPLAY_PLANE_ENABLE;
205 pipeconf |= PIPEACONF_ENABLE;
206 dpll |= DPLL_VCO_ENABLE;
207
208
209 /* Disable the panel fitter if it was on our pipe */
210 if (psb_intel_panel_fitter_pipe(dev) == pipe)
211 REG_WRITE(PFIT_CONTROL, 0);
212
213 drm_mode_debug_printmodeline(mode);
214
215 if (dpll & DPLL_VCO_ENABLE) {
216 REG_WRITE(map->fp0, fp);
217 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);
218 REG_READ(map->dpll);
219 udelay(150);
220 }
221
222 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
223 * This is an exception to the general rule that mode_set doesn't turn
224 * things on.
225 */
226 if (is_lvds) {
227 u32 lvds = REG_READ(LVDS);
228
229 lvds &= ~LVDS_PIPEB_SELECT;
230 if (pipe == 1)
231 lvds |= LVDS_PIPEB_SELECT;
232
233 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
234 /* Set the B0-B3 data pairs corresponding to
235 * whether we're going to
236 * set the DPLLs for dual-channel mode or not.
237 */
238 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
239 if (clock.p2 == 7)
240 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
241
242 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
243 * appropriately here, but we need to look more
244 * thoroughly into how panels behave in the two modes.
245 */
246
247 REG_WRITE(LVDS, lvds);
248 REG_READ(LVDS);
249 }
250
251 REG_WRITE(map->fp0, fp);
252 REG_WRITE(map->dpll, dpll);
253 REG_READ(map->dpll);
254 /* Wait for the clocks to stabilize. */
255 udelay(150);
256
257 /* write it again -- the BIOS does, after all */
258 REG_WRITE(map->dpll, dpll);
259
260 REG_READ(map->dpll);
261 /* Wait for the clocks to stabilize. */
262 udelay(150);
263
264 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
265 ((adjusted_mode->crtc_htotal - 1) << 16));
266 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
267 ((adjusted_mode->crtc_hblank_end - 1) << 16));
268 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
269 ((adjusted_mode->crtc_hsync_end - 1) << 16));
270 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
271 ((adjusted_mode->crtc_vtotal - 1) << 16));
272 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
273 ((adjusted_mode->crtc_vblank_end - 1) << 16));
274 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
275 ((adjusted_mode->crtc_vsync_end - 1) << 16));
276 /* pipesrc and dspsize control the size that is scaled from,
277 * which should always be the user's requested size.
278 */
279 REG_WRITE(map->size,
280 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
281 REG_WRITE(map->pos, 0);
282 REG_WRITE(map->src,
283 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
284 REG_WRITE(map->conf, pipeconf);
285 REG_READ(map->conf);
286
287 gma_wait_for_vblank(dev);
288
289 REG_WRITE(map->cntr, dspcntr);
290
291 /* Flush the plane changes */
292 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
293
294 gma_wait_for_vblank(dev);
295
296 return 0;
297}
298
299/* Returns the clock of the currently programmed mode of the given pipe. */
300static int psb_intel_crtc_clock_get(struct drm_device *dev,
301 struct drm_crtc *crtc)
302{
303 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
304 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
305 int pipe = gma_crtc->pipe;
306 const struct psb_offset *map = &dev_priv->regmap[pipe];
307 u32 dpll;
308 u32 fp;
309 struct gma_clock_t clock;
310 bool is_lvds;
311 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
312
313 if (gma_power_begin(dev, false)) {
314 dpll = REG_READ(map->dpll);
315 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
316 fp = REG_READ(map->fp0);
317 else
318 fp = REG_READ(map->fp1);
319 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
320 gma_power_end(dev);
321 } else {
322 dpll = p->dpll;
323
324 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
325 fp = p->fp0;
326 else
327 fp = p->fp1;
328
329 is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS &
330 LVDS_PORT_EN);
331 }
332
333 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
334 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
335 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
336
337 if (is_lvds) {
338 clock.p1 =
339 ffs((dpll &
340 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
341 DPLL_FPA01_P1_POST_DIV_SHIFT);
342 clock.p2 = 14;
343
344 if ((dpll & PLL_REF_INPUT_MASK) ==
345 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
346 /* XXX: might not be 66MHz */
347 psb_intel_clock(66000, &clock);
348 } else
349 psb_intel_clock(48000, &clock);
350 } else {
351 if (dpll & PLL_P1_DIVIDE_BY_TWO)
352 clock.p1 = 2;
353 else {
354 clock.p1 =
355 ((dpll &
356 DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
357 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
358 }
359 if (dpll & PLL_P2_DIVIDE_BY_4)
360 clock.p2 = 4;
361 else
362 clock.p2 = 2;
363
364 psb_intel_clock(48000, &clock);
365 }
366
367 /* XXX: It would be nice to validate the clocks, but we can't reuse
368 * i830PllIsValid() because it relies on the xf86_config connector
369 * configuration being accurate, which it isn't necessarily.
370 */
371
372 return clock.dot;
373}
374
375/** Returns the currently programmed mode of the given pipe. */
376struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
377 struct drm_crtc *crtc)
378{
379 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
380 int pipe = gma_crtc->pipe;
381 struct drm_display_mode *mode;
382 int htot;
383 int hsync;
384 int vtot;
385 int vsync;
386 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
387 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
388 const struct psb_offset *map = &dev_priv->regmap[pipe];
389
390 if (gma_power_begin(dev, false)) {
391 htot = REG_READ(map->htotal);
392 hsync = REG_READ(map->hsync);
393 vtot = REG_READ(map->vtotal);
394 vsync = REG_READ(map->vsync);
395 gma_power_end(dev);
396 } else {
397 htot = p->htotal;
398 hsync = p->hsync;
399 vtot = p->vtotal;
400 vsync = p->vsync;
401 }
402
403 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
404 if (!mode)
405 return NULL;
406
407 mode->clock = psb_intel_crtc_clock_get(dev, crtc);
408 mode->hdisplay = (htot & 0xffff) + 1;
409 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
410 mode->hsync_start = (hsync & 0xffff) + 1;
411 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
412 mode->vdisplay = (vtot & 0xffff) + 1;
413 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
414 mode->vsync_start = (vsync & 0xffff) + 1;
415 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
416
417 drm_mode_set_name(mode);
418 drm_mode_set_crtcinfo(mode, 0);
419
420 return mode;
421}
422
423const struct drm_crtc_helper_funcs psb_intel_helper_funcs = {
424 .dpms = gma_crtc_dpms,
425 .mode_set = psb_intel_crtc_mode_set,
426 .mode_set_base = gma_pipe_set_base,
427 .prepare = gma_crtc_prepare,
428 .commit = gma_crtc_commit,
429 .disable = gma_crtc_disable,
430};
431
432const struct gma_clock_funcs psb_clock_funcs = {
433 .clock = psb_intel_clock,
434 .limit = psb_intel_limit,
435 .pll_is_valid = gma_pll_is_valid,
436};
437
438/*
439 * Set the default value of cursor control and base register
440 * to zero. This is a workaround for h/w defect on Oaktrail
441 */
442static void psb_intel_cursor_init(struct drm_device *dev,
443 struct gma_crtc *gma_crtc)
444{
445 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
446 u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR };
447 u32 base[3] = { CURABASE, CURBBASE, CURCBASE };
448 struct psb_gem_object *cursor_pobj;
449
450 if (dev_priv->ops->cursor_needs_phys) {
451 /* Allocate 4 pages of stolen mem for a hardware cursor. That
452 * is enough for the 64 x 64 ARGB cursors we support.
453 */
454 cursor_pobj = psb_gem_create(dev, 4 * PAGE_SIZE, "cursor", true, PAGE_SIZE);
455 if (IS_ERR(cursor_pobj)) {
456 gma_crtc->cursor_pobj = NULL;
457 goto out;
458 }
459 gma_crtc->cursor_pobj = cursor_pobj;
460 gma_crtc->cursor_addr = dev_priv->stolen_base + cursor_pobj->offset;
461 } else {
462 gma_crtc->cursor_pobj = NULL;
463 }
464
465out:
466 REG_WRITE(control[gma_crtc->pipe], 0);
467 REG_WRITE(base[gma_crtc->pipe], 0);
468}
469
470void psb_intel_crtc_init(struct drm_device *dev, int pipe,
471 struct psb_intel_mode_device *mode_dev)
472{
473 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
474 struct gma_crtc *gma_crtc;
475 int i;
476
477 /* We allocate a extra array of drm_connector pointers
478 * for fbdev after the crtc */
479 gma_crtc = kzalloc(sizeof(struct gma_crtc) +
480 (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)),
481 GFP_KERNEL);
482 if (gma_crtc == NULL)
483 return;
484
485 gma_crtc->crtc_state =
486 kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL);
487 if (!gma_crtc->crtc_state) {
488 dev_err(dev->dev, "Crtc state error: No memory\n");
489 kfree(gma_crtc);
490 return;
491 }
492
493 drm_crtc_init(dev, &gma_crtc->base, &gma_crtc_funcs);
494
495 /* Set the CRTC clock functions from chip specific data */
496 gma_crtc->clock_funcs = dev_priv->ops->clock_funcs;
497
498 drm_mode_crtc_set_gamma_size(&gma_crtc->base, 256);
499 gma_crtc->pipe = pipe;
500 gma_crtc->plane = pipe;
501
502 for (i = 0; i < 256; i++)
503 gma_crtc->lut_adj[i] = 0;
504
505 gma_crtc->mode_dev = mode_dev;
506 gma_crtc->cursor_addr = 0;
507
508 drm_crtc_helper_add(&gma_crtc->base,
509 dev_priv->ops->crtc_helper);
510
511 /* Setup the array of drm_connector pointer array */
512 gma_crtc->mode_set.crtc = &gma_crtc->base;
513 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
514 dev_priv->plane_to_crtc_mapping[gma_crtc->plane] != NULL);
515 dev_priv->plane_to_crtc_mapping[gma_crtc->plane] = &gma_crtc->base;
516 dev_priv->pipe_to_crtc_mapping[gma_crtc->pipe] = &gma_crtc->base;
517 gma_crtc->mode_set.connectors = (struct drm_connector **)(gma_crtc + 1);
518 gma_crtc->mode_set.num_connectors = 0;
519 psb_intel_cursor_init(dev, gma_crtc);
520
521 /* Set to true so that the pipe is forced off on initial config. */
522 gma_crtc->active = true;
523}
524
525struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
526{
527 struct drm_crtc *crtc;
528
529 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
530 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
531
532 if (gma_crtc->pipe == pipe)
533 return crtc;
534 }
535 return NULL;
536}
537
538int gma_connector_clones(struct drm_device *dev, int type_mask)
539{
540 struct drm_connector_list_iter conn_iter;
541 struct drm_connector *connector;
542 int index_mask = 0;
543 int entry = 0;
544
545 drm_connector_list_iter_begin(dev, &conn_iter);
546 drm_for_each_connector_iter(connector, &conn_iter) {
547 struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
548 if (type_mask & (1 << gma_encoder->type))
549 index_mask |= (1 << entry);
550 entry++;
551 }
552 drm_connector_list_iter_end(&conn_iter);
553
554 return index_mask;
555}