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1/*
2 * Copyright (C) 2013-2015 ARM Limited
3 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive
7 * for more details.
8 *
9 * ARM HDLCD Driver
10 */
11
12#include <linux/module.h>
13#include <linux/spinlock.h>
14#include <linux/clk.h>
15#include <linux/component.h>
16#include <linux/console.h>
17#include <linux/dma-mapping.h>
18#include <linux/list.h>
19#include <linux/of_graph.h>
20#include <linux/of_reserved_mem.h>
21#include <linux/platform_device.h>
22#include <linux/pm_runtime.h>
23
24#include <drm/drm_aperture.h>
25#include <drm/drm_atomic_helper.h>
26#include <drm/drm_crtc.h>
27#include <drm/drm_debugfs.h>
28#include <drm/drm_drv.h>
29#include <drm/drm_fbdev_generic.h>
30#include <drm/drm_gem_dma_helper.h>
31#include <drm/drm_gem_framebuffer_helper.h>
32#include <drm/drm_modeset_helper.h>
33#include <drm/drm_module.h>
34#include <drm/drm_of.h>
35#include <drm/drm_probe_helper.h>
36#include <drm/drm_vblank.h>
37
38#include "hdlcd_drv.h"
39#include "hdlcd_regs.h"
40
41static irqreturn_t hdlcd_irq(int irq, void *arg)
42{
43 struct hdlcd_drm_private *hdlcd = arg;
44 unsigned long irq_status;
45
46 irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);
47
48#ifdef CONFIG_DEBUG_FS
49 if (irq_status & HDLCD_INTERRUPT_UNDERRUN)
50 atomic_inc(&hdlcd->buffer_underrun_count);
51
52 if (irq_status & HDLCD_INTERRUPT_DMA_END)
53 atomic_inc(&hdlcd->dma_end_count);
54
55 if (irq_status & HDLCD_INTERRUPT_BUS_ERROR)
56 atomic_inc(&hdlcd->bus_error_count);
57
58 if (irq_status & HDLCD_INTERRUPT_VSYNC)
59 atomic_inc(&hdlcd->vsync_count);
60
61#endif
62 if (irq_status & HDLCD_INTERRUPT_VSYNC)
63 drm_crtc_handle_vblank(&hdlcd->crtc);
64
65 /* acknowledge interrupt(s) */
66 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
67
68 return IRQ_HANDLED;
69}
70
71static int hdlcd_irq_install(struct hdlcd_drm_private *hdlcd)
72{
73 int ret;
74
75 /* Ensure interrupts are disabled */
76 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
77 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
78
79 ret = request_irq(hdlcd->irq, hdlcd_irq, 0, "hdlcd", hdlcd);
80 if (ret)
81 return ret;
82
83#ifdef CONFIG_DEBUG_FS
84 /* enable debug interrupts */
85 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, HDLCD_DEBUG_INT_MASK);
86#endif
87
88 return 0;
89}
90
91static void hdlcd_irq_uninstall(struct hdlcd_drm_private *hdlcd)
92{
93 /* disable all the interrupts that we might have enabled */
94 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
95
96 free_irq(hdlcd->irq, hdlcd);
97}
98
99static int hdlcd_load(struct drm_device *drm, unsigned long flags)
100{
101 struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
102 struct platform_device *pdev = to_platform_device(drm->dev);
103 struct resource *res;
104 u32 version;
105 int ret;
106
107 hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
108 if (IS_ERR(hdlcd->clk))
109 return PTR_ERR(hdlcd->clk);
110
111#ifdef CONFIG_DEBUG_FS
112 atomic_set(&hdlcd->buffer_underrun_count, 0);
113 atomic_set(&hdlcd->bus_error_count, 0);
114 atomic_set(&hdlcd->vsync_count, 0);
115 atomic_set(&hdlcd->dma_end_count, 0);
116#endif
117
118 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
119 hdlcd->mmio = devm_ioremap_resource(drm->dev, res);
120 if (IS_ERR(hdlcd->mmio)) {
121 DRM_ERROR("failed to map control registers area\n");
122 ret = PTR_ERR(hdlcd->mmio);
123 hdlcd->mmio = NULL;
124 return ret;
125 }
126
127 version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
128 if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
129 DRM_ERROR("unknown product id: 0x%x\n", version);
130 return -EINVAL;
131 }
132 DRM_INFO("found ARM HDLCD version r%dp%d\n",
133 (version & HDLCD_VERSION_MAJOR_MASK) >> 8,
134 version & HDLCD_VERSION_MINOR_MASK);
135
136 /* Get the optional framebuffer memory resource */
137 ret = of_reserved_mem_device_init(drm->dev);
138 if (ret && ret != -ENODEV)
139 return ret;
140
141 ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
142 if (ret)
143 goto setup_fail;
144
145 ret = hdlcd_setup_crtc(drm);
146 if (ret < 0) {
147 DRM_ERROR("failed to create crtc\n");
148 goto setup_fail;
149 }
150
151 ret = platform_get_irq(pdev, 0);
152 if (ret < 0)
153 goto irq_fail;
154 hdlcd->irq = ret;
155
156 ret = hdlcd_irq_install(hdlcd);
157 if (ret < 0) {
158 DRM_ERROR("failed to install IRQ handler\n");
159 goto irq_fail;
160 }
161
162 return 0;
163
164irq_fail:
165 drm_crtc_cleanup(&hdlcd->crtc);
166setup_fail:
167 of_reserved_mem_device_release(drm->dev);
168
169 return ret;
170}
171
172static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
173 .fb_create = drm_gem_fb_create,
174 .atomic_check = drm_atomic_helper_check,
175 .atomic_commit = drm_atomic_helper_commit,
176};
177
178static int hdlcd_setup_mode_config(struct drm_device *drm)
179{
180 int ret;
181
182 ret = drmm_mode_config_init(drm);
183 if (ret)
184 return ret;
185
186 drm->mode_config.min_width = 0;
187 drm->mode_config.min_height = 0;
188 drm->mode_config.max_width = HDLCD_MAX_XRES;
189 drm->mode_config.max_height = HDLCD_MAX_YRES;
190 drm->mode_config.funcs = &hdlcd_mode_config_funcs;
191
192 return 0;
193}
194
195#ifdef CONFIG_DEBUG_FS
196static int hdlcd_show_underrun_count(struct seq_file *m, void *arg)
197{
198 struct drm_info_node *node = (struct drm_info_node *)m->private;
199 struct drm_device *drm = node->minor->dev;
200 struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
201
202 seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
203 seq_printf(m, "dma_end : %d\n", atomic_read(&hdlcd->dma_end_count));
204 seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
205 seq_printf(m, "vsync : %d\n", atomic_read(&hdlcd->vsync_count));
206 return 0;
207}
208
209static int hdlcd_show_pxlclock(struct seq_file *m, void *arg)
210{
211 struct drm_info_node *node = (struct drm_info_node *)m->private;
212 struct drm_device *drm = node->minor->dev;
213 struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
214 unsigned long clkrate = clk_get_rate(hdlcd->clk);
215 unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
216
217 seq_printf(m, "hw : %lu\n", clkrate);
218 seq_printf(m, "mode: %lu\n", mode_clock);
219 return 0;
220}
221
222static struct drm_info_list hdlcd_debugfs_list[] = {
223 { "interrupt_count", hdlcd_show_underrun_count, 0 },
224 { "clocks", hdlcd_show_pxlclock, 0 },
225};
226
227static void hdlcd_debugfs_init(struct drm_minor *minor)
228{
229 drm_debugfs_create_files(hdlcd_debugfs_list,
230 ARRAY_SIZE(hdlcd_debugfs_list),
231 minor->debugfs_root, minor);
232}
233#endif
234
235DEFINE_DRM_GEM_DMA_FOPS(fops);
236
237static const struct drm_driver hdlcd_driver = {
238 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
239 DRM_GEM_DMA_DRIVER_OPS,
240#ifdef CONFIG_DEBUG_FS
241 .debugfs_init = hdlcd_debugfs_init,
242#endif
243 .fops = &fops,
244 .name = "hdlcd",
245 .desc = "ARM HDLCD Controller DRM",
246 .date = "20151021",
247 .major = 1,
248 .minor = 0,
249};
250
251static int hdlcd_drm_bind(struct device *dev)
252{
253 struct drm_device *drm;
254 struct hdlcd_drm_private *hdlcd;
255 int ret;
256
257 hdlcd = devm_drm_dev_alloc(dev, &hdlcd_driver, typeof(*hdlcd), base);
258 if (IS_ERR(hdlcd))
259 return PTR_ERR(hdlcd);
260
261 drm = &hdlcd->base;
262
263 dev_set_drvdata(dev, drm);
264
265 ret = hdlcd_setup_mode_config(drm);
266 if (ret)
267 goto err_free;
268
269 ret = hdlcd_load(drm, 0);
270 if (ret)
271 goto err_free;
272
273 /* Set the CRTC's port so that the encoder component can find it */
274 hdlcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
275
276 ret = component_bind_all(dev, drm);
277 if (ret) {
278 DRM_ERROR("Failed to bind all components\n");
279 goto err_unload;
280 }
281
282 ret = pm_runtime_set_active(dev);
283 if (ret)
284 goto err_pm_active;
285
286 pm_runtime_enable(dev);
287
288 ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
289 if (ret < 0) {
290 DRM_ERROR("failed to initialise vblank\n");
291 goto err_vblank;
292 }
293
294 /*
295 * If EFI left us running, take over from simple framebuffer
296 * drivers. Read HDLCD_REG_COMMAND to see if we are enabled.
297 */
298 if (hdlcd_read(hdlcd, HDLCD_REG_COMMAND)) {
299 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
300 drm_aperture_remove_framebuffers(false, &hdlcd_driver);
301 }
302
303 drm_mode_config_reset(drm);
304 drm_kms_helper_poll_init(drm);
305
306 ret = drm_dev_register(drm, 0);
307 if (ret)
308 goto err_register;
309
310 drm_fbdev_generic_setup(drm, 32);
311
312 return 0;
313
314err_register:
315 drm_kms_helper_poll_fini(drm);
316err_vblank:
317 pm_runtime_disable(drm->dev);
318err_pm_active:
319 drm_atomic_helper_shutdown(drm);
320 component_unbind_all(dev, drm);
321err_unload:
322 of_node_put(hdlcd->crtc.port);
323 hdlcd->crtc.port = NULL;
324 hdlcd_irq_uninstall(hdlcd);
325 of_reserved_mem_device_release(drm->dev);
326err_free:
327 dev_set_drvdata(dev, NULL);
328 return ret;
329}
330
331static void hdlcd_drm_unbind(struct device *dev)
332{
333 struct drm_device *drm = dev_get_drvdata(dev);
334 struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
335
336 drm_dev_unregister(drm);
337 drm_kms_helper_poll_fini(drm);
338 component_unbind_all(dev, drm);
339 of_node_put(hdlcd->crtc.port);
340 hdlcd->crtc.port = NULL;
341 pm_runtime_get_sync(dev);
342 drm_atomic_helper_shutdown(drm);
343 hdlcd_irq_uninstall(hdlcd);
344 pm_runtime_put(dev);
345 if (pm_runtime_enabled(dev))
346 pm_runtime_disable(dev);
347 of_reserved_mem_device_release(dev);
348 dev_set_drvdata(dev, NULL);
349}
350
351static const struct component_master_ops hdlcd_master_ops = {
352 .bind = hdlcd_drm_bind,
353 .unbind = hdlcd_drm_unbind,
354};
355
356static int compare_dev(struct device *dev, void *data)
357{
358 return dev->of_node == data;
359}
360
361static int hdlcd_probe(struct platform_device *pdev)
362{
363 struct device_node *port;
364 struct component_match *match = NULL;
365
366 /* there is only one output port inside each device, find it */
367 port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
368 if (!port)
369 return -ENODEV;
370
371 drm_of_component_match_add(&pdev->dev, &match, compare_dev, port);
372 of_node_put(port);
373
374 return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops,
375 match);
376}
377
378static int hdlcd_remove(struct platform_device *pdev)
379{
380 component_master_del(&pdev->dev, &hdlcd_master_ops);
381 return 0;
382}
383
384static const struct of_device_id hdlcd_of_match[] = {
385 { .compatible = "arm,hdlcd" },
386 {},
387};
388MODULE_DEVICE_TABLE(of, hdlcd_of_match);
389
390static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
391{
392 struct drm_device *drm = dev_get_drvdata(dev);
393
394 return drm_mode_config_helper_suspend(drm);
395}
396
397static int __maybe_unused hdlcd_pm_resume(struct device *dev)
398{
399 struct drm_device *drm = dev_get_drvdata(dev);
400
401 drm_mode_config_helper_resume(drm);
402
403 return 0;
404}
405
406static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume);
407
408static struct platform_driver hdlcd_platform_driver = {
409 .probe = hdlcd_probe,
410 .remove = hdlcd_remove,
411 .driver = {
412 .name = "hdlcd",
413 .pm = &hdlcd_pm_ops,
414 .of_match_table = hdlcd_of_match,
415 },
416};
417
418drm_module_platform_driver(hdlcd_platform_driver);
419
420MODULE_AUTHOR("Liviu Dudau");
421MODULE_DESCRIPTION("ARM HDLCD DRM driver");
422MODULE_LICENSE("GPL v2");