1/*
  2 * Copyright (C) 2013-2015 ARM Limited
  3 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
  4 *
  5 * This file is subject to the terms and conditions of the GNU General Public
  6 * License.  See the file COPYING in the main directory of this archive
  7 * for more details.
  8 *
  9 *  ARM HDLCD Driver
 10 */
 11
 12#include <linux/module.h>
 13#include <linux/spinlock.h>
 14#include <linux/clk.h>
 15#include <linux/component.h>
 16#include <linux/console.h>
 17#include <linux/list.h>
 18#include <linux/of_graph.h>
 19#include <linux/of_reserved_mem.h>
 20#include <linux/pm_runtime.h>
 21
 22#include <drm/drmP.h>
 23#include <drm/drm_atomic_helper.h>
 24#include <drm/drm_crtc.h>
 25#include <drm/drm_crtc_helper.h>
 26#include <drm/drm_fb_helper.h>
 27#include <drm/drm_fb_cma_helper.h>
 28#include <drm/drm_gem_cma_helper.h>
 29#include <drm/drm_gem_framebuffer_helper.h>
 30#include <drm/drm_of.h>
 31
 32#include "hdlcd_drv.h"
 33#include "hdlcd_regs.h"
 34
 35static int hdlcd_load(struct drm_device *drm, unsigned long flags)
 36{
 37	struct hdlcd_drm_private *hdlcd = drm->dev_private;
 38	struct platform_device *pdev = to_platform_device(drm->dev);
 39	struct resource *res;
 40	u32 version;
 41	int ret;
 42
 43	hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
 44	if (IS_ERR(hdlcd->clk))
 45		return PTR_ERR(hdlcd->clk);
 46
 47#ifdef CONFIG_DEBUG_FS
 48	atomic_set(&hdlcd->buffer_underrun_count, 0);
 49	atomic_set(&hdlcd->bus_error_count, 0);
 50	atomic_set(&hdlcd->vsync_count, 0);
 51	atomic_set(&hdlcd->dma_end_count, 0);
 52#endif
 53
 54	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 55	hdlcd->mmio = devm_ioremap_resource(drm->dev, res);
 56	if (IS_ERR(hdlcd->mmio)) {
 57		DRM_ERROR("failed to map control registers area\n");
 58		ret = PTR_ERR(hdlcd->mmio);
 59		hdlcd->mmio = NULL;
 60		return ret;
 61	}
 62
 63	version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
 64	if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
 65		DRM_ERROR("unknown product id: 0x%x\n", version);
 66		return -EINVAL;
 67	}
 68	DRM_INFO("found ARM HDLCD version r%dp%d\n",
 69		(version & HDLCD_VERSION_MAJOR_MASK) >> 8,
 70		version & HDLCD_VERSION_MINOR_MASK);
 71
 72	/* Get the optional framebuffer memory resource */
 73	ret = of_reserved_mem_device_init(drm->dev);
 74	if (ret && ret != -ENODEV)
 75		return ret;
 76
 77	ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
 78	if (ret)
 79		goto setup_fail;
 80
 81	ret = hdlcd_setup_crtc(drm);
 82	if (ret < 0) {
 83		DRM_ERROR("failed to create crtc\n");
 84		goto setup_fail;
 85	}
 86
 87	ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
 88	if (ret < 0) {
 89		DRM_ERROR("failed to install IRQ handler\n");
 90		goto irq_fail;
 91	}
 92
 93	return 0;
 94
 95irq_fail:
 96	drm_crtc_cleanup(&hdlcd->crtc);
 97setup_fail:
 98	of_reserved_mem_device_release(drm->dev);
 99
100	return ret;
101}
102
103static void hdlcd_fb_output_poll_changed(struct drm_device *drm)
104{
105	struct hdlcd_drm_private *hdlcd = drm->dev_private;
106
107	drm_fbdev_cma_hotplug_event(hdlcd->fbdev);
108}
109
110static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
111	.fb_create = drm_gem_fb_create,
112	.output_poll_changed = hdlcd_fb_output_poll_changed,
113	.atomic_check = drm_atomic_helper_check,
114	.atomic_commit = drm_atomic_helper_commit,
115};
116
117static void hdlcd_setup_mode_config(struct drm_device *drm)
118{
119	drm_mode_config_init(drm);
120	drm->mode_config.min_width = 0;
121	drm->mode_config.min_height = 0;
122	drm->mode_config.max_width = HDLCD_MAX_XRES;
123	drm->mode_config.max_height = HDLCD_MAX_YRES;
124	drm->mode_config.funcs = &hdlcd_mode_config_funcs;
125}
126
127static void hdlcd_lastclose(struct drm_device *drm)
128{
129	struct hdlcd_drm_private *hdlcd = drm->dev_private;
130
131	drm_fbdev_cma_restore_mode(hdlcd->fbdev);
132}
133
134static irqreturn_t hdlcd_irq(int irq, void *arg)
135{
136	struct drm_device *drm = arg;
137	struct hdlcd_drm_private *hdlcd = drm->dev_private;
138	unsigned long irq_status;
139
140	irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);
141
142#ifdef CONFIG_DEBUG_FS
143	if (irq_status & HDLCD_INTERRUPT_UNDERRUN)
144		atomic_inc(&hdlcd->buffer_underrun_count);
145
146	if (irq_status & HDLCD_INTERRUPT_DMA_END)
147		atomic_inc(&hdlcd->dma_end_count);
148
149	if (irq_status & HDLCD_INTERRUPT_BUS_ERROR)
150		atomic_inc(&hdlcd->bus_error_count);
151
152	if (irq_status & HDLCD_INTERRUPT_VSYNC)
153		atomic_inc(&hdlcd->vsync_count);
154
155#endif
156	if (irq_status & HDLCD_INTERRUPT_VSYNC)
157		drm_crtc_handle_vblank(&hdlcd->crtc);
158
159	/* acknowledge interrupt(s) */
160	hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
161
162	return IRQ_HANDLED;
163}
164
165static void hdlcd_irq_preinstall(struct drm_device *drm)
166{
167	struct hdlcd_drm_private *hdlcd = drm->dev_private;
168	/* Ensure interrupts are disabled */
169	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
170	hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
171}
172
173static int hdlcd_irq_postinstall(struct drm_device *drm)
174{
175#ifdef CONFIG_DEBUG_FS
176	struct hdlcd_drm_private *hdlcd = drm->dev_private;
177	unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
178
179	/* enable debug interrupts */
180	irq_mask |= HDLCD_DEBUG_INT_MASK;
181
182	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
183#endif
184	return 0;
185}
186
187static void hdlcd_irq_uninstall(struct drm_device *drm)
188{
189	struct hdlcd_drm_private *hdlcd = drm->dev_private;
190	/* disable all the interrupts that we might have enabled */
191	unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
192
193#ifdef CONFIG_DEBUG_FS
194	/* disable debug interrupts */
195	irq_mask &= ~HDLCD_DEBUG_INT_MASK;
196#endif
197
198	/* disable vsync interrupts */
199	irq_mask &= ~HDLCD_INTERRUPT_VSYNC;
200
201	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
202}
203
204#ifdef CONFIG_DEBUG_FS
205static int hdlcd_show_underrun_count(struct seq_file *m, void *arg)
206{
207	struct drm_info_node *node = (struct drm_info_node *)m->private;
208	struct drm_device *drm = node->minor->dev;
209	struct hdlcd_drm_private *hdlcd = drm->dev_private;
210
211	seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
212	seq_printf(m, "dma_end  : %d\n", atomic_read(&hdlcd->dma_end_count));
213	seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
214	seq_printf(m, "vsync    : %d\n", atomic_read(&hdlcd->vsync_count));
215	return 0;
216}
217
218static int hdlcd_show_pxlclock(struct seq_file *m, void *arg)
219{
220	struct drm_info_node *node = (struct drm_info_node *)m->private;
221	struct drm_device *drm = node->minor->dev;
222	struct hdlcd_drm_private *hdlcd = drm->dev_private;
223	unsigned long clkrate = clk_get_rate(hdlcd->clk);
224	unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
225
226	seq_printf(m, "hw  : %lu\n", clkrate);
227	seq_printf(m, "mode: %lu\n", mode_clock);
228	return 0;
229}
230
231static struct drm_info_list hdlcd_debugfs_list[] = {
232	{ "interrupt_count", hdlcd_show_underrun_count, 0 },
233	{ "clocks", hdlcd_show_pxlclock, 0 },
234};
235
236static int hdlcd_debugfs_init(struct drm_minor *minor)
237{
238	return drm_debugfs_create_files(hdlcd_debugfs_list,
239		ARRAY_SIZE(hdlcd_debugfs_list),	minor->debugfs_root, minor);
240}
241#endif
242
243DEFINE_DRM_GEM_CMA_FOPS(fops);
244
245static struct drm_driver hdlcd_driver = {
246	.driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
247			   DRIVER_MODESET | DRIVER_PRIME |
248			   DRIVER_ATOMIC,
249	.lastclose = hdlcd_lastclose,
250	.irq_handler = hdlcd_irq,
251	.irq_preinstall = hdlcd_irq_preinstall,
252	.irq_postinstall = hdlcd_irq_postinstall,
253	.irq_uninstall = hdlcd_irq_uninstall,
254	.gem_free_object_unlocked = drm_gem_cma_free_object,
255	.gem_print_info = drm_gem_cma_print_info,
256	.gem_vm_ops = &drm_gem_cma_vm_ops,
257	.dumb_create = drm_gem_cma_dumb_create,
258	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
259	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
260	.gem_prime_export = drm_gem_prime_export,
261	.gem_prime_import = drm_gem_prime_import,
262	.gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
263	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
264	.gem_prime_vmap = drm_gem_cma_prime_vmap,
265	.gem_prime_vunmap = drm_gem_cma_prime_vunmap,
266	.gem_prime_mmap = drm_gem_cma_prime_mmap,
267#ifdef CONFIG_DEBUG_FS
268	.debugfs_init = hdlcd_debugfs_init,
269#endif
270	.fops = &fops,
271	.name = "hdlcd",
272	.desc = "ARM HDLCD Controller DRM",
273	.date = "20151021",
274	.major = 1,
275	.minor = 0,
276};
277
278static int hdlcd_drm_bind(struct device *dev)
279{
280	struct drm_device *drm;
281	struct hdlcd_drm_private *hdlcd;
282	int ret;
283
284	hdlcd = devm_kzalloc(dev, sizeof(*hdlcd), GFP_KERNEL);
285	if (!hdlcd)
286		return -ENOMEM;
287
288	drm = drm_dev_alloc(&hdlcd_driver, dev);
289	if (IS_ERR(drm))
290		return PTR_ERR(drm);
291
292	drm->dev_private = hdlcd;
293	dev_set_drvdata(dev, drm);
294
295	hdlcd_setup_mode_config(drm);
296	ret = hdlcd_load(drm, 0);
297	if (ret)
298		goto err_free;
299
300	/* Set the CRTC's port so that the encoder component can find it */
301	hdlcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
302
303	ret = component_bind_all(dev, drm);
304	if (ret) {
305		DRM_ERROR("Failed to bind all components\n");
306		goto err_unload;
307	}
308
309	ret = pm_runtime_set_active(dev);
310	if (ret)
311		goto err_pm_active;
312
313	pm_runtime_enable(dev);
314
315	ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
316	if (ret < 0) {
317		DRM_ERROR("failed to initialise vblank\n");
318		goto err_vblank;
319	}
320
321	drm_mode_config_reset(drm);
322	drm_kms_helper_poll_init(drm);
323
324	hdlcd->fbdev = drm_fbdev_cma_init(drm, 32,
325					  drm->mode_config.num_connector);
326
327	if (IS_ERR(hdlcd->fbdev)) {
328		ret = PTR_ERR(hdlcd->fbdev);
329		hdlcd->fbdev = NULL;
330		goto err_fbdev;
331	}
332
333	ret = drm_dev_register(drm, 0);
334	if (ret)
335		goto err_register;
336
337	return 0;
338
339err_register:
340	if (hdlcd->fbdev) {
341		drm_fbdev_cma_fini(hdlcd->fbdev);
342		hdlcd->fbdev = NULL;
343	}
344err_fbdev:
345	drm_kms_helper_poll_fini(drm);
346err_vblank:
347	pm_runtime_disable(drm->dev);
348err_pm_active:
349	component_unbind_all(dev, drm);
350err_unload:
351	of_node_put(hdlcd->crtc.port);
352	hdlcd->crtc.port = NULL;
353	drm_irq_uninstall(drm);
354	of_reserved_mem_device_release(drm->dev);
355err_free:
356	drm_mode_config_cleanup(drm);
357	dev_set_drvdata(dev, NULL);
358	drm_dev_put(drm);
359
360	return ret;
361}
362
363static void hdlcd_drm_unbind(struct device *dev)
364{
365	struct drm_device *drm = dev_get_drvdata(dev);
366	struct hdlcd_drm_private *hdlcd = drm->dev_private;
367
368	drm_dev_unregister(drm);
369	if (hdlcd->fbdev) {
370		drm_fbdev_cma_fini(hdlcd->fbdev);
371		hdlcd->fbdev = NULL;
372	}
373	drm_kms_helper_poll_fini(drm);
374	component_unbind_all(dev, drm);
375	of_node_put(hdlcd->crtc.port);
376	hdlcd->crtc.port = NULL;
377	pm_runtime_get_sync(drm->dev);
378	drm_irq_uninstall(drm);
379	pm_runtime_put_sync(drm->dev);
380	pm_runtime_disable(drm->dev);
381	of_reserved_mem_device_release(drm->dev);
382	drm_mode_config_cleanup(drm);
383	drm_dev_put(drm);
384	drm->dev_private = NULL;
385	dev_set_drvdata(dev, NULL);
386}
387
388static const struct component_master_ops hdlcd_master_ops = {
389	.bind		= hdlcd_drm_bind,
390	.unbind		= hdlcd_drm_unbind,
391};
392
393static int compare_dev(struct device *dev, void *data)
394{
395	return dev->of_node == data;
396}
397
398static int hdlcd_probe(struct platform_device *pdev)
399{
400	struct device_node *port;
401	struct component_match *match = NULL;
402
403	/* there is only one output port inside each device, find it */
404	port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
405	if (!port)
406		return -ENODEV;
407
408	drm_of_component_match_add(&pdev->dev, &match, compare_dev, port);
409	of_node_put(port);
410
411	return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops,
412					       match);
413}
414
415static int hdlcd_remove(struct platform_device *pdev)
416{
417	component_master_del(&pdev->dev, &hdlcd_master_ops);
418	return 0;
419}
420
421static const struct of_device_id  hdlcd_of_match[] = {
422	{ .compatible	= "arm,hdlcd" },
423	{},
424};
425MODULE_DEVICE_TABLE(of, hdlcd_of_match);
426
427static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
428{
429	struct drm_device *drm = dev_get_drvdata(dev);
430	struct hdlcd_drm_private *hdlcd = drm ? drm->dev_private : NULL;
431
432	if (!hdlcd)
433		return 0;
434
435	drm_kms_helper_poll_disable(drm);
436	drm_fbdev_cma_set_suspend_unlocked(hdlcd->fbdev, 1);
437
438	hdlcd->state = drm_atomic_helper_suspend(drm);
439	if (IS_ERR(hdlcd->state)) {
440		drm_fbdev_cma_set_suspend_unlocked(hdlcd->fbdev, 0);
441		drm_kms_helper_poll_enable(drm);
442		return PTR_ERR(hdlcd->state);
443	}
444
445	return 0;
446}
447
448static int __maybe_unused hdlcd_pm_resume(struct device *dev)
449{
450	struct drm_device *drm = dev_get_drvdata(dev);
451	struct hdlcd_drm_private *hdlcd = drm ? drm->dev_private : NULL;
452
453	if (!hdlcd)
454		return 0;
455
456	drm_atomic_helper_resume(drm, hdlcd->state);
457	drm_fbdev_cma_set_suspend_unlocked(hdlcd->fbdev, 0);
458	drm_kms_helper_poll_enable(drm);
459
460	return 0;
461}
462
463static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume);
464
465static struct platform_driver hdlcd_platform_driver = {
466	.probe		= hdlcd_probe,
467	.remove		= hdlcd_remove,
468	.driver	= {
469		.name = "hdlcd",
470		.pm = &hdlcd_pm_ops,
471		.of_match_table	= hdlcd_of_match,
472	},
473};
474
475module_platform_driver(hdlcd_platform_driver);
476
477MODULE_AUTHOR("Liviu Dudau");
478MODULE_DESCRIPTION("ARM HDLCD DRM driver");
479MODULE_LICENSE("GPL v2");