1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 *
  4 * Parts of this file are based on Ralink's 2.6.21 BSP
  5 *
  6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  7 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  8 * Copyright (C) 2013 John Crispin <john@phrozen.org>
  9 */
 10
 11#include <linux/kernel.h>
 12#include <linux/init.h>
 13
 14#include <asm/mipsregs.h>
 15#include <asm/mach-ralink/ralink_regs.h>
 16#include <asm/mach-ralink/rt3883.h>
 17
 18#include "common.h"
 19
 20void __init ralink_clk_init(void)
 21{
 22	unsigned long cpu_rate, sys_rate;
 23	u32 syscfg0;
 24	u32 clksel;
 25	u32 ddr2;
 26
 27	syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
 28	clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
 29		RT3883_SYSCFG0_CPUCLK_MASK);
 30	ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
 31
 32	switch (clksel) {
 33	case RT3883_SYSCFG0_CPUCLK_250:
 34		cpu_rate = 250000000;
 35		sys_rate = (ddr2) ? 125000000 : 83000000;
 36		break;
 37	case RT3883_SYSCFG0_CPUCLK_384:
 38		cpu_rate = 384000000;
 39		sys_rate = (ddr2) ? 128000000 : 96000000;
 40		break;
 41	case RT3883_SYSCFG0_CPUCLK_480:
 42		cpu_rate = 480000000;
 43		sys_rate = (ddr2) ? 160000000 : 120000000;
 44		break;
 45	case RT3883_SYSCFG0_CPUCLK_500:
 46		cpu_rate = 500000000;
 47		sys_rate = (ddr2) ? 166000000 : 125000000;
 48		break;
 49	}
 50
 51	ralink_clk_add("cpu", cpu_rate);
 52	ralink_clk_add("10000100.timer", sys_rate);
 53	ralink_clk_add("10000120.watchdog", sys_rate);
 54	ralink_clk_add("10000500.uart", 40000000);
 55	ralink_clk_add("10000900.i2c", 40000000);
 56	ralink_clk_add("10000a00.i2s", 40000000);
 57	ralink_clk_add("10000b00.spi", sys_rate);
 58	ralink_clk_add("10000b40.spi", sys_rate);
 59	ralink_clk_add("10000c00.uartlite", 40000000);
 60	ralink_clk_add("10100000.ethernet", sys_rate);
 61	ralink_clk_add("10180000.wmac", 40000000);
 62}
 63
 64void __init ralink_of_remap(void)
 65{
 66	rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
 67	rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc");
 68
 69	if (!rt_sysc_membase || !rt_memc_membase)
 70		panic("Failed to remap core resources");
 71}
 72
 73void __init prom_soc_init(struct ralink_soc_info *soc_info)
 74{
 75	void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
 76	const char *name;
 77	u32 n0;
 78	u32 n1;
 79	u32 id;
 80
 81	n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3);
 82	n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7);
 83	id = __raw_readl(sysc + RT3883_SYSC_REG_REVID);
 84
 85	if (n0 == RT3883_CHIP_NAME0 && n1 == RT3883_CHIP_NAME1) {
 86		soc_info->compatible = "ralink,rt3883-soc";
 87		name = "RT3883";
 88	} else {
 89		panic("rt3883: unknown SoC, n0:%08x n1:%08x", n0, n1);
 90	}
 91
 92	snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
 93		"Ralink %s ver:%u eco:%u",
 94		name,
 95		(id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
 96		(id & RT3883_REVID_ECO_ID_MASK));
 97
 98	soc_info->mem_base = RT3883_SDRAM_BASE;
 99	soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
100	soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
101
102	ralink_soc = RT3883_SOC;
103}