1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 *
  4 * Parts of this file are based on Ralink's 2.6.21 BSP
  5 *
  6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  7 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  8 * Copyright (C) 2013 John Crispin <john@phrozen.org>
  9 */
 10
 11#include <linux/kernel.h>
 12#include <linux/init.h>
 13
 14#include <asm/mipsregs.h>
 15#include <asm/mach-ralink/ralink_regs.h>
 16#include <asm/mach-ralink/rt3883.h>
 17#include <asm/mach-ralink/pinmux.h>
 18
 19#include "common.h"
 20
 21static struct rt2880_pmx_func i2c_func[] =  { FUNC("i2c", 0, 1, 2) };
 22static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
 23static struct rt2880_pmx_func uartf_func[] = {
 24	FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8),
 25	FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8),
 26	FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8),
 27	FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8),
 28	FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4),
 29	FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4),
 30	FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4),
 31};
 32static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
 33static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
 34static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
 35static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
 36static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna g", 0, 35, 3) };
 37static struct rt2880_pmx_func pci_func[] = {
 38	FUNC("pci-dev", 0, 40, 32),
 39	FUNC("pci-host2", 1, 40, 32),
 40	FUNC("pci-host1", 2, 40, 32),
 41	FUNC("pci-fnc", 3, 40, 32)
 42};
 43static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) };
 44static struct rt2880_pmx_func ge2_func[] = { FUNC("ge2", 0, 84, 12) };
 45
 46static struct rt2880_pmx_group rt3883_pinmux_data[] = {
 47	GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C),
 48	GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI),
 49	GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK,
 50		RT3883_GPIO_MODE_UART0_SHIFT),
 51	GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1),
 52	GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG),
 53	GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO),
 54	GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A),
 55	GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G),
 56	GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK,
 57		RT3883_GPIO_MODE_PCI_SHIFT),
 58	GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1),
 59	GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2),
 60	{ 0 }
 61};
 62
 63void __init ralink_clk_init(void)
 64{
 65	unsigned long cpu_rate, sys_rate;
 66	u32 syscfg0;
 67	u32 clksel;
 68	u32 ddr2;
 69
 70	syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
 71	clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
 72		RT3883_SYSCFG0_CPUCLK_MASK);
 73	ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
 74
 75	switch (clksel) {
 76	case RT3883_SYSCFG0_CPUCLK_250:
 77		cpu_rate = 250000000;
 78		sys_rate = (ddr2) ? 125000000 : 83000000;
 79		break;
 80	case RT3883_SYSCFG0_CPUCLK_384:
 81		cpu_rate = 384000000;
 82		sys_rate = (ddr2) ? 128000000 : 96000000;
 83		break;
 84	case RT3883_SYSCFG0_CPUCLK_480:
 85		cpu_rate = 480000000;
 86		sys_rate = (ddr2) ? 160000000 : 120000000;
 87		break;
 88	case RT3883_SYSCFG0_CPUCLK_500:
 89		cpu_rate = 500000000;
 90		sys_rate = (ddr2) ? 166000000 : 125000000;
 91		break;
 92	}
 93
 94	ralink_clk_add("cpu", cpu_rate);
 95	ralink_clk_add("10000100.timer", sys_rate);
 96	ralink_clk_add("10000120.watchdog", sys_rate);
 97	ralink_clk_add("10000500.uart", 40000000);
 98	ralink_clk_add("10000900.i2c", 40000000);
 99	ralink_clk_add("10000a00.i2s", 40000000);
100	ralink_clk_add("10000b00.spi", sys_rate);
101	ralink_clk_add("10000b40.spi", sys_rate);
102	ralink_clk_add("10000c00.uartlite", 40000000);
103	ralink_clk_add("10100000.ethernet", sys_rate);
104	ralink_clk_add("10180000.wmac", 40000000);
105}
106
107void __init ralink_of_remap(void)
108{
109	rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
110	rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc");
111
112	if (!rt_sysc_membase || !rt_memc_membase)
113		panic("Failed to remap core resources");
114}
115
116void prom_soc_init(struct ralink_soc_info *soc_info)
117{
118	void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
119	const char *name;
120	u32 n0;
121	u32 n1;
122	u32 id;
123
124	n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3);
125	n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7);
126	id = __raw_readl(sysc + RT3883_SYSC_REG_REVID);
127
128	if (n0 == RT3883_CHIP_NAME0 && n1 == RT3883_CHIP_NAME1) {
129		soc_info->compatible = "ralink,rt3883-soc";
130		name = "RT3883";
131	} else {
132		panic("rt3883: unknown SoC, n0:%08x n1:%08x", n0, n1);
133	}
134
135	snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
136		"Ralink %s ver:%u eco:%u",
137		name,
138		(id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
139		(id & RT3883_REVID_ECO_ID_MASK));
140
141	soc_info->mem_base = RT3883_SDRAM_BASE;
142	soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
143	soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
144
145	rt2880_pinmux_data = rt3883_pinmux_data;
146
147	ralink_soc = RT3883_SOC;
148}