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1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * core_intr.c - DesignWare HS OTG Controller common interrupt handling
4 *
5 * Copyright (C) 2004-2013 Synopsys, Inc.
6 */
7
8/*
9 * This file contains the common interrupt handlers
10 */
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/spinlock.h>
15#include <linux/interrupt.h>
16#include <linux/dma-mapping.h>
17#include <linux/io.h>
18#include <linux/slab.h>
19#include <linux/usb.h>
20
21#include <linux/usb/hcd.h>
22#include <linux/usb/ch11.h>
23
24#include "core.h"
25#include "hcd.h"
26
27static const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg)
28{
29 switch (hsotg->op_state) {
30 case OTG_STATE_A_HOST:
31 return "a_host";
32 case OTG_STATE_A_SUSPEND:
33 return "a_suspend";
34 case OTG_STATE_A_PERIPHERAL:
35 return "a_peripheral";
36 case OTG_STATE_B_PERIPHERAL:
37 return "b_peripheral";
38 case OTG_STATE_B_HOST:
39 return "b_host";
40 default:
41 return "unknown";
42 }
43}
44
45/**
46 * dwc2_handle_usb_port_intr - handles OTG PRTINT interrupts.
47 * When the PRTINT interrupt fires, there are certain status bits in the Host
48 * Port that needs to get cleared.
49 *
50 * @hsotg: Programming view of DWC_otg controller
51 */
52static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg)
53{
54 u32 hprt0 = dwc2_readl(hsotg, HPRT0);
55
56 if (hprt0 & HPRT0_ENACHG) {
57 hprt0 &= ~HPRT0_ENA;
58 dwc2_writel(hsotg, hprt0, HPRT0);
59 }
60}
61
62/**
63 * dwc2_handle_mode_mismatch_intr() - Logs a mode mismatch warning message
64 *
65 * @hsotg: Programming view of DWC_otg controller
66 */
67static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg)
68{
69 /* Clear interrupt */
70 dwc2_writel(hsotg, GINTSTS_MODEMIS, GINTSTS);
71
72 dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n",
73 dwc2_is_host_mode(hsotg) ? "Host" : "Device");
74}
75
76/**
77 * dwc2_handle_otg_intr() - Handles the OTG Interrupts. It reads the OTG
78 * Interrupt Register (GOTGINT) to determine what interrupt has occurred.
79 *
80 * @hsotg: Programming view of DWC_otg controller
81 */
82static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
83{
84 u32 gotgint;
85 u32 gotgctl;
86 u32 gintmsk;
87 u32 pcgctl;
88
89 gotgint = dwc2_readl(hsotg, GOTGINT);
90 gotgctl = dwc2_readl(hsotg, GOTGCTL);
91 dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint,
92 dwc2_op_state_str(hsotg));
93
94 if (gotgint & GOTGINT_SES_END_DET) {
95 dev_dbg(hsotg->dev,
96 " ++OTG Interrupt: Session End Detected++ (%s)\n",
97 dwc2_op_state_str(hsotg));
98 gotgctl = dwc2_readl(hsotg, GOTGCTL);
99
100 if (dwc2_is_device_mode(hsotg)) {
101 if (hsotg->params.eusb2_disc) {
102 /* Clear the Gate hclk. */
103 pcgctl = dwc2_readl(hsotg, PCGCTL);
104 pcgctl &= ~PCGCTL_GATEHCLK;
105 dwc2_writel(hsotg, pcgctl, PCGCTL);
106 udelay(5);
107
108 /* Clear Phy Clock bit. */
109 pcgctl = dwc2_readl(hsotg, PCGCTL);
110 pcgctl &= ~PCGCTL_STOPPCLK;
111 dwc2_writel(hsotg, pcgctl, PCGCTL);
112 udelay(5);
113 }
114 dwc2_hsotg_disconnect(hsotg);
115 }
116
117 if (hsotg->op_state == OTG_STATE_B_HOST) {
118 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
119 } else {
120 /*
121 * If not B_HOST and Device HNP still set, HNP did
122 * not succeed!
123 */
124 if (gotgctl & GOTGCTL_DEVHNPEN) {
125 dev_dbg(hsotg->dev, "Session End Detected\n");
126 dev_err(hsotg->dev,
127 "Device Not Connected/Responding!\n");
128 }
129
130 /*
131 * If Session End Detected the B-Cable has been
132 * disconnected
133 */
134 /* Reset to a clean state */
135 hsotg->lx_state = DWC2_L3;
136 }
137
138 gotgctl = dwc2_readl(hsotg, GOTGCTL);
139 gotgctl &= ~GOTGCTL_DEVHNPEN;
140 dwc2_writel(hsotg, gotgctl, GOTGCTL);
141 }
142
143 if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) {
144 dev_dbg(hsotg->dev,
145 " ++OTG Interrupt: Session Request Success Status Change++\n");
146 gotgctl = dwc2_readl(hsotg, GOTGCTL);
147 if (gotgctl & GOTGCTL_SESREQSCS) {
148 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
149 hsotg->params.i2c_enable) {
150 hsotg->srp_success = 1;
151 } else {
152 /* Clear Session Request */
153 gotgctl = dwc2_readl(hsotg, GOTGCTL);
154 gotgctl &= ~GOTGCTL_SESREQ;
155 dwc2_writel(hsotg, gotgctl, GOTGCTL);
156 }
157 }
158 }
159
160 if (gotgint & GOTGINT_HST_NEG_SUC_STS_CHNG) {
161 /*
162 * Print statements during the HNP interrupt handling
163 * can cause it to fail
164 */
165 gotgctl = dwc2_readl(hsotg, GOTGCTL);
166 /*
167 * WA for 3.00a- HW is not setting cur_mode, even sometimes
168 * this does not help
169 */
170 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)
171 udelay(100);
172 if (gotgctl & GOTGCTL_HSTNEGSCS) {
173 if (dwc2_is_host_mode(hsotg)) {
174 hsotg->op_state = OTG_STATE_B_HOST;
175 /*
176 * Need to disable SOF interrupt immediately.
177 * When switching from device to host, the PCD
178 * interrupt handler won't handle the interrupt
179 * if host mode is already set. The HCD
180 * interrupt handler won't get called if the
181 * HCD state is HALT. This means that the
182 * interrupt does not get handled and Linux
183 * complains loudly.
184 */
185 gintmsk = dwc2_readl(hsotg, GINTMSK);
186 gintmsk &= ~GINTSTS_SOF;
187 dwc2_writel(hsotg, gintmsk, GINTMSK);
188
189 /*
190 * Call callback function with spin lock
191 * released
192 */
193 spin_unlock(&hsotg->lock);
194
195 /* Initialize the Core for Host mode */
196 dwc2_hcd_start(hsotg);
197 spin_lock(&hsotg->lock);
198 hsotg->op_state = OTG_STATE_B_HOST;
199 }
200 } else {
201 gotgctl = dwc2_readl(hsotg, GOTGCTL);
202 gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN);
203 dwc2_writel(hsotg, gotgctl, GOTGCTL);
204 dev_dbg(hsotg->dev, "HNP Failed\n");
205 dev_err(hsotg->dev,
206 "Device Not Connected/Responding\n");
207 }
208 }
209
210 if (gotgint & GOTGINT_HST_NEG_DET) {
211 /*
212 * The disconnect interrupt is set at the same time as
213 * Host Negotiation Detected. During the mode switch all
214 * interrupts are cleared so the disconnect interrupt
215 * handler will not get executed.
216 */
217 dev_dbg(hsotg->dev,
218 " ++OTG Interrupt: Host Negotiation Detected++ (%s)\n",
219 (dwc2_is_host_mode(hsotg) ? "Host" : "Device"));
220 if (dwc2_is_device_mode(hsotg)) {
221 dev_dbg(hsotg->dev, "a_suspend->a_peripheral (%d)\n",
222 hsotg->op_state);
223 spin_unlock(&hsotg->lock);
224 dwc2_hcd_disconnect(hsotg, false);
225 spin_lock(&hsotg->lock);
226 hsotg->op_state = OTG_STATE_A_PERIPHERAL;
227 } else {
228 /* Need to disable SOF interrupt immediately */
229 gintmsk = dwc2_readl(hsotg, GINTMSK);
230 gintmsk &= ~GINTSTS_SOF;
231 dwc2_writel(hsotg, gintmsk, GINTMSK);
232 spin_unlock(&hsotg->lock);
233 dwc2_hcd_start(hsotg);
234 spin_lock(&hsotg->lock);
235 hsotg->op_state = OTG_STATE_A_HOST;
236 }
237 }
238
239 if (gotgint & GOTGINT_A_DEV_TOUT_CHG)
240 dev_dbg(hsotg->dev,
241 " ++OTG Interrupt: A-Device Timeout Change++\n");
242 if (gotgint & GOTGINT_DBNCE_DONE)
243 dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n");
244
245 /* Clear GOTGINT */
246 dwc2_writel(hsotg, gotgint, GOTGINT);
247}
248
249/**
250 * dwc2_handle_conn_id_status_change_intr() - Handles the Connector ID Status
251 * Change Interrupt
252 *
253 * @hsotg: Programming view of DWC_otg controller
254 *
255 * Reads the OTG Interrupt Register (GOTCTL) to determine whether this is a
256 * Device to Host Mode transition or a Host to Device Mode transition. This only
257 * occurs when the cable is connected/removed from the PHY connector.
258 */
259static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg)
260{
261 u32 gintmsk;
262
263 /* Clear interrupt */
264 dwc2_writel(hsotg, GINTSTS_CONIDSTSCHNG, GINTSTS);
265
266 /* Need to disable SOF interrupt immediately */
267 gintmsk = dwc2_readl(hsotg, GINTMSK);
268 gintmsk &= ~GINTSTS_SOF;
269 dwc2_writel(hsotg, gintmsk, GINTMSK);
270
271 dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n",
272 dwc2_is_host_mode(hsotg) ? "Host" : "Device");
273
274 /*
275 * Need to schedule a work, as there are possible DELAY function calls.
276 */
277 if (hsotg->wq_otg)
278 queue_work(hsotg->wq_otg, &hsotg->wf_otg);
279}
280
281/**
282 * dwc2_handle_session_req_intr() - This interrupt indicates that a device is
283 * initiating the Session Request Protocol to request the host to turn on bus
284 * power so a new session can begin
285 *
286 * @hsotg: Programming view of DWC_otg controller
287 *
288 * This handler responds by turning on bus power. If the DWC_otg controller is
289 * in low power mode, this handler brings the controller out of low power mode
290 * before turning on bus power.
291 */
292static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
293{
294 int ret;
295 u32 hprt0;
296
297 /* Clear interrupt */
298 dwc2_writel(hsotg, GINTSTS_SESSREQINT, GINTSTS);
299
300 dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n",
301 hsotg->lx_state);
302
303 if (dwc2_is_device_mode(hsotg)) {
304 if (hsotg->lx_state != DWC2_L0) {
305 if (hsotg->in_ppd) {
306 ret = dwc2_exit_partial_power_down(hsotg, 0,
307 true);
308 if (ret)
309 dev_err(hsotg->dev,
310 "exit power_down failed\n");
311 }
312
313 /* Exit gadget mode clock gating. */
314 if (hsotg->params.power_down ==
315 DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended &&
316 !hsotg->params.no_clock_gating)
317 dwc2_gadget_exit_clock_gating(hsotg, 0);
318 }
319
320 /*
321 * Report disconnect if there is any previous session
322 * established
323 */
324 dwc2_hsotg_disconnect(hsotg);
325 } else {
326 /* Turn on the port power bit. */
327 hprt0 = dwc2_read_hprt0(hsotg);
328 hprt0 |= HPRT0_PWR;
329 dwc2_writel(hsotg, hprt0, HPRT0);
330 /* Connect hcd after port power is set. */
331 dwc2_hcd_connect(hsotg);
332 }
333}
334
335/**
336 * dwc2_wakeup_from_lpm_l1 - Exit the device from LPM L1 state
337 *
338 * @hsotg: Programming view of DWC_otg controller
339 *
340 */
341void dwc2_wakeup_from_lpm_l1(struct dwc2_hsotg *hsotg, bool remotewakeup)
342{
343 u32 glpmcfg;
344 u32 pcgctl;
345 u32 dctl;
346
347 if (hsotg->lx_state != DWC2_L1) {
348 dev_err(hsotg->dev, "Core isn't in DWC2_L1 state\n");
349 return;
350 }
351
352 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
353 if (dwc2_is_device_mode(hsotg)) {
354 dev_dbg(hsotg->dev, "Exit from L1 state, remotewakeup=%d\n", remotewakeup);
355 glpmcfg &= ~GLPMCFG_ENBLSLPM;
356 glpmcfg &= ~GLPMCFG_HIRD_THRES_MASK;
357 dwc2_writel(hsotg, glpmcfg, GLPMCFG);
358
359 pcgctl = dwc2_readl(hsotg, PCGCTL);
360 pcgctl &= ~PCGCTL_ENBL_SLEEP_GATING;
361 dwc2_writel(hsotg, pcgctl, PCGCTL);
362
363 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
364 if (glpmcfg & GLPMCFG_ENBESL) {
365 glpmcfg |= GLPMCFG_RSTRSLPSTS;
366 dwc2_writel(hsotg, glpmcfg, GLPMCFG);
367 }
368
369 if (remotewakeup) {
370 if (dwc2_hsotg_wait_bit_set(hsotg, GLPMCFG, GLPMCFG_L1RESUMEOK, 1000)) {
371 dev_warn(hsotg->dev, "%s: timeout GLPMCFG_L1RESUMEOK\n", __func__);
372 goto fail;
373 return;
374 }
375
376 dctl = dwc2_readl(hsotg, DCTL);
377 dctl |= DCTL_RMTWKUPSIG;
378 dwc2_writel(hsotg, dctl, DCTL);
379
380 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, GINTSTS_WKUPINT, 1000)) {
381 dev_warn(hsotg->dev, "%s: timeout GINTSTS_WKUPINT\n", __func__);
382 goto fail;
383 return;
384 }
385 }
386
387 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
388 if (glpmcfg & GLPMCFG_COREL1RES_MASK || glpmcfg & GLPMCFG_SLPSTS ||
389 glpmcfg & GLPMCFG_L1RESUMEOK) {
390 goto fail;
391 return;
392 }
393
394 /* Inform gadget to exit from L1 */
395 call_gadget(hsotg, resume);
396 /* Change to L0 state */
397 hsotg->lx_state = DWC2_L0;
398 hsotg->bus_suspended = false;
399fail: dwc2_gadget_init_lpm(hsotg);
400 } else {
401 /* TODO */
402 dev_err(hsotg->dev, "Host side LPM is not supported.\n");
403 return;
404 }
405}
406
407/*
408 * This interrupt indicates that the DWC_otg controller has detected a
409 * resume or remote wakeup sequence. If the DWC_otg controller is in
410 * low power mode, the handler must brings the controller out of low
411 * power mode. The controller automatically begins resume signaling.
412 * The handler schedules a time to stop resume signaling.
413 */
414static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
415{
416 int ret;
417
418 /* Clear interrupt */
419 dwc2_writel(hsotg, GINTSTS_WKUPINT, GINTSTS);
420
421 dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n");
422 dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state);
423
424 if (hsotg->lx_state == DWC2_L1) {
425 dwc2_wakeup_from_lpm_l1(hsotg, false);
426 return;
427 }
428
429 if (dwc2_is_device_mode(hsotg)) {
430 dev_dbg(hsotg->dev, "DSTS=0x%0x\n",
431 dwc2_readl(hsotg, DSTS));
432 if (hsotg->lx_state == DWC2_L2) {
433 if (hsotg->in_ppd) {
434 u32 dctl = dwc2_readl(hsotg, DCTL);
435 /* Clear Remote Wakeup Signaling */
436 dctl &= ~DCTL_RMTWKUPSIG;
437 dwc2_writel(hsotg, dctl, DCTL);
438 ret = dwc2_exit_partial_power_down(hsotg, 1,
439 true);
440 if (ret)
441 dev_err(hsotg->dev,
442 "exit partial_power_down failed\n");
443 call_gadget(hsotg, resume);
444 }
445
446 /* Exit gadget mode clock gating. */
447 if (hsotg->params.power_down ==
448 DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended &&
449 !hsotg->params.no_clock_gating)
450 dwc2_gadget_exit_clock_gating(hsotg, 0);
451 } else {
452 /* Change to L0 state */
453 hsotg->lx_state = DWC2_L0;
454 }
455 } else {
456 if (hsotg->lx_state == DWC2_L2) {
457 if (hsotg->in_ppd) {
458 ret = dwc2_exit_partial_power_down(hsotg, 1,
459 true);
460 if (ret)
461 dev_err(hsotg->dev,
462 "exit partial_power_down failed\n");
463 }
464
465 if (hsotg->params.power_down ==
466 DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended &&
467 !hsotg->params.no_clock_gating)
468 dwc2_host_exit_clock_gating(hsotg, 1);
469
470 /*
471 * If we've got this quirk then the PHY is stuck upon
472 * wakeup. Assert reset. This will propagate out and
473 * eventually we'll re-enumerate the device. Not great
474 * but the best we can do. We can't call phy_reset()
475 * at interrupt time but there's no hurry, so we'll
476 * schedule it for later.
477 */
478 if (hsotg->reset_phy_on_wake)
479 dwc2_host_schedule_phy_reset(hsotg);
480
481 mod_timer(&hsotg->wkp_timer,
482 jiffies + msecs_to_jiffies(71));
483 } else {
484 /* Change to L0 state */
485 hsotg->lx_state = DWC2_L0;
486 }
487 }
488}
489
490/*
491 * This interrupt indicates that a device has been disconnected from the
492 * root port
493 */
494static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg)
495{
496 dwc2_writel(hsotg, GINTSTS_DISCONNINT, GINTSTS);
497
498 dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n",
499 dwc2_is_host_mode(hsotg) ? "Host" : "Device",
500 dwc2_op_state_str(hsotg));
501
502 if (hsotg->op_state == OTG_STATE_A_HOST)
503 dwc2_hcd_disconnect(hsotg, false);
504}
505
506/*
507 * This interrupt indicates that SUSPEND state has been detected on the USB.
508 *
509 * For HNP the USB Suspend interrupt signals the change from "a_peripheral"
510 * to "a_host".
511 *
512 * When power management is enabled the core will be put in low power mode.
513 */
514static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
515{
516 u32 dsts;
517 int ret;
518
519 /* Clear interrupt */
520 dwc2_writel(hsotg, GINTSTS_USBSUSP, GINTSTS);
521
522 dev_dbg(hsotg->dev, "USB SUSPEND\n");
523
524 if (dwc2_is_device_mode(hsotg)) {
525 /*
526 * Check the Device status register to determine if the Suspend
527 * state is active
528 */
529 dsts = dwc2_readl(hsotg, DSTS);
530 dev_dbg(hsotg->dev, "%s: DSTS=0x%0x\n", __func__, dsts);
531 dev_dbg(hsotg->dev,
532 "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d HWCFG4.Hibernation=%d\n",
533 !!(dsts & DSTS_SUSPSTS),
534 hsotg->hw_params.power_optimized,
535 hsotg->hw_params.hibernation);
536
537 /* Ignore suspend request before enumeration */
538 if (!dwc2_is_device_connected(hsotg)) {
539 dev_dbg(hsotg->dev,
540 "ignore suspend request before enumeration\n");
541 return;
542 }
543 if (dsts & DSTS_SUSPSTS) {
544 switch (hsotg->params.power_down) {
545 case DWC2_POWER_DOWN_PARAM_PARTIAL:
546 ret = dwc2_enter_partial_power_down(hsotg);
547 if (ret)
548 dev_err(hsotg->dev,
549 "enter partial_power_down failed\n");
550
551 udelay(100);
552
553 /* Ask phy to be suspended */
554 if (!IS_ERR_OR_NULL(hsotg->uphy))
555 usb_phy_set_suspend(hsotg->uphy, true);
556 break;
557 case DWC2_POWER_DOWN_PARAM_HIBERNATION:
558 ret = dwc2_enter_hibernation(hsotg, 0);
559 if (ret)
560 dev_err(hsotg->dev,
561 "enter hibernation failed\n");
562 break;
563 case DWC2_POWER_DOWN_PARAM_NONE:
564 /*
565 * If neither hibernation nor partial power down are supported,
566 * clock gating is used to save power.
567 */
568 if (!hsotg->params.no_clock_gating)
569 dwc2_gadget_enter_clock_gating(hsotg);
570 }
571
572 /*
573 * Change to L2 (suspend) state before releasing
574 * spinlock
575 */
576 hsotg->lx_state = DWC2_L2;
577
578 /* Call gadget suspend callback */
579 call_gadget(hsotg, suspend);
580 }
581 } else {
582 if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) {
583 dev_dbg(hsotg->dev, "a_peripheral->a_host\n");
584
585 /* Change to L2 (suspend) state */
586 hsotg->lx_state = DWC2_L2;
587 /* Clear the a_peripheral flag, back to a_host */
588 spin_unlock(&hsotg->lock);
589 dwc2_hcd_start(hsotg);
590 spin_lock(&hsotg->lock);
591 hsotg->op_state = OTG_STATE_A_HOST;
592 }
593 }
594}
595
596/**
597 * dwc2_handle_lpm_intr - GINTSTS_LPMTRANRCVD Interrupt handler
598 *
599 * @hsotg: Programming view of DWC_otg controller
600 *
601 */
602static void dwc2_handle_lpm_intr(struct dwc2_hsotg *hsotg)
603{
604 u32 glpmcfg;
605 u32 pcgcctl;
606 u32 hird;
607 u32 hird_thres;
608 u32 hird_thres_en;
609 u32 enslpm;
610
611 /* Clear interrupt */
612 dwc2_writel(hsotg, GINTSTS_LPMTRANRCVD, GINTSTS);
613
614 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
615
616 if (!(glpmcfg & GLPMCFG_LPMCAP)) {
617 dev_err(hsotg->dev, "Unexpected LPM interrupt\n");
618 return;
619 }
620
621 hird = (glpmcfg & GLPMCFG_HIRD_MASK) >> GLPMCFG_HIRD_SHIFT;
622 hird_thres = (glpmcfg & GLPMCFG_HIRD_THRES_MASK &
623 ~GLPMCFG_HIRD_THRES_EN) >> GLPMCFG_HIRD_THRES_SHIFT;
624 hird_thres_en = glpmcfg & GLPMCFG_HIRD_THRES_EN;
625 enslpm = glpmcfg & GLPMCFG_ENBLSLPM;
626
627 if (dwc2_is_device_mode(hsotg)) {
628 dev_dbg(hsotg->dev, "HIRD_THRES_EN = %d\n", hird_thres_en);
629
630 if (hird_thres_en && hird >= hird_thres) {
631 dev_dbg(hsotg->dev, "L1 with utmi_l1_suspend_n\n");
632 } else if (enslpm) {
633 dev_dbg(hsotg->dev, "L1 with utmi_sleep_n\n");
634 } else {
635 dev_dbg(hsotg->dev, "Entering Sleep with L1 Gating\n");
636
637 pcgcctl = dwc2_readl(hsotg, PCGCTL);
638 pcgcctl |= PCGCTL_ENBL_SLEEP_GATING;
639 dwc2_writel(hsotg, pcgcctl, PCGCTL);
640 }
641 /**
642 * Examine prt_sleep_sts after TL1TokenTetry period max (10 us)
643 */
644 udelay(10);
645
646 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
647
648 if (glpmcfg & GLPMCFG_SLPSTS) {
649 /* Save the current state */
650 hsotg->lx_state = DWC2_L1;
651 dev_dbg(hsotg->dev,
652 "Core is in L1 sleep glpmcfg=%08x\n", glpmcfg);
653
654 /* Inform gadget that we are in L1 state */
655 call_gadget(hsotg, suspend);
656 }
657 }
658}
659
660#define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \
661 GINTSTS_CONIDSTSCHNG | GINTSTS_OTGINT | \
662 GINTSTS_MODEMIS | GINTSTS_DISCONNINT | \
663 GINTSTS_USBSUSP | GINTSTS_PRTINT | \
664 GINTSTS_LPMTRANRCVD)
665
666/*
667 * This function returns the Core Interrupt register
668 */
669static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg)
670{
671 u32 gintsts;
672 u32 gintmsk;
673 u32 gahbcfg;
674 u32 gintmsk_common = GINTMSK_COMMON;
675
676 gintsts = dwc2_readl(hsotg, GINTSTS);
677 gintmsk = dwc2_readl(hsotg, GINTMSK);
678 gahbcfg = dwc2_readl(hsotg, GAHBCFG);
679
680 /* If any common interrupts set */
681 if (gintsts & gintmsk_common)
682 dev_dbg(hsotg->dev, "gintsts=%08x gintmsk=%08x\n",
683 gintsts, gintmsk);
684
685 if (gahbcfg & GAHBCFG_GLBL_INTR_EN)
686 return gintsts & gintmsk & gintmsk_common;
687 else
688 return 0;
689}
690
691/**
692 * dwc_handle_gpwrdn_disc_det() - Handles the gpwrdn disconnect detect.
693 * Exits hibernation without restoring registers.
694 *
695 * @hsotg: Programming view of DWC_otg controller
696 * @gpwrdn: GPWRDN register
697 */
698static inline void dwc_handle_gpwrdn_disc_det(struct dwc2_hsotg *hsotg,
699 u32 gpwrdn)
700{
701 u32 gpwrdn_tmp;
702
703 /* Switch-on voltage to the core */
704 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
705 gpwrdn_tmp &= ~GPWRDN_PWRDNSWTCH;
706 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
707 udelay(5);
708
709 /* Reset core */
710 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
711 gpwrdn_tmp &= ~GPWRDN_PWRDNRSTN;
712 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
713 udelay(5);
714
715 /* Disable Power Down Clamp */
716 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
717 gpwrdn_tmp &= ~GPWRDN_PWRDNCLMP;
718 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
719 udelay(5);
720
721 /* Deassert reset core */
722 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
723 gpwrdn_tmp |= GPWRDN_PWRDNRSTN;
724 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
725 udelay(5);
726
727 /* Disable PMU interrupt */
728 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
729 gpwrdn_tmp &= ~GPWRDN_PMUINTSEL;
730 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
731
732 /* Reset ULPI latch */
733 gpwrdn = dwc2_readl(hsotg, GPWRDN);
734 gpwrdn &= ~GPWRDN_ULPI_LATCH_EN_DURING_HIB_ENTRY;
735 dwc2_writel(hsotg, gpwrdn, GPWRDN);
736
737 /* De-assert Wakeup Logic */
738 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
739 gpwrdn_tmp &= ~GPWRDN_PMUACTV;
740 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
741
742 hsotg->hibernated = 0;
743 hsotg->bus_suspended = 0;
744
745 if (gpwrdn & GPWRDN_IDSTS) {
746 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
747 dwc2_core_init(hsotg, false);
748 dwc2_enable_global_interrupts(hsotg);
749 dwc2_hsotg_core_init_disconnected(hsotg, false);
750 dwc2_hsotg_core_connect(hsotg);
751 } else {
752 hsotg->op_state = OTG_STATE_A_HOST;
753
754 /* Initialize the Core for Host mode */
755 dwc2_core_init(hsotg, false);
756 dwc2_enable_global_interrupts(hsotg);
757 dwc2_hcd_start(hsotg);
758 }
759}
760
761/*
762 * GPWRDN interrupt handler.
763 *
764 * The GPWRDN interrupts are those that occur in both Host and
765 * Device mode while core is in hibernated state.
766 */
767static int dwc2_handle_gpwrdn_intr(struct dwc2_hsotg *hsotg)
768{
769 u32 gpwrdn;
770 int linestate;
771 int ret = 0;
772
773 gpwrdn = dwc2_readl(hsotg, GPWRDN);
774 /* clear all interrupt */
775 dwc2_writel(hsotg, gpwrdn, GPWRDN);
776 linestate = (gpwrdn & GPWRDN_LINESTATE_MASK) >> GPWRDN_LINESTATE_SHIFT;
777 dev_dbg(hsotg->dev,
778 "%s: dwc2_handle_gpwrdwn_intr called gpwrdn= %08x\n", __func__,
779 gpwrdn);
780
781 if ((gpwrdn & GPWRDN_DISCONN_DET) &&
782 (gpwrdn & GPWRDN_DISCONN_DET_MSK) && !linestate) {
783 dev_dbg(hsotg->dev, "%s: GPWRDN_DISCONN_DET\n", __func__);
784 /*
785 * Call disconnect detect function to exit from
786 * hibernation
787 */
788 dwc_handle_gpwrdn_disc_det(hsotg, gpwrdn);
789 } else if ((gpwrdn & GPWRDN_LNSTSCHG) &&
790 (gpwrdn & GPWRDN_LNSTSCHG_MSK) && linestate) {
791 dev_dbg(hsotg->dev, "%s: GPWRDN_LNSTSCHG\n", __func__);
792 if (hsotg->hw_params.hibernation &&
793 hsotg->hibernated) {
794 if (gpwrdn & GPWRDN_IDSTS) {
795 ret = dwc2_exit_hibernation(hsotg, 0, 0, 0);
796 if (ret)
797 dev_err(hsotg->dev,
798 "exit hibernation failed.\n");
799 call_gadget(hsotg, resume);
800 } else {
801 ret = dwc2_exit_hibernation(hsotg, 1, 0, 1);
802 if (ret)
803 dev_err(hsotg->dev,
804 "exit hibernation failed.\n");
805 }
806 }
807 } else if ((gpwrdn & GPWRDN_RST_DET) &&
808 (gpwrdn & GPWRDN_RST_DET_MSK)) {
809 dev_dbg(hsotg->dev, "%s: GPWRDN_RST_DET\n", __func__);
810 if (!linestate) {
811 ret = dwc2_exit_hibernation(hsotg, 0, 1, 0);
812 if (ret)
813 dev_err(hsotg->dev,
814 "exit hibernation failed.\n");
815 }
816 } else if ((gpwrdn & GPWRDN_STS_CHGINT) &&
817 (gpwrdn & GPWRDN_STS_CHGINT_MSK)) {
818 dev_dbg(hsotg->dev, "%s: GPWRDN_STS_CHGINT\n", __func__);
819 /*
820 * As GPWRDN_STS_CHGINT exit from hibernation flow is
821 * the same as in GPWRDN_DISCONN_DET flow. Call
822 * disconnect detect helper function to exit from
823 * hibernation.
824 */
825 dwc_handle_gpwrdn_disc_det(hsotg, gpwrdn);
826 }
827
828 return ret;
829}
830
831/*
832 * Common interrupt handler
833 *
834 * The common interrupts are those that occur in both Host and Device mode.
835 * This handler handles the following interrupts:
836 * - Mode Mismatch Interrupt
837 * - OTG Interrupt
838 * - Connector ID Status Change Interrupt
839 * - Disconnect Interrupt
840 * - Session Request Interrupt
841 * - Resume / Remote Wakeup Detected Interrupt
842 * - Suspend Interrupt
843 */
844irqreturn_t dwc2_handle_common_intr(int irq, void *dev)
845{
846 struct dwc2_hsotg *hsotg = dev;
847 u32 gintsts;
848 irqreturn_t retval = IRQ_NONE;
849
850 spin_lock(&hsotg->lock);
851
852 if (!dwc2_is_controller_alive(hsotg)) {
853 dev_warn(hsotg->dev, "Controller is dead\n");
854 goto out;
855 }
856
857 /* Reading current frame number value in device or host modes. */
858 if (dwc2_is_device_mode(hsotg))
859 hsotg->frame_number = (dwc2_readl(hsotg, DSTS)
860 & DSTS_SOFFN_MASK) >> DSTS_SOFFN_SHIFT;
861 else
862 hsotg->frame_number = (dwc2_readl(hsotg, HFNUM)
863 & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
864
865 gintsts = dwc2_read_common_intr(hsotg);
866 if (gintsts & ~GINTSTS_PRTINT)
867 retval = IRQ_HANDLED;
868
869 /* In case of hibernated state gintsts must not work */
870 if (hsotg->hibernated) {
871 dwc2_handle_gpwrdn_intr(hsotg);
872 retval = IRQ_HANDLED;
873 goto out;
874 }
875
876 if (gintsts & GINTSTS_MODEMIS)
877 dwc2_handle_mode_mismatch_intr(hsotg);
878 if (gintsts & GINTSTS_OTGINT)
879 dwc2_handle_otg_intr(hsotg);
880 if (gintsts & GINTSTS_CONIDSTSCHNG)
881 dwc2_handle_conn_id_status_change_intr(hsotg);
882 if (gintsts & GINTSTS_DISCONNINT)
883 dwc2_handle_disconnect_intr(hsotg);
884 if (gintsts & GINTSTS_SESSREQINT)
885 dwc2_handle_session_req_intr(hsotg);
886 if (gintsts & GINTSTS_WKUPINT)
887 dwc2_handle_wakeup_detected_intr(hsotg);
888 if (gintsts & GINTSTS_USBSUSP)
889 dwc2_handle_usb_suspend_intr(hsotg);
890 if (gintsts & GINTSTS_LPMTRANRCVD)
891 dwc2_handle_lpm_intr(hsotg);
892
893 if (gintsts & GINTSTS_PRTINT) {
894 /*
895 * The port interrupt occurs while in device mode with HPRT0
896 * Port Enable/Disable
897 */
898 if (dwc2_is_device_mode(hsotg)) {
899 dev_dbg(hsotg->dev,
900 " --Port interrupt received in Device mode--\n");
901 dwc2_handle_usb_port_intr(hsotg);
902 retval = IRQ_HANDLED;
903 }
904 }
905
906out:
907 spin_unlock(&hsotg->lock);
908 return retval;
909}