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1/*
2 * An rtc driver for the Dallas DS1511
3 *
4 * Copyright (C) 2006 Atsushi Nemoto <anemo@mba.ocn.ne.jp>
5 * Copyright (C) 2007 Andrew Sharp <andy.sharp@lsi.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Real time clock driver for the Dallas 1511 chip, which also
12 * contains a watchdog timer. There is a tiny amount of code that
13 * platform code could use to mess with the watchdog device a little
14 * bit, but not a full watchdog driver.
15 */
16
17#include <linux/bcd.h>
18#include <linux/init.h>
19#include <linux/kernel.h>
20#include <linux/gfp.h>
21#include <linux/delay.h>
22#include <linux/interrupt.h>
23#include <linux/rtc.h>
24#include <linux/platform_device.h>
25#include <linux/io.h>
26
27#define DRV_VERSION "0.6"
28
29enum ds1511reg {
30 DS1511_SEC = 0x0,
31 DS1511_MIN = 0x1,
32 DS1511_HOUR = 0x2,
33 DS1511_DOW = 0x3,
34 DS1511_DOM = 0x4,
35 DS1511_MONTH = 0x5,
36 DS1511_YEAR = 0x6,
37 DS1511_CENTURY = 0x7,
38 DS1511_AM1_SEC = 0x8,
39 DS1511_AM2_MIN = 0x9,
40 DS1511_AM3_HOUR = 0xa,
41 DS1511_AM4_DATE = 0xb,
42 DS1511_WD_MSEC = 0xc,
43 DS1511_WD_SEC = 0xd,
44 DS1511_CONTROL_A = 0xe,
45 DS1511_CONTROL_B = 0xf,
46 DS1511_RAMADDR_LSB = 0x10,
47 DS1511_RAMDATA = 0x13
48};
49
50#define DS1511_BLF1 0x80
51#define DS1511_BLF2 0x40
52#define DS1511_PRS 0x20
53#define DS1511_PAB 0x10
54#define DS1511_TDF 0x08
55#define DS1511_KSF 0x04
56#define DS1511_WDF 0x02
57#define DS1511_IRQF 0x01
58#define DS1511_TE 0x80
59#define DS1511_CS 0x40
60#define DS1511_BME 0x20
61#define DS1511_TPE 0x10
62#define DS1511_TIE 0x08
63#define DS1511_KIE 0x04
64#define DS1511_WDE 0x02
65#define DS1511_WDS 0x01
66#define DS1511_RAM_MAX 0xff
67
68#define RTC_CMD DS1511_CONTROL_B
69#define RTC_CMD1 DS1511_CONTROL_A
70
71#define RTC_ALARM_SEC DS1511_AM1_SEC
72#define RTC_ALARM_MIN DS1511_AM2_MIN
73#define RTC_ALARM_HOUR DS1511_AM3_HOUR
74#define RTC_ALARM_DATE DS1511_AM4_DATE
75
76#define RTC_SEC DS1511_SEC
77#define RTC_MIN DS1511_MIN
78#define RTC_HOUR DS1511_HOUR
79#define RTC_DOW DS1511_DOW
80#define RTC_DOM DS1511_DOM
81#define RTC_MON DS1511_MONTH
82#define RTC_YEAR DS1511_YEAR
83#define RTC_CENTURY DS1511_CENTURY
84
85#define RTC_TIE DS1511_TIE
86#define RTC_TE DS1511_TE
87
88struct rtc_plat_data {
89 struct rtc_device *rtc;
90 void __iomem *ioaddr; /* virtual base address */
91 int size; /* amount of memory mapped */
92 int irq;
93 unsigned int irqen;
94 int alrm_sec;
95 int alrm_min;
96 int alrm_hour;
97 int alrm_mday;
98 spinlock_t lock;
99};
100
101static DEFINE_SPINLOCK(ds1511_lock);
102
103static __iomem char *ds1511_base;
104static u32 reg_spacing = 1;
105
106 static noinline void
107rtc_write(uint8_t val, uint32_t reg)
108{
109 writeb(val, ds1511_base + (reg * reg_spacing));
110}
111
112 static inline void
113rtc_write_alarm(uint8_t val, enum ds1511reg reg)
114{
115 rtc_write((val | 0x80), reg);
116}
117
118 static noinline uint8_t
119rtc_read(enum ds1511reg reg)
120{
121 return readb(ds1511_base + (reg * reg_spacing));
122}
123
124 static inline void
125rtc_disable_update(void)
126{
127 rtc_write((rtc_read(RTC_CMD) & ~RTC_TE), RTC_CMD);
128}
129
130 static void
131rtc_enable_update(void)
132{
133 rtc_write((rtc_read(RTC_CMD) | RTC_TE), RTC_CMD);
134}
135
136/*
137 * #define DS1511_WDOG_RESET_SUPPORT
138 *
139 * Uncomment this if you want to use these routines in
140 * some platform code.
141 */
142#ifdef DS1511_WDOG_RESET_SUPPORT
143/*
144 * just enough code to set the watchdog timer so that it
145 * will reboot the system
146 */
147 void
148ds1511_wdog_set(unsigned long deciseconds)
149{
150 /*
151 * the wdog timer can take 99.99 seconds
152 */
153 deciseconds %= 10000;
154 /*
155 * set the wdog values in the wdog registers
156 */
157 rtc_write(bin2bcd(deciseconds % 100), DS1511_WD_MSEC);
158 rtc_write(bin2bcd(deciseconds / 100), DS1511_WD_SEC);
159 /*
160 * set wdog enable and wdog 'steering' bit to issue a reset
161 */
162 rtc_write(DS1511_WDE | DS1511_WDS, RTC_CMD);
163}
164
165 void
166ds1511_wdog_disable(void)
167{
168 /*
169 * clear wdog enable and wdog 'steering' bits
170 */
171 rtc_write(rtc_read(RTC_CMD) & ~(DS1511_WDE | DS1511_WDS), RTC_CMD);
172 /*
173 * clear the wdog counter
174 */
175 rtc_write(0, DS1511_WD_MSEC);
176 rtc_write(0, DS1511_WD_SEC);
177}
178#endif
179
180/*
181 * set the rtc chip's idea of the time.
182 * stupidly, some callers call with year unmolested;
183 * and some call with year = year - 1900. thanks.
184 */
185static int ds1511_rtc_set_time(struct device *dev, struct rtc_time *rtc_tm)
186{
187 u8 mon, day, dow, hrs, min, sec, yrs, cen;
188 unsigned long flags;
189
190 /*
191 * won't have to change this for a while
192 */
193 if (rtc_tm->tm_year < 1900) {
194 rtc_tm->tm_year += 1900;
195 }
196
197 if (rtc_tm->tm_year < 1970) {
198 return -EINVAL;
199 }
200 yrs = rtc_tm->tm_year % 100;
201 cen = rtc_tm->tm_year / 100;
202 mon = rtc_tm->tm_mon + 1; /* tm_mon starts at zero */
203 day = rtc_tm->tm_mday;
204 dow = rtc_tm->tm_wday & 0x7; /* automatic BCD */
205 hrs = rtc_tm->tm_hour;
206 min = rtc_tm->tm_min;
207 sec = rtc_tm->tm_sec;
208
209 if ((mon > 12) || (day == 0)) {
210 return -EINVAL;
211 }
212
213 if (day > rtc_month_days(rtc_tm->tm_mon, rtc_tm->tm_year)) {
214 return -EINVAL;
215 }
216
217 if ((hrs >= 24) || (min >= 60) || (sec >= 60)) {
218 return -EINVAL;
219 }
220
221 /*
222 * each register is a different number of valid bits
223 */
224 sec = bin2bcd(sec) & 0x7f;
225 min = bin2bcd(min) & 0x7f;
226 hrs = bin2bcd(hrs) & 0x3f;
227 day = bin2bcd(day) & 0x3f;
228 mon = bin2bcd(mon) & 0x1f;
229 yrs = bin2bcd(yrs) & 0xff;
230 cen = bin2bcd(cen) & 0xff;
231
232 spin_lock_irqsave(&ds1511_lock, flags);
233 rtc_disable_update();
234 rtc_write(cen, RTC_CENTURY);
235 rtc_write(yrs, RTC_YEAR);
236 rtc_write((rtc_read(RTC_MON) & 0xe0) | mon, RTC_MON);
237 rtc_write(day, RTC_DOM);
238 rtc_write(hrs, RTC_HOUR);
239 rtc_write(min, RTC_MIN);
240 rtc_write(sec, RTC_SEC);
241 rtc_write(dow, RTC_DOW);
242 rtc_enable_update();
243 spin_unlock_irqrestore(&ds1511_lock, flags);
244
245 return 0;
246}
247
248static int ds1511_rtc_read_time(struct device *dev, struct rtc_time *rtc_tm)
249{
250 unsigned int century;
251 unsigned long flags;
252
253 spin_lock_irqsave(&ds1511_lock, flags);
254 rtc_disable_update();
255
256 rtc_tm->tm_sec = rtc_read(RTC_SEC) & 0x7f;
257 rtc_tm->tm_min = rtc_read(RTC_MIN) & 0x7f;
258 rtc_tm->tm_hour = rtc_read(RTC_HOUR) & 0x3f;
259 rtc_tm->tm_mday = rtc_read(RTC_DOM) & 0x3f;
260 rtc_tm->tm_wday = rtc_read(RTC_DOW) & 0x7;
261 rtc_tm->tm_mon = rtc_read(RTC_MON) & 0x1f;
262 rtc_tm->tm_year = rtc_read(RTC_YEAR) & 0x7f;
263 century = rtc_read(RTC_CENTURY);
264
265 rtc_enable_update();
266 spin_unlock_irqrestore(&ds1511_lock, flags);
267
268 rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec);
269 rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min);
270 rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour);
271 rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday);
272 rtc_tm->tm_wday = bcd2bin(rtc_tm->tm_wday);
273 rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon);
274 rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year);
275 century = bcd2bin(century) * 100;
276
277 /*
278 * Account for differences between how the RTC uses the values
279 * and how they are defined in a struct rtc_time;
280 */
281 century += rtc_tm->tm_year;
282 rtc_tm->tm_year = century - 1900;
283
284 rtc_tm->tm_mon--;
285
286 if (rtc_valid_tm(rtc_tm) < 0) {
287 dev_err(dev, "retrieved date/time is not valid.\n");
288 rtc_time_to_tm(0, rtc_tm);
289 }
290 return 0;
291}
292
293/*
294 * write the alarm register settings
295 *
296 * we only have the use to interrupt every second, otherwise
297 * known as the update interrupt, or the interrupt if the whole
298 * date/hours/mins/secs matches. the ds1511 has many more
299 * permutations, but the kernel doesn't.
300 */
301 static void
302ds1511_rtc_update_alarm(struct rtc_plat_data *pdata)
303{
304 unsigned long flags;
305
306 spin_lock_irqsave(&pdata->lock, flags);
307 rtc_write(pdata->alrm_mday < 0 || (pdata->irqen & RTC_UF) ?
308 0x80 : bin2bcd(pdata->alrm_mday) & 0x3f,
309 RTC_ALARM_DATE);
310 rtc_write(pdata->alrm_hour < 0 || (pdata->irqen & RTC_UF) ?
311 0x80 : bin2bcd(pdata->alrm_hour) & 0x3f,
312 RTC_ALARM_HOUR);
313 rtc_write(pdata->alrm_min < 0 || (pdata->irqen & RTC_UF) ?
314 0x80 : bin2bcd(pdata->alrm_min) & 0x7f,
315 RTC_ALARM_MIN);
316 rtc_write(pdata->alrm_sec < 0 || (pdata->irqen & RTC_UF) ?
317 0x80 : bin2bcd(pdata->alrm_sec) & 0x7f,
318 RTC_ALARM_SEC);
319 rtc_write(rtc_read(RTC_CMD) | (pdata->irqen ? RTC_TIE : 0), RTC_CMD);
320 rtc_read(RTC_CMD1); /* clear interrupts */
321 spin_unlock_irqrestore(&pdata->lock, flags);
322}
323
324 static int
325ds1511_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
326{
327 struct platform_device *pdev = to_platform_device(dev);
328 struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
329
330 if (pdata->irq <= 0)
331 return -EINVAL;
332
333 pdata->alrm_mday = alrm->time.tm_mday;
334 pdata->alrm_hour = alrm->time.tm_hour;
335 pdata->alrm_min = alrm->time.tm_min;
336 pdata->alrm_sec = alrm->time.tm_sec;
337 if (alrm->enabled) {
338 pdata->irqen |= RTC_AF;
339 }
340 ds1511_rtc_update_alarm(pdata);
341 return 0;
342}
343
344 static int
345ds1511_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
346{
347 struct platform_device *pdev = to_platform_device(dev);
348 struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
349
350 if (pdata->irq <= 0)
351 return -EINVAL;
352
353 alrm->time.tm_mday = pdata->alrm_mday < 0 ? 0 : pdata->alrm_mday;
354 alrm->time.tm_hour = pdata->alrm_hour < 0 ? 0 : pdata->alrm_hour;
355 alrm->time.tm_min = pdata->alrm_min < 0 ? 0 : pdata->alrm_min;
356 alrm->time.tm_sec = pdata->alrm_sec < 0 ? 0 : pdata->alrm_sec;
357 alrm->enabled = (pdata->irqen & RTC_AF) ? 1 : 0;
358 return 0;
359}
360
361 static irqreturn_t
362ds1511_interrupt(int irq, void *dev_id)
363{
364 struct platform_device *pdev = dev_id;
365 struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
366 unsigned long events = 0;
367
368 spin_lock(&pdata->lock);
369 /*
370 * read and clear interrupt
371 */
372 if (rtc_read(RTC_CMD1) & DS1511_IRQF) {
373 events = RTC_IRQF;
374 if (rtc_read(RTC_ALARM_SEC) & 0x80)
375 events |= RTC_UF;
376 else
377 events |= RTC_AF;
378 if (likely(pdata->rtc))
379 rtc_update_irq(pdata->rtc, 1, events);
380 }
381 spin_unlock(&pdata->lock);
382 return events ? IRQ_HANDLED : IRQ_NONE;
383}
384
385static int ds1511_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
386{
387 struct platform_device *pdev = to_platform_device(dev);
388 struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
389
390 if (pdata->irq <= 0)
391 return -EINVAL;
392 if (enabled)
393 pdata->irqen |= RTC_AF;
394 else
395 pdata->irqen &= ~RTC_AF;
396 ds1511_rtc_update_alarm(pdata);
397 return 0;
398}
399
400static const struct rtc_class_ops ds1511_rtc_ops = {
401 .read_time = ds1511_rtc_read_time,
402 .set_time = ds1511_rtc_set_time,
403 .read_alarm = ds1511_rtc_read_alarm,
404 .set_alarm = ds1511_rtc_set_alarm,
405 .alarm_irq_enable = ds1511_rtc_alarm_irq_enable,
406};
407
408 static ssize_t
409ds1511_nvram_read(struct file *filp, struct kobject *kobj,
410 struct bin_attribute *ba,
411 char *buf, loff_t pos, size_t size)
412{
413 ssize_t count;
414
415 /*
416 * if count is more than one, turn on "burst" mode
417 * turn it off when you're done
418 */
419 if (size > 1) {
420 rtc_write((rtc_read(RTC_CMD) | DS1511_BME), RTC_CMD);
421 }
422 if (pos > DS1511_RAM_MAX) {
423 pos = DS1511_RAM_MAX;
424 }
425 if (size + pos > DS1511_RAM_MAX + 1) {
426 size = DS1511_RAM_MAX - pos + 1;
427 }
428 rtc_write(pos, DS1511_RAMADDR_LSB);
429 for (count = 0; size > 0; count++, size--) {
430 *buf++ = rtc_read(DS1511_RAMDATA);
431 }
432 if (count > 1) {
433 rtc_write((rtc_read(RTC_CMD) & ~DS1511_BME), RTC_CMD);
434 }
435 return count;
436}
437
438 static ssize_t
439ds1511_nvram_write(struct file *filp, struct kobject *kobj,
440 struct bin_attribute *bin_attr,
441 char *buf, loff_t pos, size_t size)
442{
443 ssize_t count;
444
445 /*
446 * if count is more than one, turn on "burst" mode
447 * turn it off when you're done
448 */
449 if (size > 1) {
450 rtc_write((rtc_read(RTC_CMD) | DS1511_BME), RTC_CMD);
451 }
452 if (pos > DS1511_RAM_MAX) {
453 pos = DS1511_RAM_MAX;
454 }
455 if (size + pos > DS1511_RAM_MAX + 1) {
456 size = DS1511_RAM_MAX - pos + 1;
457 }
458 rtc_write(pos, DS1511_RAMADDR_LSB);
459 for (count = 0; size > 0; count++, size--) {
460 rtc_write(*buf++, DS1511_RAMDATA);
461 }
462 if (count > 1) {
463 rtc_write((rtc_read(RTC_CMD) & ~DS1511_BME), RTC_CMD);
464 }
465 return count;
466}
467
468static struct bin_attribute ds1511_nvram_attr = {
469 .attr = {
470 .name = "nvram",
471 .mode = S_IRUGO | S_IWUSR,
472 },
473 .size = DS1511_RAM_MAX,
474 .read = ds1511_nvram_read,
475 .write = ds1511_nvram_write,
476};
477
478 static int __devinit
479ds1511_rtc_probe(struct platform_device *pdev)
480{
481 struct rtc_device *rtc;
482 struct resource *res;
483 struct rtc_plat_data *pdata;
484 int ret = 0;
485
486 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
487 if (!res) {
488 return -ENODEV;
489 }
490 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
491 if (!pdata)
492 return -ENOMEM;
493 pdata->size = resource_size(res);
494 if (!devm_request_mem_region(&pdev->dev, res->start, pdata->size,
495 pdev->name))
496 return -EBUSY;
497 ds1511_base = devm_ioremap(&pdev->dev, res->start, pdata->size);
498 if (!ds1511_base)
499 return -ENOMEM;
500 pdata->ioaddr = ds1511_base;
501 pdata->irq = platform_get_irq(pdev, 0);
502
503 /*
504 * turn on the clock and the crystal, etc.
505 */
506 rtc_write(0, RTC_CMD);
507 rtc_write(0, RTC_CMD1);
508 /*
509 * clear the wdog counter
510 */
511 rtc_write(0, DS1511_WD_MSEC);
512 rtc_write(0, DS1511_WD_SEC);
513 /*
514 * start the clock
515 */
516 rtc_enable_update();
517
518 /*
519 * check for a dying bat-tree
520 */
521 if (rtc_read(RTC_CMD1) & DS1511_BLF1) {
522 dev_warn(&pdev->dev, "voltage-low detected.\n");
523 }
524
525 spin_lock_init(&pdata->lock);
526 platform_set_drvdata(pdev, pdata);
527 /*
528 * if the platform has an interrupt in mind for this device,
529 * then by all means, set it
530 */
531 if (pdata->irq > 0) {
532 rtc_read(RTC_CMD1);
533 if (devm_request_irq(&pdev->dev, pdata->irq, ds1511_interrupt,
534 IRQF_DISABLED | IRQF_SHARED, pdev->name, pdev) < 0) {
535
536 dev_warn(&pdev->dev, "interrupt not available.\n");
537 pdata->irq = 0;
538 }
539 }
540
541 rtc = rtc_device_register(pdev->name, &pdev->dev, &ds1511_rtc_ops,
542 THIS_MODULE);
543 if (IS_ERR(rtc))
544 return PTR_ERR(rtc);
545 pdata->rtc = rtc;
546
547 ret = sysfs_create_bin_file(&pdev->dev.kobj, &ds1511_nvram_attr);
548 if (ret)
549 rtc_device_unregister(pdata->rtc);
550 return ret;
551}
552
553 static int __devexit
554ds1511_rtc_remove(struct platform_device *pdev)
555{
556 struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
557
558 sysfs_remove_bin_file(&pdev->dev.kobj, &ds1511_nvram_attr);
559 rtc_device_unregister(pdata->rtc);
560 if (pdata->irq > 0) {
561 /*
562 * disable the alarm interrupt
563 */
564 rtc_write(rtc_read(RTC_CMD) & ~RTC_TIE, RTC_CMD);
565 rtc_read(RTC_CMD1);
566 }
567 return 0;
568}
569
570/* work with hotplug and coldplug */
571MODULE_ALIAS("platform:ds1511");
572
573static struct platform_driver ds1511_rtc_driver = {
574 .probe = ds1511_rtc_probe,
575 .remove = __devexit_p(ds1511_rtc_remove),
576 .driver = {
577 .name = "ds1511",
578 .owner = THIS_MODULE,
579 },
580};
581
582 static int __init
583ds1511_rtc_init(void)
584{
585 return platform_driver_register(&ds1511_rtc_driver);
586}
587
588 static void __exit
589ds1511_rtc_exit(void)
590{
591 platform_driver_unregister(&ds1511_rtc_driver);
592}
593
594module_init(ds1511_rtc_init);
595module_exit(ds1511_rtc_exit);
596
597MODULE_AUTHOR("Andrew Sharp <andy.sharp@lsi.com>");
598MODULE_DESCRIPTION("Dallas DS1511 RTC driver");
599MODULE_LICENSE("GPL");
600MODULE_VERSION(DRV_VERSION);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * An rtc driver for the Dallas DS1511
4 *
5 * Copyright (C) 2006 Atsushi Nemoto <anemo@mba.ocn.ne.jp>
6 * Copyright (C) 2007 Andrew Sharp <andy.sharp@lsi.com>
7 *
8 * Real time clock driver for the Dallas 1511 chip, which also
9 * contains a watchdog timer. There is a tiny amount of code that
10 * platform code could use to mess with the watchdog device a little
11 * bit, but not a full watchdog driver.
12 */
13
14#include <linux/bcd.h>
15#include <linux/init.h>
16#include <linux/kernel.h>
17#include <linux/gfp.h>
18#include <linux/delay.h>
19#include <linux/interrupt.h>
20#include <linux/rtc.h>
21#include <linux/platform_device.h>
22#include <linux/io.h>
23#include <linux/module.h>
24
25#define DS1511_SEC 0x0
26#define DS1511_MIN 0x1
27#define DS1511_HOUR 0x2
28#define DS1511_DOW 0x3
29#define DS1511_DOM 0x4
30#define DS1511_MONTH 0x5
31#define DS1511_YEAR 0x6
32#define DS1511_CENTURY 0x7
33#define DS1511_AM1_SEC 0x8
34#define DS1511_AM2_MIN 0x9
35#define DS1511_AM3_HOUR 0xa
36#define DS1511_AM4_DATE 0xb
37#define DS1511_WD_MSEC 0xc
38#define DS1511_WD_SEC 0xd
39#define DS1511_CONTROL_A 0xe
40#define DS1511_CONTROL_B 0xf
41#define DS1511_RAMADDR_LSB 0x10
42#define DS1511_RAMDATA 0x13
43
44#define DS1511_BLF1 0x80
45#define DS1511_BLF2 0x40
46#define DS1511_PRS 0x20
47#define DS1511_PAB 0x10
48#define DS1511_TDF 0x08
49#define DS1511_KSF 0x04
50#define DS1511_WDF 0x02
51#define DS1511_IRQF 0x01
52#define DS1511_TE 0x80
53#define DS1511_CS 0x40
54#define DS1511_BME 0x20
55#define DS1511_TPE 0x10
56#define DS1511_TIE 0x08
57#define DS1511_KIE 0x04
58#define DS1511_WDE 0x02
59#define DS1511_WDS 0x01
60#define DS1511_RAM_MAX 0x100
61
62struct ds1511_data {
63 struct rtc_device *rtc;
64 void __iomem *ioaddr; /* virtual base address */
65 int irq;
66 spinlock_t lock;
67};
68
69static DEFINE_SPINLOCK(ds1511_lock);
70
71static __iomem char *ds1511_base;
72static u32 reg_spacing = 1;
73
74static void rtc_write(uint8_t val, uint32_t reg)
75{
76 writeb(val, ds1511_base + (reg * reg_spacing));
77}
78
79static uint8_t rtc_read(uint32_t reg)
80{
81 return readb(ds1511_base + (reg * reg_spacing));
82}
83
84static void rtc_disable_update(void)
85{
86 rtc_write((rtc_read(DS1511_CONTROL_B) & ~DS1511_TE), DS1511_CONTROL_B);
87}
88
89static void rtc_enable_update(void)
90{
91 rtc_write((rtc_read(DS1511_CONTROL_B) | DS1511_TE), DS1511_CONTROL_B);
92}
93
94static int ds1511_rtc_set_time(struct device *dev, struct rtc_time *rtc_tm)
95{
96 u8 mon, day, dow, hrs, min, sec, yrs, cen;
97 unsigned long flags;
98
99 yrs = rtc_tm->tm_year % 100;
100 cen = 19 + rtc_tm->tm_year / 100;
101 mon = rtc_tm->tm_mon + 1; /* tm_mon starts at zero */
102 day = rtc_tm->tm_mday;
103 dow = rtc_tm->tm_wday & 0x7; /* automatic BCD */
104 hrs = rtc_tm->tm_hour;
105 min = rtc_tm->tm_min;
106 sec = rtc_tm->tm_sec;
107
108 /*
109 * each register is a different number of valid bits
110 */
111 sec = bin2bcd(sec) & 0x7f;
112 min = bin2bcd(min) & 0x7f;
113 hrs = bin2bcd(hrs) & 0x3f;
114 day = bin2bcd(day) & 0x3f;
115 mon = bin2bcd(mon) & 0x1f;
116 yrs = bin2bcd(yrs) & 0xff;
117 cen = bin2bcd(cen) & 0xff;
118
119 spin_lock_irqsave(&ds1511_lock, flags);
120 rtc_disable_update();
121 rtc_write(cen, DS1511_CENTURY);
122 rtc_write(yrs, DS1511_YEAR);
123 rtc_write((rtc_read(DS1511_MONTH) & 0xe0) | mon, DS1511_MONTH);
124 rtc_write(day, DS1511_DOM);
125 rtc_write(hrs, DS1511_HOUR);
126 rtc_write(min, DS1511_MIN);
127 rtc_write(sec, DS1511_SEC);
128 rtc_write(dow, DS1511_DOW);
129 rtc_enable_update();
130 spin_unlock_irqrestore(&ds1511_lock, flags);
131
132 return 0;
133}
134
135static int ds1511_rtc_read_time(struct device *dev, struct rtc_time *rtc_tm)
136{
137 unsigned int century;
138 unsigned long flags;
139
140 spin_lock_irqsave(&ds1511_lock, flags);
141 rtc_disable_update();
142
143 rtc_tm->tm_sec = rtc_read(DS1511_SEC) & 0x7f;
144 rtc_tm->tm_min = rtc_read(DS1511_MIN) & 0x7f;
145 rtc_tm->tm_hour = rtc_read(DS1511_HOUR) & 0x3f;
146 rtc_tm->tm_mday = rtc_read(DS1511_DOM) & 0x3f;
147 rtc_tm->tm_wday = rtc_read(DS1511_DOW) & 0x7;
148 rtc_tm->tm_mon = rtc_read(DS1511_MONTH) & 0x1f;
149 rtc_tm->tm_year = rtc_read(DS1511_YEAR) & 0x7f;
150 century = rtc_read(DS1511_CENTURY);
151
152 rtc_enable_update();
153 spin_unlock_irqrestore(&ds1511_lock, flags);
154
155 rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec);
156 rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min);
157 rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour);
158 rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday);
159 rtc_tm->tm_wday = bcd2bin(rtc_tm->tm_wday);
160 rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon);
161 rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year);
162 century = bcd2bin(century) * 100;
163
164 /*
165 * Account for differences between how the RTC uses the values
166 * and how they are defined in a struct rtc_time;
167 */
168 century += rtc_tm->tm_year;
169 rtc_tm->tm_year = century - 1900;
170
171 rtc_tm->tm_mon--;
172
173 return 0;
174}
175
176static void ds1511_rtc_alarm_enable(unsigned int enabled)
177{
178 rtc_write(rtc_read(DS1511_CONTROL_B) | (enabled ? DS1511_TIE : 0), DS1511_CONTROL_B);
179}
180
181static int ds1511_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
182{
183 struct ds1511_data *ds1511 = dev_get_drvdata(dev);
184 unsigned long flags;
185
186 spin_lock_irqsave(&ds1511->lock, flags);
187 rtc_write(bin2bcd(alrm->time.tm_mday) & 0x3f, DS1511_AM4_DATE);
188 rtc_write(bin2bcd(alrm->time.tm_hour) & 0x3f, DS1511_AM3_HOUR);
189 rtc_write(bin2bcd(alrm->time.tm_min) & 0x7f, DS1511_AM2_MIN);
190 rtc_write(bin2bcd(alrm->time.tm_sec) & 0x7f, DS1511_AM1_SEC);
191 ds1511_rtc_alarm_enable(alrm->enabled);
192
193 rtc_read(DS1511_CONTROL_A); /* clear interrupts */
194 spin_unlock_irqrestore(&ds1511->lock, flags);
195
196 return 0;
197}
198
199static int ds1511_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
200{
201 alrm->time.tm_mday = bcd2bin(rtc_read(DS1511_AM4_DATE) & 0x3f);
202 alrm->time.tm_hour = bcd2bin(rtc_read(DS1511_AM3_HOUR) & 0x3f);
203 alrm->time.tm_min = bcd2bin(rtc_read(DS1511_AM2_MIN) & 0x7f);
204 alrm->time.tm_sec = bcd2bin(rtc_read(DS1511_AM1_SEC) & 0x7f);
205 alrm->enabled = !!(rtc_read(DS1511_CONTROL_B) & DS1511_TIE);
206
207 return 0;
208}
209
210static irqreturn_t ds1511_interrupt(int irq, void *dev_id)
211{
212 struct platform_device *pdev = dev_id;
213 struct ds1511_data *ds1511 = platform_get_drvdata(pdev);
214 unsigned long events = 0;
215
216 spin_lock(&ds1511->lock);
217 /*
218 * read and clear interrupt
219 */
220 if (rtc_read(DS1511_CONTROL_A) & DS1511_IRQF) {
221 events = RTC_IRQF | RTC_AF;
222 rtc_update_irq(ds1511->rtc, 1, events);
223 }
224 spin_unlock(&ds1511->lock);
225 return events ? IRQ_HANDLED : IRQ_NONE;
226}
227
228static int ds1511_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
229{
230 struct ds1511_data *ds1511 = dev_get_drvdata(dev);
231 unsigned long flags;
232
233 spin_lock_irqsave(&ds1511->lock, flags);
234 ds1511_rtc_alarm_enable(enabled);
235 spin_unlock_irqrestore(&ds1511->lock, flags);
236
237 return 0;
238}
239
240static const struct rtc_class_ops ds1511_rtc_ops = {
241 .read_time = ds1511_rtc_read_time,
242 .set_time = ds1511_rtc_set_time,
243 .read_alarm = ds1511_rtc_read_alarm,
244 .set_alarm = ds1511_rtc_set_alarm,
245 .alarm_irq_enable = ds1511_rtc_alarm_irq_enable,
246};
247
248static int ds1511_nvram_read(void *priv, unsigned int pos, void *buf,
249 size_t size)
250{
251 int i;
252
253 rtc_write(pos, DS1511_RAMADDR_LSB);
254 for (i = 0; i < size; i++)
255 *(char *)buf++ = rtc_read(DS1511_RAMDATA);
256
257 return 0;
258}
259
260static int ds1511_nvram_write(void *priv, unsigned int pos, void *buf,
261 size_t size)
262{
263 int i;
264
265 rtc_write(pos, DS1511_RAMADDR_LSB);
266 for (i = 0; i < size; i++)
267 rtc_write(*(char *)buf++, DS1511_RAMDATA);
268
269 return 0;
270}
271
272static int ds1511_rtc_probe(struct platform_device *pdev)
273{
274 struct ds1511_data *ds1511;
275 int ret = 0;
276 struct nvmem_config ds1511_nvmem_cfg = {
277 .name = "ds1511_nvram",
278 .word_size = 1,
279 .stride = 1,
280 .size = DS1511_RAM_MAX,
281 .reg_read = ds1511_nvram_read,
282 .reg_write = ds1511_nvram_write,
283 .priv = &pdev->dev,
284 };
285
286 ds1511 = devm_kzalloc(&pdev->dev, sizeof(*ds1511), GFP_KERNEL);
287 if (!ds1511)
288 return -ENOMEM;
289
290 ds1511_base = devm_platform_ioremap_resource(pdev, 0);
291 if (IS_ERR(ds1511_base))
292 return PTR_ERR(ds1511_base);
293 ds1511->ioaddr = ds1511_base;
294 ds1511->irq = platform_get_irq(pdev, 0);
295
296 /*
297 * turn on the clock and the crystal, etc.
298 */
299 rtc_write(DS1511_BME, DS1511_CONTROL_B);
300 rtc_write(0, DS1511_CONTROL_A);
301 /*
302 * clear the wdog counter
303 */
304 rtc_write(0, DS1511_WD_MSEC);
305 rtc_write(0, DS1511_WD_SEC);
306 /*
307 * start the clock
308 */
309 rtc_enable_update();
310
311 /*
312 * check for a dying bat-tree
313 */
314 if (rtc_read(DS1511_CONTROL_A) & DS1511_BLF1)
315 dev_warn(&pdev->dev, "voltage-low detected.\n");
316
317 spin_lock_init(&ds1511->lock);
318 platform_set_drvdata(pdev, ds1511);
319
320 ds1511->rtc = devm_rtc_allocate_device(&pdev->dev);
321 if (IS_ERR(ds1511->rtc))
322 return PTR_ERR(ds1511->rtc);
323
324 ds1511->rtc->ops = &ds1511_rtc_ops;
325 ds1511->rtc->range_max = RTC_TIMESTAMP_END_2099;
326 ds1511->rtc->alarm_offset_max = 28 * 24 * 60 * 60 - 1;
327
328 /*
329 * if the platform has an interrupt in mind for this device,
330 * then by all means, set it
331 */
332 if (ds1511->irq > 0) {
333 rtc_read(DS1511_CONTROL_A);
334 if (devm_request_irq(&pdev->dev, ds1511->irq, ds1511_interrupt,
335 IRQF_SHARED, pdev->name, pdev) < 0) {
336
337 dev_warn(&pdev->dev, "interrupt not available.\n");
338 ds1511->irq = 0;
339 }
340 }
341
342 if (ds1511->irq == 0)
343 clear_bit(RTC_FEATURE_ALARM, ds1511->rtc->features);
344
345 ret = devm_rtc_register_device(ds1511->rtc);
346 if (ret)
347 return ret;
348
349 devm_rtc_nvmem_register(ds1511->rtc, &ds1511_nvmem_cfg);
350
351 return 0;
352}
353
354/* work with hotplug and coldplug */
355MODULE_ALIAS("platform:ds1511");
356
357static struct platform_driver ds1511_rtc_driver = {
358 .probe = ds1511_rtc_probe,
359 .driver = {
360 .name = "ds1511",
361 },
362};
363
364module_platform_driver(ds1511_rtc_driver);
365
366MODULE_AUTHOR("Andrew Sharp <andy.sharp@lsi.com>");
367MODULE_DESCRIPTION("Dallas DS1511 RTC driver");
368MODULE_LICENSE("GPL");