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1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5#include <linux/bcd.h>
6
7#include "main.h"
8#include "reg.h"
9#include "fw.h"
10#include "phy.h"
11#include "debug.h"
12#include "regd.h"
13#include "sar.h"
14
15struct phy_cfg_pair {
16 u32 addr;
17 u32 data;
18};
19
20union phy_table_tile {
21 struct {
22 struct rtw_phy_cond cond;
23 struct rtw_phy_cond2 cond2;
24 } __packed;
25 struct phy_cfg_pair cfg;
26};
27
28static const u32 db_invert_table[12][8] = {
29 {10, 13, 16, 20,
30 25, 32, 40, 50},
31 {64, 80, 101, 128,
32 160, 201, 256, 318},
33 {401, 505, 635, 800,
34 1007, 1268, 1596, 2010},
35 {316, 398, 501, 631,
36 794, 1000, 1259, 1585},
37 {1995, 2512, 3162, 3981,
38 5012, 6310, 7943, 10000},
39 {12589, 15849, 19953, 25119,
40 31623, 39811, 50119, 63098},
41 {79433, 100000, 125893, 158489,
42 199526, 251189, 316228, 398107},
43 {501187, 630957, 794328, 1000000,
44 1258925, 1584893, 1995262, 2511886},
45 {3162278, 3981072, 5011872, 6309573,
46 7943282, 1000000, 12589254, 15848932},
47 {19952623, 25118864, 31622777, 39810717,
48 50118723, 63095734, 79432823, 100000000},
49 {125892541, 158489319, 199526232, 251188643,
50 316227766, 398107171, 501187234, 630957345},
51 {794328235, 1000000000, 1258925412, 1584893192,
52 1995262315, 2511886432U, 3162277660U, 3981071706U}
53};
54
55u8 rtw_cck_rates[] = { DESC_RATE1M, DESC_RATE2M, DESC_RATE5_5M, DESC_RATE11M };
56u8 rtw_ofdm_rates[] = {
57 DESC_RATE6M, DESC_RATE9M, DESC_RATE12M,
58 DESC_RATE18M, DESC_RATE24M, DESC_RATE36M,
59 DESC_RATE48M, DESC_RATE54M
60};
61u8 rtw_ht_1s_rates[] = {
62 DESC_RATEMCS0, DESC_RATEMCS1, DESC_RATEMCS2,
63 DESC_RATEMCS3, DESC_RATEMCS4, DESC_RATEMCS5,
64 DESC_RATEMCS6, DESC_RATEMCS7
65};
66u8 rtw_ht_2s_rates[] = {
67 DESC_RATEMCS8, DESC_RATEMCS9, DESC_RATEMCS10,
68 DESC_RATEMCS11, DESC_RATEMCS12, DESC_RATEMCS13,
69 DESC_RATEMCS14, DESC_RATEMCS15
70};
71u8 rtw_vht_1s_rates[] = {
72 DESC_RATEVHT1SS_MCS0, DESC_RATEVHT1SS_MCS1,
73 DESC_RATEVHT1SS_MCS2, DESC_RATEVHT1SS_MCS3,
74 DESC_RATEVHT1SS_MCS4, DESC_RATEVHT1SS_MCS5,
75 DESC_RATEVHT1SS_MCS6, DESC_RATEVHT1SS_MCS7,
76 DESC_RATEVHT1SS_MCS8, DESC_RATEVHT1SS_MCS9
77};
78u8 rtw_vht_2s_rates[] = {
79 DESC_RATEVHT2SS_MCS0, DESC_RATEVHT2SS_MCS1,
80 DESC_RATEVHT2SS_MCS2, DESC_RATEVHT2SS_MCS3,
81 DESC_RATEVHT2SS_MCS4, DESC_RATEVHT2SS_MCS5,
82 DESC_RATEVHT2SS_MCS6, DESC_RATEVHT2SS_MCS7,
83 DESC_RATEVHT2SS_MCS8, DESC_RATEVHT2SS_MCS9
84};
85u8 *rtw_rate_section[RTW_RATE_SECTION_MAX] = {
86 rtw_cck_rates, rtw_ofdm_rates,
87 rtw_ht_1s_rates, rtw_ht_2s_rates,
88 rtw_vht_1s_rates, rtw_vht_2s_rates
89};
90EXPORT_SYMBOL(rtw_rate_section);
91
92u8 rtw_rate_size[RTW_RATE_SECTION_MAX] = {
93 ARRAY_SIZE(rtw_cck_rates),
94 ARRAY_SIZE(rtw_ofdm_rates),
95 ARRAY_SIZE(rtw_ht_1s_rates),
96 ARRAY_SIZE(rtw_ht_2s_rates),
97 ARRAY_SIZE(rtw_vht_1s_rates),
98 ARRAY_SIZE(rtw_vht_2s_rates)
99};
100EXPORT_SYMBOL(rtw_rate_size);
101
102static const u8 rtw_cck_size = ARRAY_SIZE(rtw_cck_rates);
103static const u8 rtw_ofdm_size = ARRAY_SIZE(rtw_ofdm_rates);
104static const u8 rtw_ht_1s_size = ARRAY_SIZE(rtw_ht_1s_rates);
105static const u8 rtw_ht_2s_size = ARRAY_SIZE(rtw_ht_2s_rates);
106static const u8 rtw_vht_1s_size = ARRAY_SIZE(rtw_vht_1s_rates);
107static const u8 rtw_vht_2s_size = ARRAY_SIZE(rtw_vht_2s_rates);
108
109enum rtw_phy_band_type {
110 PHY_BAND_2G = 0,
111 PHY_BAND_5G = 1,
112};
113
114static void rtw_phy_cck_pd_init(struct rtw_dev *rtwdev)
115{
116 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
117 u8 i, j;
118
119 for (i = 0; i <= RTW_CHANNEL_WIDTH_40; i++) {
120 for (j = 0; j < RTW_RF_PATH_MAX; j++)
121 dm_info->cck_pd_lv[i][j] = CCK_PD_LV0;
122 }
123
124 dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
125}
126
127void rtw_phy_set_edcca_th(struct rtw_dev *rtwdev, u8 l2h, u8 h2l)
128{
129 const struct rtw_hw_reg_offset *edcca_th = rtwdev->chip->edcca_th;
130
131 rtw_write32_mask(rtwdev,
132 edcca_th[EDCCA_TH_L2H_IDX].hw_reg.addr,
133 edcca_th[EDCCA_TH_L2H_IDX].hw_reg.mask,
134 l2h + edcca_th[EDCCA_TH_L2H_IDX].offset);
135 rtw_write32_mask(rtwdev,
136 edcca_th[EDCCA_TH_H2L_IDX].hw_reg.addr,
137 edcca_th[EDCCA_TH_H2L_IDX].hw_reg.mask,
138 h2l + edcca_th[EDCCA_TH_H2L_IDX].offset);
139}
140EXPORT_SYMBOL(rtw_phy_set_edcca_th);
141
142void rtw_phy_adaptivity_set_mode(struct rtw_dev *rtwdev)
143{
144 const struct rtw_chip_info *chip = rtwdev->chip;
145 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
146
147 /* turn off in debugfs for debug usage */
148 if (!rtw_edcca_enabled) {
149 dm_info->edcca_mode = RTW_EDCCA_NORMAL;
150 rtw_dbg(rtwdev, RTW_DBG_PHY, "EDCCA disabled, cannot be set\n");
151 return;
152 }
153
154 switch (rtwdev->regd.dfs_region) {
155 case NL80211_DFS_ETSI:
156 dm_info->edcca_mode = RTW_EDCCA_ADAPTIVITY;
157 dm_info->l2h_th_ini = chip->l2h_th_ini_ad;
158 break;
159 case NL80211_DFS_JP:
160 dm_info->edcca_mode = RTW_EDCCA_ADAPTIVITY;
161 dm_info->l2h_th_ini = chip->l2h_th_ini_cs;
162 break;
163 default:
164 dm_info->edcca_mode = RTW_EDCCA_NORMAL;
165 break;
166 }
167}
168
169static void rtw_phy_adaptivity_init(struct rtw_dev *rtwdev)
170{
171 const struct rtw_chip_info *chip = rtwdev->chip;
172
173 rtw_phy_adaptivity_set_mode(rtwdev);
174 if (chip->ops->adaptivity_init)
175 chip->ops->adaptivity_init(rtwdev);
176}
177
178static void rtw_phy_adaptivity(struct rtw_dev *rtwdev)
179{
180 if (rtwdev->chip->ops->adaptivity)
181 rtwdev->chip->ops->adaptivity(rtwdev);
182}
183
184static void rtw_phy_cfo_init(struct rtw_dev *rtwdev)
185{
186 const struct rtw_chip_info *chip = rtwdev->chip;
187
188 if (chip->ops->cfo_init)
189 chip->ops->cfo_init(rtwdev);
190}
191
192static void rtw_phy_tx_path_div_init(struct rtw_dev *rtwdev)
193{
194 struct rtw_path_div *path_div = &rtwdev->dm_path_div;
195
196 path_div->current_tx_path = rtwdev->chip->default_1ss_tx_path;
197 path_div->path_a_cnt = 0;
198 path_div->path_a_sum = 0;
199 path_div->path_b_cnt = 0;
200 path_div->path_b_sum = 0;
201}
202
203void rtw_phy_init(struct rtw_dev *rtwdev)
204{
205 const struct rtw_chip_info *chip = rtwdev->chip;
206 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
207 u32 addr, mask;
208
209 dm_info->fa_history[3] = 0;
210 dm_info->fa_history[2] = 0;
211 dm_info->fa_history[1] = 0;
212 dm_info->fa_history[0] = 0;
213 dm_info->igi_bitmap = 0;
214 dm_info->igi_history[3] = 0;
215 dm_info->igi_history[2] = 0;
216 dm_info->igi_history[1] = 0;
217
218 addr = chip->dig[0].addr;
219 mask = chip->dig[0].mask;
220 dm_info->igi_history[0] = rtw_read32_mask(rtwdev, addr, mask);
221 rtw_phy_cck_pd_init(rtwdev);
222
223 dm_info->iqk.done = false;
224 rtw_phy_adaptivity_init(rtwdev);
225 rtw_phy_cfo_init(rtwdev);
226 rtw_phy_tx_path_div_init(rtwdev);
227}
228EXPORT_SYMBOL(rtw_phy_init);
229
230void rtw_phy_dig_write(struct rtw_dev *rtwdev, u8 igi)
231{
232 const struct rtw_chip_info *chip = rtwdev->chip;
233 struct rtw_hal *hal = &rtwdev->hal;
234 u32 addr, mask;
235 u8 path;
236
237 if (chip->dig_cck) {
238 const struct rtw_hw_reg *dig_cck = &chip->dig_cck[0];
239 rtw_write32_mask(rtwdev, dig_cck->addr, dig_cck->mask, igi >> 1);
240 }
241
242 for (path = 0; path < hal->rf_path_num; path++) {
243 addr = chip->dig[path].addr;
244 mask = chip->dig[path].mask;
245 rtw_write32_mask(rtwdev, addr, mask, igi);
246 }
247}
248
249static void rtw_phy_stat_false_alarm(struct rtw_dev *rtwdev)
250{
251 const struct rtw_chip_info *chip = rtwdev->chip;
252
253 chip->ops->false_alarm_statistics(rtwdev);
254}
255
256#define RA_FLOOR_TABLE_SIZE 7
257#define RA_FLOOR_UP_GAP 3
258
259static u8 rtw_phy_get_rssi_level(u8 old_level, u8 rssi)
260{
261 u8 table[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100};
262 u8 new_level = 0;
263 int i;
264
265 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++)
266 if (i >= old_level)
267 table[i] += RA_FLOOR_UP_GAP;
268
269 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
270 if (rssi < table[i]) {
271 new_level = i;
272 break;
273 }
274 }
275
276 return new_level;
277}
278
279struct rtw_phy_stat_iter_data {
280 struct rtw_dev *rtwdev;
281 u8 min_rssi;
282};
283
284static void rtw_phy_stat_rssi_iter(void *data, struct ieee80211_sta *sta)
285{
286 struct rtw_phy_stat_iter_data *iter_data = data;
287 struct rtw_dev *rtwdev = iter_data->rtwdev;
288 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
289 u8 rssi;
290
291 rssi = ewma_rssi_read(&si->avg_rssi);
292 si->rssi_level = rtw_phy_get_rssi_level(si->rssi_level, rssi);
293
294 rtw_fw_send_rssi_info(rtwdev, si);
295
296 iter_data->min_rssi = min_t(u8, rssi, iter_data->min_rssi);
297}
298
299static void rtw_phy_stat_rssi(struct rtw_dev *rtwdev)
300{
301 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
302 struct rtw_phy_stat_iter_data data = {};
303
304 data.rtwdev = rtwdev;
305 data.min_rssi = U8_MAX;
306 rtw_iterate_stas(rtwdev, rtw_phy_stat_rssi_iter, &data);
307
308 dm_info->pre_min_rssi = dm_info->min_rssi;
309 dm_info->min_rssi = data.min_rssi;
310}
311
312static void rtw_phy_stat_rate_cnt(struct rtw_dev *rtwdev)
313{
314 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
315
316 dm_info->last_pkt_count = dm_info->cur_pkt_count;
317 memset(&dm_info->cur_pkt_count, 0, sizeof(dm_info->cur_pkt_count));
318}
319
320static void rtw_phy_statistics(struct rtw_dev *rtwdev)
321{
322 rtw_phy_stat_rssi(rtwdev);
323 rtw_phy_stat_false_alarm(rtwdev);
324 rtw_phy_stat_rate_cnt(rtwdev);
325}
326
327#define DIG_PERF_FA_TH_LOW 250
328#define DIG_PERF_FA_TH_HIGH 500
329#define DIG_PERF_FA_TH_EXTRA_HIGH 750
330#define DIG_PERF_MAX 0x5a
331#define DIG_PERF_MID 0x40
332#define DIG_CVRG_FA_TH_LOW 2000
333#define DIG_CVRG_FA_TH_HIGH 4000
334#define DIG_CVRG_FA_TH_EXTRA_HIGH 5000
335#define DIG_CVRG_MAX 0x2a
336#define DIG_CVRG_MID 0x26
337#define DIG_CVRG_MIN 0x1c
338#define DIG_RSSI_GAIN_OFFSET 15
339
340static bool
341rtw_phy_dig_check_damping(struct rtw_dm_info *dm_info)
342{
343 u16 fa_lo = DIG_PERF_FA_TH_LOW;
344 u16 fa_hi = DIG_PERF_FA_TH_HIGH;
345 u16 *fa_history;
346 u8 *igi_history;
347 u8 damping_rssi;
348 u8 min_rssi;
349 u8 diff;
350 u8 igi_bitmap;
351 bool damping = false;
352
353 min_rssi = dm_info->min_rssi;
354 if (dm_info->damping) {
355 damping_rssi = dm_info->damping_rssi;
356 diff = min_rssi > damping_rssi ? min_rssi - damping_rssi :
357 damping_rssi - min_rssi;
358 if (diff > 3 || dm_info->damping_cnt++ > 20) {
359 dm_info->damping = false;
360 return false;
361 }
362
363 return true;
364 }
365
366 igi_history = dm_info->igi_history;
367 fa_history = dm_info->fa_history;
368 igi_bitmap = dm_info->igi_bitmap & 0xf;
369 switch (igi_bitmap) {
370 case 5:
371 /* down -> up -> down -> up */
372 if (igi_history[0] > igi_history[1] &&
373 igi_history[2] > igi_history[3] &&
374 igi_history[0] - igi_history[1] >= 2 &&
375 igi_history[2] - igi_history[3] >= 2 &&
376 fa_history[0] > fa_hi && fa_history[1] < fa_lo &&
377 fa_history[2] > fa_hi && fa_history[3] < fa_lo)
378 damping = true;
379 break;
380 case 9:
381 /* up -> down -> down -> up */
382 if (igi_history[0] > igi_history[1] &&
383 igi_history[3] > igi_history[2] &&
384 igi_history[0] - igi_history[1] >= 4 &&
385 igi_history[3] - igi_history[2] >= 2 &&
386 fa_history[0] > fa_hi && fa_history[1] < fa_lo &&
387 fa_history[2] < fa_lo && fa_history[3] > fa_hi)
388 damping = true;
389 break;
390 default:
391 return false;
392 }
393
394 if (damping) {
395 dm_info->damping = true;
396 dm_info->damping_cnt = 0;
397 dm_info->damping_rssi = min_rssi;
398 }
399
400 return damping;
401}
402
403static void rtw_phy_dig_get_boundary(struct rtw_dev *rtwdev,
404 struct rtw_dm_info *dm_info,
405 u8 *upper, u8 *lower, bool linked)
406{
407 u8 dig_max, dig_min, dig_mid;
408 u8 min_rssi;
409
410 if (linked) {
411 dig_max = DIG_PERF_MAX;
412 dig_mid = DIG_PERF_MID;
413 dig_min = rtwdev->chip->dig_min;
414 min_rssi = max_t(u8, dm_info->min_rssi, dig_min);
415 } else {
416 dig_max = DIG_CVRG_MAX;
417 dig_mid = DIG_CVRG_MID;
418 dig_min = DIG_CVRG_MIN;
419 min_rssi = dig_min;
420 }
421
422 /* DIG MAX should be bounded by minimum RSSI with offset +15 */
423 dig_max = min_t(u8, dig_max, min_rssi + DIG_RSSI_GAIN_OFFSET);
424
425 *lower = clamp_t(u8, min_rssi, dig_min, dig_mid);
426 *upper = clamp_t(u8, *lower + DIG_RSSI_GAIN_OFFSET, dig_min, dig_max);
427}
428
429static void rtw_phy_dig_get_threshold(struct rtw_dm_info *dm_info,
430 u16 *fa_th, u8 *step, bool linked)
431{
432 u8 min_rssi, pre_min_rssi;
433
434 min_rssi = dm_info->min_rssi;
435 pre_min_rssi = dm_info->pre_min_rssi;
436 step[0] = 4;
437 step[1] = 3;
438 step[2] = 2;
439
440 if (linked) {
441 fa_th[0] = DIG_PERF_FA_TH_EXTRA_HIGH;
442 fa_th[1] = DIG_PERF_FA_TH_HIGH;
443 fa_th[2] = DIG_PERF_FA_TH_LOW;
444 if (pre_min_rssi > min_rssi) {
445 step[0] = 6;
446 step[1] = 4;
447 step[2] = 2;
448 }
449 } else {
450 fa_th[0] = DIG_CVRG_FA_TH_EXTRA_HIGH;
451 fa_th[1] = DIG_CVRG_FA_TH_HIGH;
452 fa_th[2] = DIG_CVRG_FA_TH_LOW;
453 }
454}
455
456static void rtw_phy_dig_recorder(struct rtw_dm_info *dm_info, u8 igi, u16 fa)
457{
458 u8 *igi_history;
459 u16 *fa_history;
460 u8 igi_bitmap;
461 bool up;
462
463 igi_bitmap = dm_info->igi_bitmap << 1 & 0xfe;
464 igi_history = dm_info->igi_history;
465 fa_history = dm_info->fa_history;
466
467 up = igi > igi_history[0];
468 igi_bitmap |= up;
469
470 igi_history[3] = igi_history[2];
471 igi_history[2] = igi_history[1];
472 igi_history[1] = igi_history[0];
473 igi_history[0] = igi;
474
475 fa_history[3] = fa_history[2];
476 fa_history[2] = fa_history[1];
477 fa_history[1] = fa_history[0];
478 fa_history[0] = fa;
479
480 dm_info->igi_bitmap = igi_bitmap;
481}
482
483static void rtw_phy_dig(struct rtw_dev *rtwdev)
484{
485 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
486 u8 upper_bound, lower_bound;
487 u8 pre_igi, cur_igi;
488 u16 fa_th[3], fa_cnt;
489 u8 level;
490 u8 step[3];
491 bool linked;
492
493 if (test_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags))
494 return;
495
496 if (rtw_phy_dig_check_damping(dm_info))
497 return;
498
499 linked = !!rtwdev->sta_cnt;
500
501 fa_cnt = dm_info->total_fa_cnt;
502 pre_igi = dm_info->igi_history[0];
503
504 rtw_phy_dig_get_threshold(dm_info, fa_th, step, linked);
505
506 /* test the false alarm count from the highest threshold level first,
507 * and increase it by corresponding step size
508 *
509 * note that the step size is offset by -2, compensate it afterall
510 */
511 cur_igi = pre_igi;
512 for (level = 0; level < 3; level++) {
513 if (fa_cnt > fa_th[level]) {
514 cur_igi += step[level];
515 break;
516 }
517 }
518 cur_igi -= 2;
519
520 /* calculate the upper/lower bound by the minimum rssi we have among
521 * the peers connected with us, meanwhile make sure the igi value does
522 * not beyond the hardware limitation
523 */
524 rtw_phy_dig_get_boundary(rtwdev, dm_info, &upper_bound, &lower_bound,
525 linked);
526 cur_igi = clamp_t(u8, cur_igi, lower_bound, upper_bound);
527
528 /* record current igi value and false alarm statistics for further
529 * damping checks, and record the trend of igi values
530 */
531 rtw_phy_dig_recorder(dm_info, cur_igi, fa_cnt);
532
533 /* Mitigate beacon loss and connectivity issues, mainly (only?)
534 * in the 5 GHz band
535 */
536 if (rtwdev->chip->id == RTW_CHIP_TYPE_8812A && rtwdev->beacon_loss &&
537 linked && dm_info->total_fa_cnt < DIG_PERF_FA_TH_EXTRA_HIGH)
538 cur_igi = DIG_CVRG_MIN;
539
540 if (cur_igi != pre_igi)
541 rtw_phy_dig_write(rtwdev, cur_igi);
542}
543
544static void rtw_phy_ra_info_update_iter(void *data, struct ieee80211_sta *sta)
545{
546 struct rtw_dev *rtwdev = data;
547 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
548
549 rtw_update_sta_info(rtwdev, si, false);
550}
551
552static void rtw_phy_ra_info_update(struct rtw_dev *rtwdev)
553{
554 if (rtwdev->watch_dog_cnt & 0x3)
555 return;
556
557 rtw_iterate_stas(rtwdev, rtw_phy_ra_info_update_iter, rtwdev);
558}
559
560static u32 rtw_phy_get_rrsr_mask(struct rtw_dev *rtwdev, u8 rate_idx)
561{
562 u8 rate_order;
563
564 rate_order = rate_idx;
565
566 if (rate_idx >= DESC_RATEVHT4SS_MCS0)
567 rate_order -= DESC_RATEVHT4SS_MCS0;
568 else if (rate_idx >= DESC_RATEVHT3SS_MCS0)
569 rate_order -= DESC_RATEVHT3SS_MCS0;
570 else if (rate_idx >= DESC_RATEVHT2SS_MCS0)
571 rate_order -= DESC_RATEVHT2SS_MCS0;
572 else if (rate_idx >= DESC_RATEVHT1SS_MCS0)
573 rate_order -= DESC_RATEVHT1SS_MCS0;
574 else if (rate_idx >= DESC_RATEMCS24)
575 rate_order -= DESC_RATEMCS24;
576 else if (rate_idx >= DESC_RATEMCS16)
577 rate_order -= DESC_RATEMCS16;
578 else if (rate_idx >= DESC_RATEMCS8)
579 rate_order -= DESC_RATEMCS8;
580 else if (rate_idx >= DESC_RATEMCS0)
581 rate_order -= DESC_RATEMCS0;
582 else if (rate_idx >= DESC_RATE6M)
583 rate_order -= DESC_RATE6M;
584 else
585 rate_order -= DESC_RATE1M;
586
587 if (rate_idx >= DESC_RATEMCS0 || rate_order == 0)
588 rate_order++;
589
590 return GENMASK(rate_order + RRSR_RATE_ORDER_CCK_LEN - 1, 0);
591}
592
593static void rtw_phy_rrsr_mask_min_iter(void *data, struct ieee80211_sta *sta)
594{
595 struct rtw_dev *rtwdev = (struct rtw_dev *)data;
596 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
597 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
598 u32 mask = 0;
599
600 mask = rtw_phy_get_rrsr_mask(rtwdev, si->ra_report.desc_rate);
601 if (mask < dm_info->rrsr_mask_min)
602 dm_info->rrsr_mask_min = mask;
603}
604
605static void rtw_phy_rrsr_update(struct rtw_dev *rtwdev)
606{
607 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
608
609 dm_info->rrsr_mask_min = RRSR_RATE_ORDER_MAX;
610 rtw_iterate_stas(rtwdev, rtw_phy_rrsr_mask_min_iter, rtwdev);
611 rtw_write32(rtwdev, REG_RRSR, dm_info->rrsr_val_init & dm_info->rrsr_mask_min);
612}
613
614static void rtw_phy_dpk_track(struct rtw_dev *rtwdev)
615{
616 const struct rtw_chip_info *chip = rtwdev->chip;
617
618 if (chip->ops->dpk_track)
619 chip->ops->dpk_track(rtwdev);
620}
621
622struct rtw_rx_addr_match_data {
623 struct rtw_dev *rtwdev;
624 struct ieee80211_hdr *hdr;
625 struct rtw_rx_pkt_stat *pkt_stat;
626 u8 *bssid;
627};
628
629static void rtw_phy_parsing_cfo_iter(void *data, u8 *mac,
630 struct ieee80211_vif *vif)
631{
632 struct rtw_rx_addr_match_data *iter_data = data;
633 struct rtw_dev *rtwdev = iter_data->rtwdev;
634 struct rtw_rx_pkt_stat *pkt_stat = iter_data->pkt_stat;
635 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
636 struct rtw_cfo_track *cfo = &dm_info->cfo_track;
637 u8 *bssid = iter_data->bssid;
638 u8 i;
639
640 if (!ether_addr_equal(vif->bss_conf.bssid, bssid))
641 return;
642
643 for (i = 0; i < rtwdev->hal.rf_path_num; i++) {
644 cfo->cfo_tail[i] += pkt_stat->cfo_tail[i];
645 cfo->cfo_cnt[i]++;
646 }
647
648 cfo->packet_count++;
649}
650
651void rtw_phy_parsing_cfo(struct rtw_dev *rtwdev,
652 struct rtw_rx_pkt_stat *pkt_stat)
653{
654 struct ieee80211_hdr *hdr = pkt_stat->hdr;
655 struct rtw_rx_addr_match_data data = {};
656
657 if (pkt_stat->crc_err || pkt_stat->icv_err || !pkt_stat->phy_status ||
658 ieee80211_is_ctl(hdr->frame_control))
659 return;
660
661 data.rtwdev = rtwdev;
662 data.hdr = hdr;
663 data.pkt_stat = pkt_stat;
664 data.bssid = get_hdr_bssid(hdr);
665
666 rtw_iterate_vifs_atomic(rtwdev, rtw_phy_parsing_cfo_iter, &data);
667}
668EXPORT_SYMBOL(rtw_phy_parsing_cfo);
669
670static void rtw_phy_cfo_track(struct rtw_dev *rtwdev)
671{
672 const struct rtw_chip_info *chip = rtwdev->chip;
673
674 if (chip->ops->cfo_track)
675 chip->ops->cfo_track(rtwdev);
676}
677
678#define CCK_PD_FA_LV1_MIN 1000
679#define CCK_PD_FA_LV0_MAX 500
680
681static u8 rtw_phy_cck_pd_lv_unlink(struct rtw_dev *rtwdev)
682{
683 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
684 u32 cck_fa_avg = dm_info->cck_fa_avg;
685
686 if (cck_fa_avg > CCK_PD_FA_LV1_MIN)
687 return CCK_PD_LV1;
688
689 if (cck_fa_avg < CCK_PD_FA_LV0_MAX)
690 return CCK_PD_LV0;
691
692 return CCK_PD_LV_MAX;
693}
694
695#define CCK_PD_IGI_LV4_VAL 0x38
696#define CCK_PD_IGI_LV3_VAL 0x2a
697#define CCK_PD_IGI_LV2_VAL 0x24
698#define CCK_PD_RSSI_LV4_VAL 32
699#define CCK_PD_RSSI_LV3_VAL 32
700#define CCK_PD_RSSI_LV2_VAL 24
701
702static u8 rtw_phy_cck_pd_lv_link(struct rtw_dev *rtwdev)
703{
704 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
705 u8 igi = dm_info->igi_history[0];
706 u8 rssi = dm_info->min_rssi;
707 u32 cck_fa_avg = dm_info->cck_fa_avg;
708
709 if (igi > CCK_PD_IGI_LV4_VAL && rssi > CCK_PD_RSSI_LV4_VAL)
710 return CCK_PD_LV4;
711 if (igi > CCK_PD_IGI_LV3_VAL && rssi > CCK_PD_RSSI_LV3_VAL)
712 return CCK_PD_LV3;
713 if (igi > CCK_PD_IGI_LV2_VAL || rssi > CCK_PD_RSSI_LV2_VAL)
714 return CCK_PD_LV2;
715 if (cck_fa_avg > CCK_PD_FA_LV1_MIN)
716 return CCK_PD_LV1;
717 if (cck_fa_avg < CCK_PD_FA_LV0_MAX)
718 return CCK_PD_LV0;
719
720 return CCK_PD_LV_MAX;
721}
722
723static u8 rtw_phy_cck_pd_lv(struct rtw_dev *rtwdev)
724{
725 if (!rtw_is_assoc(rtwdev))
726 return rtw_phy_cck_pd_lv_unlink(rtwdev);
727 else
728 return rtw_phy_cck_pd_lv_link(rtwdev);
729}
730
731static void rtw_phy_cck_pd(struct rtw_dev *rtwdev)
732{
733 const struct rtw_chip_info *chip = rtwdev->chip;
734 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
735 u32 cck_fa = dm_info->cck_fa_cnt;
736 u8 level;
737
738 if (rtwdev->hal.current_band_type != RTW_BAND_2G)
739 return;
740
741 if (dm_info->cck_fa_avg == CCK_FA_AVG_RESET)
742 dm_info->cck_fa_avg = cck_fa;
743 else
744 dm_info->cck_fa_avg = (dm_info->cck_fa_avg * 3 + cck_fa) >> 2;
745
746 rtw_dbg(rtwdev, RTW_DBG_PHY, "IGI=0x%x, rssi_min=%d, cck_fa=%d\n",
747 dm_info->igi_history[0], dm_info->min_rssi,
748 dm_info->fa_history[0]);
749 rtw_dbg(rtwdev, RTW_DBG_PHY, "cck_fa_avg=%d, cck_pd_default=%d\n",
750 dm_info->cck_fa_avg, dm_info->cck_pd_default);
751
752 level = rtw_phy_cck_pd_lv(rtwdev);
753
754 if (level >= CCK_PD_LV_MAX)
755 return;
756
757 if (chip->ops->cck_pd_set)
758 chip->ops->cck_pd_set(rtwdev, level);
759}
760
761static void rtw_phy_pwr_track(struct rtw_dev *rtwdev)
762{
763 rtwdev->chip->ops->pwr_track(rtwdev);
764}
765
766static void rtw_phy_ra_track(struct rtw_dev *rtwdev)
767{
768 rtw_fw_update_wl_phy_info(rtwdev);
769 rtw_phy_ra_info_update(rtwdev);
770 rtw_phy_rrsr_update(rtwdev);
771}
772
773void rtw_phy_dynamic_mechanism(struct rtw_dev *rtwdev)
774{
775 /* for further calculation */
776 rtw_phy_statistics(rtwdev);
777 rtw_phy_dig(rtwdev);
778 rtw_phy_cck_pd(rtwdev);
779 rtw_phy_ra_track(rtwdev);
780 rtw_phy_tx_path_diversity(rtwdev);
781 rtw_phy_cfo_track(rtwdev);
782 rtw_phy_dpk_track(rtwdev);
783 rtw_phy_pwr_track(rtwdev);
784
785 if (rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_ADAPTIVITY))
786 rtw_fw_adaptivity(rtwdev);
787 else
788 rtw_phy_adaptivity(rtwdev);
789}
790
791#define FRAC_BITS 3
792
793static u8 rtw_phy_power_2_db(s8 power)
794{
795 if (power <= -100 || power >= 20)
796 return 0;
797 else if (power >= 0)
798 return 100;
799 else
800 return 100 + power;
801}
802
803static u64 rtw_phy_db_2_linear(u8 power_db)
804{
805 u8 i, j;
806 u64 linear;
807
808 if (power_db > 96)
809 power_db = 96;
810 else if (power_db < 1)
811 return 1;
812
813 /* 1dB ~ 96dB */
814 i = (power_db - 1) >> 3;
815 j = (power_db - 1) - (i << 3);
816
817 linear = db_invert_table[i][j];
818 linear = i > 2 ? linear << FRAC_BITS : linear;
819
820 return linear;
821}
822
823static u8 rtw_phy_linear_2_db(u64 linear)
824{
825 u8 i;
826 u8 j;
827 u32 dB;
828
829 for (i = 0; i < 12; i++) {
830 for (j = 0; j < 8; j++) {
831 if (i <= 2 && (linear << FRAC_BITS) <= db_invert_table[i][j])
832 goto cnt;
833 else if (i > 2 && linear <= db_invert_table[i][j])
834 goto cnt;
835 }
836 }
837
838 return 96; /* maximum 96 dB */
839
840cnt:
841 if (j == 0 && i == 0)
842 goto end;
843
844 if (j == 0) {
845 if (i != 3) {
846 if (db_invert_table[i][0] - linear >
847 linear - db_invert_table[i - 1][7]) {
848 i = i - 1;
849 j = 7;
850 }
851 } else {
852 if (db_invert_table[3][0] - linear >
853 linear - db_invert_table[2][7]) {
854 i = 2;
855 j = 7;
856 }
857 }
858 } else {
859 if (db_invert_table[i][j] - linear >
860 linear - db_invert_table[i][j - 1]) {
861 j = j - 1;
862 }
863 }
864end:
865 dB = (i << 3) + j + 1;
866
867 return dB;
868}
869
870u8 rtw_phy_rf_power_2_rssi(s8 *rf_power, u8 path_num)
871{
872 s8 power;
873 u8 power_db;
874 u64 linear;
875 u64 sum = 0;
876 u8 path;
877
878 for (path = 0; path < path_num; path++) {
879 power = rf_power[path];
880 power_db = rtw_phy_power_2_db(power);
881 linear = rtw_phy_db_2_linear(power_db);
882 sum += linear;
883 }
884
885 sum = (sum + (1 << (FRAC_BITS - 1))) >> FRAC_BITS;
886 switch (path_num) {
887 case 2:
888 sum >>= 1;
889 break;
890 case 3:
891 sum = ((sum) + ((sum) << 1) + ((sum) << 3)) >> 5;
892 break;
893 case 4:
894 sum >>= 2;
895 break;
896 default:
897 break;
898 }
899
900 return rtw_phy_linear_2_db(sum);
901}
902EXPORT_SYMBOL(rtw_phy_rf_power_2_rssi);
903
904u32 rtw_phy_read_rf(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
905 u32 addr, u32 mask)
906{
907 struct rtw_hal *hal = &rtwdev->hal;
908 const struct rtw_chip_info *chip = rtwdev->chip;
909 const u32 *base_addr = chip->rf_base_addr;
910 u32 val, direct_addr;
911
912 if (rf_path >= hal->rf_phy_num) {
913 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
914 return INV_RF_DATA;
915 }
916
917 addr &= 0xff;
918 direct_addr = base_addr[rf_path] + (addr << 2);
919 mask &= RFREG_MASK;
920
921 val = rtw_read32_mask(rtwdev, direct_addr, mask);
922
923 return val;
924}
925EXPORT_SYMBOL(rtw_phy_read_rf);
926
927u32 rtw_phy_read_rf_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
928 u32 addr, u32 mask)
929{
930 struct rtw_hal *hal = &rtwdev->hal;
931 const struct rtw_chip_info *chip = rtwdev->chip;
932 const struct rtw_rf_sipi_addr *rf_sipi_addr;
933 const struct rtw_rf_sipi_addr *rf_sipi_addr_a;
934 u32 val32;
935 u32 en_pi;
936 u32 r_addr;
937 u32 shift;
938
939 if (rf_path >= hal->rf_phy_num) {
940 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
941 return INV_RF_DATA;
942 }
943
944 if (!chip->rf_sipi_read_addr) {
945 rtw_err(rtwdev, "rf_sipi_read_addr isn't defined\n");
946 return INV_RF_DATA;
947 }
948
949 rf_sipi_addr = &chip->rf_sipi_read_addr[rf_path];
950 rf_sipi_addr_a = &chip->rf_sipi_read_addr[RF_PATH_A];
951
952 addr &= 0xff;
953
954 val32 = rtw_read32(rtwdev, rf_sipi_addr->hssi_2);
955 val32 = (val32 & ~LSSI_READ_ADDR_MASK) | (addr << 23);
956 rtw_write32(rtwdev, rf_sipi_addr->hssi_2, val32);
957
958 /* toggle read edge of path A */
959 val32 = rtw_read32(rtwdev, rf_sipi_addr_a->hssi_2);
960 rtw_write32(rtwdev, rf_sipi_addr_a->hssi_2, val32 & ~LSSI_READ_EDGE_MASK);
961 rtw_write32(rtwdev, rf_sipi_addr_a->hssi_2, val32 | LSSI_READ_EDGE_MASK);
962
963 udelay(120);
964
965 en_pi = rtw_read32_mask(rtwdev, rf_sipi_addr->hssi_1, BIT(8));
966 r_addr = en_pi ? rf_sipi_addr->lssi_read_pi : rf_sipi_addr->lssi_read;
967
968 val32 = rtw_read32_mask(rtwdev, r_addr, LSSI_READ_DATA_MASK);
969
970 shift = __ffs(mask);
971
972 return (val32 & mask) >> shift;
973}
974EXPORT_SYMBOL(rtw_phy_read_rf_sipi);
975
976bool rtw_phy_write_rf_reg_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
977 u32 addr, u32 mask, u32 data)
978{
979 struct rtw_hal *hal = &rtwdev->hal;
980 const struct rtw_chip_info *chip = rtwdev->chip;
981 const u32 *sipi_addr = chip->rf_sipi_addr;
982 u32 data_and_addr;
983 u32 old_data = 0;
984 u32 shift;
985
986 if (rf_path >= hal->rf_phy_num) {
987 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
988 return false;
989 }
990
991 addr &= 0xff;
992 mask &= RFREG_MASK;
993
994 if (mask != RFREG_MASK) {
995 old_data = chip->ops->read_rf(rtwdev, rf_path, addr, RFREG_MASK);
996
997 if (old_data == INV_RF_DATA) {
998 rtw_err(rtwdev, "Write fail, rf is disabled\n");
999 return false;
1000 }
1001
1002 shift = __ffs(mask);
1003 data = ((old_data) & (~mask)) | (data << shift);
1004 }
1005
1006 data_and_addr = ((addr << 20) | (data & 0x000fffff)) & 0x0fffffff;
1007
1008 rtw_write32(rtwdev, sipi_addr[rf_path], data_and_addr);
1009
1010 udelay(13);
1011
1012 return true;
1013}
1014EXPORT_SYMBOL(rtw_phy_write_rf_reg_sipi);
1015
1016bool rtw_phy_write_rf_reg(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
1017 u32 addr, u32 mask, u32 data)
1018{
1019 struct rtw_hal *hal = &rtwdev->hal;
1020 const struct rtw_chip_info *chip = rtwdev->chip;
1021 const u32 *base_addr = chip->rf_base_addr;
1022 u32 direct_addr;
1023
1024 if (rf_path >= hal->rf_phy_num) {
1025 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1026 return false;
1027 }
1028
1029 addr &= 0xff;
1030 direct_addr = base_addr[rf_path] + (addr << 2);
1031 mask &= RFREG_MASK;
1032
1033 rtw_write32_mask(rtwdev, direct_addr, mask, data);
1034
1035 udelay(1);
1036
1037 return true;
1038}
1039
1040bool rtw_phy_write_rf_reg_mix(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
1041 u32 addr, u32 mask, u32 data)
1042{
1043 if (addr != 0x00)
1044 return rtw_phy_write_rf_reg(rtwdev, rf_path, addr, mask, data);
1045
1046 return rtw_phy_write_rf_reg_sipi(rtwdev, rf_path, addr, mask, data);
1047}
1048EXPORT_SYMBOL(rtw_phy_write_rf_reg_mix);
1049
1050void rtw_phy_setup_phy_cond(struct rtw_dev *rtwdev, u32 pkg)
1051{
1052 struct rtw_hal *hal = &rtwdev->hal;
1053 struct rtw_efuse *efuse = &rtwdev->efuse;
1054 struct rtw_phy_cond cond = {};
1055 struct rtw_phy_cond2 cond2 = {};
1056
1057 cond.cut = hal->cut_version ? hal->cut_version : 15;
1058 cond.pkg = pkg ? pkg : 15;
1059 cond.plat = 0x04;
1060 cond.rfe = efuse->rfe_option;
1061
1062 switch (rtw_hci_type(rtwdev)) {
1063 case RTW_HCI_TYPE_USB:
1064 cond.intf = INTF_USB;
1065 break;
1066 case RTW_HCI_TYPE_SDIO:
1067 cond.intf = INTF_SDIO;
1068 break;
1069 case RTW_HCI_TYPE_PCIE:
1070 default:
1071 cond.intf = INTF_PCIE;
1072 break;
1073 }
1074
1075 if (rtwdev->chip->id == RTW_CHIP_TYPE_8812A ||
1076 rtwdev->chip->id == RTW_CHIP_TYPE_8821A) {
1077 cond.rfe = 0;
1078 cond.rfe |= efuse->ext_lna_2g;
1079 cond.rfe |= efuse->ext_pa_2g << 1;
1080 cond.rfe |= efuse->ext_lna_5g << 2;
1081 cond.rfe |= efuse->ext_pa_5g << 3;
1082 cond.rfe |= efuse->btcoex << 4;
1083
1084 cond2.type_alna = efuse->alna_type;
1085 cond2.type_glna = efuse->glna_type;
1086 cond2.type_apa = efuse->apa_type;
1087 cond2.type_gpa = efuse->gpa_type;
1088 }
1089
1090 hal->phy_cond = cond;
1091 hal->phy_cond2 = cond2;
1092
1093 rtw_dbg(rtwdev, RTW_DBG_PHY, "phy cond=0x%08x cond2=0x%08x\n",
1094 *((u32 *)&hal->phy_cond), *((u32 *)&hal->phy_cond2));
1095}
1096
1097static bool check_positive(struct rtw_dev *rtwdev, struct rtw_phy_cond cond,
1098 struct rtw_phy_cond2 cond2)
1099{
1100 struct rtw_hal *hal = &rtwdev->hal;
1101 struct rtw_phy_cond drv_cond = hal->phy_cond;
1102 struct rtw_phy_cond2 drv_cond2 = hal->phy_cond2;
1103
1104 if (cond.cut && cond.cut != drv_cond.cut)
1105 return false;
1106
1107 if (cond.pkg && cond.pkg != drv_cond.pkg)
1108 return false;
1109
1110 if (cond.intf && cond.intf != drv_cond.intf)
1111 return false;
1112
1113 if (rtwdev->chip->id == RTW_CHIP_TYPE_8812A ||
1114 rtwdev->chip->id == RTW_CHIP_TYPE_8821A) {
1115 if (!(cond.rfe & 0x0f))
1116 return true;
1117
1118 if ((cond.rfe & drv_cond.rfe) != cond.rfe)
1119 return false;
1120
1121 if ((cond.rfe & BIT(0)) && cond2.type_glna != drv_cond2.type_glna)
1122 return false;
1123
1124 if ((cond.rfe & BIT(1)) && cond2.type_gpa != drv_cond2.type_gpa)
1125 return false;
1126
1127 if ((cond.rfe & BIT(2)) && cond2.type_alna != drv_cond2.type_alna)
1128 return false;
1129
1130 if ((cond.rfe & BIT(3)) && cond2.type_apa != drv_cond2.type_apa)
1131 return false;
1132 } else {
1133 if (cond.rfe != drv_cond.rfe)
1134 return false;
1135 }
1136
1137 return true;
1138}
1139
1140void rtw_parse_tbl_phy_cond(struct rtw_dev *rtwdev, const struct rtw_table *tbl)
1141{
1142 const union phy_table_tile *p = tbl->data;
1143 const union phy_table_tile *end = p + tbl->size / 2;
1144 struct rtw_phy_cond pos_cond = {};
1145 struct rtw_phy_cond2 pos_cond2 = {};
1146 bool is_matched = true, is_skipped = false;
1147
1148 BUILD_BUG_ON(sizeof(union phy_table_tile) != sizeof(struct phy_cfg_pair));
1149
1150 for (; p < end; p++) {
1151 if (p->cond.pos) {
1152 switch (p->cond.branch) {
1153 case BRANCH_ENDIF:
1154 is_matched = true;
1155 is_skipped = false;
1156 break;
1157 case BRANCH_ELSE:
1158 is_matched = is_skipped ? false : true;
1159 break;
1160 case BRANCH_IF:
1161 case BRANCH_ELIF:
1162 default:
1163 pos_cond = p->cond;
1164 pos_cond2 = p->cond2;
1165 break;
1166 }
1167 } else if (p->cond.neg) {
1168 if (!is_skipped) {
1169 if (check_positive(rtwdev, pos_cond, pos_cond2)) {
1170 is_matched = true;
1171 is_skipped = true;
1172 } else {
1173 is_matched = false;
1174 is_skipped = false;
1175 }
1176 } else {
1177 is_matched = false;
1178 }
1179 } else if (is_matched) {
1180 (*tbl->do_cfg)(rtwdev, tbl, p->cfg.addr, p->cfg.data);
1181 }
1182 }
1183}
1184EXPORT_SYMBOL(rtw_parse_tbl_phy_cond);
1185
1186#define bcd_to_dec_pwr_by_rate(val, i) bcd2bin(val >> (i * 8))
1187
1188static u8 tbl_to_dec_pwr_by_rate(struct rtw_dev *rtwdev, u32 hex, u8 i)
1189{
1190 if (rtwdev->chip->is_pwr_by_rate_dec)
1191 return bcd_to_dec_pwr_by_rate(hex, i);
1192
1193 return (hex >> (i * 8)) & 0xFF;
1194}
1195
1196static void
1197rtw_phy_get_rate_values_of_txpwr_by_rate(struct rtw_dev *rtwdev,
1198 u32 addr, u32 mask, u32 val, u8 *rate,
1199 u8 *pwr_by_rate, u8 *rate_num)
1200{
1201 int i;
1202
1203 switch (addr) {
1204 case 0xE00:
1205 case 0x830:
1206 rate[0] = DESC_RATE6M;
1207 rate[1] = DESC_RATE9M;
1208 rate[2] = DESC_RATE12M;
1209 rate[3] = DESC_RATE18M;
1210 for (i = 0; i < 4; ++i)
1211 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1212 *rate_num = 4;
1213 break;
1214 case 0xE04:
1215 case 0x834:
1216 rate[0] = DESC_RATE24M;
1217 rate[1] = DESC_RATE36M;
1218 rate[2] = DESC_RATE48M;
1219 rate[3] = DESC_RATE54M;
1220 for (i = 0; i < 4; ++i)
1221 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1222 *rate_num = 4;
1223 break;
1224 case 0xE08:
1225 rate[0] = DESC_RATE1M;
1226 pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 1);
1227 *rate_num = 1;
1228 break;
1229 case 0x86C:
1230 if (mask == 0xffffff00) {
1231 rate[0] = DESC_RATE2M;
1232 rate[1] = DESC_RATE5_5M;
1233 rate[2] = DESC_RATE11M;
1234 for (i = 1; i < 4; ++i)
1235 pwr_by_rate[i - 1] =
1236 tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1237 *rate_num = 3;
1238 } else if (mask == 0x000000ff) {
1239 rate[0] = DESC_RATE11M;
1240 pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 0);
1241 *rate_num = 1;
1242 }
1243 break;
1244 case 0xE10:
1245 case 0x83C:
1246 rate[0] = DESC_RATEMCS0;
1247 rate[1] = DESC_RATEMCS1;
1248 rate[2] = DESC_RATEMCS2;
1249 rate[3] = DESC_RATEMCS3;
1250 for (i = 0; i < 4; ++i)
1251 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1252 *rate_num = 4;
1253 break;
1254 case 0xE14:
1255 case 0x848:
1256 rate[0] = DESC_RATEMCS4;
1257 rate[1] = DESC_RATEMCS5;
1258 rate[2] = DESC_RATEMCS6;
1259 rate[3] = DESC_RATEMCS7;
1260 for (i = 0; i < 4; ++i)
1261 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1262 *rate_num = 4;
1263 break;
1264 case 0xE18:
1265 case 0x84C:
1266 rate[0] = DESC_RATEMCS8;
1267 rate[1] = DESC_RATEMCS9;
1268 rate[2] = DESC_RATEMCS10;
1269 rate[3] = DESC_RATEMCS11;
1270 for (i = 0; i < 4; ++i)
1271 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1272 *rate_num = 4;
1273 break;
1274 case 0xE1C:
1275 case 0x868:
1276 rate[0] = DESC_RATEMCS12;
1277 rate[1] = DESC_RATEMCS13;
1278 rate[2] = DESC_RATEMCS14;
1279 rate[3] = DESC_RATEMCS15;
1280 for (i = 0; i < 4; ++i)
1281 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1282 *rate_num = 4;
1283 break;
1284 case 0x838:
1285 rate[0] = DESC_RATE1M;
1286 rate[1] = DESC_RATE2M;
1287 rate[2] = DESC_RATE5_5M;
1288 for (i = 1; i < 4; ++i)
1289 pwr_by_rate[i - 1] = tbl_to_dec_pwr_by_rate(rtwdev,
1290 val, i);
1291 *rate_num = 3;
1292 break;
1293 case 0xC20:
1294 case 0xE20:
1295 case 0x1820:
1296 case 0x1A20:
1297 rate[0] = DESC_RATE1M;
1298 rate[1] = DESC_RATE2M;
1299 rate[2] = DESC_RATE5_5M;
1300 rate[3] = DESC_RATE11M;
1301 for (i = 0; i < 4; ++i)
1302 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1303 *rate_num = 4;
1304 break;
1305 case 0xC24:
1306 case 0xE24:
1307 case 0x1824:
1308 case 0x1A24:
1309 rate[0] = DESC_RATE6M;
1310 rate[1] = DESC_RATE9M;
1311 rate[2] = DESC_RATE12M;
1312 rate[3] = DESC_RATE18M;
1313 for (i = 0; i < 4; ++i)
1314 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1315 *rate_num = 4;
1316 break;
1317 case 0xC28:
1318 case 0xE28:
1319 case 0x1828:
1320 case 0x1A28:
1321 rate[0] = DESC_RATE24M;
1322 rate[1] = DESC_RATE36M;
1323 rate[2] = DESC_RATE48M;
1324 rate[3] = DESC_RATE54M;
1325 for (i = 0; i < 4; ++i)
1326 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1327 *rate_num = 4;
1328 break;
1329 case 0xC2C:
1330 case 0xE2C:
1331 case 0x182C:
1332 case 0x1A2C:
1333 rate[0] = DESC_RATEMCS0;
1334 rate[1] = DESC_RATEMCS1;
1335 rate[2] = DESC_RATEMCS2;
1336 rate[3] = DESC_RATEMCS3;
1337 for (i = 0; i < 4; ++i)
1338 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1339 *rate_num = 4;
1340 break;
1341 case 0xC30:
1342 case 0xE30:
1343 case 0x1830:
1344 case 0x1A30:
1345 rate[0] = DESC_RATEMCS4;
1346 rate[1] = DESC_RATEMCS5;
1347 rate[2] = DESC_RATEMCS6;
1348 rate[3] = DESC_RATEMCS7;
1349 for (i = 0; i < 4; ++i)
1350 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1351 *rate_num = 4;
1352 break;
1353 case 0xC34:
1354 case 0xE34:
1355 case 0x1834:
1356 case 0x1A34:
1357 rate[0] = DESC_RATEMCS8;
1358 rate[1] = DESC_RATEMCS9;
1359 rate[2] = DESC_RATEMCS10;
1360 rate[3] = DESC_RATEMCS11;
1361 for (i = 0; i < 4; ++i)
1362 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1363 *rate_num = 4;
1364 break;
1365 case 0xC38:
1366 case 0xE38:
1367 case 0x1838:
1368 case 0x1A38:
1369 rate[0] = DESC_RATEMCS12;
1370 rate[1] = DESC_RATEMCS13;
1371 rate[2] = DESC_RATEMCS14;
1372 rate[3] = DESC_RATEMCS15;
1373 for (i = 0; i < 4; ++i)
1374 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1375 *rate_num = 4;
1376 break;
1377 case 0xC3C:
1378 case 0xE3C:
1379 case 0x183C:
1380 case 0x1A3C:
1381 rate[0] = DESC_RATEVHT1SS_MCS0;
1382 rate[1] = DESC_RATEVHT1SS_MCS1;
1383 rate[2] = DESC_RATEVHT1SS_MCS2;
1384 rate[3] = DESC_RATEVHT1SS_MCS3;
1385 for (i = 0; i < 4; ++i)
1386 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1387 *rate_num = 4;
1388 break;
1389 case 0xC40:
1390 case 0xE40:
1391 case 0x1840:
1392 case 0x1A40:
1393 rate[0] = DESC_RATEVHT1SS_MCS4;
1394 rate[1] = DESC_RATEVHT1SS_MCS5;
1395 rate[2] = DESC_RATEVHT1SS_MCS6;
1396 rate[3] = DESC_RATEVHT1SS_MCS7;
1397 for (i = 0; i < 4; ++i)
1398 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1399 *rate_num = 4;
1400 break;
1401 case 0xC44:
1402 case 0xE44:
1403 case 0x1844:
1404 case 0x1A44:
1405 rate[0] = DESC_RATEVHT1SS_MCS8;
1406 rate[1] = DESC_RATEVHT1SS_MCS9;
1407 rate[2] = DESC_RATEVHT2SS_MCS0;
1408 rate[3] = DESC_RATEVHT2SS_MCS1;
1409 for (i = 0; i < 4; ++i)
1410 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1411 *rate_num = 4;
1412 break;
1413 case 0xC48:
1414 case 0xE48:
1415 case 0x1848:
1416 case 0x1A48:
1417 rate[0] = DESC_RATEVHT2SS_MCS2;
1418 rate[1] = DESC_RATEVHT2SS_MCS3;
1419 rate[2] = DESC_RATEVHT2SS_MCS4;
1420 rate[3] = DESC_RATEVHT2SS_MCS5;
1421 for (i = 0; i < 4; ++i)
1422 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1423 *rate_num = 4;
1424 break;
1425 case 0xC4C:
1426 case 0xE4C:
1427 case 0x184C:
1428 case 0x1A4C:
1429 rate[0] = DESC_RATEVHT2SS_MCS6;
1430 rate[1] = DESC_RATEVHT2SS_MCS7;
1431 rate[2] = DESC_RATEVHT2SS_MCS8;
1432 rate[3] = DESC_RATEVHT2SS_MCS9;
1433 for (i = 0; i < 4; ++i)
1434 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1435 *rate_num = 4;
1436 break;
1437 case 0xCD8:
1438 case 0xED8:
1439 case 0x18D8:
1440 case 0x1AD8:
1441 rate[0] = DESC_RATEMCS16;
1442 rate[1] = DESC_RATEMCS17;
1443 rate[2] = DESC_RATEMCS18;
1444 rate[3] = DESC_RATEMCS19;
1445 for (i = 0; i < 4; ++i)
1446 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1447 *rate_num = 4;
1448 break;
1449 case 0xCDC:
1450 case 0xEDC:
1451 case 0x18DC:
1452 case 0x1ADC:
1453 rate[0] = DESC_RATEMCS20;
1454 rate[1] = DESC_RATEMCS21;
1455 rate[2] = DESC_RATEMCS22;
1456 rate[3] = DESC_RATEMCS23;
1457 for (i = 0; i < 4; ++i)
1458 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1459 *rate_num = 4;
1460 break;
1461 case 0xCE0:
1462 case 0xEE0:
1463 case 0x18E0:
1464 case 0x1AE0:
1465 rate[0] = DESC_RATEVHT3SS_MCS0;
1466 rate[1] = DESC_RATEVHT3SS_MCS1;
1467 rate[2] = DESC_RATEVHT3SS_MCS2;
1468 rate[3] = DESC_RATEVHT3SS_MCS3;
1469 for (i = 0; i < 4; ++i)
1470 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1471 *rate_num = 4;
1472 break;
1473 case 0xCE4:
1474 case 0xEE4:
1475 case 0x18E4:
1476 case 0x1AE4:
1477 rate[0] = DESC_RATEVHT3SS_MCS4;
1478 rate[1] = DESC_RATEVHT3SS_MCS5;
1479 rate[2] = DESC_RATEVHT3SS_MCS6;
1480 rate[3] = DESC_RATEVHT3SS_MCS7;
1481 for (i = 0; i < 4; ++i)
1482 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1483 *rate_num = 4;
1484 break;
1485 case 0xCE8:
1486 case 0xEE8:
1487 case 0x18E8:
1488 case 0x1AE8:
1489 rate[0] = DESC_RATEVHT3SS_MCS8;
1490 rate[1] = DESC_RATEVHT3SS_MCS9;
1491 for (i = 0; i < 2; ++i)
1492 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1493 *rate_num = 2;
1494 break;
1495 default:
1496 rtw_warn(rtwdev, "invalid tx power index addr 0x%08x\n", addr);
1497 break;
1498 }
1499}
1500
1501static void rtw_phy_store_tx_power_by_rate(struct rtw_dev *rtwdev,
1502 u32 band, u32 rfpath, u32 txnum,
1503 u32 regaddr, u32 bitmask, u32 data)
1504{
1505 struct rtw_hal *hal = &rtwdev->hal;
1506 u8 rate_num = 0;
1507 u8 rate;
1508 u8 rates[RTW_RF_PATH_MAX] = {0};
1509 s8 offset;
1510 s8 pwr_by_rate[RTW_RF_PATH_MAX] = {0};
1511 int i;
1512
1513 rtw_phy_get_rate_values_of_txpwr_by_rate(rtwdev, regaddr, bitmask, data,
1514 rates, pwr_by_rate, &rate_num);
1515
1516 if (WARN_ON(rfpath >= RTW_RF_PATH_MAX ||
1517 (band != PHY_BAND_2G && band != PHY_BAND_5G) ||
1518 rate_num > RTW_RF_PATH_MAX))
1519 return;
1520
1521 for (i = 0; i < rate_num; i++) {
1522 offset = pwr_by_rate[i];
1523 rate = rates[i];
1524 if (band == PHY_BAND_2G)
1525 hal->tx_pwr_by_rate_offset_2g[rfpath][rate] = offset;
1526 else
1527 hal->tx_pwr_by_rate_offset_5g[rfpath][rate] = offset;
1528 }
1529}
1530
1531void rtw_parse_tbl_bb_pg(struct rtw_dev *rtwdev, const struct rtw_table *tbl)
1532{
1533 const struct rtw_phy_pg_cfg_pair *p = tbl->data;
1534 const struct rtw_phy_pg_cfg_pair *end = p + tbl->size;
1535
1536 for (; p < end; p++) {
1537 if (p->addr == 0xfe || p->addr == 0xffe) {
1538 msleep(50);
1539 continue;
1540 }
1541 rtw_phy_store_tx_power_by_rate(rtwdev, p->band, p->rf_path,
1542 p->tx_num, p->addr, p->bitmask,
1543 p->data);
1544 }
1545}
1546EXPORT_SYMBOL(rtw_parse_tbl_bb_pg);
1547
1548static const u8 rtw_channel_idx_5g[RTW_MAX_CHANNEL_NUM_5G] = {
1549 36, 38, 40, 42, 44, 46, 48, /* Band 1 */
1550 52, 54, 56, 58, 60, 62, 64, /* Band 2 */
1551 100, 102, 104, 106, 108, 110, 112, /* Band 3 */
1552 116, 118, 120, 122, 124, 126, 128, /* Band 3 */
1553 132, 134, 136, 138, 140, 142, 144, /* Band 3 */
1554 149, 151, 153, 155, 157, 159, 161, /* Band 4 */
1555 165, 167, 169, 171, 173, 175, 177}; /* Band 4 */
1556
1557static int rtw_channel_to_idx(u8 band, u8 channel)
1558{
1559 int ch_idx;
1560 u8 n_channel;
1561
1562 if (band == PHY_BAND_2G) {
1563 ch_idx = channel - 1;
1564 n_channel = RTW_MAX_CHANNEL_NUM_2G;
1565 } else if (band == PHY_BAND_5G) {
1566 n_channel = RTW_MAX_CHANNEL_NUM_5G;
1567 for (ch_idx = 0; ch_idx < n_channel; ch_idx++)
1568 if (rtw_channel_idx_5g[ch_idx] == channel)
1569 break;
1570 } else {
1571 return -1;
1572 }
1573
1574 if (ch_idx >= n_channel)
1575 return -1;
1576
1577 return ch_idx;
1578}
1579
1580static void rtw_phy_set_tx_power_limit(struct rtw_dev *rtwdev, u8 regd, u8 band,
1581 u8 bw, u8 rs, u8 ch, s8 pwr_limit)
1582{
1583 struct rtw_hal *hal = &rtwdev->hal;
1584 u8 max_power_index = rtwdev->chip->max_power_index;
1585 s8 ww;
1586 int ch_idx;
1587
1588 pwr_limit = clamp_t(s8, pwr_limit,
1589 -max_power_index, max_power_index);
1590 ch_idx = rtw_channel_to_idx(band, ch);
1591
1592 if (regd >= RTW_REGD_MAX || bw >= RTW_CHANNEL_WIDTH_MAX ||
1593 rs >= RTW_RATE_SECTION_MAX || ch_idx < 0) {
1594 WARN(1,
1595 "wrong txpwr_lmt regd=%u, band=%u bw=%u, rs=%u, ch_idx=%u, pwr_limit=%d\n",
1596 regd, band, bw, rs, ch_idx, pwr_limit);
1597 return;
1598 }
1599
1600 if (band == PHY_BAND_2G) {
1601 hal->tx_pwr_limit_2g[regd][bw][rs][ch_idx] = pwr_limit;
1602 ww = hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx];
1603 ww = min_t(s8, ww, pwr_limit);
1604 hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx] = ww;
1605 } else if (band == PHY_BAND_5G) {
1606 hal->tx_pwr_limit_5g[regd][bw][rs][ch_idx] = pwr_limit;
1607 ww = hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx];
1608 ww = min_t(s8, ww, pwr_limit);
1609 hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx] = ww;
1610 }
1611}
1612
1613/* cross-reference 5G power limits if values are not assigned */
1614static void
1615rtw_xref_5g_txpwr_lmt(struct rtw_dev *rtwdev, u8 regd,
1616 u8 bw, u8 ch_idx, u8 rs_ht, u8 rs_vht)
1617{
1618 struct rtw_hal *hal = &rtwdev->hal;
1619 u8 max_power_index = rtwdev->chip->max_power_index;
1620 s8 lmt_ht = hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx];
1621 s8 lmt_vht = hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx];
1622
1623 if (lmt_ht == lmt_vht)
1624 return;
1625
1626 if (lmt_ht == max_power_index)
1627 hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx] = lmt_vht;
1628
1629 else if (lmt_vht == max_power_index)
1630 hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx] = lmt_ht;
1631}
1632
1633/* cross-reference power limits for ht and vht */
1634static void
1635rtw_xref_txpwr_lmt_by_rs(struct rtw_dev *rtwdev, u8 regd, u8 bw, u8 ch_idx)
1636{
1637 u8 rs_idx, rs_ht, rs_vht;
1638 u8 rs_cmp[2][2] = {{RTW_RATE_SECTION_HT_1S, RTW_RATE_SECTION_VHT_1S},
1639 {RTW_RATE_SECTION_HT_2S, RTW_RATE_SECTION_VHT_2S} };
1640
1641 for (rs_idx = 0; rs_idx < 2; rs_idx++) {
1642 rs_ht = rs_cmp[rs_idx][0];
1643 rs_vht = rs_cmp[rs_idx][1];
1644
1645 rtw_xref_5g_txpwr_lmt(rtwdev, regd, bw, ch_idx, rs_ht, rs_vht);
1646 }
1647}
1648
1649/* cross-reference power limits for 5G channels */
1650static void
1651rtw_xref_5g_txpwr_lmt_by_ch(struct rtw_dev *rtwdev, u8 regd, u8 bw)
1652{
1653 u8 ch_idx;
1654
1655 for (ch_idx = 0; ch_idx < RTW_MAX_CHANNEL_NUM_5G; ch_idx++)
1656 rtw_xref_txpwr_lmt_by_rs(rtwdev, regd, bw, ch_idx);
1657}
1658
1659/* cross-reference power limits for 20/40M bandwidth */
1660static void
1661rtw_xref_txpwr_lmt_by_bw(struct rtw_dev *rtwdev, u8 regd)
1662{
1663 u8 bw;
1664
1665 for (bw = RTW_CHANNEL_WIDTH_20; bw <= RTW_CHANNEL_WIDTH_40; bw++)
1666 rtw_xref_5g_txpwr_lmt_by_ch(rtwdev, regd, bw);
1667}
1668
1669/* cross-reference power limits */
1670static void rtw_xref_txpwr_lmt(struct rtw_dev *rtwdev)
1671{
1672 u8 regd;
1673
1674 for (regd = 0; regd < RTW_REGD_MAX; regd++)
1675 rtw_xref_txpwr_lmt_by_bw(rtwdev, regd);
1676}
1677
1678static void
1679__cfg_txpwr_lmt_by_alt(struct rtw_hal *hal, u8 regd, u8 regd_alt, u8 bw, u8 rs)
1680{
1681 u8 ch;
1682
1683 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++)
1684 hal->tx_pwr_limit_2g[regd][bw][rs][ch] =
1685 hal->tx_pwr_limit_2g[regd_alt][bw][rs][ch];
1686
1687 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++)
1688 hal->tx_pwr_limit_5g[regd][bw][rs][ch] =
1689 hal->tx_pwr_limit_5g[regd_alt][bw][rs][ch];
1690}
1691
1692static void
1693rtw_cfg_txpwr_lmt_by_alt(struct rtw_dev *rtwdev, u8 regd, u8 regd_alt)
1694{
1695 u8 bw, rs;
1696
1697 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++)
1698 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++)
1699 __cfg_txpwr_lmt_by_alt(&rtwdev->hal, regd, regd_alt,
1700 bw, rs);
1701}
1702
1703void rtw_parse_tbl_txpwr_lmt(struct rtw_dev *rtwdev,
1704 const struct rtw_table *tbl)
1705{
1706 const struct rtw_txpwr_lmt_cfg_pair *p = tbl->data;
1707 const struct rtw_txpwr_lmt_cfg_pair *end = p + tbl->size;
1708 u32 regd_cfg_flag = 0;
1709 u8 regd_alt;
1710 u8 i;
1711
1712 for (; p < end; p++) {
1713 regd_cfg_flag |= BIT(p->regd);
1714 rtw_phy_set_tx_power_limit(rtwdev, p->regd, p->band,
1715 p->bw, p->rs, p->ch, p->txpwr_lmt);
1716 }
1717
1718 for (i = 0; i < RTW_REGD_MAX; i++) {
1719 if (i == RTW_REGD_WW)
1720 continue;
1721
1722 if (regd_cfg_flag & BIT(i))
1723 continue;
1724
1725 rtw_dbg(rtwdev, RTW_DBG_REGD,
1726 "txpwr regd %d does not be configured\n", i);
1727
1728 if (rtw_regd_has_alt(i, ®d_alt) &&
1729 regd_cfg_flag & BIT(regd_alt)) {
1730 rtw_dbg(rtwdev, RTW_DBG_REGD,
1731 "cfg txpwr regd %d by regd %d as alternative\n",
1732 i, regd_alt);
1733
1734 rtw_cfg_txpwr_lmt_by_alt(rtwdev, i, regd_alt);
1735 continue;
1736 }
1737
1738 rtw_dbg(rtwdev, RTW_DBG_REGD, "cfg txpwr regd %d by WW\n", i);
1739 rtw_cfg_txpwr_lmt_by_alt(rtwdev, i, RTW_REGD_WW);
1740 }
1741
1742 rtw_xref_txpwr_lmt(rtwdev);
1743}
1744EXPORT_SYMBOL(rtw_parse_tbl_txpwr_lmt);
1745
1746void rtw_phy_cfg_mac(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1747 u32 addr, u32 data)
1748{
1749 rtw_write8(rtwdev, addr, data);
1750}
1751EXPORT_SYMBOL(rtw_phy_cfg_mac);
1752
1753void rtw_phy_cfg_agc(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1754 u32 addr, u32 data)
1755{
1756 rtw_write32(rtwdev, addr, data);
1757}
1758EXPORT_SYMBOL(rtw_phy_cfg_agc);
1759
1760void rtw_phy_cfg_bb(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1761 u32 addr, u32 data)
1762{
1763 if (addr == 0xfe)
1764 msleep(50);
1765 else if (addr == 0xfd)
1766 mdelay(5);
1767 else if (addr == 0xfc)
1768 mdelay(1);
1769 else if (addr == 0xfb)
1770 usleep_range(50, 60);
1771 else if (addr == 0xfa)
1772 udelay(5);
1773 else if (addr == 0xf9)
1774 udelay(1);
1775 else
1776 rtw_write32(rtwdev, addr, data);
1777}
1778EXPORT_SYMBOL(rtw_phy_cfg_bb);
1779
1780void rtw_phy_cfg_rf(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1781 u32 addr, u32 data)
1782{
1783 if (addr == 0xffe) {
1784 msleep(50);
1785 } else if (addr == 0xfe) {
1786 usleep_range(100, 110);
1787 } else {
1788 rtw_write_rf(rtwdev, tbl->rf_path, addr, RFREG_MASK, data);
1789 udelay(1);
1790 }
1791}
1792EXPORT_SYMBOL(rtw_phy_cfg_rf);
1793
1794static void rtw_load_rfk_table(struct rtw_dev *rtwdev)
1795{
1796 const struct rtw_chip_info *chip = rtwdev->chip;
1797 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
1798
1799 if (!chip->rfk_init_tbl)
1800 return;
1801
1802 rtw_write32_mask(rtwdev, 0x1e24, BIT(17), 0x1);
1803 rtw_write32_mask(rtwdev, 0x1cd0, BIT(28), 0x1);
1804 rtw_write32_mask(rtwdev, 0x1cd0, BIT(29), 0x1);
1805 rtw_write32_mask(rtwdev, 0x1cd0, BIT(30), 0x1);
1806 rtw_write32_mask(rtwdev, 0x1cd0, BIT(31), 0x0);
1807
1808 rtw_load_table(rtwdev, chip->rfk_init_tbl);
1809
1810 dpk_info->is_dpk_pwr_on = true;
1811}
1812
1813void rtw_phy_load_tables(struct rtw_dev *rtwdev)
1814{
1815 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev);
1816 const struct rtw_chip_info *chip = rtwdev->chip;
1817 u8 rf_path;
1818
1819 rtw_load_table(rtwdev, chip->mac_tbl);
1820 rtw_load_table(rtwdev, chip->bb_tbl);
1821 rtw_load_table(rtwdev, chip->agc_tbl);
1822 if (rfe_def->agc_btg_tbl)
1823 rtw_load_table(rtwdev, rfe_def->agc_btg_tbl);
1824 rtw_load_rfk_table(rtwdev);
1825
1826 for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++) {
1827 const struct rtw_table *tbl;
1828
1829 tbl = chip->rf_tbl[rf_path];
1830 rtw_load_table(rtwdev, tbl);
1831 }
1832}
1833EXPORT_SYMBOL(rtw_phy_load_tables);
1834
1835static u8 rtw_get_channel_group(u8 channel, u8 rate)
1836{
1837 switch (channel) {
1838 default:
1839 WARN_ON(1);
1840 fallthrough;
1841 case 1:
1842 case 2:
1843 case 36:
1844 case 38:
1845 case 40:
1846 case 42:
1847 return 0;
1848 case 3:
1849 case 4:
1850 case 5:
1851 case 44:
1852 case 46:
1853 case 48:
1854 case 50:
1855 return 1;
1856 case 6:
1857 case 7:
1858 case 8:
1859 case 52:
1860 case 54:
1861 case 56:
1862 case 58:
1863 return 2;
1864 case 9:
1865 case 10:
1866 case 11:
1867 case 60:
1868 case 62:
1869 case 64:
1870 return 3;
1871 case 12:
1872 case 13:
1873 case 100:
1874 case 102:
1875 case 104:
1876 case 106:
1877 return 4;
1878 case 14:
1879 return rate <= DESC_RATE11M ? 5 : 4;
1880 case 108:
1881 case 110:
1882 case 112:
1883 case 114:
1884 return 5;
1885 case 116:
1886 case 118:
1887 case 120:
1888 case 122:
1889 return 6;
1890 case 124:
1891 case 126:
1892 case 128:
1893 case 130:
1894 return 7;
1895 case 132:
1896 case 134:
1897 case 136:
1898 case 138:
1899 return 8;
1900 case 140:
1901 case 142:
1902 case 144:
1903 return 9;
1904 case 149:
1905 case 151:
1906 case 153:
1907 case 155:
1908 return 10;
1909 case 157:
1910 case 159:
1911 case 161:
1912 return 11;
1913 case 165:
1914 case 167:
1915 case 169:
1916 case 171:
1917 return 12;
1918 case 173:
1919 case 175:
1920 case 177:
1921 return 13;
1922 }
1923}
1924
1925static s8 rtw_phy_get_dis_dpd_by_rate_diff(struct rtw_dev *rtwdev, u16 rate)
1926{
1927 const struct rtw_chip_info *chip = rtwdev->chip;
1928 s8 dpd_diff = 0;
1929
1930 if (!chip->en_dis_dpd)
1931 return 0;
1932
1933#define RTW_DPD_RATE_CHECK(_rate) \
1934 case DESC_RATE ## _rate: \
1935 if (DIS_DPD_RATE ## _rate & chip->dpd_ratemask) \
1936 dpd_diff = -6 * chip->txgi_factor; \
1937 break
1938
1939 switch (rate) {
1940 RTW_DPD_RATE_CHECK(6M);
1941 RTW_DPD_RATE_CHECK(9M);
1942 RTW_DPD_RATE_CHECK(MCS0);
1943 RTW_DPD_RATE_CHECK(MCS1);
1944 RTW_DPD_RATE_CHECK(MCS8);
1945 RTW_DPD_RATE_CHECK(MCS9);
1946 RTW_DPD_RATE_CHECK(VHT1SS_MCS0);
1947 RTW_DPD_RATE_CHECK(VHT1SS_MCS1);
1948 RTW_DPD_RATE_CHECK(VHT2SS_MCS0);
1949 RTW_DPD_RATE_CHECK(VHT2SS_MCS1);
1950 }
1951#undef RTW_DPD_RATE_CHECK
1952
1953 return dpd_diff;
1954}
1955
1956static u8 rtw_phy_get_2g_tx_power_index(struct rtw_dev *rtwdev,
1957 struct rtw_2g_txpwr_idx *pwr_idx_2g,
1958 enum rtw_bandwidth bandwidth,
1959 u8 rate, u8 group)
1960{
1961 const struct rtw_chip_info *chip = rtwdev->chip;
1962 u8 tx_power;
1963 bool mcs_rate;
1964 bool above_2ss;
1965 u8 factor = chip->txgi_factor;
1966
1967 if (rate <= DESC_RATE11M)
1968 tx_power = pwr_idx_2g->cck_base[group];
1969 else
1970 tx_power = pwr_idx_2g->bw40_base[group];
1971
1972 if (rate >= DESC_RATE6M && rate <= DESC_RATE54M)
1973 tx_power += pwr_idx_2g->ht_1s_diff.ofdm * factor;
1974
1975 mcs_rate = (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS15) ||
1976 (rate >= DESC_RATEVHT1SS_MCS0 &&
1977 rate <= DESC_RATEVHT2SS_MCS9);
1978 above_2ss = (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) ||
1979 (rate >= DESC_RATEVHT2SS_MCS0);
1980
1981 if (!mcs_rate)
1982 return tx_power;
1983
1984 switch (bandwidth) {
1985 default:
1986 WARN_ON(1);
1987 fallthrough;
1988 case RTW_CHANNEL_WIDTH_20:
1989 tx_power += pwr_idx_2g->ht_1s_diff.bw20 * factor;
1990 if (above_2ss)
1991 tx_power += pwr_idx_2g->ht_2s_diff.bw20 * factor;
1992 break;
1993 case RTW_CHANNEL_WIDTH_40:
1994 /* bw40 is the base power */
1995 if (above_2ss)
1996 tx_power += pwr_idx_2g->ht_2s_diff.bw40 * factor;
1997 break;
1998 }
1999
2000 return tx_power;
2001}
2002
2003static u8 rtw_phy_get_5g_tx_power_index(struct rtw_dev *rtwdev,
2004 struct rtw_5g_txpwr_idx *pwr_idx_5g,
2005 enum rtw_bandwidth bandwidth,
2006 u8 rate, u8 group)
2007{
2008 const struct rtw_chip_info *chip = rtwdev->chip;
2009 u8 tx_power;
2010 u8 upper, lower;
2011 bool mcs_rate;
2012 bool above_2ss;
2013 u8 factor = chip->txgi_factor;
2014
2015 tx_power = pwr_idx_5g->bw40_base[group];
2016
2017 mcs_rate = (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS15) ||
2018 (rate >= DESC_RATEVHT1SS_MCS0 &&
2019 rate <= DESC_RATEVHT2SS_MCS9);
2020 above_2ss = (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) ||
2021 (rate >= DESC_RATEVHT2SS_MCS0);
2022
2023 if (!mcs_rate) {
2024 tx_power += pwr_idx_5g->ht_1s_diff.ofdm * factor;
2025 return tx_power;
2026 }
2027
2028 switch (bandwidth) {
2029 default:
2030 WARN_ON(1);
2031 fallthrough;
2032 case RTW_CHANNEL_WIDTH_20:
2033 tx_power += pwr_idx_5g->ht_1s_diff.bw20 * factor;
2034 if (above_2ss)
2035 tx_power += pwr_idx_5g->ht_2s_diff.bw20 * factor;
2036 break;
2037 case RTW_CHANNEL_WIDTH_40:
2038 /* bw40 is the base power */
2039 if (above_2ss)
2040 tx_power += pwr_idx_5g->ht_2s_diff.bw40 * factor;
2041 break;
2042 case RTW_CHANNEL_WIDTH_80:
2043 /* the base idx of bw80 is the average of bw40+/bw40- */
2044 lower = pwr_idx_5g->bw40_base[group];
2045 upper = pwr_idx_5g->bw40_base[group + 1];
2046
2047 tx_power = (lower + upper) / 2;
2048 tx_power += pwr_idx_5g->vht_1s_diff.bw80 * factor;
2049 if (above_2ss)
2050 tx_power += pwr_idx_5g->vht_2s_diff.bw80 * factor;
2051 break;
2052 }
2053
2054 return tx_power;
2055}
2056
2057/* return RTW_RATE_SECTION_MAX to indicate rate is invalid */
2058static u8 rtw_phy_rate_to_rate_section(u8 rate)
2059{
2060 if (rate >= DESC_RATE1M && rate <= DESC_RATE11M)
2061 return RTW_RATE_SECTION_CCK;
2062 else if (rate >= DESC_RATE6M && rate <= DESC_RATE54M)
2063 return RTW_RATE_SECTION_OFDM;
2064 else if (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS7)
2065 return RTW_RATE_SECTION_HT_1S;
2066 else if (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15)
2067 return RTW_RATE_SECTION_HT_2S;
2068 else if (rate >= DESC_RATEVHT1SS_MCS0 && rate <= DESC_RATEVHT1SS_MCS9)
2069 return RTW_RATE_SECTION_VHT_1S;
2070 else if (rate >= DESC_RATEVHT2SS_MCS0 && rate <= DESC_RATEVHT2SS_MCS9)
2071 return RTW_RATE_SECTION_VHT_2S;
2072 else
2073 return RTW_RATE_SECTION_MAX;
2074}
2075
2076static s8 rtw_phy_get_tx_power_limit(struct rtw_dev *rtwdev, u8 band,
2077 enum rtw_bandwidth bw, u8 rf_path,
2078 u8 rate, u8 channel, u8 regd)
2079{
2080 struct rtw_hal *hal = &rtwdev->hal;
2081 u8 *cch_by_bw = hal->cch_by_bw;
2082 s8 power_limit = (s8)rtwdev->chip->max_power_index;
2083 u8 rs = rtw_phy_rate_to_rate_section(rate);
2084 int ch_idx;
2085 u8 cur_bw, cur_ch;
2086 s8 cur_lmt;
2087
2088 if (regd > RTW_REGD_WW)
2089 return power_limit;
2090
2091 if (rs == RTW_RATE_SECTION_MAX)
2092 goto err;
2093
2094 /* only 20M BW with cck and ofdm */
2095 if (rs == RTW_RATE_SECTION_CCK || rs == RTW_RATE_SECTION_OFDM)
2096 bw = RTW_CHANNEL_WIDTH_20;
2097
2098 /* only 20/40M BW with ht */
2099 if (rs == RTW_RATE_SECTION_HT_1S || rs == RTW_RATE_SECTION_HT_2S)
2100 bw = min_t(u8, bw, RTW_CHANNEL_WIDTH_40);
2101
2102 /* select min power limit among [20M BW ~ current BW] */
2103 for (cur_bw = RTW_CHANNEL_WIDTH_20; cur_bw <= bw; cur_bw++) {
2104 cur_ch = cch_by_bw[cur_bw];
2105
2106 ch_idx = rtw_channel_to_idx(band, cur_ch);
2107 if (ch_idx < 0)
2108 goto err;
2109
2110 cur_lmt = cur_ch <= RTW_MAX_CHANNEL_NUM_2G ?
2111 hal->tx_pwr_limit_2g[regd][cur_bw][rs][ch_idx] :
2112 hal->tx_pwr_limit_5g[regd][cur_bw][rs][ch_idx];
2113
2114 power_limit = min_t(s8, cur_lmt, power_limit);
2115 }
2116
2117 return power_limit;
2118
2119err:
2120 WARN(1, "invalid arguments, band=%d, bw=%d, path=%d, rate=%d, ch=%d\n",
2121 band, bw, rf_path, rate, channel);
2122 return (s8)rtwdev->chip->max_power_index;
2123}
2124
2125static s8 rtw_phy_get_tx_power_sar(struct rtw_dev *rtwdev, u8 sar_band,
2126 u8 rf_path, u8 rate)
2127{
2128 u8 rs = rtw_phy_rate_to_rate_section(rate);
2129 struct rtw_sar_arg arg = {
2130 .sar_band = sar_band,
2131 .path = rf_path,
2132 .rs = rs,
2133 };
2134
2135 if (rs == RTW_RATE_SECTION_MAX)
2136 goto err;
2137
2138 return rtw_query_sar(rtwdev, &arg);
2139
2140err:
2141 WARN(1, "invalid arguments, sar_band=%d, path=%d, rate=%d\n",
2142 sar_band, rf_path, rate);
2143 return (s8)rtwdev->chip->max_power_index;
2144}
2145
2146void rtw_get_tx_power_params(struct rtw_dev *rtwdev, u8 path, u8 rate, u8 bw,
2147 u8 ch, u8 regd, struct rtw_power_params *pwr_param)
2148{
2149 struct rtw_hal *hal = &rtwdev->hal;
2150 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2151 struct rtw_txpwr_idx *pwr_idx;
2152 u8 group, band;
2153 u8 *base = &pwr_param->pwr_base;
2154 s8 *offset = &pwr_param->pwr_offset;
2155 s8 *limit = &pwr_param->pwr_limit;
2156 s8 *remnant = &pwr_param->pwr_remnant;
2157 s8 *sar = &pwr_param->pwr_sar;
2158
2159 pwr_idx = &rtwdev->efuse.txpwr_idx_table[path];
2160 group = rtw_get_channel_group(ch, rate);
2161
2162 /* base power index for 2.4G/5G */
2163 if (IS_CH_2G_BAND(ch)) {
2164 band = PHY_BAND_2G;
2165 *base = rtw_phy_get_2g_tx_power_index(rtwdev,
2166 &pwr_idx->pwr_idx_2g,
2167 bw, rate, group);
2168 *offset = hal->tx_pwr_by_rate_offset_2g[path][rate];
2169 } else {
2170 band = PHY_BAND_5G;
2171 *base = rtw_phy_get_5g_tx_power_index(rtwdev,
2172 &pwr_idx->pwr_idx_5g,
2173 bw, rate, group);
2174 *offset = hal->tx_pwr_by_rate_offset_5g[path][rate];
2175 }
2176
2177 *limit = rtw_phy_get_tx_power_limit(rtwdev, band, bw, path,
2178 rate, ch, regd);
2179 *remnant = rate <= DESC_RATE11M ? dm_info->txagc_remnant_cck :
2180 dm_info->txagc_remnant_ofdm[path];
2181 *sar = rtw_phy_get_tx_power_sar(rtwdev, hal->sar_band, path, rate);
2182}
2183
2184u8
2185rtw_phy_get_tx_power_index(struct rtw_dev *rtwdev, u8 rf_path, u8 rate,
2186 enum rtw_bandwidth bandwidth, u8 channel, u8 regd)
2187{
2188 struct rtw_power_params pwr_param = {0};
2189 u8 tx_power;
2190 s8 offset;
2191
2192 rtw_get_tx_power_params(rtwdev, rf_path, rate, bandwidth,
2193 channel, regd, &pwr_param);
2194
2195 tx_power = pwr_param.pwr_base;
2196 offset = min3(pwr_param.pwr_offset,
2197 pwr_param.pwr_limit,
2198 pwr_param.pwr_sar);
2199
2200 if (rtwdev->chip->en_dis_dpd)
2201 offset += rtw_phy_get_dis_dpd_by_rate_diff(rtwdev, rate);
2202
2203 tx_power += offset + pwr_param.pwr_remnant;
2204
2205 if (tx_power > rtwdev->chip->max_power_index)
2206 tx_power = rtwdev->chip->max_power_index;
2207
2208 return tx_power;
2209}
2210EXPORT_SYMBOL(rtw_phy_get_tx_power_index);
2211
2212static void rtw_phy_set_tx_power_index_by_rs(struct rtw_dev *rtwdev,
2213 u8 ch, u8 path, u8 rs)
2214{
2215 struct rtw_hal *hal = &rtwdev->hal;
2216 u8 regd = rtw_regd_get(rtwdev);
2217 u8 *rates;
2218 u8 size;
2219 u8 rate;
2220 u8 pwr_idx;
2221 u8 bw;
2222 int i;
2223
2224 if (rs >= RTW_RATE_SECTION_MAX)
2225 return;
2226
2227 rates = rtw_rate_section[rs];
2228 size = rtw_rate_size[rs];
2229 bw = hal->current_band_width;
2230 for (i = 0; i < size; i++) {
2231 rate = rates[i];
2232 pwr_idx = rtw_phy_get_tx_power_index(rtwdev, path, rate,
2233 bw, ch, regd);
2234 hal->tx_pwr_tbl[path][rate] = pwr_idx;
2235 }
2236}
2237
2238/* set tx power level by path for each rates, note that the order of the rates
2239 * are *very* important, bacause 8822B/8821C combines every four bytes of tx
2240 * power index into a four-byte power index register, and calls set_tx_agc to
2241 * write these values into hardware
2242 */
2243static void rtw_phy_set_tx_power_level_by_path(struct rtw_dev *rtwdev,
2244 u8 ch, u8 path)
2245{
2246 struct rtw_hal *hal = &rtwdev->hal;
2247 u8 rs;
2248
2249 /* do not need cck rates if we are not in 2.4G */
2250 if (hal->current_band_type == RTW_BAND_2G)
2251 rs = RTW_RATE_SECTION_CCK;
2252 else
2253 rs = RTW_RATE_SECTION_OFDM;
2254
2255 for (; rs < RTW_RATE_SECTION_MAX; rs++)
2256 rtw_phy_set_tx_power_index_by_rs(rtwdev, ch, path, rs);
2257}
2258
2259void rtw_phy_set_tx_power_level(struct rtw_dev *rtwdev, u8 channel)
2260{
2261 const struct rtw_chip_info *chip = rtwdev->chip;
2262 struct rtw_hal *hal = &rtwdev->hal;
2263 u8 path;
2264
2265 mutex_lock(&hal->tx_power_mutex);
2266
2267 for (path = 0; path < hal->rf_path_num; path++)
2268 rtw_phy_set_tx_power_level_by_path(rtwdev, channel, path);
2269
2270 chip->ops->set_tx_power_index(rtwdev);
2271 mutex_unlock(&hal->tx_power_mutex);
2272}
2273EXPORT_SYMBOL(rtw_phy_set_tx_power_level);
2274
2275static void
2276rtw_phy_tx_power_by_rate_config_by_path(struct rtw_hal *hal, u8 path,
2277 u8 rs, u8 size, u8 *rates)
2278{
2279 u8 rate;
2280 u8 base_idx, rate_idx;
2281 s8 base_2g, base_5g;
2282
2283 if (rs >= RTW_RATE_SECTION_VHT_1S)
2284 base_idx = rates[size - 3];
2285 else
2286 base_idx = rates[size - 1];
2287 base_2g = hal->tx_pwr_by_rate_offset_2g[path][base_idx];
2288 base_5g = hal->tx_pwr_by_rate_offset_5g[path][base_idx];
2289 hal->tx_pwr_by_rate_base_2g[path][rs] = base_2g;
2290 hal->tx_pwr_by_rate_base_5g[path][rs] = base_5g;
2291 for (rate = 0; rate < size; rate++) {
2292 rate_idx = rates[rate];
2293 hal->tx_pwr_by_rate_offset_2g[path][rate_idx] -= base_2g;
2294 hal->tx_pwr_by_rate_offset_5g[path][rate_idx] -= base_5g;
2295 }
2296}
2297
2298void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal)
2299{
2300 u8 path;
2301
2302 for (path = 0; path < RTW_RF_PATH_MAX; path++) {
2303 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
2304 RTW_RATE_SECTION_CCK,
2305 rtw_cck_size, rtw_cck_rates);
2306 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
2307 RTW_RATE_SECTION_OFDM,
2308 rtw_ofdm_size, rtw_ofdm_rates);
2309 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
2310 RTW_RATE_SECTION_HT_1S,
2311 rtw_ht_1s_size, rtw_ht_1s_rates);
2312 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
2313 RTW_RATE_SECTION_HT_2S,
2314 rtw_ht_2s_size, rtw_ht_2s_rates);
2315 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
2316 RTW_RATE_SECTION_VHT_1S,
2317 rtw_vht_1s_size, rtw_vht_1s_rates);
2318 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
2319 RTW_RATE_SECTION_VHT_2S,
2320 rtw_vht_2s_size, rtw_vht_2s_rates);
2321 }
2322}
2323
2324static void
2325__rtw_phy_tx_power_limit_config(struct rtw_hal *hal, u8 regd, u8 bw, u8 rs)
2326{
2327 s8 base;
2328 u8 ch;
2329
2330 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++) {
2331 base = hal->tx_pwr_by_rate_base_2g[0][rs];
2332 hal->tx_pwr_limit_2g[regd][bw][rs][ch] -= base;
2333 }
2334
2335 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++) {
2336 base = hal->tx_pwr_by_rate_base_5g[0][rs];
2337 hal->tx_pwr_limit_5g[regd][bw][rs][ch] -= base;
2338 }
2339}
2340
2341void rtw_phy_tx_power_limit_config(struct rtw_hal *hal)
2342{
2343 u8 regd, bw, rs;
2344
2345 /* default at channel 1 */
2346 hal->cch_by_bw[RTW_CHANNEL_WIDTH_20] = 1;
2347
2348 for (regd = 0; regd < RTW_REGD_MAX; regd++)
2349 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++)
2350 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++)
2351 __rtw_phy_tx_power_limit_config(hal, regd, bw, rs);
2352}
2353
2354static void rtw_phy_init_tx_power_limit(struct rtw_dev *rtwdev,
2355 u8 regd, u8 bw, u8 rs)
2356{
2357 struct rtw_hal *hal = &rtwdev->hal;
2358 s8 max_power_index = (s8)rtwdev->chip->max_power_index;
2359 u8 ch;
2360
2361 /* 2.4G channels */
2362 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++)
2363 hal->tx_pwr_limit_2g[regd][bw][rs][ch] = max_power_index;
2364
2365 /* 5G channels */
2366 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++)
2367 hal->tx_pwr_limit_5g[regd][bw][rs][ch] = max_power_index;
2368}
2369
2370void rtw_phy_init_tx_power(struct rtw_dev *rtwdev)
2371{
2372 struct rtw_hal *hal = &rtwdev->hal;
2373 u8 regd, path, rate, rs, bw;
2374
2375 /* init tx power by rate offset */
2376 for (path = 0; path < RTW_RF_PATH_MAX; path++) {
2377 for (rate = 0; rate < DESC_RATE_MAX; rate++) {
2378 hal->tx_pwr_by_rate_offset_2g[path][rate] = 0;
2379 hal->tx_pwr_by_rate_offset_5g[path][rate] = 0;
2380 }
2381 }
2382
2383 /* init tx power limit */
2384 for (regd = 0; regd < RTW_REGD_MAX; regd++)
2385 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++)
2386 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++)
2387 rtw_phy_init_tx_power_limit(rtwdev, regd, bw,
2388 rs);
2389}
2390
2391void rtw_phy_config_swing_table(struct rtw_dev *rtwdev,
2392 struct rtw_swing_table *swing_table)
2393{
2394 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev);
2395 const struct rtw_pwr_track_tbl *tbl = rfe_def->pwr_track_tbl;
2396 u8 channel = rtwdev->hal.current_channel;
2397
2398 if (IS_CH_2G_BAND(channel)) {
2399 if (rtwdev->dm_info.tx_rate <= DESC_RATE11M) {
2400 swing_table->p[RF_PATH_A] = tbl->pwrtrk_2g_ccka_p;
2401 swing_table->n[RF_PATH_A] = tbl->pwrtrk_2g_ccka_n;
2402 swing_table->p[RF_PATH_B] = tbl->pwrtrk_2g_cckb_p;
2403 swing_table->n[RF_PATH_B] = tbl->pwrtrk_2g_cckb_n;
2404 } else {
2405 swing_table->p[RF_PATH_A] = tbl->pwrtrk_2ga_p;
2406 swing_table->n[RF_PATH_A] = tbl->pwrtrk_2ga_n;
2407 swing_table->p[RF_PATH_B] = tbl->pwrtrk_2gb_p;
2408 swing_table->n[RF_PATH_B] = tbl->pwrtrk_2gb_n;
2409 }
2410 } else if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) {
2411 swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_1];
2412 swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_1];
2413 swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_1];
2414 swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_1];
2415 } else if (IS_CH_5G_BAND_3(channel)) {
2416 swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_2];
2417 swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_2];
2418 swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_2];
2419 swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_2];
2420 } else if (IS_CH_5G_BAND_4(channel)) {
2421 swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_3];
2422 swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_3];
2423 swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_3];
2424 swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_3];
2425 } else {
2426 swing_table->p[RF_PATH_A] = tbl->pwrtrk_2ga_p;
2427 swing_table->n[RF_PATH_A] = tbl->pwrtrk_2ga_n;
2428 swing_table->p[RF_PATH_B] = tbl->pwrtrk_2gb_p;
2429 swing_table->n[RF_PATH_B] = tbl->pwrtrk_2gb_n;
2430 }
2431}
2432EXPORT_SYMBOL(rtw_phy_config_swing_table);
2433
2434void rtw_phy_pwrtrack_avg(struct rtw_dev *rtwdev, u8 thermal, u8 path)
2435{
2436 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2437
2438 ewma_thermal_add(&dm_info->avg_thermal[path], thermal);
2439 dm_info->thermal_avg[path] =
2440 ewma_thermal_read(&dm_info->avg_thermal[path]);
2441}
2442EXPORT_SYMBOL(rtw_phy_pwrtrack_avg);
2443
2444bool rtw_phy_pwrtrack_thermal_changed(struct rtw_dev *rtwdev, u8 thermal,
2445 u8 path)
2446{
2447 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2448 u8 avg = ewma_thermal_read(&dm_info->avg_thermal[path]);
2449
2450 if (avg == thermal)
2451 return false;
2452
2453 return true;
2454}
2455EXPORT_SYMBOL(rtw_phy_pwrtrack_thermal_changed);
2456
2457u8 rtw_phy_pwrtrack_get_delta(struct rtw_dev *rtwdev, u8 path)
2458{
2459 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2460 u8 therm_avg, therm_efuse, therm_delta;
2461
2462 therm_avg = dm_info->thermal_avg[path];
2463 therm_efuse = rtwdev->efuse.thermal_meter[path];
2464 therm_delta = abs(therm_avg - therm_efuse);
2465
2466 return min_t(u8, therm_delta, RTW_PWR_TRK_TBL_SZ - 1);
2467}
2468EXPORT_SYMBOL(rtw_phy_pwrtrack_get_delta);
2469
2470s8 rtw_phy_pwrtrack_get_pwridx(struct rtw_dev *rtwdev,
2471 struct rtw_swing_table *swing_table,
2472 u8 tbl_path, u8 therm_path, u8 delta)
2473{
2474 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2475 const u8 *delta_swing_table_idx_pos;
2476 const u8 *delta_swing_table_idx_neg;
2477
2478 if (delta >= RTW_PWR_TRK_TBL_SZ) {
2479 rtw_warn(rtwdev, "power track table overflow\n");
2480 return 0;
2481 }
2482
2483 if (!swing_table) {
2484 rtw_warn(rtwdev, "swing table not configured\n");
2485 return 0;
2486 }
2487
2488 delta_swing_table_idx_pos = swing_table->p[tbl_path];
2489 delta_swing_table_idx_neg = swing_table->n[tbl_path];
2490
2491 if (!delta_swing_table_idx_pos || !delta_swing_table_idx_neg) {
2492 rtw_warn(rtwdev, "invalid swing table index\n");
2493 return 0;
2494 }
2495
2496 if (dm_info->thermal_avg[therm_path] >
2497 rtwdev->efuse.thermal_meter[therm_path])
2498 return delta_swing_table_idx_pos[delta];
2499 else
2500 return -delta_swing_table_idx_neg[delta];
2501}
2502EXPORT_SYMBOL(rtw_phy_pwrtrack_get_pwridx);
2503
2504bool rtw_phy_pwrtrack_need_lck(struct rtw_dev *rtwdev)
2505{
2506 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2507 u8 delta_lck;
2508
2509 delta_lck = abs(dm_info->thermal_avg[0] - dm_info->thermal_meter_lck);
2510 if (delta_lck >= rtwdev->chip->lck_threshold) {
2511 dm_info->thermal_meter_lck = dm_info->thermal_avg[0];
2512 return true;
2513 }
2514 return false;
2515}
2516EXPORT_SYMBOL(rtw_phy_pwrtrack_need_lck);
2517
2518bool rtw_phy_pwrtrack_need_iqk(struct rtw_dev *rtwdev)
2519{
2520 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2521 u8 delta_iqk;
2522
2523 delta_iqk = abs(dm_info->thermal_avg[0] - dm_info->thermal_meter_k);
2524 if (delta_iqk >= rtwdev->chip->iqk_threshold) {
2525 dm_info->thermal_meter_k = dm_info->thermal_avg[0];
2526 return true;
2527 }
2528 return false;
2529}
2530EXPORT_SYMBOL(rtw_phy_pwrtrack_need_iqk);
2531
2532static void rtw_phy_set_tx_path_by_reg(struct rtw_dev *rtwdev,
2533 enum rtw_bb_path tx_path_sel_1ss)
2534{
2535 struct rtw_path_div *path_div = &rtwdev->dm_path_div;
2536 enum rtw_bb_path tx_path_sel_cck = tx_path_sel_1ss;
2537 const struct rtw_chip_info *chip = rtwdev->chip;
2538
2539 if (tx_path_sel_1ss == path_div->current_tx_path)
2540 return;
2541
2542 path_div->current_tx_path = tx_path_sel_1ss;
2543 rtw_dbg(rtwdev, RTW_DBG_PATH_DIV, "Switch TX path=%s\n",
2544 tx_path_sel_1ss == BB_PATH_A ? "A" : "B");
2545 chip->ops->config_tx_path(rtwdev, rtwdev->hal.antenna_tx,
2546 tx_path_sel_1ss, tx_path_sel_cck, false);
2547}
2548
2549static void rtw_phy_tx_path_div_select(struct rtw_dev *rtwdev)
2550{
2551 struct rtw_path_div *path_div = &rtwdev->dm_path_div;
2552 enum rtw_bb_path path = path_div->current_tx_path;
2553 s32 rssi_a = 0, rssi_b = 0;
2554
2555 if (path_div->path_a_cnt)
2556 rssi_a = path_div->path_a_sum / path_div->path_a_cnt;
2557 else
2558 rssi_a = 0;
2559 if (path_div->path_b_cnt)
2560 rssi_b = path_div->path_b_sum / path_div->path_b_cnt;
2561 else
2562 rssi_b = 0;
2563
2564 if (rssi_a != rssi_b)
2565 path = (rssi_a > rssi_b) ? BB_PATH_A : BB_PATH_B;
2566
2567 path_div->path_a_cnt = 0;
2568 path_div->path_a_sum = 0;
2569 path_div->path_b_cnt = 0;
2570 path_div->path_b_sum = 0;
2571 rtw_phy_set_tx_path_by_reg(rtwdev, path);
2572}
2573
2574static void rtw_phy_tx_path_diversity_2ss(struct rtw_dev *rtwdev)
2575{
2576 if (rtwdev->hal.antenna_rx != BB_PATH_AB) {
2577 rtw_dbg(rtwdev, RTW_DBG_PATH_DIV,
2578 "[Return] tx_Path_en=%d, rx_Path_en=%d\n",
2579 rtwdev->hal.antenna_tx, rtwdev->hal.antenna_rx);
2580 return;
2581 }
2582 if (rtwdev->sta_cnt == 0) {
2583 rtw_dbg(rtwdev, RTW_DBG_PATH_DIV, "No Link\n");
2584 return;
2585 }
2586
2587 rtw_phy_tx_path_div_select(rtwdev);
2588}
2589
2590void rtw_phy_tx_path_diversity(struct rtw_dev *rtwdev)
2591{
2592 const struct rtw_chip_info *chip = rtwdev->chip;
2593
2594 if (!chip->path_div_supported)
2595 return;
2596
2597 rtw_phy_tx_path_diversity_2ss(rtwdev);
2598}