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1# SPDX-License-Identifier: GPL-2.0-only
2menu "IRQ chip support"
3
4config IRQCHIP
5 def_bool y
6 depends on (OF_IRQ || ACPI_GENERIC_GSI)
7
8config ARM_GIC
9 bool
10 depends on OF
11 select IRQ_DOMAIN_HIERARCHY
12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
13
14config ARM_GIC_PM
15 bool
16 depends on PM
17 select ARM_GIC
18
19config ARM_GIC_MAX_NR
20 int
21 depends on ARM_GIC
22 default 2 if ARCH_REALVIEW
23 default 1
24
25config ARM_GIC_V2M
26 bool
27 depends on PCI
28 select ARM_GIC
29 select IRQ_MSI_LIB
30 select PCI_MSI
31
32config GIC_NON_BANKED
33 bool
34
35config ARM_GIC_V3
36 bool
37 select IRQ_DOMAIN_HIERARCHY
38 select PARTITION_PERCPU
39 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
40 select HAVE_ARM_SMCCC_DISCOVERY
41
42config ARM_GIC_V3_ITS
43 bool
44 select GENERIC_MSI_IRQ
45 select IRQ_MSI_LIB
46 default ARM_GIC_V3
47
48config ARM_GIC_V3_ITS_FSL_MC
49 bool
50 depends on ARM_GIC_V3_ITS
51 depends on FSL_MC_BUS
52 default ARM_GIC_V3_ITS
53
54config ARM_NVIC
55 bool
56 select IRQ_DOMAIN_HIERARCHY
57 select GENERIC_IRQ_CHIP
58
59config ARM_VIC
60 bool
61 select IRQ_DOMAIN
62
63config ARM_VIC_NR
64 int
65 default 4 if ARCH_S5PV210
66 default 2
67 depends on ARM_VIC
68 help
69 The maximum number of VICs available in the system, for
70 power management.
71
72config IRQ_MSI_LIB
73 bool
74
75config ARMADA_370_XP_IRQ
76 bool
77 select GENERIC_IRQ_CHIP
78 select PCI_MSI if PCI
79 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
80
81config ALPINE_MSI
82 bool
83 depends on PCI
84 select PCI_MSI
85 select GENERIC_IRQ_CHIP
86
87config AL_FIC
88 bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
89 depends on OF
90 depends on HAS_IOMEM
91 select GENERIC_IRQ_CHIP
92 select IRQ_DOMAIN
93 help
94 Support Amazon's Annapurna Labs Fabric Interrupt Controller.
95
96config ATMEL_AIC_IRQ
97 bool
98 select GENERIC_IRQ_CHIP
99 select IRQ_DOMAIN
100 select SPARSE_IRQ
101
102config ATMEL_AIC5_IRQ
103 bool
104 select GENERIC_IRQ_CHIP
105 select IRQ_DOMAIN
106 select SPARSE_IRQ
107
108config I8259
109 bool
110 select IRQ_DOMAIN
111
112config BCM6345_L1_IRQ
113 bool
114 select GENERIC_IRQ_CHIP
115 select IRQ_DOMAIN
116 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
117
118config BCM7038_L1_IRQ
119 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
120 depends on ARCH_BRCMSTB || BMIPS_GENERIC
121 default ARCH_BRCMSTB || BMIPS_GENERIC
122 select GENERIC_IRQ_CHIP
123 select IRQ_DOMAIN
124 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
125
126config BCM7120_L2_IRQ
127 tristate "Broadcom STB 7120-style L2 interrupt controller driver"
128 depends on ARCH_BRCMSTB || BMIPS_GENERIC
129 default ARCH_BRCMSTB || BMIPS_GENERIC
130 select GENERIC_IRQ_CHIP
131 select IRQ_DOMAIN
132
133config BRCMSTB_L2_IRQ
134 tristate "Broadcom STB generic L2 interrupt controller driver"
135 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
136 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
137 select GENERIC_IRQ_CHIP
138 select IRQ_DOMAIN
139
140config DAVINCI_CP_INTC
141 bool
142 select GENERIC_IRQ_CHIP
143 select IRQ_DOMAIN
144
145config DW_APB_ICTL
146 bool
147 select GENERIC_IRQ_CHIP
148 select IRQ_DOMAIN_HIERARCHY
149
150config FARADAY_FTINTC010
151 bool
152 select IRQ_DOMAIN
153 select SPARSE_IRQ
154
155config HISILICON_IRQ_MBIGEN
156 bool
157 select ARM_GIC_V3
158 select ARM_GIC_V3_ITS
159
160config IMGPDC_IRQ
161 bool
162 select GENERIC_IRQ_CHIP
163 select IRQ_DOMAIN
164
165config IXP4XX_IRQ
166 bool
167 select IRQ_DOMAIN
168 select SPARSE_IRQ
169
170config LAN966X_OIC
171 tristate "Microchip LAN966x OIC Support"
172 depends on MCHP_LAN966X_PCI || COMPILE_TEST
173 select GENERIC_IRQ_CHIP
174 select IRQ_DOMAIN
175 help
176 Enable support for the LAN966x Outbound Interrupt Controller.
177 This controller is present on the Microchip LAN966x PCI device and
178 maps the internal interrupts sources to PCIe interrupt.
179
180 To compile this driver as a module, choose M here: the module
181 will be called irq-lan966x-oic.
182
183config MADERA_IRQ
184 tristate
185
186config IRQ_MIPS_CPU
187 bool
188 select GENERIC_IRQ_CHIP
189 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING
190 select IRQ_DOMAIN
191 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
192
193config CLPS711X_IRQCHIP
194 bool
195 depends on ARCH_CLPS711X
196 select IRQ_DOMAIN
197 select SPARSE_IRQ
198 default y
199
200config OMPIC
201 bool
202
203config OR1K_PIC
204 bool
205 select IRQ_DOMAIN
206
207config OMAP_IRQCHIP
208 bool
209 select GENERIC_IRQ_CHIP
210 select IRQ_DOMAIN
211
212config ORION_IRQCHIP
213 bool
214 select IRQ_DOMAIN
215
216config PIC32_EVIC
217 bool
218 select GENERIC_IRQ_CHIP
219 select IRQ_DOMAIN
220
221config JCORE_AIC
222 bool "J-Core integrated AIC" if COMPILE_TEST
223 depends on OF
224 select IRQ_DOMAIN
225 help
226 Support for the J-Core integrated AIC.
227
228config RDA_INTC
229 bool
230 select IRQ_DOMAIN
231
232config RENESAS_INTC_IRQPIN
233 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
234 select IRQ_DOMAIN
235 help
236 Enable support for the Renesas Interrupt Controller for external
237 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
238
239config RENESAS_IRQC
240 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
241 select GENERIC_IRQ_CHIP
242 select IRQ_DOMAIN
243 help
244 Enable support for the Renesas Interrupt Controller for external
245 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
246
247config RENESAS_RZA1_IRQC
248 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
249 select IRQ_DOMAIN_HIERARCHY
250 help
251 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
252 to 8 external interrupts with configurable sense select.
253
254config RENESAS_RZG2L_IRQC
255 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST
256 select GENERIC_IRQ_CHIP
257 select IRQ_DOMAIN_HIERARCHY
258 help
259 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller
260 for external devices.
261
262config RENESAS_RZV2H_ICU
263 bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST
264 select GENERIC_IRQ_CHIP
265 select IRQ_DOMAIN_HIERARCHY
266 help
267 Enable support for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU)
268
269config SL28CPLD_INTC
270 bool "Kontron sl28cpld IRQ controller"
271 depends on MFD_SL28CPLD=y || COMPILE_TEST
272 select REGMAP_IRQ
273 help
274 Interrupt controller driver for the board management controller
275 found on the Kontron sl28 CPLD.
276
277config ST_IRQCHIP
278 bool
279 select REGMAP
280 select MFD_SYSCON
281 help
282 Enables SysCfg Controlled IRQs on STi based platforms.
283
284config SUN4I_INTC
285 bool
286
287config SUN6I_R_INTC
288 bool
289 select IRQ_DOMAIN_HIERARCHY
290 select IRQ_FASTEOI_HIERARCHY_HANDLERS
291
292config SUNXI_NMI_INTC
293 bool
294 select GENERIC_IRQ_CHIP
295
296config TB10X_IRQC
297 bool
298 select IRQ_DOMAIN
299 select GENERIC_IRQ_CHIP
300
301config TS4800_IRQ
302 tristate "TS-4800 IRQ controller"
303 select IRQ_DOMAIN
304 depends on HAS_IOMEM
305 depends on SOC_IMX51 || COMPILE_TEST
306 help
307 Support for the TS-4800 FPGA IRQ controller
308
309config VERSATILE_FPGA_IRQ
310 bool
311 select IRQ_DOMAIN
312
313config VERSATILE_FPGA_IRQ_NR
314 int
315 default 4
316 depends on VERSATILE_FPGA_IRQ
317
318config XTENSA_MX
319 bool
320 select IRQ_DOMAIN
321 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
322
323config XILINX_INTC
324 bool "Xilinx Interrupt Controller IP"
325 depends on OF_ADDRESS
326 select IRQ_DOMAIN
327 help
328 Support for the Xilinx Interrupt Controller IP core.
329 This is used as a primary controller with MicroBlaze and can also
330 be used as a secondary chained controller on other platforms.
331
332config IRQ_CROSSBAR
333 bool
334 help
335 Support for a CROSSBAR ip that precedes the main interrupt controller.
336 The primary irqchip invokes the crossbar's callback which inturn allocates
337 a free irq and configures the IP. Thus the peripheral interrupts are
338 routed to one of the free irqchip interrupt lines.
339
340config KEYSTONE_IRQ
341 tristate "Keystone 2 IRQ controller IP"
342 depends on ARCH_KEYSTONE
343 help
344 Support for Texas Instruments Keystone 2 IRQ controller IP which
345 is part of the Keystone 2 IPC mechanism
346
347config MIPS_GIC
348 bool
349 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
350 select GENERIC_IRQ_IPI if SMP
351 select IRQ_DOMAIN_HIERARCHY
352 select MIPS_CM
353
354config INGENIC_IRQ
355 bool
356 depends on MACH_INGENIC
357 default y
358
359config INGENIC_TCU_IRQ
360 bool "Ingenic JZ47xx TCU interrupt controller"
361 default MACH_INGENIC
362 depends on MIPS || COMPILE_TEST
363 select MFD_SYSCON
364 select GENERIC_IRQ_CHIP
365 help
366 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
367 JZ47xx SoCs.
368
369 If unsure, say N.
370
371config IMX_GPCV2
372 bool
373 select IRQ_DOMAIN
374 help
375 Enables the wakeup IRQs for IMX platforms with GPCv2 block
376
377config IRQ_MXS
378 def_bool y if MACH_ASM9260 || ARCH_MXS
379 select IRQ_DOMAIN
380 select STMP_DEVICE
381
382config MSCC_OCELOT_IRQ
383 bool
384 select IRQ_DOMAIN
385 select GENERIC_IRQ_CHIP
386
387config MVEBU_GICP
388 select IRQ_MSI_LIB
389 bool
390
391config MVEBU_ICU
392 bool
393
394config MVEBU_ODMI
395 bool
396 select IRQ_MSI_LIB
397 select GENERIC_MSI_IRQ
398
399config MVEBU_PIC
400 bool
401
402config MVEBU_SEI
403 bool
404
405config LS_EXTIRQ
406 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
407 select MFD_SYSCON
408
409config LS_SCFG_MSI
410 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
411 depends on PCI_MSI
412
413config PARTITION_PERCPU
414 bool
415
416config STM32MP_EXTI
417 tristate "STM32MP extended interrupts and event controller"
418 depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST
419 default ARCH_STM32 && !ARM_SINGLE_ARMV7M
420 select IRQ_DOMAIN_HIERARCHY
421 select GENERIC_IRQ_CHIP
422 help
423 Support STM32MP EXTI (extended interrupts and event) controller.
424
425config STM32_EXTI
426 bool
427 select IRQ_DOMAIN
428 select GENERIC_IRQ_CHIP
429
430config QCOM_IRQ_COMBINER
431 bool "QCOM IRQ combiner support"
432 depends on ARCH_QCOM && ACPI
433 select IRQ_DOMAIN_HIERARCHY
434 help
435 Say yes here to add support for the IRQ combiner devices embedded
436 in Qualcomm Technologies chips.
437
438config IRQ_UNIPHIER_AIDET
439 bool "UniPhier AIDET support" if COMPILE_TEST
440 depends on ARCH_UNIPHIER || COMPILE_TEST
441 default ARCH_UNIPHIER
442 select IRQ_DOMAIN_HIERARCHY
443 help
444 Support for the UniPhier AIDET (ARM Interrupt Detector).
445
446config MESON_IRQ_GPIO
447 tristate "Meson GPIO Interrupt Multiplexer"
448 depends on ARCH_MESON || COMPILE_TEST
449 default ARCH_MESON
450 select IRQ_DOMAIN_HIERARCHY
451 help
452 Support Meson SoC Family GPIO Interrupt Multiplexer
453
454config GOLDFISH_PIC
455 bool "Goldfish programmable interrupt controller"
456 depends on MIPS && (GOLDFISH || COMPILE_TEST)
457 select GENERIC_IRQ_CHIP
458 select IRQ_DOMAIN
459 help
460 Say yes here to enable Goldfish interrupt controller driver used
461 for Goldfish based virtual platforms.
462
463config QCOM_PDC
464 tristate "QCOM PDC"
465 depends on ARCH_QCOM
466 select IRQ_DOMAIN_HIERARCHY
467 help
468 Power Domain Controller driver to manage and configure wakeup
469 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
470
471config QCOM_MPM
472 tristate "QCOM MPM"
473 depends on ARCH_QCOM
474 depends on MAILBOX
475 select IRQ_DOMAIN_HIERARCHY
476 help
477 MSM Power Manager driver to manage and configure wakeup
478 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
479
480config CSKY_MPINTC
481 bool
482 depends on CSKY
483 help
484 Say yes here to enable C-SKY SMP interrupt controller driver used
485 for C-SKY SMP system.
486 In fact it's not mmio map in hardware and it uses ld/st to visit the
487 controller's register inside CPU.
488
489config CSKY_APB_INTC
490 bool "C-SKY APB Interrupt Controller"
491 depends on CSKY
492 help
493 Say yes here to enable C-SKY APB interrupt controller driver used
494 by C-SKY single core SOC system. It uses mmio map apb-bus to visit
495 the controller's register.
496
497config IMX_IRQSTEER
498 bool "i.MX IRQSTEER support"
499 depends on ARCH_MXC || COMPILE_TEST
500 default ARCH_MXC
501 select IRQ_DOMAIN
502 help
503 Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
504
505config IMX_INTMUX
506 bool "i.MX INTMUX support" if COMPILE_TEST
507 default y if ARCH_MXC
508 select IRQ_DOMAIN
509 help
510 Support for the i.MX INTMUX interrupt multiplexer.
511
512config IMX_MU_MSI
513 tristate "i.MX MU used as MSI controller"
514 depends on OF && HAS_IOMEM
515 depends on ARCH_MXC || COMPILE_TEST
516 default m if ARCH_MXC
517 select IRQ_DOMAIN
518 select IRQ_DOMAIN_HIERARCHY
519 select GENERIC_MSI_IRQ
520 select IRQ_MSI_LIB
521 help
522 Provide a driver for the i.MX Messaging Unit block used as a
523 CPU-to-CPU MSI controller. This requires a specially crafted DT
524 to make use of this driver.
525
526 If unsure, say N
527
528config LS1X_IRQ
529 bool "Loongson-1 Interrupt Controller"
530 depends on MACH_LOONGSON32
531 default y
532 select IRQ_DOMAIN
533 select GENERIC_IRQ_CHIP
534 help
535 Support for the Loongson-1 platform Interrupt Controller.
536
537config TI_SCI_INTR_IRQCHIP
538 bool
539 depends on TI_SCI_PROTOCOL
540 select IRQ_DOMAIN_HIERARCHY
541 help
542 This enables the irqchip driver support for K3 Interrupt router
543 over TI System Control Interface available on some new TI's SoCs.
544 If you wish to use interrupt router irq resources managed by the
545 TI System Controller, say Y here. Otherwise, say N.
546
547config TI_SCI_INTA_IRQCHIP
548 bool
549 depends on TI_SCI_PROTOCOL
550 select IRQ_DOMAIN_HIERARCHY
551 select TI_SCI_INTA_MSI_DOMAIN
552 help
553 This enables the irqchip driver support for K3 Interrupt aggregator
554 over TI System Control Interface available on some new TI's SoCs.
555 If you wish to use interrupt aggregator irq resources managed by the
556 TI System Controller, say Y here. Otherwise, say N.
557
558config TI_PRUSS_INTC
559 tristate
560 depends on TI_PRUSS
561 default TI_PRUSS
562 select IRQ_DOMAIN
563 help
564 This enables support for the PRU-ICSS Local Interrupt Controller
565 present within a PRU-ICSS subsystem present on various TI SoCs.
566 The PRUSS INTC enables various interrupts to be routed to multiple
567 different processors within the SoC.
568
569config RISCV_INTC
570 bool
571 depends on RISCV
572 select IRQ_DOMAIN_HIERARCHY
573
574config RISCV_APLIC
575 bool
576 depends on RISCV
577 select IRQ_DOMAIN_HIERARCHY
578
579config RISCV_APLIC_MSI
580 bool
581 depends on RISCV_APLIC
582 select GENERIC_MSI_IRQ
583 default RISCV_APLIC
584
585config RISCV_IMSIC
586 bool
587 depends on RISCV
588 select IRQ_DOMAIN_HIERARCHY
589 select GENERIC_IRQ_MATRIX_ALLOCATOR
590 select GENERIC_MSI_IRQ
591
592config RISCV_IMSIC_PCI
593 bool
594 depends on RISCV_IMSIC
595 depends on PCI
596 depends on PCI_MSI
597 default RISCV_IMSIC
598
599config SIFIVE_PLIC
600 bool
601 depends on RISCV
602 select IRQ_DOMAIN_HIERARCHY
603 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
604
605config STARFIVE_JH8100_INTC
606 bool "StarFive JH8100 External Interrupt Controller"
607 depends on ARCH_STARFIVE || COMPILE_TEST
608 default ARCH_STARFIVE
609 select IRQ_DOMAIN_HIERARCHY
610 help
611 This enables support for the INTC chip found in StarFive JH8100
612 SoC.
613
614 If you don't know what to do here, say Y.
615
616config THEAD_C900_ACLINT_SSWI
617 bool "THEAD C9XX ACLINT S-mode IPI Interrupt Controller"
618 depends on RISCV
619 depends on SMP
620 select IRQ_DOMAIN_HIERARCHY
621 select GENERIC_IRQ_IPI_MUX
622 help
623 This enables support for T-HEAD specific ACLINT SSWI device
624 support.
625
626 If you don't know what to do here, say Y.
627
628config EXYNOS_IRQ_COMBINER
629 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
630 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
631 help
632 Say yes here to add support for the IRQ combiner devices embedded
633 in Samsung Exynos chips.
634
635config IRQ_LOONGARCH_CPU
636 bool
637 select GENERIC_IRQ_CHIP
638 select IRQ_DOMAIN
639 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
640 select LOONGSON_HTVEC
641 select LOONGSON_LIOINTC
642 select LOONGSON_EIOINTC
643 select LOONGSON_PCH_PIC
644 select LOONGSON_PCH_MSI
645 select LOONGSON_PCH_LPC
646 help
647 Support for the LoongArch CPU Interrupt Controller. For details of
648 irq chip hierarchy on LoongArch platforms please read the document
649 Documentation/arch/loongarch/irq-chip-model.rst.
650
651config LOONGSON_LIOINTC
652 bool "Loongson Local I/O Interrupt Controller"
653 depends on MACH_LOONGSON64
654 default y
655 select IRQ_DOMAIN
656 select GENERIC_IRQ_CHIP
657 help
658 Support for the Loongson Local I/O Interrupt Controller.
659
660config LOONGSON_EIOINTC
661 bool "Loongson Extend I/O Interrupt Controller"
662 depends on LOONGARCH
663 depends on MACH_LOONGSON64
664 default MACH_LOONGSON64
665 select IRQ_DOMAIN_HIERARCHY
666 select GENERIC_IRQ_CHIP
667 help
668 Support for the Loongson3 Extend I/O Interrupt Vector Controller.
669
670config LOONGSON_HTPIC
671 bool "Loongson3 HyperTransport PIC Controller"
672 depends on MACH_LOONGSON64 && MIPS
673 default y
674 select IRQ_DOMAIN
675 select GENERIC_IRQ_CHIP
676 help
677 Support for the Loongson-3 HyperTransport PIC Controller.
678
679config LOONGSON_HTVEC
680 bool "Loongson HyperTransport Interrupt Vector Controller"
681 depends on MACH_LOONGSON64
682 default MACH_LOONGSON64
683 select IRQ_DOMAIN_HIERARCHY
684 help
685 Support for the Loongson HyperTransport Interrupt Vector Controller.
686
687config LOONGSON_PCH_PIC
688 bool "Loongson PCH PIC Controller"
689 depends on MACH_LOONGSON64
690 default MACH_LOONGSON64
691 select IRQ_DOMAIN_HIERARCHY
692 select IRQ_FASTEOI_HIERARCHY_HANDLERS
693 help
694 Support for the Loongson PCH PIC Controller.
695
696config LOONGSON_PCH_MSI
697 bool "Loongson PCH MSI Controller"
698 depends on MACH_LOONGSON64
699 depends on PCI
700 default MACH_LOONGSON64
701 select IRQ_DOMAIN_HIERARCHY
702 select IRQ_MSI_LIB
703 select PCI_MSI
704 help
705 Support for the Loongson PCH MSI Controller.
706
707config LOONGSON_PCH_LPC
708 bool "Loongson PCH LPC Controller"
709 depends on LOONGARCH
710 depends on MACH_LOONGSON64
711 default MACH_LOONGSON64
712 select IRQ_DOMAIN_HIERARCHY
713 help
714 Support for the Loongson PCH LPC Controller.
715
716config MST_IRQ
717 bool "MStar Interrupt Controller"
718 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
719 default ARCH_MEDIATEK
720 select IRQ_DOMAIN
721 select IRQ_DOMAIN_HIERARCHY
722 help
723 Support MStar Interrupt Controller.
724
725config WPCM450_AIC
726 bool "Nuvoton WPCM450 Advanced Interrupt Controller"
727 depends on ARCH_WPCM450
728 help
729 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC.
730
731config IRQ_IDT3243X
732 bool
733 select GENERIC_IRQ_CHIP
734 select IRQ_DOMAIN
735
736config APPLE_AIC
737 bool "Apple Interrupt Controller (AIC)"
738 depends on ARM64
739 depends on ARCH_APPLE || COMPILE_TEST
740 select GENERIC_IRQ_IPI_MUX
741 help
742 Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
743 such as the M1.
744
745config MCHP_EIC
746 bool "Microchip External Interrupt Controller"
747 depends on ARCH_AT91 || COMPILE_TEST
748 select IRQ_DOMAIN
749 select IRQ_DOMAIN_HIERARCHY
750 help
751 Support for Microchip External Interrupt Controller.
752
753config SUNPLUS_SP7021_INTC
754 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST
755 default SOC_SP7021
756 help
757 Support for the Sunplus SP7021 Interrupt Controller IP core.
758 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a
759 chained controller, routing all interrupt source in P-Chip to
760 the primary controller on C-Chip.
761
762endmenu