1/* SPDX-License-Identifier: GPL-2.0-only */
  2/* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3 */
  4#ifndef __A5XX_GPU_H__
  5#define __A5XX_GPU_H__
  6
  7#include "adreno_gpu.h"
  8
  9/* Bringing over the hack from the previous targets */
 10#undef ROP_COPY
 11#undef ROP_XOR
 12
 13#include "a5xx.xml.h"
 14
 15struct a5xx_gpu {
 16	struct adreno_gpu base;
 17
 18	struct drm_gem_object *pm4_bo;
 19	uint64_t pm4_iova;
 20
 21	struct drm_gem_object *pfp_bo;
 22	uint64_t pfp_iova;
 23
 24	struct drm_gem_object *gpmu_bo;
 25	uint64_t gpmu_iova;
 26	uint32_t gpmu_dwords;
 27
 28	uint32_t lm_leakage;
 29
 30	struct msm_ringbuffer *cur_ring;
 31	struct msm_ringbuffer *next_ring;
 32
 33	struct drm_gem_object *preempt_bo[MSM_GPU_MAX_RINGS];
 34	struct drm_gem_object *preempt_counters_bo[MSM_GPU_MAX_RINGS];
 35	struct a5xx_preempt_record *preempt[MSM_GPU_MAX_RINGS];
 36	uint64_t preempt_iova[MSM_GPU_MAX_RINGS];
 37	uint32_t last_seqno[MSM_GPU_MAX_RINGS];
 38
 39	atomic_t preempt_state;
 40	spinlock_t preempt_start_lock;
 41	struct timer_list preempt_timer;
 42
 43	struct drm_gem_object *shadow_bo;
 44	uint64_t shadow_iova;
 45	uint32_t *shadow;
 46
 47	/* True if the microcode supports the WHERE_AM_I opcode */
 48	bool has_whereami;
 49};
 50
 51#define to_a5xx_gpu(x) container_of(x, struct a5xx_gpu, base)
 52
 53#ifdef CONFIG_DEBUG_FS
 54void a5xx_debugfs_init(struct msm_gpu *gpu, struct drm_minor *minor);
 55#endif
 56
 57/*
 58 * In order to do lockless preemption we use a simple state machine to progress
 59 * through the process.
 60 *
 61 * PREEMPT_NONE - no preemption in progress.  Next state START.
 62 * PREEMPT_START - The trigger is evaulating if preemption is possible. Next
 63 * states: TRIGGERED, NONE
 64 * PREEMPT_ABORT - An intermediate state before moving back to NONE. Next
 65 * state: NONE.
 66 * PREEMPT_TRIGGERED: A preemption has been executed on the hardware. Next
 67 * states: FAULTED, PENDING
 68 * PREEMPT_FAULTED: A preemption timed out (never completed). This will trigger
 69 * recovery.  Next state: N/A
 70 * PREEMPT_PENDING: Preemption complete interrupt fired - the callback is
 71 * checking the success of the operation. Next state: FAULTED, NONE.
 72 */
 73
 74enum preempt_state {
 75	PREEMPT_NONE = 0,
 76	PREEMPT_START,
 77	PREEMPT_ABORT,
 78	PREEMPT_TRIGGERED,
 79	PREEMPT_FAULTED,
 80	PREEMPT_PENDING,
 81};
 82
 83/*
 84 * struct a5xx_preempt_record is a shared buffer between the microcode and the
 85 * CPU to store the state for preemption. The record itself is much larger
 86 * (64k) but most of that is used by the CP for storage.
 87 *
 88 * There is a preemption record assigned per ringbuffer. When the CPU triggers a
 89 * preemption, it fills out the record with the useful information (wptr, ring
 90 * base, etc) and the microcode uses that information to set up the CP following
 91 * the preemption.  When a ring is switched out, the CP will save the ringbuffer
 92 * state back to the record. In this way, once the records are properly set up
 93 * the CPU can quickly switch back and forth between ringbuffers by only
 94 * updating a few registers (often only the wptr).
 95 *
 96 * These are the CPU aware registers in the record:
 97 * @magic: Must always be 0x27C4BAFC
 98 * @info: Type of the record - written 0 by the CPU, updated by the CP
 99 * @data: Data field from SET_RENDER_MODE or a checkpoint. Written and used by
100 * the CP
101 * @cntl: Value of RB_CNTL written by CPU, save/restored by CP
102 * @rptr: Value of RB_RPTR written by CPU, save/restored by CP
103 * @wptr: Value of RB_WPTR written by CPU, save/restored by CP
104 * @rptr_addr: Value of RB_RPTR_ADDR written by CPU, save/restored by CP
105 * @rbase: Value of RB_BASE written by CPU, save/restored by CP
106 * @counter: GPU address of the storage area for the performance counters
107 */
108struct a5xx_preempt_record {
109	uint32_t magic;
110	uint32_t info;
111	uint32_t data;
112	uint32_t cntl;
113	uint32_t rptr;
114	uint32_t wptr;
115	uint64_t rptr_addr;
116	uint64_t rbase;
117	uint64_t counter;
118};
119
120/* Magic identifier for the preemption record */
121#define A5XX_PREEMPT_RECORD_MAGIC 0x27C4BAFCUL
122
123/*
124 * Even though the structure above is only a few bytes, we need a full 64k to
125 * store the entire preemption record from the CP
126 */
127#define A5XX_PREEMPT_RECORD_SIZE (64 * 1024)
128
129/*
130 * The preemption counter block is a storage area for the value of the
131 * preemption counters that are saved immediately before context switch. We
132 * append it on to the end of the allocation for the preemption record.
133 */
134#define A5XX_PREEMPT_COUNTER_SIZE (16 * 4)
135
136
137int a5xx_power_init(struct msm_gpu *gpu);
138void a5xx_gpmu_ucode_init(struct msm_gpu *gpu);
139
140static inline int spin_usecs(struct msm_gpu *gpu, uint32_t usecs,
141		uint32_t reg, uint32_t mask, uint32_t value)
142{
143	while (usecs--) {
144		udelay(1);
145		if ((gpu_read(gpu, reg) & mask) == value)
146			return 0;
147		cpu_relax();
148	}
149
150	return -ETIMEDOUT;
151}
152
153#define shadowptr(a5xx_gpu, ring) ((a5xx_gpu)->shadow_iova + \
154		((ring)->id * sizeof(uint32_t)))
155
156bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
157void a5xx_set_hwcg(struct msm_gpu *gpu, bool state);
158
159void a5xx_preempt_init(struct msm_gpu *gpu);
160void a5xx_preempt_hw_init(struct msm_gpu *gpu);
161void a5xx_preempt_trigger(struct msm_gpu *gpu);
162void a5xx_preempt_irq(struct msm_gpu *gpu);
163void a5xx_preempt_fini(struct msm_gpu *gpu);
164
165void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, bool sync);
166
167/* Return true if we are in a preempt state */
168static inline bool a5xx_in_preempt(struct a5xx_gpu *a5xx_gpu)
169{
170	int preempt_state = atomic_read(&a5xx_gpu->preempt_state);
171
172	return !(preempt_state == PREEMPT_NONE ||
173			preempt_state == PREEMPT_ABORT);
174}
175
176#endif /* __A5XX_GPU_H__ */