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1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include "i915_reg.h"
34#include "intel_bios.h"
35#include "intel_ringbuffer.h"
36#include <linux/io-mapping.h>
37#include <linux/i2c.h>
38#include <drm/intel-gtt.h>
39#include <linux/backlight.h>
40
41/* General customization:
42 */
43
44#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
45
46#define DRIVER_NAME "i915"
47#define DRIVER_DESC "Intel Graphics"
48#define DRIVER_DATE "20080730"
49
50enum pipe {
51 PIPE_A = 0,
52 PIPE_B,
53 PIPE_C,
54 I915_MAX_PIPES
55};
56#define pipe_name(p) ((p) + 'A')
57
58enum plane {
59 PLANE_A = 0,
60 PLANE_B,
61 PLANE_C,
62};
63#define plane_name(p) ((p) + 'A')
64
65#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
66
67#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
68
69/* Interface history:
70 *
71 * 1.1: Original.
72 * 1.2: Add Power Management
73 * 1.3: Add vblank support
74 * 1.4: Fix cmdbuffer path, add heap destroy
75 * 1.5: Add vblank pipe configuration
76 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
77 * - Support vertical blank on secondary display pipe
78 */
79#define DRIVER_MAJOR 1
80#define DRIVER_MINOR 6
81#define DRIVER_PATCHLEVEL 0
82
83#define WATCH_COHERENCY 0
84#define WATCH_LISTS 0
85
86#define I915_GEM_PHYS_CURSOR_0 1
87#define I915_GEM_PHYS_CURSOR_1 2
88#define I915_GEM_PHYS_OVERLAY_REGS 3
89#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
90
91struct drm_i915_gem_phys_object {
92 int id;
93 struct page **page_list;
94 drm_dma_handle_t *handle;
95 struct drm_i915_gem_object *cur_obj;
96};
97
98struct mem_block {
99 struct mem_block *next;
100 struct mem_block *prev;
101 int start;
102 int size;
103 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
104};
105
106struct opregion_header;
107struct opregion_acpi;
108struct opregion_swsci;
109struct opregion_asle;
110
111struct intel_opregion {
112 struct opregion_header *header;
113 struct opregion_acpi *acpi;
114 struct opregion_swsci *swsci;
115 struct opregion_asle *asle;
116 void *vbt;
117 u32 __iomem *lid_state;
118};
119#define OPREGION_SIZE (8*1024)
120
121struct intel_overlay;
122struct intel_overlay_error_state;
123
124struct drm_i915_master_private {
125 drm_local_map_t *sarea;
126 struct _drm_i915_sarea *sarea_priv;
127};
128#define I915_FENCE_REG_NONE -1
129
130struct drm_i915_fence_reg {
131 struct list_head lru_list;
132 struct drm_i915_gem_object *obj;
133 uint32_t setup_seqno;
134};
135
136struct sdvo_device_mapping {
137 u8 initialized;
138 u8 dvo_port;
139 u8 slave_addr;
140 u8 dvo_wiring;
141 u8 i2c_pin;
142 u8 i2c_speed;
143 u8 ddc_pin;
144};
145
146struct intel_display_error_state;
147
148struct drm_i915_error_state {
149 u32 eir;
150 u32 pgtbl_er;
151 u32 pipestat[I915_MAX_PIPES];
152 u32 ipeir;
153 u32 ipehr;
154 u32 instdone;
155 u32 acthd;
156 u32 error; /* gen6+ */
157 u32 bcs_acthd; /* gen6+ blt engine */
158 u32 bcs_ipehr;
159 u32 bcs_ipeir;
160 u32 bcs_instdone;
161 u32 bcs_seqno;
162 u32 vcs_acthd; /* gen6+ bsd engine */
163 u32 vcs_ipehr;
164 u32 vcs_ipeir;
165 u32 vcs_instdone;
166 u32 vcs_seqno;
167 u32 instpm;
168 u32 instps;
169 u32 instdone1;
170 u32 seqno;
171 u64 bbaddr;
172 u64 fence[16];
173 struct timeval time;
174 struct drm_i915_error_object {
175 int page_count;
176 u32 gtt_offset;
177 u32 *pages[0];
178 } *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS];
179 struct drm_i915_error_buffer {
180 u32 size;
181 u32 name;
182 u32 seqno;
183 u32 gtt_offset;
184 u32 read_domains;
185 u32 write_domain;
186 s32 fence_reg:5;
187 s32 pinned:2;
188 u32 tiling:2;
189 u32 dirty:1;
190 u32 purgeable:1;
191 u32 ring:4;
192 u32 cache_level:2;
193 } *active_bo, *pinned_bo;
194 u32 active_bo_count, pinned_bo_count;
195 struct intel_overlay_error_state *overlay;
196 struct intel_display_error_state *display;
197};
198
199struct drm_i915_display_funcs {
200 void (*dpms)(struct drm_crtc *crtc, int mode);
201 bool (*fbc_enabled)(struct drm_device *dev);
202 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
203 void (*disable_fbc)(struct drm_device *dev);
204 int (*get_display_clock_speed)(struct drm_device *dev);
205 int (*get_fifo_size)(struct drm_device *dev, int plane);
206 void (*update_wm)(struct drm_device *dev);
207 int (*crtc_mode_set)(struct drm_crtc *crtc,
208 struct drm_display_mode *mode,
209 struct drm_display_mode *adjusted_mode,
210 int x, int y,
211 struct drm_framebuffer *old_fb);
212 void (*fdi_link_train)(struct drm_crtc *crtc);
213 void (*init_clock_gating)(struct drm_device *dev);
214 void (*init_pch_clock_gating)(struct drm_device *dev);
215 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
216 struct drm_framebuffer *fb,
217 struct drm_i915_gem_object *obj);
218 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
219 int x, int y);
220 /* clock updates for mode set */
221 /* cursor updates */
222 /* render clock increase/decrease */
223 /* display clock increase/decrease */
224 /* pll clock increase/decrease */
225};
226
227struct intel_device_info {
228 u8 gen;
229 u8 is_mobile : 1;
230 u8 is_i85x : 1;
231 u8 is_i915g : 1;
232 u8 is_i945gm : 1;
233 u8 is_g33 : 1;
234 u8 need_gfx_hws : 1;
235 u8 is_g4x : 1;
236 u8 is_pineview : 1;
237 u8 is_broadwater : 1;
238 u8 is_crestline : 1;
239 u8 is_ivybridge : 1;
240 u8 has_fbc : 1;
241 u8 has_pipe_cxsr : 1;
242 u8 has_hotplug : 1;
243 u8 cursor_needs_physical : 1;
244 u8 has_overlay : 1;
245 u8 overlay_needs_physical : 1;
246 u8 supports_tv : 1;
247 u8 has_bsd_ring : 1;
248 u8 has_blt_ring : 1;
249};
250
251enum no_fbc_reason {
252 FBC_NO_OUTPUT, /* no outputs enabled to compress */
253 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
254 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
255 FBC_MODE_TOO_LARGE, /* mode too large for compression */
256 FBC_BAD_PLANE, /* fbc not supported on plane */
257 FBC_NOT_TILED, /* buffer not tiled */
258 FBC_MULTIPLE_PIPES, /* more than one pipe active */
259 FBC_MODULE_PARAM,
260};
261
262enum intel_pch {
263 PCH_IBX, /* Ibexpeak PCH */
264 PCH_CPT, /* Cougarpoint PCH */
265};
266
267#define QUIRK_PIPEA_FORCE (1<<0)
268#define QUIRK_LVDS_SSC_DISABLE (1<<1)
269
270struct intel_fbdev;
271struct intel_fbc_work;
272
273typedef struct drm_i915_private {
274 struct drm_device *dev;
275
276 const struct intel_device_info *info;
277
278 int has_gem;
279 int relative_constants_mode;
280
281 void __iomem *regs;
282 u32 gt_fifo_count;
283
284 struct intel_gmbus {
285 struct i2c_adapter adapter;
286 struct i2c_adapter *force_bit;
287 u32 reg0;
288 } *gmbus;
289
290 struct pci_dev *bridge_dev;
291 struct intel_ring_buffer ring[I915_NUM_RINGS];
292 uint32_t next_seqno;
293
294 drm_dma_handle_t *status_page_dmah;
295 uint32_t counter;
296 drm_local_map_t hws_map;
297 struct drm_i915_gem_object *pwrctx;
298 struct drm_i915_gem_object *renderctx;
299
300 struct resource mch_res;
301
302 unsigned int cpp;
303 int back_offset;
304 int front_offset;
305 int current_page;
306 int page_flipping;
307
308 atomic_t irq_received;
309
310 /* protects the irq masks */
311 spinlock_t irq_lock;
312 /** Cached value of IMR to avoid reads in updating the bitfield */
313 u32 pipestat[2];
314 u32 irq_mask;
315 u32 gt_irq_mask;
316 u32 pch_irq_mask;
317
318 u32 hotplug_supported_mask;
319 struct work_struct hotplug_work;
320
321 int tex_lru_log_granularity;
322 int allow_batchbuffer;
323 struct mem_block *agp_heap;
324 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
325 int vblank_pipe;
326 int num_pipe;
327
328 /* For hangcheck timer */
329#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
330 struct timer_list hangcheck_timer;
331 int hangcheck_count;
332 uint32_t last_acthd;
333 uint32_t last_instdone;
334 uint32_t last_instdone1;
335
336 unsigned long cfb_size;
337 unsigned int cfb_fb;
338 enum plane cfb_plane;
339 int cfb_y;
340 struct intel_fbc_work *fbc_work;
341
342 struct intel_opregion opregion;
343
344 /* overlay */
345 struct intel_overlay *overlay;
346
347 /* LVDS info */
348 int backlight_level; /* restore backlight to this value */
349 bool backlight_enabled;
350 struct drm_display_mode *panel_fixed_mode;
351 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
352 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
353
354 /* Feature bits from the VBIOS */
355 unsigned int int_tv_support:1;
356 unsigned int lvds_dither:1;
357 unsigned int lvds_vbt:1;
358 unsigned int int_crt_support:1;
359 unsigned int lvds_use_ssc:1;
360 int lvds_ssc_freq;
361 struct {
362 int rate;
363 int lanes;
364 int preemphasis;
365 int vswing;
366
367 bool initialized;
368 bool support;
369 int bpp;
370 struct edp_power_seq pps;
371 } edp;
372 bool no_aux_handshake;
373
374 struct notifier_block lid_notifier;
375
376 int crt_ddc_pin;
377 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
378 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
379 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
380
381 unsigned int fsb_freq, mem_freq, is_ddr3;
382
383 spinlock_t error_lock;
384 struct drm_i915_error_state *first_error;
385 struct work_struct error_work;
386 struct completion error_completion;
387 struct workqueue_struct *wq;
388
389 /* Display functions */
390 struct drm_i915_display_funcs display;
391
392 /* PCH chipset type */
393 enum intel_pch pch_type;
394
395 unsigned long quirks;
396
397 /* Register state */
398 bool modeset_on_lid;
399 u8 saveLBB;
400 u32 saveDSPACNTR;
401 u32 saveDSPBCNTR;
402 u32 saveDSPARB;
403 u32 saveHWS;
404 u32 savePIPEACONF;
405 u32 savePIPEBCONF;
406 u32 savePIPEASRC;
407 u32 savePIPEBSRC;
408 u32 saveFPA0;
409 u32 saveFPA1;
410 u32 saveDPLL_A;
411 u32 saveDPLL_A_MD;
412 u32 saveHTOTAL_A;
413 u32 saveHBLANK_A;
414 u32 saveHSYNC_A;
415 u32 saveVTOTAL_A;
416 u32 saveVBLANK_A;
417 u32 saveVSYNC_A;
418 u32 saveBCLRPAT_A;
419 u32 saveTRANSACONF;
420 u32 saveTRANS_HTOTAL_A;
421 u32 saveTRANS_HBLANK_A;
422 u32 saveTRANS_HSYNC_A;
423 u32 saveTRANS_VTOTAL_A;
424 u32 saveTRANS_VBLANK_A;
425 u32 saveTRANS_VSYNC_A;
426 u32 savePIPEASTAT;
427 u32 saveDSPASTRIDE;
428 u32 saveDSPASIZE;
429 u32 saveDSPAPOS;
430 u32 saveDSPAADDR;
431 u32 saveDSPASURF;
432 u32 saveDSPATILEOFF;
433 u32 savePFIT_PGM_RATIOS;
434 u32 saveBLC_HIST_CTL;
435 u32 saveBLC_PWM_CTL;
436 u32 saveBLC_PWM_CTL2;
437 u32 saveBLC_CPU_PWM_CTL;
438 u32 saveBLC_CPU_PWM_CTL2;
439 u32 saveFPB0;
440 u32 saveFPB1;
441 u32 saveDPLL_B;
442 u32 saveDPLL_B_MD;
443 u32 saveHTOTAL_B;
444 u32 saveHBLANK_B;
445 u32 saveHSYNC_B;
446 u32 saveVTOTAL_B;
447 u32 saveVBLANK_B;
448 u32 saveVSYNC_B;
449 u32 saveBCLRPAT_B;
450 u32 saveTRANSBCONF;
451 u32 saveTRANS_HTOTAL_B;
452 u32 saveTRANS_HBLANK_B;
453 u32 saveTRANS_HSYNC_B;
454 u32 saveTRANS_VTOTAL_B;
455 u32 saveTRANS_VBLANK_B;
456 u32 saveTRANS_VSYNC_B;
457 u32 savePIPEBSTAT;
458 u32 saveDSPBSTRIDE;
459 u32 saveDSPBSIZE;
460 u32 saveDSPBPOS;
461 u32 saveDSPBADDR;
462 u32 saveDSPBSURF;
463 u32 saveDSPBTILEOFF;
464 u32 saveVGA0;
465 u32 saveVGA1;
466 u32 saveVGA_PD;
467 u32 saveVGACNTRL;
468 u32 saveADPA;
469 u32 saveLVDS;
470 u32 savePP_ON_DELAYS;
471 u32 savePP_OFF_DELAYS;
472 u32 saveDVOA;
473 u32 saveDVOB;
474 u32 saveDVOC;
475 u32 savePP_ON;
476 u32 savePP_OFF;
477 u32 savePP_CONTROL;
478 u32 savePP_DIVISOR;
479 u32 savePFIT_CONTROL;
480 u32 save_palette_a[256];
481 u32 save_palette_b[256];
482 u32 saveDPFC_CB_BASE;
483 u32 saveFBC_CFB_BASE;
484 u32 saveFBC_LL_BASE;
485 u32 saveFBC_CONTROL;
486 u32 saveFBC_CONTROL2;
487 u32 saveIER;
488 u32 saveIIR;
489 u32 saveIMR;
490 u32 saveDEIER;
491 u32 saveDEIMR;
492 u32 saveGTIER;
493 u32 saveGTIMR;
494 u32 saveFDI_RXA_IMR;
495 u32 saveFDI_RXB_IMR;
496 u32 saveCACHE_MODE_0;
497 u32 saveMI_ARB_STATE;
498 u32 saveSWF0[16];
499 u32 saveSWF1[16];
500 u32 saveSWF2[3];
501 u8 saveMSR;
502 u8 saveSR[8];
503 u8 saveGR[25];
504 u8 saveAR_INDEX;
505 u8 saveAR[21];
506 u8 saveDACMASK;
507 u8 saveCR[37];
508 uint64_t saveFENCE[16];
509 u32 saveCURACNTR;
510 u32 saveCURAPOS;
511 u32 saveCURABASE;
512 u32 saveCURBCNTR;
513 u32 saveCURBPOS;
514 u32 saveCURBBASE;
515 u32 saveCURSIZE;
516 u32 saveDP_B;
517 u32 saveDP_C;
518 u32 saveDP_D;
519 u32 savePIPEA_GMCH_DATA_M;
520 u32 savePIPEB_GMCH_DATA_M;
521 u32 savePIPEA_GMCH_DATA_N;
522 u32 savePIPEB_GMCH_DATA_N;
523 u32 savePIPEA_DP_LINK_M;
524 u32 savePIPEB_DP_LINK_M;
525 u32 savePIPEA_DP_LINK_N;
526 u32 savePIPEB_DP_LINK_N;
527 u32 saveFDI_RXA_CTL;
528 u32 saveFDI_TXA_CTL;
529 u32 saveFDI_RXB_CTL;
530 u32 saveFDI_TXB_CTL;
531 u32 savePFA_CTL_1;
532 u32 savePFB_CTL_1;
533 u32 savePFA_WIN_SZ;
534 u32 savePFB_WIN_SZ;
535 u32 savePFA_WIN_POS;
536 u32 savePFB_WIN_POS;
537 u32 savePCH_DREF_CONTROL;
538 u32 saveDISP_ARB_CTL;
539 u32 savePIPEA_DATA_M1;
540 u32 savePIPEA_DATA_N1;
541 u32 savePIPEA_LINK_M1;
542 u32 savePIPEA_LINK_N1;
543 u32 savePIPEB_DATA_M1;
544 u32 savePIPEB_DATA_N1;
545 u32 savePIPEB_LINK_M1;
546 u32 savePIPEB_LINK_N1;
547 u32 saveMCHBAR_RENDER_STANDBY;
548 u32 savePCH_PORT_HOTPLUG;
549
550 struct {
551 /** Bridge to intel-gtt-ko */
552 const struct intel_gtt *gtt;
553 /** Memory allocator for GTT stolen memory */
554 struct drm_mm stolen;
555 /** Memory allocator for GTT */
556 struct drm_mm gtt_space;
557 /** List of all objects in gtt_space. Used to restore gtt
558 * mappings on resume */
559 struct list_head gtt_list;
560
561 /** Usable portion of the GTT for GEM */
562 unsigned long gtt_start;
563 unsigned long gtt_mappable_end;
564 unsigned long gtt_end;
565
566 struct io_mapping *gtt_mapping;
567 int gtt_mtrr;
568
569 struct shrinker inactive_shrinker;
570
571 /**
572 * List of objects currently involved in rendering.
573 *
574 * Includes buffers having the contents of their GPU caches
575 * flushed, not necessarily primitives. last_rendering_seqno
576 * represents when the rendering involved will be completed.
577 *
578 * A reference is held on the buffer while on this list.
579 */
580 struct list_head active_list;
581
582 /**
583 * List of objects which are not in the ringbuffer but which
584 * still have a write_domain which needs to be flushed before
585 * unbinding.
586 *
587 * last_rendering_seqno is 0 while an object is in this list.
588 *
589 * A reference is held on the buffer while on this list.
590 */
591 struct list_head flushing_list;
592
593 /**
594 * LRU list of objects which are not in the ringbuffer and
595 * are ready to unbind, but are still in the GTT.
596 *
597 * last_rendering_seqno is 0 while an object is in this list.
598 *
599 * A reference is not held on the buffer while on this list,
600 * as merely being GTT-bound shouldn't prevent its being
601 * freed, and we'll pull it off the list in the free path.
602 */
603 struct list_head inactive_list;
604
605 /**
606 * LRU list of objects which are not in the ringbuffer but
607 * are still pinned in the GTT.
608 */
609 struct list_head pinned_list;
610
611 /** LRU list of objects with fence regs on them. */
612 struct list_head fence_list;
613
614 /**
615 * List of objects currently pending being freed.
616 *
617 * These objects are no longer in use, but due to a signal
618 * we were prevented from freeing them at the appointed time.
619 */
620 struct list_head deferred_free_list;
621
622 /**
623 * We leave the user IRQ off as much as possible,
624 * but this means that requests will finish and never
625 * be retired once the system goes idle. Set a timer to
626 * fire periodically while the ring is running. When it
627 * fires, go retire requests.
628 */
629 struct delayed_work retire_work;
630
631 /**
632 * Are we in a non-interruptible section of code like
633 * modesetting?
634 */
635 bool interruptible;
636
637 /**
638 * Flag if the X Server, and thus DRM, is not currently in
639 * control of the device.
640 *
641 * This is set between LeaveVT and EnterVT. It needs to be
642 * replaced with a semaphore. It also needs to be
643 * transitioned away from for kernel modesetting.
644 */
645 int suspended;
646
647 /**
648 * Flag if the hardware appears to be wedged.
649 *
650 * This is set when attempts to idle the device timeout.
651 * It prevents command submission from occurring and makes
652 * every pending request fail
653 */
654 atomic_t wedged;
655
656 /** Bit 6 swizzling required for X tiling */
657 uint32_t bit_6_swizzle_x;
658 /** Bit 6 swizzling required for Y tiling */
659 uint32_t bit_6_swizzle_y;
660
661 /* storage for physical objects */
662 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
663
664 /* accounting, useful for userland debugging */
665 size_t gtt_total;
666 size_t mappable_gtt_total;
667 size_t object_memory;
668 u32 object_count;
669 } mm;
670 struct sdvo_device_mapping sdvo_mappings[2];
671 /* indicate whether the LVDS_BORDER should be enabled or not */
672 unsigned int lvds_border_bits;
673 /* Panel fitter placement and size for Ironlake+ */
674 u32 pch_pf_pos, pch_pf_size;
675 int panel_t3, panel_t12;
676
677 struct drm_crtc *plane_to_crtc_mapping[2];
678 struct drm_crtc *pipe_to_crtc_mapping[2];
679 wait_queue_head_t pending_flip_queue;
680 bool flip_pending_is_done;
681
682 /* Reclocking support */
683 bool render_reclock_avail;
684 bool lvds_downclock_avail;
685 /* indicates the reduced downclock for LVDS*/
686 int lvds_downclock;
687 struct work_struct idle_work;
688 struct timer_list idle_timer;
689 bool busy;
690 u16 orig_clock;
691 int child_dev_num;
692 struct child_device_config *child_dev;
693 struct drm_connector *int_lvds_connector;
694 struct drm_connector *int_edp_connector;
695
696 bool mchbar_need_disable;
697
698 struct work_struct rps_work;
699 spinlock_t rps_lock;
700 u32 pm_iir;
701
702 u8 cur_delay;
703 u8 min_delay;
704 u8 max_delay;
705 u8 fmax;
706 u8 fstart;
707
708 u64 last_count1;
709 unsigned long last_time1;
710 u64 last_count2;
711 struct timespec last_time2;
712 unsigned long gfx_power;
713 int c_m;
714 int r_t;
715 u8 corr;
716 spinlock_t *mchdev_lock;
717
718 enum no_fbc_reason no_fbc_reason;
719
720 struct drm_mm_node *compressed_fb;
721 struct drm_mm_node *compressed_llb;
722
723 unsigned long last_gpu_reset;
724
725 /* list of fbdev register on this device */
726 struct intel_fbdev *fbdev;
727
728 struct backlight_device *backlight;
729
730 struct drm_property *broadcast_rgb_property;
731 struct drm_property *force_audio_property;
732
733 atomic_t forcewake_count;
734} drm_i915_private_t;
735
736enum i915_cache_level {
737 I915_CACHE_NONE,
738 I915_CACHE_LLC,
739 I915_CACHE_LLC_MLC, /* gen6+ */
740};
741
742struct drm_i915_gem_object {
743 struct drm_gem_object base;
744
745 /** Current space allocated to this object in the GTT, if any. */
746 struct drm_mm_node *gtt_space;
747 struct list_head gtt_list;
748
749 /** This object's place on the active/flushing/inactive lists */
750 struct list_head ring_list;
751 struct list_head mm_list;
752 /** This object's place on GPU write list */
753 struct list_head gpu_write_list;
754 /** This object's place in the batchbuffer or on the eviction list */
755 struct list_head exec_list;
756
757 /**
758 * This is set if the object is on the active or flushing lists
759 * (has pending rendering), and is not set if it's on inactive (ready
760 * to be unbound).
761 */
762 unsigned int active : 1;
763
764 /**
765 * This is set if the object has been written to since last bound
766 * to the GTT
767 */
768 unsigned int dirty : 1;
769
770 /**
771 * This is set if the object has been written to since the last
772 * GPU flush.
773 */
774 unsigned int pending_gpu_write : 1;
775
776 /**
777 * Fence register bits (if any) for this object. Will be set
778 * as needed when mapped into the GTT.
779 * Protected by dev->struct_mutex.
780 *
781 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
782 */
783 signed int fence_reg : 5;
784
785 /**
786 * Advice: are the backing pages purgeable?
787 */
788 unsigned int madv : 2;
789
790 /**
791 * Current tiling mode for the object.
792 */
793 unsigned int tiling_mode : 2;
794 unsigned int tiling_changed : 1;
795
796 /** How many users have pinned this object in GTT space. The following
797 * users can each hold at most one reference: pwrite/pread, pin_ioctl
798 * (via user_pin_count), execbuffer (objects are not allowed multiple
799 * times for the same batchbuffer), and the framebuffer code. When
800 * switching/pageflipping, the framebuffer code has at most two buffers
801 * pinned per crtc.
802 *
803 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
804 * bits with absolutely no headroom. So use 4 bits. */
805 unsigned int pin_count : 4;
806#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
807
808 /**
809 * Is the object at the current location in the gtt mappable and
810 * fenceable? Used to avoid costly recalculations.
811 */
812 unsigned int map_and_fenceable : 1;
813
814 /**
815 * Whether the current gtt mapping needs to be mappable (and isn't just
816 * mappable by accident). Track pin and fault separate for a more
817 * accurate mappable working set.
818 */
819 unsigned int fault_mappable : 1;
820 unsigned int pin_mappable : 1;
821
822 /*
823 * Is the GPU currently using a fence to access this buffer,
824 */
825 unsigned int pending_fenced_gpu_access:1;
826 unsigned int fenced_gpu_access:1;
827
828 unsigned int cache_level:2;
829
830 struct page **pages;
831
832 /**
833 * DMAR support
834 */
835 struct scatterlist *sg_list;
836 int num_sg;
837
838 /**
839 * Used for performing relocations during execbuffer insertion.
840 */
841 struct hlist_node exec_node;
842 unsigned long exec_handle;
843 struct drm_i915_gem_exec_object2 *exec_entry;
844
845 /**
846 * Current offset of the object in GTT space.
847 *
848 * This is the same as gtt_space->start
849 */
850 uint32_t gtt_offset;
851
852 /** Breadcrumb of last rendering to the buffer. */
853 uint32_t last_rendering_seqno;
854 struct intel_ring_buffer *ring;
855
856 /** Breadcrumb of last fenced GPU access to the buffer. */
857 uint32_t last_fenced_seqno;
858 struct intel_ring_buffer *last_fenced_ring;
859
860 /** Current tiling stride for the object, if it's tiled. */
861 uint32_t stride;
862
863 /** Record of address bit 17 of each page at last unbind. */
864 unsigned long *bit_17;
865
866
867 /**
868 * If present, while GEM_DOMAIN_CPU is in the read domain this array
869 * flags which individual pages are valid.
870 */
871 uint8_t *page_cpu_valid;
872
873 /** User space pin count and filp owning the pin */
874 uint32_t user_pin_count;
875 struct drm_file *pin_filp;
876
877 /** for phy allocated objects */
878 struct drm_i915_gem_phys_object *phys_obj;
879
880 /**
881 * Number of crtcs where this object is currently the fb, but
882 * will be page flipped away on the next vblank. When it
883 * reaches 0, dev_priv->pending_flip_queue will be woken up.
884 */
885 atomic_t pending_flip;
886};
887
888#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
889
890/**
891 * Request queue structure.
892 *
893 * The request queue allows us to note sequence numbers that have been emitted
894 * and may be associated with active buffers to be retired.
895 *
896 * By keeping this list, we can avoid having to do questionable
897 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
898 * an emission time with seqnos for tracking how far ahead of the GPU we are.
899 */
900struct drm_i915_gem_request {
901 /** On Which ring this request was generated */
902 struct intel_ring_buffer *ring;
903
904 /** GEM sequence number associated with this request. */
905 uint32_t seqno;
906
907 /** Time at which this request was emitted, in jiffies. */
908 unsigned long emitted_jiffies;
909
910 /** global list entry for this request */
911 struct list_head list;
912
913 struct drm_i915_file_private *file_priv;
914 /** file_priv list entry for this request */
915 struct list_head client_list;
916};
917
918struct drm_i915_file_private {
919 struct {
920 struct spinlock lock;
921 struct list_head request_list;
922 } mm;
923};
924
925#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
926
927#define IS_I830(dev) ((dev)->pci_device == 0x3577)
928#define IS_845G(dev) ((dev)->pci_device == 0x2562)
929#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
930#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
931#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
932#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
933#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
934#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
935#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
936#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
937#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
938#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
939#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
940#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
941#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
942#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
943#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
944#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
945#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
946#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
947
948/*
949 * The genX designation typically refers to the render engine, so render
950 * capability related checks should use IS_GEN, while display and other checks
951 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
952 * chips, etc.).
953 */
954#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
955#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
956#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
957#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
958#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
959#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
960
961#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
962#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
963#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
964
965#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
966#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
967
968/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
969 * rows, which changed the alignment requirements and fence programming.
970 */
971#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
972 IS_I915GM(dev)))
973#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
974#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
975#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
976#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
977#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
978#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
979/* dsparb controlled by hw only */
980#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
981
982#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
983#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
984#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
985
986#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
987#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
988
989#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
990#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
991#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
992
993#include "i915_trace.h"
994
995extern struct drm_ioctl_desc i915_ioctls[];
996extern int i915_max_ioctl;
997extern unsigned int i915_fbpercrtc __always_unused;
998extern int i915_panel_ignore_lid __read_mostly;
999extern unsigned int i915_powersave __read_mostly;
1000extern unsigned int i915_semaphores __read_mostly;
1001extern unsigned int i915_lvds_downclock __read_mostly;
1002extern unsigned int i915_panel_use_ssc __read_mostly;
1003extern int i915_vbt_sdvo_panel_type __read_mostly;
1004extern unsigned int i915_enable_rc6 __read_mostly;
1005extern unsigned int i915_enable_fbc __read_mostly;
1006extern bool i915_enable_hangcheck __read_mostly;
1007
1008extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1009extern int i915_resume(struct drm_device *dev);
1010extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1011extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1012
1013 /* i915_dma.c */
1014extern void i915_kernel_lost_context(struct drm_device * dev);
1015extern int i915_driver_load(struct drm_device *, unsigned long flags);
1016extern int i915_driver_unload(struct drm_device *);
1017extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1018extern void i915_driver_lastclose(struct drm_device * dev);
1019extern void i915_driver_preclose(struct drm_device *dev,
1020 struct drm_file *file_priv);
1021extern void i915_driver_postclose(struct drm_device *dev,
1022 struct drm_file *file_priv);
1023extern int i915_driver_device_is_agp(struct drm_device * dev);
1024extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1025 unsigned long arg);
1026extern int i915_emit_box(struct drm_device *dev,
1027 struct drm_clip_rect *box,
1028 int DR1, int DR4);
1029extern int i915_reset(struct drm_device *dev, u8 flags);
1030extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1031extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1032extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1033extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1034
1035
1036/* i915_irq.c */
1037void i915_hangcheck_elapsed(unsigned long data);
1038void i915_handle_error(struct drm_device *dev, bool wedged);
1039extern int i915_irq_emit(struct drm_device *dev, void *data,
1040 struct drm_file *file_priv);
1041extern int i915_irq_wait(struct drm_device *dev, void *data,
1042 struct drm_file *file_priv);
1043
1044extern void intel_irq_init(struct drm_device *dev);
1045
1046extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1047 struct drm_file *file_priv);
1048extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1049 struct drm_file *file_priv);
1050extern int i915_vblank_swap(struct drm_device *dev, void *data,
1051 struct drm_file *file_priv);
1052
1053void
1054i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1055
1056void
1057i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1058
1059void intel_enable_asle (struct drm_device *dev);
1060
1061#ifdef CONFIG_DEBUG_FS
1062extern void i915_destroy_error_state(struct drm_device *dev);
1063#else
1064#define i915_destroy_error_state(x)
1065#endif
1066
1067
1068/* i915_mem.c */
1069extern int i915_mem_alloc(struct drm_device *dev, void *data,
1070 struct drm_file *file_priv);
1071extern int i915_mem_free(struct drm_device *dev, void *data,
1072 struct drm_file *file_priv);
1073extern int i915_mem_init_heap(struct drm_device *dev, void *data,
1074 struct drm_file *file_priv);
1075extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
1076 struct drm_file *file_priv);
1077extern void i915_mem_takedown(struct mem_block **heap);
1078extern void i915_mem_release(struct drm_device * dev,
1079 struct drm_file *file_priv, struct mem_block *heap);
1080/* i915_gem.c */
1081int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1082 struct drm_file *file_priv);
1083int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1084 struct drm_file *file_priv);
1085int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1086 struct drm_file *file_priv);
1087int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1088 struct drm_file *file_priv);
1089int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1090 struct drm_file *file_priv);
1091int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1092 struct drm_file *file_priv);
1093int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1094 struct drm_file *file_priv);
1095int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1096 struct drm_file *file_priv);
1097int i915_gem_execbuffer(struct drm_device *dev, void *data,
1098 struct drm_file *file_priv);
1099int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1100 struct drm_file *file_priv);
1101int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1102 struct drm_file *file_priv);
1103int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1104 struct drm_file *file_priv);
1105int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1106 struct drm_file *file_priv);
1107int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1108 struct drm_file *file_priv);
1109int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1110 struct drm_file *file_priv);
1111int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1112 struct drm_file *file_priv);
1113int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1114 struct drm_file *file_priv);
1115int i915_gem_set_tiling(struct drm_device *dev, void *data,
1116 struct drm_file *file_priv);
1117int i915_gem_get_tiling(struct drm_device *dev, void *data,
1118 struct drm_file *file_priv);
1119int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1120 struct drm_file *file_priv);
1121void i915_gem_load(struct drm_device *dev);
1122int i915_gem_init_object(struct drm_gem_object *obj);
1123int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
1124 uint32_t invalidate_domains,
1125 uint32_t flush_domains);
1126struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1127 size_t size);
1128void i915_gem_free_object(struct drm_gem_object *obj);
1129int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1130 uint32_t alignment,
1131 bool map_and_fenceable);
1132void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1133int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1134void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1135void i915_gem_lastclose(struct drm_device *dev);
1136
1137int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1138int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj);
1139void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1140 struct intel_ring_buffer *ring,
1141 u32 seqno);
1142
1143int i915_gem_dumb_create(struct drm_file *file_priv,
1144 struct drm_device *dev,
1145 struct drm_mode_create_dumb *args);
1146int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1147 uint32_t handle, uint64_t *offset);
1148int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1149 uint32_t handle);
1150/**
1151 * Returns true if seq1 is later than seq2.
1152 */
1153static inline bool
1154i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1155{
1156 return (int32_t)(seq1 - seq2) >= 0;
1157}
1158
1159static inline u32
1160i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1161{
1162 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1163 return ring->outstanding_lazy_request = dev_priv->next_seqno;
1164}
1165
1166int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
1167 struct intel_ring_buffer *pipelined);
1168int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1169
1170void i915_gem_retire_requests(struct drm_device *dev);
1171void i915_gem_reset(struct drm_device *dev);
1172void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1173int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1174 uint32_t read_domains,
1175 uint32_t write_domain);
1176int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1177int __must_check i915_gem_init_ringbuffer(struct drm_device *dev);
1178void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1179void i915_gem_do_init(struct drm_device *dev,
1180 unsigned long start,
1181 unsigned long mappable_end,
1182 unsigned long end);
1183int __must_check i915_gpu_idle(struct drm_device *dev);
1184int __must_check i915_gem_idle(struct drm_device *dev);
1185int __must_check i915_add_request(struct intel_ring_buffer *ring,
1186 struct drm_file *file,
1187 struct drm_i915_gem_request *request);
1188int __must_check i915_wait_request(struct intel_ring_buffer *ring,
1189 uint32_t seqno);
1190int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1191int __must_check
1192i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1193 bool write);
1194int __must_check
1195i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1196 u32 alignment,
1197 struct intel_ring_buffer *pipelined);
1198int i915_gem_attach_phys_object(struct drm_device *dev,
1199 struct drm_i915_gem_object *obj,
1200 int id,
1201 int align);
1202void i915_gem_detach_phys_object(struct drm_device *dev,
1203 struct drm_i915_gem_object *obj);
1204void i915_gem_free_all_phys_object(struct drm_device *dev);
1205void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1206
1207uint32_t
1208i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1209 uint32_t size,
1210 int tiling_mode);
1211
1212int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1213 enum i915_cache_level cache_level);
1214
1215/* i915_gem_gtt.c */
1216void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1217int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
1218void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
1219 enum i915_cache_level cache_level);
1220void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1221
1222/* i915_gem_evict.c */
1223int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1224 unsigned alignment, bool mappable);
1225int __must_check i915_gem_evict_everything(struct drm_device *dev,
1226 bool purgeable_only);
1227int __must_check i915_gem_evict_inactive(struct drm_device *dev,
1228 bool purgeable_only);
1229
1230/* i915_gem_tiling.c */
1231void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1232void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1233void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1234
1235/* i915_gem_debug.c */
1236void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1237 const char *where, uint32_t mark);
1238#if WATCH_LISTS
1239int i915_verify_lists(struct drm_device *dev);
1240#else
1241#define i915_verify_lists(dev) 0
1242#endif
1243void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1244 int handle);
1245void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1246 const char *where, uint32_t mark);
1247
1248/* i915_debugfs.c */
1249int i915_debugfs_init(struct drm_minor *minor);
1250void i915_debugfs_cleanup(struct drm_minor *minor);
1251
1252/* i915_suspend.c */
1253extern int i915_save_state(struct drm_device *dev);
1254extern int i915_restore_state(struct drm_device *dev);
1255
1256/* i915_suspend.c */
1257extern int i915_save_state(struct drm_device *dev);
1258extern int i915_restore_state(struct drm_device *dev);
1259
1260/* intel_i2c.c */
1261extern int intel_setup_gmbus(struct drm_device *dev);
1262extern void intel_teardown_gmbus(struct drm_device *dev);
1263extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1264extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1265extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1266{
1267 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1268}
1269extern void intel_i2c_reset(struct drm_device *dev);
1270
1271/* intel_opregion.c */
1272extern int intel_opregion_setup(struct drm_device *dev);
1273#ifdef CONFIG_ACPI
1274extern void intel_opregion_init(struct drm_device *dev);
1275extern void intel_opregion_fini(struct drm_device *dev);
1276extern void intel_opregion_asle_intr(struct drm_device *dev);
1277extern void intel_opregion_gse_intr(struct drm_device *dev);
1278extern void intel_opregion_enable_asle(struct drm_device *dev);
1279#else
1280static inline void intel_opregion_init(struct drm_device *dev) { return; }
1281static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1282static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1283static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1284static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1285#endif
1286
1287/* intel_acpi.c */
1288#ifdef CONFIG_ACPI
1289extern void intel_register_dsm_handler(void);
1290extern void intel_unregister_dsm_handler(void);
1291#else
1292static inline void intel_register_dsm_handler(void) { return; }
1293static inline void intel_unregister_dsm_handler(void) { return; }
1294#endif /* CONFIG_ACPI */
1295
1296/* modesetting */
1297extern void intel_modeset_init(struct drm_device *dev);
1298extern void intel_modeset_gem_init(struct drm_device *dev);
1299extern void intel_modeset_cleanup(struct drm_device *dev);
1300extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1301extern bool intel_fbc_enabled(struct drm_device *dev);
1302extern void intel_disable_fbc(struct drm_device *dev);
1303extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1304extern void ironlake_enable_rc6(struct drm_device *dev);
1305extern void gen6_set_rps(struct drm_device *dev, u8 val);
1306extern void intel_detect_pch (struct drm_device *dev);
1307extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1308
1309/* overlay */
1310#ifdef CONFIG_DEBUG_FS
1311extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1312extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1313
1314extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1315extern void intel_display_print_error_state(struct seq_file *m,
1316 struct drm_device *dev,
1317 struct intel_display_error_state *error);
1318#endif
1319
1320#define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1321
1322#define BEGIN_LP_RING(n) \
1323 intel_ring_begin(LP_RING(dev_priv), (n))
1324
1325#define OUT_RING(x) \
1326 intel_ring_emit(LP_RING(dev_priv), x)
1327
1328#define ADVANCE_LP_RING() \
1329 intel_ring_advance(LP_RING(dev_priv))
1330
1331/**
1332 * Lock test for when it's just for synchronization of ring access.
1333 *
1334 * In that case, we don't need to do it when GEM is initialized as nobody else
1335 * has access to the ring.
1336 */
1337#define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
1338 if (LP_RING(dev->dev_private)->obj == NULL) \
1339 LOCK_TEST_WITH_RETURN(dev, file); \
1340} while (0)
1341
1342/* On SNB platform, before reading ring registers forcewake bit
1343 * must be set to prevent GT core from power down and stale values being
1344 * returned.
1345 */
1346void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1347void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1348void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1349
1350/* We give fast paths for the really cool registers */
1351#define NEEDS_FORCE_WAKE(dev_priv, reg) \
1352 (((dev_priv)->info->gen >= 6) && \
1353 ((reg) < 0x40000) && \
1354 ((reg) != FORCEWAKE))
1355
1356#define __i915_read(x, y) \
1357static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1358 u##x val = 0; \
1359 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1360 gen6_gt_force_wake_get(dev_priv); \
1361 val = read##y(dev_priv->regs + reg); \
1362 gen6_gt_force_wake_put(dev_priv); \
1363 } else { \
1364 val = read##y(dev_priv->regs + reg); \
1365 } \
1366 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1367 return val; \
1368}
1369
1370__i915_read(8, b)
1371__i915_read(16, w)
1372__i915_read(32, l)
1373__i915_read(64, q)
1374#undef __i915_read
1375
1376#define __i915_write(x, y) \
1377static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1378 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1379 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1380 __gen6_gt_wait_for_fifo(dev_priv); \
1381 } \
1382 write##y(val, dev_priv->regs + reg); \
1383}
1384__i915_write(8, b)
1385__i915_write(16, w)
1386__i915_write(32, l)
1387__i915_write(64, q)
1388#undef __i915_write
1389
1390#define I915_READ8(reg) i915_read8(dev_priv, (reg))
1391#define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1392
1393#define I915_READ16(reg) i915_read16(dev_priv, (reg))
1394#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1395#define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1396#define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1397
1398#define I915_READ(reg) i915_read32(dev_priv, (reg))
1399#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1400#define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1401#define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1402
1403#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1404#define I915_READ64(reg) i915_read64(dev_priv, (reg))
1405
1406#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1407#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1408
1409
1410#endif
1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include <uapi/drm/i915_drm.h>
34
35#include <linux/pm_qos.h>
36
37#include <drm/ttm/ttm_device.h>
38
39#include "display/intel_display_limits.h"
40#include "display/intel_display_core.h"
41
42#include "gem/i915_gem_context_types.h"
43#include "gem/i915_gem_shrinker.h"
44#include "gem/i915_gem_stolen.h"
45
46#include "gt/intel_engine.h"
47#include "gt/intel_gt_types.h"
48#include "gt/intel_region_lmem.h"
49#include "gt/intel_workarounds.h"
50#include "gt/uc/intel_uc.h"
51
52#include "soc/intel_pch.h"
53
54#include "i915_drm_client.h"
55#include "i915_gem.h"
56#include "i915_gpu_error.h"
57#include "i915_params.h"
58#include "i915_perf_types.h"
59#include "i915_scheduler.h"
60#include "i915_utils.h"
61#include "intel_device_info.h"
62#include "intel_memory_region.h"
63#include "intel_runtime_pm.h"
64#include "intel_step.h"
65#include "intel_uncore.h"
66
67struct drm_i915_clock_gating_funcs;
68struct vlv_s0ix_state;
69struct intel_pxp;
70
71#define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)
72
73/* Data Stolen Memory (DSM) aka "i915 stolen memory" */
74struct i915_dsm {
75 /*
76 * The start and end of DSM which we can optionally use to create GEM
77 * objects backed by stolen memory.
78 *
79 * Note that usable_size tells us exactly how much of this we are
80 * actually allowed to use, given that some portion of it is in fact
81 * reserved for use by hardware functions.
82 */
83 struct resource stolen;
84
85 /*
86 * Reserved portion of DSM.
87 */
88 struct resource reserved;
89
90 /*
91 * Total size minus reserved ranges.
92 *
93 * DSM is segmented in hardware with different portions offlimits to
94 * certain functions.
95 *
96 * The drm_mm is initialised to the total accessible range, as found
97 * from the PCI config. On Broadwell+, this is further restricted to
98 * avoid the first page! The upper end of DSM is reserved for hardware
99 * functions and similarly removed from the accessible range.
100 */
101 resource_size_t usable_size;
102};
103
104struct i915_suspend_saved_registers {
105 u32 saveDSPARB;
106 u32 saveSWF0[16];
107 u32 saveSWF1[16];
108 u32 saveSWF3[3];
109 u16 saveGCDGMBUS;
110};
111
112#define MAX_L3_SLICES 2
113struct intel_l3_parity {
114 u32 *remap_info[MAX_L3_SLICES];
115 struct work_struct error_work;
116 int which_slice;
117};
118
119struct i915_gem_mm {
120 /*
121 * Shortcut for the stolen region. This points to either
122 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or
123 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't
124 * support stolen.
125 */
126 struct intel_memory_region *stolen_region;
127 /** Memory allocator for GTT stolen memory */
128 struct drm_mm stolen;
129 /** Protects the usage of the GTT stolen memory allocator. This is
130 * always the inner lock when overlapping with struct_mutex. */
131 struct mutex stolen_lock;
132
133 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
134 spinlock_t obj_lock;
135
136 /**
137 * List of objects which are purgeable.
138 */
139 struct list_head purge_list;
140
141 /**
142 * List of objects which have allocated pages and are shrinkable.
143 */
144 struct list_head shrink_list;
145
146 /**
147 * List of objects which are pending destruction.
148 */
149 struct llist_head free_list;
150 struct work_struct free_work;
151 /**
152 * Count of objects pending destructions. Used to skip needlessly
153 * waiting on an RCU barrier if no objects are waiting to be freed.
154 */
155 atomic_t free_count;
156
157 /**
158 * tmpfs instance used for shmem backed objects
159 */
160 struct vfsmount *gemfs;
161
162 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
163
164 struct notifier_block oom_notifier;
165 struct notifier_block vmap_notifier;
166 struct shrinker *shrinker;
167
168 /* shrinker accounting, also useful for userland debugging */
169 u64 shrink_memory;
170 u32 shrink_count;
171};
172
173struct i915_virtual_gpu {
174 struct mutex lock; /* serialises sending of g2v_notify command pkts */
175 bool active;
176 u32 caps;
177 u32 *initial_mmio;
178 u8 *initial_cfg_space;
179 struct list_head entry;
180};
181
182struct i915_selftest_stash {
183 atomic_t counter;
184 struct ida mock_region_instances;
185};
186
187struct drm_i915_private {
188 struct drm_device drm;
189
190 struct intel_display display;
191
192 /* FIXME: Device release actions should all be moved to drmm_ */
193 bool do_release;
194
195 /* i915 device parameters */
196 struct i915_params params;
197
198 const struct intel_device_info *__info; /* Use INTEL_INFO() to access. */
199 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
200 struct intel_driver_caps caps;
201
202 struct i915_dsm dsm;
203
204 struct intel_uncore uncore;
205 struct intel_uncore_mmio_debug mmio_debug;
206
207 struct i915_virtual_gpu vgpu;
208
209 struct intel_gvt *gvt;
210
211 struct {
212 struct pci_dev *pdev;
213 struct resource mch_res;
214 bool mchbar_need_disable;
215 } gmch;
216
217 /*
218 * Chaining user engines happens in multiple stages, starting with a
219 * simple lock-less linked list created by intel_engine_add_user(),
220 * which later gets sorted and converted to an intermediate regular
221 * list, just to be converted once again to its final rb tree structure
222 * in intel_engines_driver_register().
223 *
224 * Make sure to use the right iterator helper, depending on if the code
225 * in question runs before or after intel_engines_driver_register() --
226 * for_each_uabi_engine() can only be used afterwards!
227 */
228 union {
229 struct llist_head uabi_engines_llist;
230 struct list_head uabi_engines_list;
231 struct rb_root uabi_engines;
232 };
233 unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1];
234
235 /* protects the irq masks */
236 spinlock_t irq_lock;
237 bool irqs_enabled;
238
239 /* Sideband mailbox protection */
240 struct mutex sb_lock;
241 struct pm_qos_request sb_qos;
242
243 /** Cached value of IMR to avoid reads in updating the bitfield */
244 u32 irq_mask;
245
246 bool preserve_bios_swizzle;
247
248 unsigned int fsb_freq, mem_freq, is_ddr3;
249
250 unsigned int hpll_freq;
251 unsigned int czclk_freq;
252
253 /**
254 * wq - Driver workqueue for GEM.
255 *
256 * NOTE: Work items scheduled here are not allowed to grab any modeset
257 * locks, for otherwise the flushing done in the pageflip code will
258 * result in deadlocks.
259 */
260 struct workqueue_struct *wq;
261
262 /**
263 * unordered_wq - internal workqueue for unordered work
264 *
265 * This workqueue should be used for all unordered work
266 * scheduling within i915, which used to be scheduled on the
267 * system_wq before moving to a driver instance due
268 * deprecation of flush_scheduled_work().
269 */
270 struct workqueue_struct *unordered_wq;
271
272 /* pm private clock gating functions */
273 const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
274
275 /* PCH chipset type */
276 enum intel_pch pch_type;
277 unsigned short pch_id;
278
279 unsigned long gem_quirks;
280
281 struct i915_gem_mm mm;
282
283 struct intel_l3_parity l3_parity;
284
285 /*
286 * edram size in MB.
287 * Cannot be determined by PCIID. You must always read a register.
288 */
289 u32 edram_size_mb;
290
291 struct i915_gpu_error gpu_error;
292
293 u32 suspend_count;
294 struct i915_suspend_saved_registers regfile;
295 struct vlv_s0ix_state *vlv_s0ix_state;
296
297 struct dram_info {
298 bool wm_lv_0_adjust_needed;
299 u8 num_channels;
300 bool symmetric_memory;
301 enum intel_dram_type {
302 INTEL_DRAM_UNKNOWN,
303 INTEL_DRAM_DDR3,
304 INTEL_DRAM_DDR4,
305 INTEL_DRAM_LPDDR3,
306 INTEL_DRAM_LPDDR4,
307 INTEL_DRAM_DDR5,
308 INTEL_DRAM_LPDDR5,
309 INTEL_DRAM_GDDR,
310 } type;
311 u8 num_qgv_points;
312 u8 num_psf_gv_points;
313 } dram_info;
314
315 struct intel_runtime_pm runtime_pm;
316
317 struct i915_perf perf;
318
319 struct i915_hwmon *hwmon;
320
321 struct intel_gt *gt[I915_MAX_GT];
322
323 struct kobject *sysfs_gt;
324
325 /* Quick lookup of media GT (current platforms only have one) */
326 struct intel_gt *media_gt;
327
328 struct {
329 struct i915_gem_contexts {
330 spinlock_t lock; /* locks list */
331 struct list_head list;
332 } contexts;
333
334 /*
335 * We replace the local file with a global mappings as the
336 * backing storage for the mmap is on the device and not
337 * on the struct file, and we do not want to prolong the
338 * lifetime of the local fd. To minimise the number of
339 * anonymous inodes we create, we use a global singleton to
340 * share the global mapping.
341 */
342 struct file *mmap_singleton;
343 } gem;
344
345 struct intel_pxp *pxp;
346
347 struct i915_pmu pmu;
348
349 /* The TTM device structure. */
350 struct ttm_device bdev;
351
352 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
353
354 /*
355 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
356 * will be rejected. Instead look for a better place.
357 */
358};
359
360static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
361{
362 return container_of(dev, struct drm_i915_private, drm);
363}
364
365static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
366{
367 struct drm_device *drm = dev_get_drvdata(kdev);
368
369 return drm ? to_i915(drm) : NULL;
370}
371
372static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
373{
374 struct drm_device *drm = pci_get_drvdata(pdev);
375
376 return drm ? to_i915(drm) : NULL;
377}
378
379static inline struct intel_gt *to_gt(const struct drm_i915_private *i915)
380{
381 return i915->gt[0];
382}
383
384#define rb_to_uabi_engine(rb) \
385 rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
386
387#define for_each_uabi_engine(engine__, i915__) \
388 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
389 (engine__); \
390 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
391
392#define INTEL_INFO(i915) ((i915)->__info)
393#define RUNTIME_INFO(i915) (&(i915)->__runtime)
394#define DRIVER_CAPS(i915) (&(i915)->caps)
395
396#define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id)
397
398#define IP_VER(ver, rel) ((ver) << 8 | (rel))
399
400#define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver)
401#define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \
402 RUNTIME_INFO(i915)->graphics.ip.rel)
403#define IS_GRAPHICS_VER(i915, from, until) \
404 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
405
406#define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver)
407#define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
408 RUNTIME_INFO(i915)->media.ip.rel)
409#define IS_MEDIA_VER(i915, from, until) \
410 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
411
412#define INTEL_REVID(i915) (to_pci_dev((i915)->drm.dev)->revision)
413
414#define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
415#define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step)
416
417#define IS_GRAPHICS_STEP(__i915, since, until) \
418 (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \
419 INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until))
420
421#define IS_MEDIA_STEP(__i915, since, until) \
422 (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \
423 INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until))
424
425static __always_inline unsigned int
426__platform_mask_index(const struct intel_runtime_info *info,
427 enum intel_platform p)
428{
429 const unsigned int pbits =
430 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
431
432 /* Expand the platform_mask array if this fails. */
433 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
434 pbits * ARRAY_SIZE(info->platform_mask));
435
436 return p / pbits;
437}
438
439static __always_inline unsigned int
440__platform_mask_bit(const struct intel_runtime_info *info,
441 enum intel_platform p)
442{
443 const unsigned int pbits =
444 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
445
446 return p % pbits + INTEL_SUBPLATFORM_BITS;
447}
448
449static inline u32
450intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
451{
452 const unsigned int pi = __platform_mask_index(info, p);
453
454 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
455}
456
457static __always_inline bool
458IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
459{
460 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
461 const unsigned int pi = __platform_mask_index(info, p);
462 const unsigned int pb = __platform_mask_bit(info, p);
463
464 BUILD_BUG_ON(!__builtin_constant_p(p));
465
466 return info->platform_mask[pi] & BIT(pb);
467}
468
469static __always_inline bool
470IS_SUBPLATFORM(const struct drm_i915_private *i915,
471 enum intel_platform p, unsigned int s)
472{
473 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
474 const unsigned int pi = __platform_mask_index(info, p);
475 const unsigned int pb = __platform_mask_bit(info, p);
476 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
477 const u32 mask = info->platform_mask[pi];
478
479 BUILD_BUG_ON(!__builtin_constant_p(p));
480 BUILD_BUG_ON(!__builtin_constant_p(s));
481 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
482
483 /* Shift and test on the MSB position so sign flag can be used. */
484 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
485}
486
487#define IS_MOBILE(i915) (INTEL_INFO(i915)->is_mobile)
488#define IS_DGFX(i915) (INTEL_INFO(i915)->is_dgfx)
489
490#define IS_I830(i915) IS_PLATFORM(i915, INTEL_I830)
491#define IS_I845G(i915) IS_PLATFORM(i915, INTEL_I845G)
492#define IS_I85X(i915) IS_PLATFORM(i915, INTEL_I85X)
493#define IS_I865G(i915) IS_PLATFORM(i915, INTEL_I865G)
494#define IS_I915G(i915) IS_PLATFORM(i915, INTEL_I915G)
495#define IS_I915GM(i915) IS_PLATFORM(i915, INTEL_I915GM)
496#define IS_I945G(i915) IS_PLATFORM(i915, INTEL_I945G)
497#define IS_I945GM(i915) IS_PLATFORM(i915, INTEL_I945GM)
498#define IS_I965G(i915) IS_PLATFORM(i915, INTEL_I965G)
499#define IS_I965GM(i915) IS_PLATFORM(i915, INTEL_I965GM)
500#define IS_G45(i915) IS_PLATFORM(i915, INTEL_G45)
501#define IS_GM45(i915) IS_PLATFORM(i915, INTEL_GM45)
502#define IS_G4X(i915) (IS_G45(i915) || IS_GM45(i915))
503#define IS_PINEVIEW(i915) IS_PLATFORM(i915, INTEL_PINEVIEW)
504#define IS_G33(i915) IS_PLATFORM(i915, INTEL_G33)
505#define IS_IRONLAKE(i915) IS_PLATFORM(i915, INTEL_IRONLAKE)
506#define IS_IRONLAKE_M(i915) \
507 (IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915))
508#define IS_SANDYBRIDGE(i915) IS_PLATFORM(i915, INTEL_SANDYBRIDGE)
509#define IS_IVYBRIDGE(i915) IS_PLATFORM(i915, INTEL_IVYBRIDGE)
510#define IS_VALLEYVIEW(i915) IS_PLATFORM(i915, INTEL_VALLEYVIEW)
511#define IS_CHERRYVIEW(i915) IS_PLATFORM(i915, INTEL_CHERRYVIEW)
512#define IS_HASWELL(i915) IS_PLATFORM(i915, INTEL_HASWELL)
513#define IS_BROADWELL(i915) IS_PLATFORM(i915, INTEL_BROADWELL)
514#define IS_SKYLAKE(i915) IS_PLATFORM(i915, INTEL_SKYLAKE)
515#define IS_BROXTON(i915) IS_PLATFORM(i915, INTEL_BROXTON)
516#define IS_KABYLAKE(i915) IS_PLATFORM(i915, INTEL_KABYLAKE)
517#define IS_GEMINILAKE(i915) IS_PLATFORM(i915, INTEL_GEMINILAKE)
518#define IS_COFFEELAKE(i915) IS_PLATFORM(i915, INTEL_COFFEELAKE)
519#define IS_COMETLAKE(i915) IS_PLATFORM(i915, INTEL_COMETLAKE)
520#define IS_ICELAKE(i915) IS_PLATFORM(i915, INTEL_ICELAKE)
521#define IS_JASPERLAKE(i915) IS_PLATFORM(i915, INTEL_JASPERLAKE)
522#define IS_ELKHARTLAKE(i915) IS_PLATFORM(i915, INTEL_ELKHARTLAKE)
523#define IS_TIGERLAKE(i915) IS_PLATFORM(i915, INTEL_TIGERLAKE)
524#define IS_ROCKETLAKE(i915) IS_PLATFORM(i915, INTEL_ROCKETLAKE)
525#define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1)
526#define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S)
527#define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P)
528#define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2)
529#define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
530/*
531 * Display code shared by i915 and Xe relies on macros like IS_LUNARLAKE,
532 * so we need to define these even on platforms that the i915 base driver
533 * doesn't support. Ensure the parameter is used in the definition to
534 * avoid 'unused variable' warnings when compiling the shared display code
535 * for i915.
536 */
537#define IS_LUNARLAKE(i915) (0 && i915)
538#define IS_BATTLEMAGE(i915) (0 && i915)
539#define IS_PANTHERLAKE(i915) (0 && i915)
540
541#define IS_ARROWLAKE_H(i915) \
542 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_H)
543#define IS_ARROWLAKE_U(i915) \
544 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_U)
545#define IS_ARROWLAKE_S(i915) \
546 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_S)
547#define IS_DG2_G10(i915) \
548 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
549#define IS_DG2_G11(i915) \
550 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
551#define IS_DG2_G12(i915) \
552 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
553#define IS_RAPTORLAKE_S(i915) \
554 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
555#define IS_ALDERLAKE_P_N(i915) \
556 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
557#define IS_RAPTORLAKE_P(i915) \
558 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
559#define IS_RAPTORLAKE_U(i915) \
560 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
561#define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \
562 (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
563#define IS_BROADWELL_ULT(i915) \
564 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
565#define IS_BROADWELL_ULX(i915) \
566 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
567#define IS_HASWELL_ULT(i915) \
568 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
569/* ULX machines are also considered ULT. */
570#define IS_HASWELL_ULX(i915) \
571 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
572#define IS_SKYLAKE_ULT(i915) \
573 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
574#define IS_SKYLAKE_ULX(i915) \
575 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
576#define IS_KABYLAKE_ULT(i915) \
577 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
578#define IS_KABYLAKE_ULX(i915) \
579 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
580#define IS_COFFEELAKE_ULT(i915) \
581 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
582#define IS_COFFEELAKE_ULX(i915) \
583 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
584#define IS_COMETLAKE_ULT(i915) \
585 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
586#define IS_COMETLAKE_ULX(i915) \
587 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
588
589#define IS_ICL_WITH_PORT_F(i915) \
590 IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
591
592#define IS_TIGERLAKE_UY(i915) \
593 IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
594
595#define IS_GEN9_LP(i915) (IS_BROXTON(i915) || IS_GEMINILAKE(i915))
596#define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_GEN9_LP(i915))
597
598#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
599#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
600
601#define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \
602 unsigned int first__ = (first); \
603 unsigned int count__ = (count); \
604 ((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \
605})
606
607#define ENGINE_INSTANCES_MASK(gt, first, count) \
608 __ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)
609
610#define RCS_MASK(gt) \
611 ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
612#define BCS_MASK(gt) \
613 ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
614#define VDBOX_MASK(gt) \
615 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
616#define VEBOX_MASK(gt) \
617 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
618#define CCS_MASK(gt) \
619 ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
620
621#define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode)
622
623/*
624 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
625 * All later gens can run the final buffer from the ppgtt
626 */
627#define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7)
628
629#define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc)
630#define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop)
631#define HAS_EDRAM(i915) ((i915)->edram_size_mb)
632#define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6)
633#define HAS_WT(i915) HAS_EDRAM(i915)
634
635#define HWS_NEEDS_PHYSICAL(i915) (INTEL_INFO(i915)->hws_needs_physical)
636
637#define HAS_LOGICAL_RING_CONTEXTS(i915) \
638 (INTEL_INFO(i915)->has_logical_ring_contexts)
639#define HAS_LOGICAL_RING_ELSQ(i915) \
640 (INTEL_INFO(i915)->has_logical_ring_elsq)
641
642#define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915)
643
644#define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type)
645#define HAS_PPGTT(i915) \
646 (INTEL_PPGTT(i915) != INTEL_PPGTT_NONE)
647#define HAS_FULL_PPGTT(i915) \
648 (INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL)
649
650#define HAS_PAGE_SIZES(i915, sizes) ({ \
651 GEM_BUG_ON((sizes) == 0); \
652 ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \
653})
654
655#define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \
656 (IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9)
657
658/* WaRsDisableCoarsePowerGating:skl,cnl */
659#define NEEDS_WaRsDisableCoarsePowerGating(i915) \
660 (IS_SKYLAKE(i915) && (INTEL_INFO(i915)->gt == 3 || INTEL_INFO(i915)->gt == 4))
661
662/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
663 * rows, which changed the alignment requirements and fence programming.
664 */
665#define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \
666 !(IS_I915G(i915) || IS_I915GM(i915)))
667
668#define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6)
669#define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p)
670#define HAS_RC6pp(i915) (false) /* HW was never validated */
671
672#define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps)
673
674#define HAS_PXP(i915) \
675 (IS_ENABLED(CONFIG_DRM_I915_PXP) && INTEL_INFO(i915)->has_pxp)
676
677#define HAS_HECI_PXP(i915) \
678 (INTEL_INFO(i915)->has_heci_pxp)
679
680#define HAS_HECI_GSCFI(i915) \
681 (INTEL_INFO(i915)->has_heci_gscfi)
682
683#define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915))
684
685#define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm)
686#define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc)
687
688#define HAS_OA_BPC_REPORTING(i915) \
689 (INTEL_INFO(i915)->has_oa_bpc_reporting)
690#define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \
691 (INTEL_INFO(i915)->has_oa_slice_contrib_limits)
692#define HAS_OAM(i915) \
693 (INTEL_INFO(i915)->has_oam)
694
695/*
696 * Set this flag, when platform requires 64K GTT page sizes or larger for
697 * device local memory access.
698 */
699#define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages)
700
701#define HAS_REGION(i915, id) (INTEL_INFO(i915)->memory_regions & BIT(id))
702#define HAS_LMEM(i915) HAS_REGION(i915, INTEL_REGION_LMEM_0)
703
704#define HAS_EXTRA_GT_LIST(i915) (INTEL_INFO(i915)->extra_gt_list)
705
706/*
707 * Platform has the dedicated compression control state for each lmem surfaces
708 * stored in lmem to support the 3D and media compression formats.
709 */
710#define HAS_FLAT_CCS(i915) (INTEL_INFO(i915)->has_flat_ccs)
711
712#define HAS_GT_UC(i915) (INTEL_INFO(i915)->has_gt_uc)
713
714#define HAS_POOLED_EU(i915) (RUNTIME_INFO(i915)->has_pooled_eu)
715
716#define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs)
717
718#define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id)
719
720#define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
721
722/* DPF == dynamic parity feature */
723#define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf)
724#define NUM_L3_SLICES(i915) (IS_HASWELL(i915) && INTEL_INFO(i915)->gt == 3 ? \
725 2 : HAS_L3_DPF(i915))
726
727#define HAS_GUC_DEPRIVILEGE(i915) \
728 (INTEL_INFO(i915)->has_guc_deprivilege)
729
730#define HAS_GUC_TLB_INVALIDATION(i915) (INTEL_INFO(i915)->has_guc_tlb_invalidation)
731
732#define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline)
733
734#define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
735
736#define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
737 GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
738
739#endif